OpenOCD
LOG_LVL_DEBUG
is only used within OpenOCD.
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OpenOCD
LOG_LVL_DEBUG
LOG_LVL_DEBUG value
Syntax
Show:
Summary
Declaration
from
log.h:47
LOG_LVL_DEBUG
=
3
;
Examples
References
from
examples
Code
Location
Referrer
LOG_LVL_DEBUG
=
3
,
log.h:47
LOG_DEBUG
(
"FLASH plugin: placing the stack at 0x%08x-0x%08x"
,
lastSectionEnd
,
lastSectionEnd
+
stackSize
)
;
FLASHPlugin.c:157
loaded_plugin_load()
LOG_DEBUG
(
"FreeRTOS: Read uxCurrentNumberOfTasks at 0x%"
PRIx64
", value %"
PRIu32
,
FreeRTOS.c:158
freertos_update_threads()
LOG_DEBUG
(
"FreeRTOS: Read pxCurrentTCB at 0x%"
PRIx64
", value 0x%"
PRIx64
,
FreeRTOS.c:180
freertos_update_threads()
LOG_DEBUG
(
"FreeRTOS: Read xSchedulerRunning at 0x%"
PRIx64
", value 0x%"
PRIx32
,
FreeRTOS.c:193
freertos_update_threads()
LOG_DEBUG
(
"FreeRTOS: Read uxTopUsedPriority at 0x%"
PRIx64
", value %"
PRIu32
,
FreeRTOS.c:242
freertos_update_threads()
LOG_DEBUG
(
"FreeRTOS: Read thread count for list %u at 0x%"
PRIx64
", value %"
PRIu32
,
FreeRTOS.c:290
freertos_update_threads()
LOG_DEBUG
(
"FreeRTOS: Read first item for list %u at 0x%"
PRIx64
", value 0x%"
PRIx32
,
FreeRTOS.c:307
freertos_update_threads()
LOG_DEBUG
(
"FreeRTOS: Read Thread ID at 0x%"
PRIx32
", value 0x%"
PRIx64
,
FreeRTOS.c:323
freertos_update_threads()
LOG_DEBUG
(
"FreeRTOS: Read Thread Name at 0x%"
PRIx64
", value '%s'"
,
FreeRTOS.c:343
freertos_update_threads()
LOG_DEBUG
(
"FreeRTOS: Read next thread location at 0x%"
PRIx32
", value 0x%"
PRIx32
,
FreeRTOS.c:378
freertos_update_threads()
LOG_DEBUG
(
"FreeRTOS: Read stack pointer at 0x%"
PRIx64
", value 0x%"
PRIx64
,
FreeRTOS.c:416
freertos_get_thread_reg_list()
LOG_DEBUG
(
" solicited stack"
)
;
ThreadX.c:244
get_stacking_info_arm926ejs()
LOG_DEBUG
(
" interrupt stack: %"
PRIu32
,
flag
)
;
ThreadX.c:247
get_stacking_info_arm926ejs()
LOG_DEBUG
(
"unknown cpu state 0x%x"
,
armv8
->
arm
.
core_mode
)
;
aarch64.c:184
aarch64_mmu_modify()
LOG_DEBUG
(
"%s"
,
target_name
(
target
)
)
;
aarch64.c:212
aarch64_init_debug_access()
LOG_DEBUG
(
"Examine %s failed"
,
"oslock"
)
;
aarch64.c:217
aarch64_init_debug_access()
LOG_DEBUG
(
"target %s timeout, prsr=0x%08"
PRIx32
,
target_name
(
target
)
,
prsr
)
;
aarch64.c:324
aarch64_wait_halt_one()
LOG_DEBUG
(
"target %s exc %i"
,
target_name
(
target
)
,
exc_target
)
;
aarch64.c:337
aarch64_prepare_halt_smp()
LOG_DEBUG
(
"target %s prepared"
,
target_name
(
curr
)
)
;
aarch64.c:360
aarch64_prepare_halt_smp()
LOG_DEBUG
(
"%s"
,
target_name
(
target
)
)
;
aarch64.c:381
aarch64_halt_one()
LOG_DEBUG
(
"Halting remaining targets in SMP group"
)
;
aarch64.c:480
update_halt_gdb()
LOG_DEBUG
(
"Target %s halted"
,
target_name
(
target
)
)
;
aarch64.c:537
aarch64_poll()
LOG_DEBUG
(
"%s"
,
target_name
(
target
)
)
;
aarch64.c:586
aarch64_restore_one()
LOG_DEBUG
(
"resume pc = 0x%016"
PRIx64
,
resume_pc
)
;
aarch64.c:619
aarch64_restore_one()
LOG_DEBUG
(
"%s"
,
target_name
(
target
)
)
;
aarch64.c:645
aarch64_prepare_restart_one()
LOG_DEBUG
(
"%s"
,
target_name
(
target
)
)
;
aarch64.c:690
aarch64_do_restart_one()
LOG_DEBUG
(
"%s"
,
target_name
(
target
)
)
;
aarch64.c:731
aarch64_restart_one()
LOG_DEBUG
(
"%s"
,
target_name
(
target
)
)
;
aarch64.c:787
aarch64_step_restart_smp()
LOG_DEBUG
(
"error restarting target %s"
,
target_name
(
first
)
)
;
aarch64.c:796
aarch64_step_restart_smp()
LOG_DEBUG
(
"target resumed at 0x%"
PRIx64
,
addr
)
;
aarch64.c:949
aarch64_resume()
LOG_DEBUG
(
"target debug resumed at 0x%"
PRIx64
,
addr
)
;
aarch64.c:953
aarch64_resume()
LOG_DEBUG
(
"%s dscr = 0x%08"
PRIx32
,
target_name
(
target
)
,
dscr
)
;
aarch64.c:979
aarch64_debug_entry()
LOG_DEBUG
(
"System_register: %8.8"
PRIx64
,
aarch64
->
system_control_reg
)
;
aarch64.c:1080
aarch64_post_debug_entry()
LOG_DEBUG
(
"Restarted all non-stepping targets in SMP group"
)
;
aarch64.c:1150
aarch64_step()
LOG_DEBUG
(
"target step-resumed at 0x%"
PRIx64
,
address
)
;
aarch64.c:1161
aarch64_step()
LOG_DEBUG
(
"%s"
,
target_name
(
target
)
)
;
aarch64.c:1223
aarch64_restore_context()
LOG_DEBUG
(
"brp %i control 0x%0"
PRIx32
" value 0x%"
TARGET_PRIxADDR
,
brp_i
,
aarch64.c:1295
aarch64_set_breakpoint()
LOG_DEBUG
(
"Failed to set DSCR.HDE"
)
;
aarch64.c:1357
aarch64_set_breakpoint()
LOG_DEBUG
(
"brp %i control 0x%0"
PRIx32
" value 0x%"
TARGET_PRIxADDR
,
brp_i
,
aarch64.c:1407
aarch64_set_context_breakpoint()
LOG_DEBUG
(
"brp(CTX) found num: %d"
,
brp_1
)
;
aarch64.c:1437
aarch64_set_hybrid_breakpoint()
LOG_DEBUG
(
"brp(IVA) found num: %d"
,
brp_2
)
;
aarch64.c:1447
aarch64_set_hybrid_breakpoint()
LOG_DEBUG
(
"Invalid BRP number in breakpoint"
)
;
aarch64.c:1518
aarch64_unset_breakpoint()
LOG_DEBUG
(
"rbp %i control 0x%0"
PRIx32
" value 0x%"
TARGET_PRIxADDR
,
brp_i
,
aarch64.c:1521
aarch64_unset_breakpoint()
LOG_DEBUG
(
"Invalid BRP number in breakpoint"
)
;
aarch64.c:1542
aarch64_unset_breakpoint()
LOG_DEBUG
(
"rbp %i control 0x%0"
PRIx32
" value 0x%0"
PRIx64
,
brp_j
,
aarch64.c:1545
aarch64_unset_breakpoint()
LOG_DEBUG
(
"Invalid BRP number in breakpoint"
)
;
aarch64.c:1573
aarch64_unset_breakpoint()
LOG_DEBUG
(
"rbp %i control 0x%0"
PRIx32
" value 0x%0"
PRIx64
,
brp_i
,
aarch64.c:1576
aarch64_unset_breakpoint()
LOG_DEBUG
(
"wp %i control 0x%0"
PRIx32
" value 0x%"
TARGET_PRIxADDR
,
wp_i
,
aarch64.c:1771
aarch64_set_watchpoint()
LOG_DEBUG
(
"Failed to set DSCR.HDE"
)
;
aarch64.c:1777
aarch64_set_watchpoint()
LOG_DEBUG
(
"Invalid WP number in watchpoint"
)
;
aarch64.c:1803
aarch64_unset_watchpoint()
LOG_DEBUG
(
"rwp %i control 0x%0"
PRIx32
" value 0x%0"
PRIx64
,
wp_i
,
aarch64.c:1806
aarch64_unset_watchpoint()
LOG_DEBUG
(
"EDECR = 0x%08"
PRIx32
", enable=%d"
,
edecr
,
enable
)
;
aarch64.c:1904
aarch64_enable_reset_catch()
LOG_DEBUG
(
"Reset Catch debug event %s"
,
aarch64.c:1931
aarch64_clear_reset_catch()
LOG_DEBUG
(
" "
)
;
aarch64.c:1952
aarch64_assert_reset()
LOG_DEBUG
(
" "
)
;
aarch64.c:2012
aarch64_deassert_reset()
LOG_DEBUG
(
"Reading CPU memory address 0x%016"
PRIx64
" size %"
PRIu32
" count %"
PRIu32
,
aarch64.c:2418
aarch64_read_cpu_memory()
LOG_DEBUG
(
"Detected core %"
PRId32
" dbgbase: "
TARGET_ADDR_FMT
,
aarch64.c:2665
aarch64_examine_first()
LOG_DEBUG
(
"Examine %s failed"
,
"oslock"
)
;
aarch64.c:2673
aarch64_examine_first()
LOG_DEBUG
(
"Examine %s failed"
,
"CPUID"
)
;
aarch64.c:2680
aarch64_examine_first()
LOG_DEBUG
(
"Examine %s failed"
,
"Memory Model Type"
)
;
aarch64.c:2689
aarch64_examine_first()
LOG_DEBUG
(
"Examine %s failed"
,
"ID_AA64DFR0_EL1"
)
;
aarch64.c:2697
aarch64_examine_first()
LOG_DEBUG
(
"cpuid = 0x%08"
PRIx32
,
cpuid
)
;
aarch64.c:2712
aarch64_examine_first()
LOG_DEBUG
(
"ttypr = 0x%08"
PRIx64
,
ttypr
)
;
aarch64.c:2713
aarch64_examine_first()
LOG_DEBUG
(
"debug = 0x%08"
PRIx64
,
debug
)
;
aarch64.c:2714
aarch64_examine_first()
LOG_DEBUG
(
"Configured %i hw breakpoints, %i watchpoints"
,
aarch64.c:2755
aarch64_examine_first()
LOG_DEBUG
(
"convert khz to adapter specific speed value"
)
;
adapter.c:214
adapter_khz_to_speed()
LOG_DEBUG
(
"have adapter set up"
)
;
adapter.c:218
adapter_khz_to_speed()
LOG_DEBUG
(
"trying fallback speed..."
)
;
adapter.c:235
adapter_rclk_to_speed()
LOG_DEBUG
(
"handle adapter khz"
)
;
adapter.c:250
adapter_config_khz()
LOG_DEBUG
(
"handle adapter rclk"
)
;
adapter.c:259
adapter_config_rclk()
LOG_DEBUG
(
"Processing %s"
,
CMD_ARGV
[
i
]
)
;
adapter.c:948
adapter_gpio_config_handler()
LOG_DEBUG
(
"-chip arg is %s"
,
CMD_ARGV
[
i
+
1
]
)
;
adapter.c:961
adapter_gpio_config_handler()
LOG_DEBUG
(
"dapdirect_jtag_empty_command(\"%s\")"
,
CMD_NAME
)
;
adi_v5_dapdirect.c:33
dapdirect_jtag_empty_command()
LOG_DEBUG
(
"dapdirect_jtag_select()"
)
;
adi_v5_dapdirect.c:180
dapdirect_jtag_select()
LOG_DEBUG
(
"dapdirect_swd_select()"
)
;
adi_v5_dapdirect.c:187
dapdirect_swd_select()
LOG_DEBUG
(
"dapdirect_init()"
)
;
adi_v5_dapdirect.c:196
dapdirect_init()
LOG_DEBUG_IO
(
"DP BANK SELECT: %"
PRIx32
,
(
uint32_t
)
sel
)
;
adi_v5_jtag.c:364
adi_jtag_dp_scan_u32()
LOG_DEBUG
(
"DAP transaction stalled during replay (WAIT) - resending"
)
;
adi_v5_jtag.c:617
jtagdp_overrun_check()
LOG_DEBUG
(
"jtag-dp: CTRL/STAT 0x%"
PRIx32
,
ctrlstat
)
;
adi_v5_jtag.c:671
jtagdp_transaction_endcheck()
LOG_DEBUG
(
"JTAG-DP STICKY OVERRUN"
)
;
adi_v5_jtag.c:684
jtagdp_transaction_endcheck()
LOG_DEBUG_IO
(
"AP BANK SELECT: %"
PRIx32
,
(
uint32_t
)
sel
)
;
adi_v5_jtag.c:798
jtag_ap_q_bankselect()
LOG_DEBUG_IO
(
"AP BANK SELECT1: %"
PRIx32
,
(
uint32_t
)
(
sel
>
>
32
)
)
;
adi_v5_jtag.c:808
jtag_ap_q_bankselect()
LOG_DEBUG_IO
(
"DP BANK SELECT: %"
PRIx32
,
sel
)
;
adi_v5_swd.c:116
swd_queue_dp_bankselect()
LOG_DEBUG_IO
(
"Selected DP_TARGETSEL 0x%08"
PRIx32
,
dap
->
multidrop_targetsel
)
;
adi_v5_swd.c:251
swd_multidrop_select_inner()
LOG_DEBUG
(
"Failed to select multidrop %s, retrying..."
,
adi_v5_swd.c:287
swd_multidrop_select()
LOG_DEBUG_IO
(
"AP BANK SELECT: %"
PRIx32
,
(
uint32_t
)
sel
)
;
adi_v5_swd.c:552
swd_queue_ap_bankselect()
LOG_DEBUG_IO
(
"AP BANK SELECT1: %"
PRIx32
,
(
uint32_t
)
(
sel
>
>
32
)
)
;
adi_v5_swd.c:560
swd_queue_ap_bankselect()
LOG_DEBUG
(
"no SWD driver?"
)
;
adi_v5_swd.c:741
swd_select()
LOG_DEBUG
(
"can't init SWD driver"
)
;
adi_v5_swd.c:747
swd_select()
LOG_DEBUG
(
"performing mass erase."
)
;
aduc702x.c:78
aduc702x_erase()
LOG_DEBUG
(
"mass erase successful."
)
;
aduc702x.c:89
aduc702x_erase()
LOG_DEBUG
(
"erased sector at address 0x%08lX"
,
adr
)
;
aduc702x.c:107
aduc702x_erase()
LOG_DEBUG
(
"wrote %d bytes at address 0x%08lX"
,
(
int
)
count
,
(
unsigned
long
)
(
offset
+
x
)
)
;
aduc702x.c:297
aduc702x_write_single()
LOG_DEBUG
(
"bank=%p"
,
bank
)
;
aducm302x.c:137
aducm302x_probe()
LOG_DEBUG
(
"bank=%p first=%d last = %d"
,
bank
,
first
,
last
)
;
aducm302x.c:240
aducm302x_erase()
LOG_DEBUG
(
"WRPROT 0x%"
PRIx32
,
wrprot
)
;
aducm302x.c:304
aducm302x_protect()
LOG_DEBUG
(
"bank=%p buffer=%p offset=%08"
PRIx32
" dwcount=%"
PRIx32
,
aducm302x.c:355
aducm302x_write_block()
LOG_DEBUG
(
"no working area for block memory writes"
)
;
aducm302x.c:365
aducm302x_write_block()
LOG_DEBUG
(
"retry target_alloc_working_area(%s, size=%"
PRIu32
")"
,
aducm302x.c:384
aducm302x_write_block()
LOG_DEBUG
(
"bank=%p buffer=%p offset=%08"
PRIx32
" count=%"
PRIx32
,
aducm302x.c:443
aducm302x_write()
LOG_DEBUG
(
"writing flash word-at-a-time"
)
;
aducm302x.c:476
aducm302x_write()
LOG_DEBUG
(
"'aducm360_write_block_sync' requested, dst:0x%08"
PRIx32
", count:0x%08"
PRIx32
"bytes."
,
aducm360.c:207
aducm360_write_block_sync()
LOG_DEBUG
(
"'aducm360_write_block_async' requested, dst:0x%08"
PRIx32
", count:0x%08"
PRIx32
"bytes."
,
aducm360.c:329
aducm360_write_block_async()
LOG_DEBUG
(
"performing slow write (offset=0x%08"
PRIx32
", count=0x%08"
PRIx32
")..."
,
aducm360.c:447
aducm360_write_modified()
LOG_DEBUG
(
"Part number: 0x%"
PRIx32
,
part_num
)
;
ambiqmicro.c:185
ambiqmicro_read_part_info()
LOG_DEBUG
(
"num_pages: %"
PRIu32
", pagesize: %"
PRIu32
", flash: %"
PRIu32
", sram: %"
PRIu32
,
ambiqmicro.c:233
ambiqmicro_read_part_info()
LOG_DEBUG
(
"%s:%d:%s(): status(0x%x)\n"
,
ambiqmicro.c:271
check_flash_status()
LOG_DEBUG
(
"state = %d"
,
target
->
state
)
;
ambiqmicro.c:312
ambiqmicro_exec_command()
LOG_DEBUG
(
"address = 0x%08"
PRIx32
,
address
)
;
ambiqmicro.c:588
ambiqmicro_write_block()
LOG_DEBUG
(
"Adding %s reg_data_type"
,
data_type
->
data_type
.
id
)
;
arc.c:64
arc_reg_data_type_add()
LOG_DEBUG
(
"Resetting internal variables of caches states"
)
;
arc.c:107
arc_reset_caches_states()
LOG_DEBUG
(
arc.c:208
arc_reg_add()
LOG_DEBUG
(
"Get register (cached) gdb_num=%"
PRIu32
", name=%s, value=0x%"
PRIx32
,
arc.c:230
arc_get_register()
CHECK_RETVAL
(
arc_jtag_read_core_reg_one
(
&
arc
->
jtag_info
,
desc
->
arch_num
,
arc.c:241
arc_get_register()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
desc
->
arch_num
,
arc.c:244
arc_get_register()
LOG_DEBUG
(
"Get register gdb_num=%"
PRIu32
", name=%s, value=0x%"
PRIx32
,
arc.c:258
arc_get_register()
LOG_DEBUG
(
"Set register gdb_num=%"
PRIu32
", name=%s, value=0x%08"
PRIx32
,
arc.c:284
arc_set_register()
CHECK_RETVAL
(
arc_init_reg
(
target
,
&
reg_list
[
i
]
,
reg_desc
,
i
)
)
;
arc.c:376
arc_build_reg_cache()
LOG_DEBUG
(
"reg n=%3li name=%3s group=%s feature=%s"
,
i
,
arc.c:378
arc_build_reg_cache()
CHECK_RETVAL
(
arc_init_reg
(
target
,
&
reg_list
[
i
]
,
reg_desc
,
i
)
)
;
arc.c:391
arc_build_reg_cache()
LOG_DEBUG
(
"reg n=%3li name=%3s group=%s feature=%s"
,
i
,
arc.c:393
arc_build_reg_cache()
CHECK_RETVAL
(
arc_init_reg
(
target
,
&
reg_list
[
i
]
,
reg_desc
,
gdb_regnum
)
)
;
arc.c:467
arc_build_bcr_reg_cache()
LOG_DEBUG
(
"reg n=%3li name=%3s group=%s feature=%s"
,
i
,
arc.c:472
arc_build_bcr_reg_cache()
LOG_DEBUG
(
"REG_CLASS_ALL: number of regs=%i"
,
*
reg_list_size
)
;
arc.c:524
arc_get_gdb_reg_list()
LOG_DEBUG
(
"REG_CLASS_GENERAL: number of regs=%i"
,
*
reg_list_size
)
;
arc.c:542
arc_get_gdb_reg_list()
LOG_DEBUG
(
"getting register field (reg_name=%s, field_name=%s)"
,
reg_name
,
field_name
)
;
arc.c:554
arc_reg_get_field()
CHECK_RETVAL
(
reg
->
type
->
get
(
reg
)
)
;
arc.c:585
arc_reg_get_field()
LOG_DEBUG
(
"reg_name=%s"
,
reg_name
)
;
arc.c:600
arc_get_register_value()
CHECK_RETVAL
(
reg
->
type
->
get
(
reg
)
)
;
arc.c:608
arc_get_register_value()
LOG_DEBUG
(
"reg_name=%s value=0x%08"
PRIx32
,
reg_name
,
value
)
;
arc.c:618
arc_set_register_value()
CHECK_RETVAL
(
reg
->
type
->
set
(
reg
,
value_buf
)
)
;
arc.c:632
arc_set_register_value()
CHECK_RETVAL
(
arc_reg_get_field
(
target
,
"dccm_build"
,
"version"
,
arc.c:643
arc_configure_dccm()
CHECK_RETVAL
(
arc_reg_get_field
(
target
,
"dccm_build"
,
"size0"
,
arc.c:645
arc_configure_dccm()
CHECK_RETVAL
(
arc_reg_get_field
(
target
,
"dccm_build"
,
"size1"
,
arc.c:647
arc_configure_dccm()
CHECK_RETVAL
(
arc_get_register_value
(
target
,
"aux_dccm"
,
&
(
arc
->
dccm_start
)
)
)
;
arc.c:652
arc_configure_dccm()
LOG_DEBUG
(
"DCCM detected start=0x%"
PRIx32
" end=0x%"
PRIx32
,
arc.c:658
arc_configure_dccm()
CHECK_RETVAL
(
arc_reg_get_field
(
target
,
"iccm_build"
,
"version"
,
arc.c:675
arc_configure_iccm()
CHECK_RETVAL
(
arc_reg_get_field
(
target
,
"iccm_build"
,
"iccm0_size0"
,
arc.c:677
arc_configure_iccm()
CHECK_RETVAL
(
arc_reg_get_field
(
target
,
"iccm_build"
,
"iccm0_size1"
,
arc.c:679
arc_configure_iccm()
CHECK_RETVAL
(
arc_get_register_value
(
target
,
"aux_iccm"
,
&
aux_iccm
)
)
;
arc.c:682
arc_configure_iccm()
LOG_DEBUG
(
"ICCM0 detected start=0x%"
PRIx32
" end=0x%"
PRIx32
,
arc.c:690
arc_configure_iccm()
CHECK_RETVAL
(
arc_reg_get_field
(
target
,
"iccm_build"
,
"iccm1_size0"
,
arc.c:696
arc_configure_iccm()
CHECK_RETVAL
(
arc_reg_get_field
(
target
,
"iccm_build"
,
"iccm1_size1"
,
arc.c:698
arc_configure_iccm()
CHECK_RETVAL
(
arc_get_register_value
(
target
,
"aux_iccm"
,
&
aux_iccm
)
)
;
arc.c:703
arc_configure_iccm()
LOG_DEBUG
(
"ICCM1 detected start=0x%"
PRIx32
" end=0x%"
PRIx32
,
arc.c:710
arc_configure_iccm()
LOG_DEBUG
(
"Configuring ARC ICCM and DCCM"
)
;
arc.c:719
arc_configure()
CHECK_RETVAL
(
arc_configure_dccm
(
target
)
)
;
arc.c:724
arc_configure()
CHECK_RETVAL
(
arc_configure_iccm
(
target
)
)
;
arc.c:729
arc_configure()
CHECK_RETVAL
(
arc_jtag_startup
(
&
arc
->
jtag_info
)
)
;
arc.c:740
arc_examine()
CHECK_RETVAL
(
arc_jtag_status
(
&
arc
->
jtag_info
,
&
status
)
)
;
arc.c:743
arc_examine()
CHECK_RETVAL
(
arc_configure
(
target
)
)
;
arc.c:750
arc_examine()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DEBUG_REG
,
&
value
)
)
;
arc.c:764
arc_exit_debug()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DEBUG_REG
,
value
)
)
;
arc.c:766
arc_exit_debug()
CHECK_RETVAL
(
target_call_event_callbacks
(
target
,
TARGET_EVENT_HALTED
)
)
;
arc.c:770
arc_exit_debug()
if
(
debug_level
>=
LOG_LVL_DEBUG
)
{
arc.c:772
arc_exit_debug()
LOG_DEBUG
(
"core stopped (halted) debug-reg: 0x%08"
PRIx32
,
value
)
;
arc.c:773
arc_exit_debug()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_STATUS32_REG
,
&
value
)
)
;
arc.c:774
arc_exit_debug()
LOG_DEBUG
(
"core STATUS32: 0x%08"
PRIx32
,
value
)
;
arc.c:775
arc_exit_debug()
LOG_DEBUG
(
"target->state: %s"
,
target_state_name
(
target
)
)
;
arc.c:786
arc_halt()
LOG_DEBUG
(
"target was already halted"
)
;
arc.c:789
arc_halt()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DEBUG_REG
,
&
value
)
)
;
arc.c:809
arc_halt()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DEBUG_REG
,
value
)
)
;
arc.c:811
arc_halt()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_STATUS32_REG
,
&
irq_state
)
)
;
arc.c:815
arc_halt()
CHECK_RETVAL
(
target_call_event_callbacks
(
target
,
TARGET_EVENT_HALTED
)
)
;
arc.c:824
arc_halt()
if
(
debug_level
>=
LOG_LVL_DEBUG
)
{
arc.c:827
arc_halt()
LOG_DEBUG
(
"core stopped (halted) DEGUB-REG: 0x%08"
PRIx32
,
value
)
;
arc.c:828
arc_halt()
CHECK_RETVAL
(
arc_get_register_value
(
target
,
"status32"
,
&
value
)
)
;
arc.c:829
arc_halt()
LOG_DEBUG
(
"core STATUS32: 0x%08"
PRIx32
,
value
)
;
arc.c:830
arc_halt()
LOG_DEBUG
(
"Saving aux and core registers values"
)
;
arc.c:849
arc_save_context()
LOG_DEBUG
(
"Get core register regnum=%u, name=%s, value=0x%08"
PRIx32
,
arc.c:919
arc_save_context()
LOG_DEBUG
(
"Get aux register regnum=%u, name=%s, value=0x%08"
PRIx32
,
arc.c:934
arc_save_context()
CHECK_RETVAL
(
arc_reg_get_field
(
target
,
"debug"
,
"ah"
,
arc.c:965
get_current_actionpoint()
CHECK_RETVAL
(
arc_reg_get_field
(
target
,
"debug"
,
arc.c:972
get_current_actionpoint()
CHECK_RETVAL
(
arc_reg_get_field
(
target
,
"debug"
,
"bh"
,
arc.c:1000
arc_examine_debug_reason()
CHECK_RETVAL
(
get_current_actionpoint
(
target
,
&
actionpoint
)
)
;
arc.c:1008
arc_examine_debug_reason()
CHECK_RETVAL
(
arc_save_context
(
target
)
)
;
arc.c:1028
arc_debug_entry()
CHECK_RETVAL
(
arc_reset_caches_states
(
target
)
)
;
arc.c:1032
arc_debug_entry()
CHECK_RETVAL
(
arc_examine_debug_reason
(
target
)
)
;
arc.c:1033
arc_debug_entry()
CHECK_RETVAL
(
arc_jtag_status
(
&
arc
->
jtag_info
,
&
status
)
)
;
arc.c:1044
arc_poll()
CHECK_RETVAL
(
arc_get_register_value
(
target
,
"status32"
,
&
value
)
)
;
arc.c:1058
arc_poll()
LOG_DEBUG
(
"ARC core in halt or reset state."
)
;
arc.c:1060
arc_poll()
CHECK_RETVAL
(
arc_debug_entry
(
target
)
)
;
arc.c:1063
arc_poll()
CHECK_RETVAL
(
target_call_event_callbacks
(
target
,
TARGET_EVENT_HALTED
)
)
;
arc.c:1065
arc_poll()
LOG_DEBUG
(
"Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
arc.c:1067
arc_poll()
LOG_DEBUG
(
"ARC core is in debug running mode"
)
;
arc.c:1074
arc_poll()
CHECK_RETVAL
(
arc_debug_entry
(
target
)
)
;
arc.c:1076
arc_poll()
CHECK_RETVAL
(
target_call_event_callbacks
(
target
,
TARGET_EVENT_DEBUG_HALTED
)
)
;
arc.c:1078
arc_poll()
LOG_DEBUG
(
"target->state: %s"
,
target_state_name
(
target
)
)
;
arc.c:1090
arc_assert_reset()
LOG_DEBUG
(
"Starting CPU execution after reset"
)
;
arc.c:1104
arc_assert_reset()
CHECK_RETVAL
(
target_resume
(
target
,
1
,
0
,
0
,
0
)
)
;
arc.c:1105
arc_assert_reset()
CHECK_RETVAL
(
target_halt
(
target
)
)
;
arc.c:1134
arc_assert_reset()
LOG_DEBUG
(
"target->state: %s"
,
target_state_name
(
target
)
)
;
arc.c:1141
arc_deassert_reset()
if
(
debug_level
<
LOG_LVL_DEBUG
)
arc.c:1153
arc_arch_state()
CHECK_RETVAL
(
arc_get_register_value
(
target
,
"pc"
,
&
pc_value
)
)
;
arc.c:1156
arc_arch_state()
LOG_DEBUG
(
"target state: %s; PC at: 0x%08"
PRIx32
,
arc.c:1158
arc_arch_state()
LOG_DEBUG
(
"Restoring registers values"
)
;
arc.c:1177
arc_restore_context()
LOG_DEBUG
(
"Will write regnum=%u"
,
i
)
;
arc.c:1204
arc_restore_context()
LOG_DEBUG
(
"Will write regnum=%lu"
,
arc
->
num_core_regs
+
i
)
;
arc.c:1215
arc_restore_context()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_STATUS32_REG
,
&
value
)
)
;
arc.c:1257
arc_enable_interrupts()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_STATUS32_REG
,
value
)
)
;
arc.c:1262
arc_enable_interrupts()
LOG_DEBUG
(
"interrupts enabled"
)
;
arc.c:1263
arc_enable_interrupts()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_STATUS32_REG
,
value
)
)
;
arc.c:1267
arc_enable_interrupts()
LOG_DEBUG
(
"interrupts disabled"
)
;
arc.c:1268
arc_enable_interrupts()
LOG_DEBUG
(
"current:%i, address:0x%08"
TARGET_PRIxADDR
", handle_breakpoints:%i,"
arc.c:1282
arc_resume()
CHECK_RETVAL
(
arc_reset_caches_states
(
target
)
)
;
arc.c:1288
arc_resume()
CHECK_RETVAL
(
arc_enable_breakpoints
(
target
)
)
;
arc.c:1298
arc_resume()
CHECK_RETVAL
(
arc_enable_watchpoints
(
target
)
)
;
arc.c:1299
arc_resume()
LOG_DEBUG
(
"Changing the value of current PC to 0x%08"
TARGET_PRIxADDR
,
address
)
;
arc.c:1307
arc_resume()
CHECK_RETVAL
(
arc_restore_context
(
target
)
)
;
arc.c:1315
arc_resume()
LOG_DEBUG
(
"Target resumes from PC=0x%"
PRIx32
", pc.dirty=%i, pc.valid=%i"
,
arc.c:1317
arc_resume()
LOG_DEBUG
(
"resume Core (when start-core) with PC @:0x%08"
PRIx32
,
value
)
;
arc.c:1323
arc_resume()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_PC_REG
,
value
)
)
;
arc.c:1324
arc_resume()
LOG_DEBUG
(
"skipping past breakpoint at 0x%08"
TARGET_PRIxADDR
,
arc.c:1332
arc_resume()
CHECK_RETVAL
(
arc_unset_breakpoint
(
target
,
breakpoint
)
)
;
arc.c:1334
arc_resume()
CHECK_RETVAL
(
arc_single_step_core
(
target
)
)
;
arc.c:1335
arc_resume()
CHECK_RETVAL
(
arc_set_breakpoint
(
target
,
breakpoint
)
)
;
arc.c:1336
arc_resume()
CHECK_RETVAL
(
arc_enable_interrupts
(
target
,
arc
->
irq_state
)
)
;
arc.c:1342
arc_resume()
CHECK_RETVAL
(
arc_enable_interrupts
(
target
,
!
debug_execution
)
)
;
arc.c:1344
arc_resume()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_STATUS32_REG
,
&
value
)
)
;
arc.c:1350
arc_resume()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_STATUS32_REG
,
value
)
)
;
arc.c:1352
arc_resume()
LOG_DEBUG
(
"Core started to run"
)
;
arc.c:1353
arc_resume()
CHECK_RETVAL
(
target_call_event_callbacks
(
target
,
TARGET_EVENT_RESUMED
)
)
;
arc.c:1360
arc_resume()
LOG_DEBUG
(
"target resumed at 0x%08"
PRIx32
,
resume_pc
)
;
arc.c:1361
arc_resume()
CHECK_RETVAL
(
target_call_event_callbacks
(
target
,
TARGET_EVENT_DEBUG_RESUMED
)
)
;
arc.c:1364
arc_resume()
LOG_DEBUG
(
"target debug resumed at 0x%08"
PRIx32
,
resume_pc
)
;
arc.c:1365
arc_resume()
CHECK_RETVAL
(
arc_build_reg_cache
(
target
)
)
;
arc.c:1373
arc_init_target()
CHECK_RETVAL
(
arc_build_bcr_reg_cache
(
target
)
)
;
arc.c:1374
arc_init_target()
LOG_DEBUG
(
"deinitialization of target"
)
;
arc.c:1389
arc_deinit_target()
LOG_DEBUG
(
"Entering"
)
;
arc.c:1438
arc_target_create()
CHECK_RETVAL
(
arc_init_arch_info
(
target
,
arc
,
target
->
tap
)
)
;
arc.c:1439
arc_target_create()
LOG_DEBUG
(
"Address: 0x%08"
PRIx32
", value: 0x%08"
PRIx32
,
address
,
arc.c:1459
arc_write_instruction_u32()
CHECK_RETVAL
(
target_write_buffer
(
target
,
address
,
4
,
value_buf
)
)
;
arc.c:1467
arc_write_instruction_u32()
CHECK_RETVAL
(
target_read_buffer
(
target
,
address
,
4
,
value_buf
)
)
;
arc.c:1488
arc_read_instruction_u32()
LOG_DEBUG
(
"Address: 0x%08"
PRIx32
", value: 0x%08"
PRIx32
,
address
,
arc.c:1495
arc_read_instruction_u32()
CHECK_RETVAL
(
arc_set_register_value
(
target
,
ap_amv_reg_name
,
arc.c:1529
arc_configure_actionpoint()
CHECK_RETVAL
(
arc_set_register_value
(
target
,
ap_amm_reg_name
,
0
)
)
;
arc.c:1531
arc_configure_actionpoint()
CHECK_RETVAL
(
arc_set_register_value
(
target
,
ap_ac_reg_name
,
arc.c:1532
arc_configure_actionpoint()
CHECK_RETVAL
(
arc_set_register_value
(
target
,
ap_ac_reg_name
,
arc.c:1538
arc_configure_actionpoint()
LOG_DEBUG
(
"bpid: %"
PRIu32
,
breakpoint
->
unique_id
)
;
arc.c:1555
arc_set_breakpoint()
CHECK_RETVAL
(
target_read_buffer
(
target
,
breakpoint
->
address
,
breakpoint
->
length
,
arc.c:1560
arc_set_breakpoint()
CHECK_RETVAL
(
arc_write_instruction_u32
(
target
,
breakpoint
->
address
,
arc.c:1563
arc_set_breakpoint()
CHECK_RETVAL
(
arc_read_instruction_u32
(
target
,
breakpoint
->
address
,
&
verify
)
)
;
arc.c:1566
arc_set_breakpoint()
CHECK_RETVAL
(
target_read_buffer
(
target
,
breakpoint
->
address
,
breakpoint
->
length
,
arc.c:1576
arc_set_breakpoint()
CHECK_RETVAL
(
target_write_u16
(
target
,
breakpoint
->
address
,
ARC_SDBBP_16
)
)
;
arc.c:1578
arc_set_breakpoint()
CHECK_RETVAL
(
target_read_u16
(
target
,
breakpoint
->
address
,
&
verify
)
)
;
arc.c:1580
arc_set_breakpoint()
LOG_DEBUG
(
"bpid: %"
PRIu32
", bp_num %u bp_value 0x%"
PRIx32
,
arc.c:1617
arc_set_breakpoint()
LOG_DEBUG
(
"ERROR: setting unknown breakpoint type"
)
;
arc.c:1622
arc_set_breakpoint()
LOG_DEBUG
(
"bpid: %"
PRIu32
,
breakpoint
->
unique_id
)
;
arc.c:1641
arc_unset_breakpoint()
CHECK_RETVAL
(
arc_read_instruction_u32
(
target
,
breakpoint
->
address
,
&
current_instr
)
)
;
arc.c:1646
arc_unset_breakpoint()
CHECK_RETVAL
(
target_read_u16
(
target
,
breakpoint
->
address
,
&
current_instr
)
)
;
arc.c:1663
arc_unset_breakpoint()
LOG_DEBUG
(
"Invalid actionpoint ID: %u in breakpoint: %"
PRIu32
,
arc.c:1687
arc_unset_breakpoint()
LOG_DEBUG
(
"bpid: %"
PRIu32
" - released actionpoint ID: %u"
,
arc.c:1700
arc_unset_breakpoint()
LOG_DEBUG
(
"ERROR: unsetting unknown breakpoint type"
)
;
arc.c:1704
arc_unset_breakpoint()
CHECK_RETVAL
(
arc_set_breakpoint
(
target
,
breakpoint
)
)
;
arc.c:1718
arc_enable_breakpoints()
CHECK_RETVAL
(
arc_unset_breakpoint
(
target
,
breakpoint
)
)
;
arc.c:1741
arc_remove_breakpoint()
LOG_DEBUG
(
"target=%s actionpoints=%"
PRIu32
,
target_name
(
target
)
,
ap_num
)
;
arc.c:1778
arc_set_actionpoints_num()
LOG_DEBUG
(
"wpid: %"
PRIu32
", wp_num %u wp_value 0x%"
PRIx32
,
arc.c:1920
arc_set_watchpoint()
LOG_DEBUG
(
"Invalid actionpoint ID: %u in watchpoint: %"
PRIu32
,
arc.c:1941
arc_unset_watchpoint()
LOG_DEBUG
(
"wpid: %"
PRIu32
" - releasing actionpoint ID: %u"
,
arc.c:1954
arc_unset_watchpoint()
CHECK_RETVAL
(
arc_set_watchpoint
(
target
,
watchpoint
)
)
;
arc.c:1968
arc_enable_watchpoints()
CHECK_RETVAL
(
arc_set_watchpoint
(
target
,
watchpoint
)
)
;
arc.c:1983
arc_add_watchpoint()
CHECK_RETVAL
(
arc_unset_watchpoint
(
target
,
watchpoint
)
)
;
arc.c:1997
arc_remove_watchpoint()
CHECK_RETVAL
(
get_current_actionpoint
(
target
,
&
actionpoint
)
)
;
arc.c:2008
arc_hit_watchpoint()
LOG_DEBUG
(
"Hit watchpoint, wpid: %"
PRIu32
", watchpoint num: %u"
,
arc.c:2023
arc_hit_watchpoint()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_STATUS32_REG
,
arc.c:2043
arc_config_step()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_STATUS32_REG
,
arc.c:2046
arc_config_step()
LOG_DEBUG
(
" [status32:0x%08"
PRIx32
"]"
,
value
)
;
arc.c:2048
arc_config_step()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
arc.c:2052
arc_config_step()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DEBUG_REG
,
arc.c:2055
arc_config_step()
LOG_DEBUG
(
"core debug step mode enabled [debug-reg:0x%08"
PRIx32
"]"
,
value
)
;
arc.c:2057
arc_config_step()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DEBUG_REG
,
arc.c:2060
arc_config_step()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DEBUG_REG
,
arc.c:2063
arc_config_step()
LOG_DEBUG
(
"core debug step mode disabled"
)
;
arc.c:2065
arc_config_step()
CHECK_RETVAL
(
arc_debug_entry
(
target
)
)
;
arc.c:2073
arc_single_step_core()
CHECK_RETVAL
(
arc_enable_interrupts
(
target
,
0
)
)
;
arc.c:2076
arc_single_step_core()
CHECK_RETVAL
(
arc_config_step
(
target
,
1
)
)
;
arc.c:2079
arc_single_step_core()
CHECK_RETVAL
(
arc_exit_debug
(
target
)
)
;
arc.c:2082
arc_single_step_core()
LOG_DEBUG
(
"Target steps one instruction from PC=0x%"
PRIx32
,
arc.c:2107
arc_step()
CHECK_RETVAL
(
arc_unset_breakpoint
(
target
,
breakpoint
)
)
;
arc.c:2114
arc_step()
CHECK_RETVAL
(
arc_restore_context
(
target
)
)
;
arc.c:2118
arc_step()
CHECK_RETVAL
(
target_call_event_callbacks
(
target
,
TARGET_EVENT_RESUMED
)
)
;
arc.c:2122
arc_step()
CHECK_RETVAL
(
arc_enable_interrupts
(
target
,
0
)
)
;
arc.c:2125
arc_step()
CHECK_RETVAL
(
arc_config_step
(
target
,
1
)
)
;
arc.c:2128
arc_step()
CHECK_RETVAL
(
arc_set_breakpoint
(
target
,
breakpoint
)
)
;
arc.c:2137
arc_step()
LOG_DEBUG
(
"target stepped "
)
;
arc.c:2139
arc_step()
CHECK_RETVAL
(
arc_debug_entry
(
target
)
)
;
arc.c:2144
arc_step()
CHECK_RETVAL
(
target_call_event_callbacks
(
target
,
TARGET_EVENT_HALTED
)
)
;
arc.c:2145
arc_step()
LOG_DEBUG
(
"Invalidating I$."
)
;
arc.c:2162
arc_icache_invalidate()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_IC_IVIC_REG
,
value
)
)
;
arc.c:2165
arc_icache_invalidate()
LOG_DEBUG
(
"Invalidating D$."
)
;
arc.c:2182
arc_dcache_invalidate()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DC_CTRL_REG
,
&
value
)
)
;
arc.c:2184
arc_dcache_invalidate()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DC_CTRL_REG
,
value
)
)
;
arc.c:2189
arc_dcache_invalidate()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DC_IVDC_REG
,
value
)
)
;
arc.c:2191
arc_dcache_invalidate()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DC_CTRL_REG
,
dc_ctrl_value
)
)
;
arc.c:2194
arc_dcache_invalidate()
LOG_DEBUG
(
"Invalidating L2$."
)
;
arc.c:2211
arc_l2cache_invalidate()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
SLC_AUX_CACHE_CTRL
,
&
value
)
)
;
arc.c:2213
arc_l2cache_invalidate()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
SLC_AUX_CACHE_CTRL
,
value
)
)
;
arc.c:2218
arc_l2cache_invalidate()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
SLC_AUX_CACHE_INV
,
L2_INV_IV
)
)
;
arc.c:2220
arc_l2cache_invalidate()
LOG_DEBUG
(
"Waiting for invalidation end."
)
;
arc.c:2224
arc_l2cache_invalidate()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
SLC_AUX_CACHE_CTRL
,
&
value
)
)
;
arc.c:2225
arc_l2cache_invalidate()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
SLC_AUX_CACHE_CTRL
,
slc_ctrl_value
)
)
;
arc.c:2229
arc_l2cache_invalidate()
CHECK_RETVAL
(
arc_icache_invalidate
(
target
)
)
;
arc.c:2239
arc_cache_invalidate()
CHECK_RETVAL
(
arc_dcache_invalidate
(
target
)
)
;
arc.c:2240
arc_cache_invalidate()
CHECK_RETVAL
(
arc_l2cache_invalidate
(
target
)
)
;
arc.c:2241
arc_cache_invalidate()
LOG_DEBUG
(
"Flushing D$."
)
;
arc.c:2262
arc_dcache_flush()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DC_CTRL_REG
,
&
dc_ctrl_value
)
)
;
arc.c:2265
arc_dcache_flush()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DC_CTRL_REG
,
value
)
)
;
arc.c:2271
arc_dcache_flush()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DC_IVDC_REG
,
value
)
)
;
arc.c:2276
arc_dcache_flush()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
AUX_DC_CTRL_REG
,
dc_ctrl_value
)
)
;
arc.c:2280
arc_dcache_flush()
LOG_DEBUG
(
"Flushing L2$."
)
;
arc.c:2298
arc_l2cache_flush()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
SLC_AUX_CACHE_FLUSH
,
L2_FLUSH_FL
)
)
;
arc.c:2301
arc_l2cache_flush()
LOG_DEBUG
(
"Waiting for flushing end."
)
;
arc.c:2305
arc_l2cache_flush()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
SLC_AUX_CACHE_CTRL
,
&
value
)
)
;
arc.c:2306
arc_l2cache_flush()
CHECK_RETVAL
(
arc_dcache_flush
(
target
)
)
;
arc.c:2316
arc_cache_flush()
CHECK_RETVAL
(
arc_l2cache_flush
(
target
)
)
;
arc.c:2317
arc_cache_flush()
LOG_DEBUG
(
"-"
)
;
arc_cmd.c:133
arc_handle_add_reg_type_flags()
LOG_DEBUG
(
"added flags type {name=%s}"
,
type
->
data_type
.
id
)
;
arc_cmd.c:180
arc_handle_add_reg_type_flags()
CHECK_RETVAL
(
arc_jtag_write_aux_reg_one
(
&
arc
->
jtag_info
,
regnum
,
value
)
)
;
arc_cmd.c:226
arc_handle_set_aux_reg()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
regnum
,
&
value
)
)
;
arc_cmd.c:250
arc_handle_get_aux_reg()
CHECK_RETVAL
(
arc_jtag_read_core_reg_one
(
&
arc
->
jtag_info
,
regnum
,
&
value
)
)
;
arc_cmd.c:282
arc_handle_get_core_reg()
CHECK_RETVAL
(
arc_jtag_write_core_reg_one
(
&
arc
->
jtag_info
,
regnum
,
value
)
)
;
arc_cmd.c:316
arc_handle_set_core_reg()
LOG_DEBUG
(
"-"
)
;
arc_cmd.c:446
arc_handle_add_reg_type_struct()
LOG_DEBUG
(
"added struct type {name=%s}"
,
type
->
data_type
.
id
)
;
arc_cmd.c:493
arc_handle_add_reg_type_struct()
LOG_DEBUG
(
"-"
)
;
arc_cmd.c:764
arc_handle_actionpoints_num()
CHECK_RETVAL
(
jtag_execute_queue
(
)
)
;
arc_jtag.c:192
arc_jtag_status()
LOG_DEBUG
(
"Writing to %s registers: addr[0]=0x%"
PRIx32
";count=%"
PRIu32
arc_jtag.c:245
arc_jtag_write_registers()
LOG_DEBUG
(
"Reading %s registers: addr[0]=0x%"
PRIx32
";count=%"
PRIu32
,
arc_jtag.c:286
arc_jtag_read_registers()
LOG_DEBUG
(
"Read from register: buf[0]=0x%"
PRIx32
,
buffer
[
0
]
)
;
arc_jtag.c:316
arc_jtag_read_registers()
LOG_DEBUG
(
"Writing to memory: addr=0x%08"
PRIx32
";count=%"
PRIu32
";buffer[0]=0x%08"
PRIx32
,
arc_jtag.c:442
arc_jtag_write_memory()
LOG_DEBUG
(
"Reading memory: addr=0x%"
PRIx32
";count=%"
PRIu32
";slow=%c"
,
arc_jtag.c:495
arc_jtag_read_memory()
LOG_DEBUG
(
"Write 4-byte memory block: addr=0x%08"
PRIx32
", count=%"
PRIu32
,
arc_mem.c:38
arc_mem_write_block32()
CHECK_RETVAL
(
arc_cache_flush
(
target
)
)
;
arc_mem.c:46
arc_mem_write_block32()
CHECK_RETVAL
(
arc_jtag_write_memory
(
&
arc
->
jtag_info
,
addr
,
count
,
arc_mem.c:50
arc_mem_write_block32()
CHECK_RETVAL
(
arc_cache_invalidate
(
target
)
)
;
arc_mem.c:54
arc_mem_write_block32()
LOG_DEBUG
(
"Write 2-byte memory block: addr=0x%08"
PRIx32
", count=%"
PRIu32
,
arc_mem.c:69
arc_mem_write_block16()
CHECK_RETVAL
(
arc_cache_flush
(
target
)
)
;
arc_mem.c:76
arc_mem_write_block16()
CHECK_RETVAL
(
arc_jtag_read_memory
(
&
arc
->
jtag_info
,
arc_mem.c:94
arc_mem_write_block16()
CHECK_RETVAL
(
arc_jtag_write_memory
(
&
arc
->
jtag_info
,
arc_mem.c:107
arc_mem_write_block16()
CHECK_RETVAL
(
arc_cache_invalidate
(
target
)
)
;
arc_mem.c:112
arc_mem_write_block16()
LOG_DEBUG
(
"Write 1-byte memory block: addr=0x%08"
PRIx32
", count=%"
PRIu32
,
arc_mem.c:127
arc_mem_write_block8()
CHECK_RETVAL
(
arc_cache_flush
(
target
)
)
;
arc_mem.c:131
arc_mem_write_block8()
CHECK_RETVAL
(
arc_jtag_read_memory
(
&
arc
->
jtag_info
,
(
addr
+
i
)
&
~
3
,
1
,
&
buffer_he
,
arc_mem.c:140
arc_mem_write_block8()
CHECK_RETVAL
(
arc_jtag_write_memory
(
&
arc
->
jtag_info
,
(
addr
+
i
)
&
~
3
,
1
,
&
buffer_he
)
)
;
arc_mem.c:145
arc_mem_write_block8()
CHECK_RETVAL
(
arc_cache_invalidate
(
target
)
)
;
arc_mem.c:149
arc_mem_write_block8()
LOG_DEBUG
(
"address: 0x%08"
TARGET_PRIxADDR
", size: %"
PRIu32
", count: %"
PRIu32
,
arc_mem.c:161
arc_mem_write()
LOG_DEBUG
(
"Read memory: addr=0x%08"
TARGET_PRIxADDR
", size=%"
PRIu32
arc_mem.c:223
arc_mem_read_block()
CHECK_RETVAL
(
arc_cache_flush
(
target
)
)
;
arc_mem.c:229
arc_mem_read_block()
CHECK_RETVAL
(
arc_jtag_read_memory
(
&
arc
->
jtag_info
,
addr
,
count
,
buf
,
arc_mem.c:231
arc_mem_read_block()
LOG_DEBUG
(
"Read memory: addr=0x%08"
TARGET_PRIxADDR
", size=%"
PRIu32
arc_mem.c:246
arc_mem_read()
LOG_DEBUG_IO
(
"runtest %u cycles, end in %i"
,
arm-jtag-ew.c:98
armjtagew_execute_queue()
LOG_DEBUG_IO
(
"statemove end in %i"
,
cmd
->
cmd
.
statemove
->
end_state
)
;
arm-jtag-ew.c:107
armjtagew_execute_queue()
LOG_DEBUG_IO
(
"pathmove: %u states, end in %i"
,
arm-jtag-ew.c:114
armjtagew_execute_queue()
LOG_DEBUG_IO
(
"scan end in %i"
,
cmd
->
cmd
.
scan
->
end_state
)
;
arm-jtag-ew.c:123
armjtagew_execute_queue()
LOG_DEBUG_IO
(
"scan input, length = %d"
,
scan_size
)
;
arm-jtag-ew.c:128
armjtagew_execute_queue()
LOG_DEBUG_IO
(
"reset trst: %i srst %i"
,
arm-jtag-ew.c:140
armjtagew_execute_queue()
tap_set_state
(
TAP_RESET
)
;
arm-jtag-ew.c:147
armjtagew_execute_queue()
LOG_DEBUG_IO
(
"sleep %"
PRIu32
,
cmd
->
cmd
.
sleep
->
us
)
;
arm-jtag-ew.c:152
armjtagew_execute_queue()
tap_set_state
(
tap_get_end_state
(
)
)
;
arm-jtag-ew.c:279
armjtagew_state_move()
tap_set_state
(
path
[
i
]
)
;
arm-jtag-ew.c:300
armjtagew_path_move()
tap_set_state
(
ir_scan
?
TAP_IRPAUSE
:
TAP_DRPAUSE
)
;
arm-jtag-ew.c:353
armjtagew_scan()
LOG_DEBUG
(
"trst: %i, srst: %i"
,
trst
,
srst
)
;
arm-jtag-ew.c:368
armjtagew_reset()
LOG_DEBUG_IO
(
"pending scan result, length = %d"
,
length
)
;
arm-jtag-ew.c:641
armjtagew_tap_execute()
LOG_DEBUG_IO
(
"armjtagew_usb_write, out_length = %d, result = %d"
,
out_length
,
result
)
;
arm-jtag-ew.c:743
armjtagew_usb_write()
LOG_DEBUG_IO
(
"armjtagew_usb_read, result = %d"
,
result
)
;
arm-jtag-ew.c:760
armjtagew_usb_read()
CHECK_RETVAL
(
arm11_read_dscr
(
arm11
)
)
;
arm11.c:43
arm11_check_init()
LOG_DEBUG
(
"DSCR %08x"
,
(
unsigned
)
arm11
->
dscr
)
;
arm11.c:46
arm11_check_init()
LOG_DEBUG
(
"Bringing target into debug mode"
)
;
arm11.c:47
arm11_check_init()
CHECK_RETVAL
(
arm11_write_dscr
(
arm11
,
arm11
->
dscr
)
)
;
arm11.c:50
arm11_check_init()
CHECK_RETVAL
(
arm11_sc7_clear_vbw
(
arm11
)
)
;
arm11.c:70
arm11_check_init()
CHECK_RETVAL
(
arm11_write_dscr
(
arm11
,
DSCR_ITR_EN
|
arm11
->
dscr
)
)
;
arm11.c:118
arm11_debug_entry()
LOG_DEBUG
(
"Reset c1 Control Register"
)
;
arm11.c:181
arm11_debug_entry()
CHECK_RETVAL
(
arm11_read_dscr
(
arm11
)
)
;
arm11.c:234
arm11_leave_debug_state()
CHECK_RETVAL
(
arm_dpm_write_dirty_registers
(
&
arm11
->
dpm
,
bpwp
)
)
;
arm11.c:270
arm11_leave_debug_state()
CHECK_RETVAL
(
arm11_bpwp_flush
(
arm11
)
)
;
arm11.c:272
arm11_leave_debug_state()
CHECK_RETVAL
(
arm11_write_dscr
(
arm11
,
arm11
->
dscr
)
)
;
arm11.c:277
arm11_leave_debug_state()
CHECK_RETVAL
(
arm11_check_init
(
arm11
)
)
;
arm11.c:310
arm11_poll()
LOG_DEBUG
(
"enter TARGET_HALTED"
)
;
arm11.c:316
arm11_poll()
LOG_DEBUG
(
"enter TARGET_RUNNING"
)
;
arm11.c:328
arm11_poll()
LOG_DEBUG
(
"target->state: %s"
,
arm11.c:357
arm11_halt()
LOG_DEBUG
(
"target was already halted"
)
;
arm11.c:364
arm11_halt()
CHECK_RETVAL
(
jtag_execute_queue
(
)
)
;
arm11.c:370
arm11_halt()
CHECK_RETVAL
(
arm11_read_dscr
(
arm11
)
)
;
arm11.c:375
arm11_halt()
CHECK_RETVAL
(
arm11_debug_entry
(
arm11
)
)
;
arm11.c:395
arm11_halt()
CHECK_RETVAL
(
arm11.c:397
arm11_halt()
LOG_DEBUG
(
"target->state: %s"
,
arm11.c:447
arm11_resume()
LOG_DEBUG
(
"RESUME PC %08"
TARGET_PRIxADDR
"%s"
,
address
,
!
current
?
"!"
:
""
)
;
arm11.c:458
arm11_resume()
CHECK_RETVAL
(
arm11_sc7_clear_vbw
(
arm11
)
)
;
arm11.c:461
arm11_resume()
LOG_DEBUG
(
"must step over %08"
TARGET_PRIxADDR
""
,
bp
->
address
)
;
arm11.c:472
arm11_resume()
CHECK_RETVAL
(
arm11_sc7_run
(
arm11
,
brp
,
ARRAY_SIZE
(
brp
)
)
)
;
arm11.c:496
arm11_resume()
LOG_DEBUG
(
"Add BP %d at %08"
TARGET_PRIxADDR
,
brp_num
,
arm11.c:498
arm11_resume()
CHECK_RETVAL
(
arm11_sc7_set_vcr
(
arm11
,
arm11
->
vcr
)
)
;
arm11.c:505
arm11_resume()
CHECK_RETVAL
(
arm11_leave_debug_state
(
arm11
,
true
)
)
;
arm11.c:509
arm11_resume()
CHECK_RETVAL
(
jtag_execute_queue
(
)
)
;
arm11.c:513
arm11_resume()
CHECK_RETVAL
(
arm11_read_dscr
(
arm11
)
)
;
arm11.c:517
arm11_resume()
LOG_DEBUG
(
"DSCR %08x"
,
(
unsigned
)
arm11
->
dscr
)
;
arm11.c:519
arm11_resume()
CHECK_RETVAL
(
target_call_event_callbacks
(
target
,
TARGET_EVENT_RESUMED
)
)
;
arm11.c:542
arm11_resume()
LOG_DEBUG
(
"target->state: %s"
,
arm11.c:550
arm11_step()
LOG_DEBUG
(
"STEP PC %08"
TARGET_PRIxADDR
"%s"
,
address
,
!
current
?
"!"
:
""
)
;
arm11.c:562
arm11_step()
CHECK_RETVAL
(
arm11_read_memory_word
(
arm11
,
address
,
&
next_instruction
)
)
;
arm11.c:569
arm11_step()
LOG_DEBUG
(
"Skipping BKPT %08"
TARGET_PRIxADDR
,
address
)
;
arm11.c:574
arm11_step()
LOG_DEBUG
(
"Skipping WFI %08"
TARGET_PRIxADDR
,
address
)
;
arm11.c:580
arm11_step()
LOG_DEBUG
(
"Not stepping jump to self"
)
;
arm11.c:584
arm11_step()
CHECK_RETVAL
(
arm11_sc7_run
(
arm11
,
brp
,
ARRAY_SIZE
(
brp
)
)
)
;
arm11.c:639
arm11_step()
CHECK_RETVAL
(
arm11_leave_debug_state
(
arm11
,
handle_breakpoints
)
)
;
arm11.c:651
arm11_step()
CHECK_RETVAL
(
jtag_execute_queue
(
)
)
;
arm11.c:655
arm11_step()
CHECK_RETVAL
(
arm11_read_dscr
(
arm11
)
)
;
arm11.c:664
arm11_step()
LOG_DEBUG
(
"DSCR %08x e"
,
(
unsigned
)
arm11
->
dscr
)
;
arm11.c:665
arm11_step()
CHECK_RETVAL
(
arm11_sc7_clear_vbw
(
arm11
)
)
;
arm11.c:684
arm11_step()
CHECK_RETVAL
(
arm11_debug_entry
(
arm11
)
)
;
arm11.c:687
arm11_step()
CHECK_RETVAL
(
target_call_event_callbacks
(
target
,
TARGET_EVENT_HALTED
)
)
;
arm11.c:696
arm11_step()
CHECK_RETVAL
(
arm11_sc7_set_vcr
(
arm11
,
arm11
->
vcr
|
1
)
)
;
arm11.c:717
arm11_assert_reset()
CHECK_RETVAL
(
arm11_poll
(
target
)
)
;
arm11.c:765
arm11_deassert_reset()
CHECK_RETVAL
(
arm11_sc7_set_vcr
(
arm11
,
arm11
->
vcr
)
)
;
arm11.c:779
arm11_deassert_reset()
LOG_DEBUG
(
"ADDR %08"
PRIx32
" SIZE %08"
PRIx32
" COUNT %08"
PRIx32
""
,
arm11.c:805
arm11_read_memory_inner()
CHECK_RETVAL
(
arm11_run_instr_no_data1
(
arm11
,
arm11.c:828
arm11_read_memory_inner()
CHECK_RETVAL
(
arm11_run_instr_data_from_core
(
arm11
,
0xEE001E15
,
&
res
,
1
)
)
;
arm11.c:833
arm11_read_memory_inner()
CHECK_RETVAL
(
arm11_run_instr_no_data1
(
arm11
,
arm11.c:846
arm11_read_memory_inner()
CHECK_RETVAL
(
arm11_run_instr_data_from_core
(
arm11
,
0xEE001E15
,
&
res
,
1
)
)
;
arm11.c:852
arm11_read_memory_inner()
CHECK_RETVAL
(
arm11_run_instr_data_from_core
(
arm11
,
instr
,
words
,
count
)
)
;
arm11.c:869
arm11_read_memory_inner()
LOG_DEBUG
(
"ADDR %08"
PRIx32
" SIZE %08"
PRIx32
" COUNT %08"
PRIx32
""
,
arm11.c:903
arm11_write_memory_inner()
LOG_DEBUG
(
"no breakpoint unit available for hardware breakpoint"
)
;
arm11.c:1060
arm11_add_breakpoint()
LOG_DEBUG
(
"only breakpoints of four bytes length supported"
)
;
arm11.c:1065
arm11_add_breakpoint()
CHECK_RETVAL
(
jtag_execute_queue
(
)
)
;
arm11.c:1165
arm11_examine()
LOG_DEBUG
(
"IDCODE %08"
PRIx32
" IMPLEMENTOR %02x DIDR %08"
PRIx32
,
arm11.c:1204
arm11_examine()
CHECK_RETVAL
(
arm11_dpm_init
(
arm11
,
didr
)
)
;
arm11.c:1211
arm11_examine()
CHECK_RETVAL
(
etm_setup
(
target
)
)
;
arm11.c:1227
arm11_examine()
JTAG_DEBUG
(
"IR <= 0x%02x SKIPPED"
,
instr
)
;
arm11_dbgtap.c:129
arm11_add_ir()
JTAG_DEBUG
(
"IR <= %s (0x%02x)"
,
arm11_ir_to_string
(
instr
)
,
instr
)
;
arm11_dbgtap.c:133
arm11_add_ir()
JTAG_DEBUG
(
"SCREG <= %d"
,
chain
)
;
arm11_dbgtap.c:201
arm11_add_debug_scan_n()
JTAG_DEBUG
(
"INST <= 0x%08x"
,
(
unsigned
)
inst
)
;
arm11_dbgtap.c:245
arm11_add_debug_inst()
CHECK_RETVAL
(
jtag_execute_queue
(
)
)
;
arm11_dbgtap.c:282
arm11_read_dscr()
JTAG_DEBUG
(
"DSCR = %08x (OLD %08x)"
,
arm11_dbgtap.c:285
arm11_read_dscr()
CHECK_RETVAL
(
jtag_execute_queue
(
)
)
;
arm11_dbgtap.c:318
arm11_write_dscr()
JTAG_DEBUG
(
"DSCR <= %08x (OLD %08x)"
,
arm11_dbgtap.c:320
arm11_write_dscr()
CHECK_RETVAL
(
jtag_execute_queue
(
)
)
;
arm11_dbgtap.c:395
arm11_run_instr_no_data()
CHECK_RETVAL
(
jtag_execute_queue
(
)
)
;
arm11_dbgtap.c:479
arm11_run_instr_data_to_core()
JTAG_DEBUG
(
"DTR ready %d n_retry %d"
,
ready
,
n_retry
)
;
arm11_dbgtap.c:481
arm11_run_instr_data_to_core()
CHECK_RETVAL
(
jtag_execute_queue
(
)
)
;
arm11_dbgtap.c:510
arm11_run_instr_data_to_core()
JTAG_DEBUG
(
"DTR _data %08x ready %d n_retry %d"
,
arm11_dbgtap.c:512
arm11_run_instr_data_to_core()
CHECK_RETVAL
(
jtag_execute_queue
(
)
)
;
arm11_dbgtap.c:755
arm11_run_instr_data_from_core()
JTAG_DEBUG
(
"DTR _data %08x ready %d n_retry %d"
,
arm11_dbgtap.c:757
arm11_run_instr_data_from_core()
JTAG_DEBUG
(
"SC7 <= c%-3d Data %08x %s"
,
arm11_dbgtap.c:881
arm11_sc7_run()
CHECK_RETVAL
(
jtag_execute_queue
(
)
)
;
arm11_dbgtap.c:889
arm11_sc7_run()
JTAG_DEBUG
(
"SC7 => Data %08x"
,
(
unsigned
)
data_in
)
;
arm11_dbgtap.c:911
arm11_sc7_run()
CHECK_RETVAL
(
arm11_run_instr_data_to_core1
(
arm11
,
0xee100e15
,
address
)
)
;
arm11_dbgtap.c:988
arm11_read_memory_word()
CHECK_RETVAL
(
arm11_run_instr_data_from_core
(
arm11
,
0xecb05e01
,
result
,
1
)
)
;
arm11_dbgtap.c:991
arm11_read_memory_word()
LOG_DEBUG
(
"out: %8.8"
PRIx32
", instruction: %i, clock: %i"
,
out
,
instruction
,
clock_arg
)
;
arm720t.c:80
arm720t_scan_cp15()
LOG_DEBUG
(
"cp15_control_reg: %8.8"
PRIx32
""
,
arm720t
->
cp15_control_reg
)
;
arm720t.c:199
arm720t_post_debug_entry()
LOG_DEBUG
(
"-"
)
;
arm7_9_common.c:62
arm7_9_clear_watchpoints()
LOG_DEBUG
(
"BPID: %"
PRIu32
" (0x%08"
TARGET_PRIxADDR
") using hw wp: %u"
,
arm7_9_common.c:95
arm7_9_assign_wp()
LOG_DEBUG
(
"SW BP using hw wp: %d"
,
arm7_9_common.c:146
arm7_9_set_software_breakpoints()
LOG_DEBUG
(
"BPID: %"
PRIu32
", Address: 0x%08"
TARGET_PRIxADDR
", Type: %d"
,
arm7_9_common.c:181
arm7_9_set_breakpoint()
LOG_DEBUG
(
"BPID: %"
PRIu32
", Address: 0x%08"
TARGET_PRIxADDR
,
arm7_9_common.c:293
arm7_9_unset_breakpoint()
LOG_DEBUG
(
"BPID: %"
PRIu32
" Releasing hw wp: %d"
,
arm7_9_common.c:303
arm7_9_unset_breakpoint()
LOG_DEBUG
(
"DBGACK already set during server startup."
)
;
arm7_9_common.c:813
arm7_9_poll()
LOG_DEBUG
(
"target->state: %s"
,
target_state_name
(
target
)
)
;
arm7_9_common.c:875
arm7_9_assert_reset()
LOG_DEBUG
(
"target->state: %s"
,
target_state_name
(
target
)
)
;
arm7_9_common.c:970
arm7_9_deassert_reset()
LOG_DEBUG
(
"target entered debug from Thumb state, changing to ARM"
)
;
arm7_9_common.c:1117
arm7_9_soft_reset_halt()
LOG_DEBUG
(
"target->state: %s"
,
arm7_9_common.c:1178
arm7_9_halt()
LOG_DEBUG
(
"target was already halted"
)
;
arm7_9_common.c:1182
arm7_9_halt()
LOG_DEBUG
(
"target entered debug from Thumb state"
)
;
arm7_9_common.c:1269
arm7_9_debug_entry()
LOG_DEBUG
(
"r0_thumb: 0x%8.8"
PRIx32
arm7_9_common.c:1274
arm7_9_debug_entry()
LOG_DEBUG
(
"target entered debug from Jazelle state"
)
;
arm7_9_common.c:1282
arm7_9_debug_entry()
LOG_DEBUG
(
"target entered debug from ARM state"
)
;
arm7_9_common.c:1287
arm7_9_debug_entry()
LOG_DEBUG
(
"target entered debug state in %s mode"
,
arm7_9_common.c:1314
arm7_9_debug_entry()
LOG_DEBUG
(
"thumb state, applying fixups"
)
;
arm7_9_common.c:1318
arm7_9_debug_entry()
LOG_DEBUG
(
"r%i: 0x%8.8"
PRIx32
""
,
i
,
context
[
i
]
)
;
arm7_9_common.c:1335
arm7_9_debug_entry()
LOG_DEBUG
(
"entered debug state at PC 0x%"
PRIx32
""
,
context
[
15
]
)
;
arm7_9_common.c:1343
arm7_9_debug_entry()
LOG_DEBUG
(
"-"
)
;
arm7_9_common.c:1391
arm7_9_full_context()
LOG_DEBUG
(
"-"
)
;
arm7_9_common.c:1507
arm7_9_restore_context()
LOG_DEBUG
(
"examining %s mode"
,
arm7_9_common.c:1526
arm7_9_restore_context()
LOG_DEBUG
(
"examining dirty reg: %s"
,
reg
->
name
)
;
arm7_9_common.c:1537
arm7_9_restore_context()
LOG_DEBUG
(
"require mode change"
)
;
arm7_9_common.c:1547
arm7_9_restore_context()
LOG_DEBUG
(
"writing register %i mode %s "
arm7_9_common.c:1581
arm7_9_restore_context()
LOG_DEBUG
(
"writing SPSR of mode %i with value 0x%8.8"
PRIx32
""
,
arm7_9_common.c:1597
arm7_9_restore_context()
LOG_DEBUG
(
"writing lower 8 bit of cpsr with value 0x%2.2x"
,
(
unsigned
)
(
tmp_cpsr
)
)
;
arm7_9_common.c:1612
arm7_9_restore_context()
LOG_DEBUG
(
"writing cpsr with value 0x%8.8"
PRIx32
,
arm7_9_common.c:1617
arm7_9_restore_context()
LOG_DEBUG
(
"writing PC with value 0x%8.8"
PRIx32
,
arm7_9_common.c:1627
arm7_9_restore_context()
LOG_DEBUG
(
"-"
)
;
arm7_9_common.c:1710
arm7_9_resume()
LOG_DEBUG
(
"unset breakpoint at 0x%8.8"
TARGET_PRIxADDR
" (id: %"
PRIu32
,
arm7_9_common.c:1733
arm7_9_resume()
LOG_DEBUG
(
"enable single-step"
)
;
arm7_9_common.c:1752
arm7_9_resume()
LOG_DEBUG
(
"disable single-step"
)
;
arm7_9_common.c:1775
arm7_9_resume()
LOG_DEBUG
(
"new PC after step: 0x%8.8"
PRIx32
,
arm7_9_common.c:1789
arm7_9_resume()
LOG_DEBUG
(
"set breakpoint at 0x%8.8"
TARGET_PRIxADDR
""
,
breakpoint
->
address
)
;
arm7_9_common.c:1792
arm7_9_resume()
LOG_DEBUG
(
"target resumed"
)
;
arm7_9_common.c:1843
arm7_9_resume()
LOG_DEBUG
(
"target stepped"
)
;
arm7_9_common.c:1978
arm7_9_step()
LOG_DEBUG
(
"address: 0x%8.8"
TARGET_PRIxADDR
", size: 0x%8.8"
PRIx32
", count: 0x%8.8"
PRIx32
""
,
arm7_9_common.c:2118
arm7_9_read_memory()
LOG_DEBUG
(
"xpsr: %8.8"
PRIx32
", spsr: %i"
,
xpsr
,
spsr
)
;
arm7tdmi.c:367
arm7tdmi_write_xpsr()
LOG_DEBUG
(
"xpsr_im: %2.2x, rot: %i, spsr: %i"
,
xpsr_im
,
rot
,
spsr
)
;
arm7tdmi.c:397
arm7tdmi_write_xpsr_im8()
LOG_DEBUG
(
"-"
)
;
arm7tdmi.c:541
arm7tdmi_branch_resume_thumb()
LOG_DEBUG
(
"cp15_control_reg: %8.8"
PRIx32
,
arm920t
->
cp15_control_reg
)
;
arm920t.c:412
arm920t_post_debug_entry()
LOG_DEBUG
(
"D FSR: 0x%8.8"
PRIx32
", D FAR: 0x%8.8"
PRIx32
arm920t.c:450
arm920t_post_debug_entry()
LOG_DEBUG
(
"D-Cache buffered, "
arm920t.c:626
arm920t_write_memory()
LOG_DEBUG
(
"D-Cache in 'write back' mode, "
arm920t.c:650
arm920t_write_memory()
LOG_DEBUG
(
"D-Cache enabled, "
arm920t.c:674
arm920t_write_memory()
LOG_DEBUG
(
"I-Cache enabled, "
arm920t.c:708
arm920t_write_memory()
LOG_DEBUG
(
"error opening cache content file"
)
;
arm920t.c:880
arm920t_handle_read_cache_command()
LOG_DEBUG
(
"error opening mmu content file"
)
;
arm920t.c:1162
arm920t_handle_read_mmu_command()
LOG_DEBUG
(
"no *NEW* debug entry (?missed one?)"
)
;
arm926ejs.c:224
arm926ejs_examine_debug_reason()
LOG_DEBUG
(
"breakpoint from EICE unit 0"
)
;
arm926ejs.c:229
arm926ejs_examine_debug_reason()
LOG_DEBUG
(
"breakpoint from EICE unit 1"
)
;
arm926ejs.c:233
arm926ejs_examine_debug_reason()
LOG_DEBUG
(
"soft breakpoint (BKPT instruction)"
)
;
arm926ejs.c:237
arm926ejs_examine_debug_reason()
LOG_DEBUG
(
"vector catch breakpoint"
)
;
arm926ejs.c:241
arm926ejs_examine_debug_reason()
LOG_DEBUG
(
"external breakpoint"
)
;
arm926ejs.c:245
arm926ejs_examine_debug_reason()
LOG_DEBUG
(
"watchpoint from EICE unit 0"
)
;
arm926ejs.c:249
arm926ejs_examine_debug_reason()
LOG_DEBUG
(
"watchpoint from EICE unit 1"
)
;
arm926ejs.c:253
arm926ejs_examine_debug_reason()
LOG_DEBUG
(
"external watchpoint"
)
;
arm926ejs.c:257
arm926ejs_examine_debug_reason()
LOG_DEBUG
(
"internal debug request"
)
;
arm926ejs.c:261
arm926ejs_examine_debug_reason()
LOG_DEBUG
(
"external debug request"
)
;
arm926ejs.c:265
arm926ejs_examine_debug_reason()
LOG_DEBUG
(
"debug re-entry from system speed access"
)
;
arm926ejs.c:269
arm926ejs_examine_debug_reason()
LOG_DEBUG
(
"cp15_control_reg: %8.8"
PRIx32
""
,
arm926ejs
->
cp15_control_reg
)
;
arm926ejs.c:429
arm926ejs_post_debug_entry()
LOG_DEBUG
(
"D FSR: 0x%8.8"
PRIx32
", D FAR: 0x%8.8"
PRIx32
", I FSR: 0x%8.8"
PRIx32
""
,
arm926ejs.c:458
arm926ejs_post_debug_entry()
LOG_DEBUG
(
"ERROR writing index"
)
;
arm946e.c:263
arm946e_invalidate_whole_dcache()
LOG_DEBUG
(
"ERROR reading dtag"
)
;
arm946e.c:271
arm946e_invalidate_whole_dcache()
LOG_DEBUG
(
"ERROR cleaning cache line"
)
;
arm946e.c:282
arm946e_invalidate_whole_dcache()
LOG_DEBUG
(
"ERROR flushing cache line"
)
;
arm946e.c:289
arm946e_invalidate_whole_dcache()
LOG_DEBUG
(
"FLUSHING I$"
)
;
arm946e.c:305
arm946e_invalidate_whole_icache()
LOG_DEBUG
(
"ERROR flushing I$"
)
;
arm946e.c:312
arm946e_invalidate_whole_icache()
LOG_DEBUG
(
"ERROR disabling cache"
)
;
arm946e.c:352
arm946e_post_debug_entry()
LOG_DEBUG
(
"ERROR enabling cache"
)
;
arm946e.c:381
arm946e_pre_restore_context()
LOG_DEBUG
(
"ERROR writing index"
)
;
arm946e.c:411
arm946e_invalidate_dcache()
LOG_DEBUG
(
"ERROR reading dtag"
)
;
arm946e.c:418
arm946e_invalidate_dcache()
LOG_DEBUG
(
"ERROR cleaning cache line"
)
;
arm946e.c:431
arm946e_invalidate_dcache()
LOG_DEBUG
(
"ERROR flushing cache line"
)
;
arm946e.c:438
arm946e_invalidate_dcache()
LOG_DEBUG
(
"ERROR writing index"
)
;
arm946e.c:468
arm946e_invalidate_icache()
LOG_DEBUG
(
"ERROR reading itag"
)
;
arm946e.c:475
arm946e_invalidate_icache()
LOG_DEBUG
(
"ERROR flushing cache line"
)
;
arm946e.c:488
arm946e_invalidate_icache()
LOG_DEBUG
(
"-"
)
;
arm946e.c:506
arm946e_write_memory()
LOG_DEBUG
(
"-"
)
;
arm946e.c:554
arm946e_read_memory()
LOG_DEBUG
(
"xpsr: %8.8"
PRIx32
", spsr: %i"
,
xpsr
,
spsr
)
;
arm9tdmi.c:441
arm9tdmi_write_xpsr()
LOG_DEBUG
(
"xpsr_im: %2.2x, rot: %i, spsr: %i"
,
xpsr_im
,
rot
,
spsr
)
;
arm9tdmi.c:476
arm9tdmi_write_xpsr_im8()
LOG_DEBUG
(
"-"
)
;
arm9tdmi.c:614
arm9tdmi_branch_resume_thumb()
LOG_DEBUG
(
"AP#0x%"
PRIx64
" probed size %u: %s"
,
ap
->
ap_num
,
size
,
arm_adi_v5.c:400
mem_ap_setup_transfer_verify_size_packing()
LOG_DEBUG
(
"probed packing: %s"
,
arm_adi_v5.c:409
mem_ap_setup_transfer_verify_size_packing()
LOG_DEBUG
(
"%s"
,
adiv5_dap_name
(
dap
)
)
;
arm_adi_v5.c:783
dap_dp_init()
LOG_DEBUG
(
"DAP: wait CDBGPWRUPACK"
)
;
arm_adi_v5.c:816
dap_dp_init()
LOG_DEBUG
(
"DAP: wait CSYSPWRUPACK"
)
;
arm_adi_v5.c:824
dap_dp_init()
LOG_DEBUG
(
"%s"
,
adiv5_dap_name
(
dap
)
)
;
arm_adi_v5.c:859
dap_dp_init_or_reconnect()
LOG_DEBUG
(
"MEM_AP CFG: large data %d, long address %d, big-endian %d"
,
arm_adi_v5.c:934
mem_ap_init()
LOG_DEBUG
(
"Enter SWD mode"
)
;
arm_adi_v5.c:954
dap_to_swd()
LOG_DEBUG
(
"Enter JTAG mode"
)
;
arm_adi_v5.c:972
dap_to_jtag()
LOG_DEBUG
(
"On ADIv6 we cannot scan all the possible AP"
)
;
arm_adi_v5.c:1111
dap_find_get_ap()
LOG_DEBUG
(
"Found %s at AP index: %d (IDR=0x%08"
PRIX32
")"
,
arm_adi_v5.c:1136
dap_find_get_ap()
LOG_DEBUG
(
"No %s found"
,
ap_type_to_description
(
type_to_find
)
)
;
arm_adi_v5.c:1146
dap_find_get_ap()
LOG_DEBUG
(
"refcount AP#0x%"
PRIx64
" get %u"
,
ap_num
,
ap
->
refcount
)
;
arm_adi_v5.c:1193
dap_get_ap()
LOG_DEBUG
(
"refcount AP#0x%"
PRIx64
" get_config %u"
,
ap_num
,
ap
->
refcount
)
;
arm_adi_v5.c:1203
dap_get_config_ap()
LOG_DEBUG
(
"refcount AP#0x%"
PRIx64
" put %u"
,
ap
->
ap_num
,
ap
->
refcount
)
;
arm_adi_v5.c:1218
dap_put_ap()
LOG_DEBUG
(
"Failed read CoreSight registers"
)
;
arm_adi_v5.c:1402
rtp_read_cs_regs()
LOG_DEBUG
(
"Failed read ROM table entry"
)
;
arm_adi_v5.c:1879
rtp_rom_loop()
LOG_DEBUG
(
"Wrong AP # 0x%"
PRIx64
,
component_base
)
;
arm_adi_v5.c:1910
rtp_rom_loop()
LOG_DEBUG
(
"Ignore error parsing CoreSight component"
)
;
arm_adi_v5.c:1923
rtp_rom_loop()
LOG_DEBUG
(
"CS lookup ended in AP # 0x%"
PRIx64
". Ignore it"
,
lookup
.
ap_num
)
;
arm_adi_v5.c:2305
dap_lookup_cs_component()
LOG_DEBUG
(
"CS lookup found at 0x%"
PRIx64
,
lookup
.
component_base
)
;
arm_adi_v5.c:2308
dap_lookup_cs_component()
LOG_DEBUG
(
"CS lookup error %d"
,
retval
)
;
arm_adi_v5.c:2313
dap_lookup_cs_component()
LOG_DEBUG
(
"CS lookup not found"
)
;
arm_adi_v5.c:2316
dap_lookup_cs_component()
LOG_DEBUG
(
"DAP: poll %x, mask 0x%08"
PRIx32
", value 0x%08"
PRIx32
,
arm_adi_v5.h:682
dap_dp_poll_register()
LOG_DEBUG
(
"DAP: poll %x timeout"
,
reg
)
;
arm_adi_v5.h:696
dap_dp_poll_register()
LOG_DEBUG
(
"Initializing all DAPs ..."
)
;
arm_dap.c:96
dap_init_all()
LOG_DEBUG
(
"DAP %s configured by default to use ADIv5 protocol"
,
jtag_tap_name
(
dap
->
tap
)
)
;
arm_dap.c:120
dap_init_all()
LOG_DEBUG
(
"DAP %s configured to use %s protocol by user cfg file"
,
jtag_tap_name
(
dap
->
tap
)
,
arm_dap.c:123
dap_init_all()
LOG_DEBUG
(
"MRC p%d, %d, r0, c%d, c%d, %d"
,
cpnum
,
arm_dpm.c:53
dpm_mrc()
LOG_DEBUG
(
"MRRC p%d, %d, r0, r1, c%d"
,
cpnum
,
arm_dpm.c:77
dpm_mrrc()
LOG_DEBUG
(
"MCR p%d, %d, r0, c%d, c%d, %d"
,
cpnum
,
arm_dpm.c:101
dpm_mcr()
LOG_DEBUG
(
"MCRR p%d, %d, r0, r1, c%d"
,
cpnum
,
arm_dpm.c:125
dpm_mcrr()
LOG_DEBUG
(
"READ: %s, %8.8x, %8.8x"
,
r
->
name
,
arm_dpm.c:201
dpm_read_reg_u64()
LOG_DEBUG
(
"READ: %s, %8.8x"
,
r
->
name
,
(
unsigned
)
value
)
;
arm_dpm.c:269
arm_dpm_read_reg()
LOG_DEBUG
(
"WRITE: %s, %8.8x, %8.8x"
,
r
->
name
,
arm_dpm.c:305
dpm_write_reg_u64()
LOG_DEBUG
(
"WRITE: %s, %8.8x"
,
r
->
name
,
(
unsigned
)
value
)
;
arm_dpm.c:354
dpm_write_reg()
LOG_DEBUG
(
"BPWP: addr %8.8"
PRIx32
", control %"
PRIx32
", number %d"
,
arm_dpm.c:904
dpm_bpwp_setup()
LOG_DEBUG
(
"using HW bkpt, not SW..."
)
;
arm_dpm.c:924
dpm_add_breakpoint()
LOG_DEBUG
(
"watchpoint values and masking not supported"
)
;
arm_dpm.c:968
dpm_watchpoint_setup()
LOG_DEBUG
(
"%s: no %d byte buffer"
,
__func__
,
(
int
)
size
)
;
arm_io.c:50
arm_code_to_working_area()
LOG_DEBUG
(
"TPIU/SWO: %s event: %s (%d) action : %s"
,
arm_tpiu_swo.c:169
arm_tpiu_swo_handle_event()
LOG_DEBUG
(
"%s: enable deferred"
,
obj
->
name
)
;
arm_tpiu_swo.c:610
handle_arm_tpiu_swo_enable()
LOG_DEBUG
(
"SWO pin frequency not set, will be autodetected by the adapter"
)
;
arm_tpiu_swo.c:639
handle_arm_tpiu_swo_enable()
LOG_DEBUG
(
"%s: running enable during init"
,
obj
->
name
)
;
arm_tpiu_swo.c:1027
handle_arm_tpiu_swo_init()
LOG_DEBUG
(
"set CPSR %#8.8x: %s mode, %s state"
,
(
unsigned
)
cpsr
,
armv4_5.c:485
arm_set_cpsr()
LOG_DEBUG
(
"changing ARM core mode to '%s'"
,
armv4_5.c:620
armv4_5_set_core_reg()
LOG_DEBUG
(
"Running algorithm"
)
;
armv4_5.c:1406
armv4_5_run_algorithm_inner()
LOG_DEBUG
(
"setting core_mode: 0x%2.2x"
,
armv4_5.c:1485
armv4_5_run_algorithm_inner()
LOG_DEBUG
(
"restoring register %s with value 0x%8.8"
PRIx32
""
,
armv4_5.c:1554
armv4_5_run_algorithm_inner()
LOG_DEBUG
(
"1st lvl desc: %8.8"
PRIx32
""
,
first_lvl_descriptor
)
;
armv4_5_mmu.c:34
armv4_5_mmu_translate_va()
LOG_DEBUG
(
"2nd lvl desc: %8.8"
PRIx32
""
,
second_lvl_descriptor
)
;
armv4_5_mmu.c:71
armv4_5_mmu_translate_va()
LOG_DEBUG
(
"%s rev %"
PRIx32
", partnum %"
PRIx32
", arch %"
PRIx32
armv7a.c:104
armv7a_read_midr()
LOG_DEBUG
(
"ttbcr %"
PRIx32
,
ttbcr
)
;
armv7a.c:137
armv7a_read_ttbcr()
LOG_DEBUG
(
"ttbr1 %s, ttbr0_mask %"
PRIx32
" ttbr1_mask %"
PRIx32
,
armv7a.c:172
armv7a_read_ttbcr()
LOG_DEBUG
(
"%s: MPIDR 0x%"
PRIx32
,
target_name
(
target
)
,
mpidr
)
;
armv7a.c:300
armv7a_read_mpidr()
LOG_DEBUG
(
"ctr %"
PRIx32
" ctr.iminline %"
PRIu32
" ctr.dminline %"
PRIu32
,
armv7a.c:390
armv7a_identify_cache()
LOG_DEBUG
(
"Number of cache levels to PoC %"
PRId32
,
cache
->
loc
)
;
armv7a.c:402
armv7a_identify_cache()
LOG_DEBUG
(
"data/unified cache index %"
PRIu32
" << %"
PRIu32
", way %"
PRIu32
" << %"
PRIu32
,
armv7a.c:430
armv7a_identify_cache()
LOG_DEBUG
(
"cacheline %"
PRIu32
" bytes %"
PRIu32
" KBytes asso %"
PRIu32
" ways"
,
armv7a.c:436
armv7a_identify_cache()
LOG_DEBUG
(
"instruction cache index %"
PRIu32
" << %"
PRIu32
", way %"
PRIu32
" << %"
PRIu32
,
armv7a.c:450
armv7a_identify_cache()
LOG_DEBUG
(
"cacheline %"
PRIu32
" bytes %"
PRIu32
" KBytes asso %"
PRIu32
" ways"
,
armv7a.c:456
armv7a_identify_cache()
LOG_DEBUG
(
"data cache is not enabled"
)
;
armv7a_cache.c:31
armv7a_l1_d_cache_sanity_check()
LOG_DEBUG
(
"instruction cache is not enabled"
)
;
armv7a_cache.c:49
armv7a_l1_i_cache_sanity_check()
LOG_DEBUG
(
"cl %"
PRId32
,
cl
)
;
armv7a_cache.c:61
armv7a_l1_d_cache_flush_level()
LOG_DEBUG
(
"l2x is not configured!"
)
;
armv7a_cache_l2x.c:33
arm7a_l2x_sanity_check()
LOG_DEBUG
(
"L1 desc[%8.8x]: %8.8"
PRIx32
,
pt_idx
<
<
20
,
first_lvl_descriptor
)
;
armv7a_mmu.c:258
armv7a_mmu_dump_table()
LOG_DEBUG
(
" "
)
;
armv7m.c:174
armv7m_restore_context()
LOG_DEBUG
(
"read %s value 0x%016"
PRIx64
,
r
->
name
,
q
)
;
armv7m.c:369
armv7m_read_core_reg()
LOG_DEBUG
(
"read %s value 0x%08"
PRIx32
,
r
->
name
,
reg_value
)
;
armv7m.c:371
armv7m_read_core_reg()
LOG_DEBUG
(
"write %s value 0x%016"
PRIx64
,
r
->
name
,
q
)
;
armv7m.c:439
armv7m_write_core_reg()
LOG_DEBUG
(
"write %s value 0x%08"
PRIx32
,
r
->
name
,
t
)
;
armv7m.c:441
armv7m_write_core_reg()
LOG_DEBUG
(
"setting core_mode: 0x%2.2x"
,
armv7m_algorithm_info
->
core_mode
)
;
armv7m.c:606
armv7m_start_algorithm()
LOG_DEBUG
(
"failed algorithm halted at 0x%"
PRIx32
", expected 0x%"
TARGET_PRIxADDR
,
armv7m.c:656
armv7m_wait_algorithm()
LOG_DEBUG
(
"restoring register %s with value 0x%8.8"
PRIx32
,
armv7m.c:704
armv7m_wait_algorithm()
LOG_DEBUG
(
"restoring core_mode: 0x%2.2x"
,
armv7m_algorithm_info
->
core_mode
)
;
armv7m.c:715
armv7m_wait_algorithm()
LOG_DEBUG
(
"Starting erase check of %d blocks, parameters@"
armv7m.c:1006
armv7m_blank_check_memory()
LOG_DEBUG
(
"Skipping over BKPT instruction"
)
;
armv7m.c:1088
armv7m_maybe_skip_bkpt_inst()
LOG_DEBUG
(
"ttbcr %"
PRIx32
,
ttbcr
)
;
armv8.c:162
armv8_read_ttbcr32()
LOG_DEBUG
(
"ttbr1 %s, ttbr0_mask %"
PRIx32
" ttbr1_mask %"
PRIx32
,
armv8.c:176
armv8_read_ttbcr32()
LOG_DEBUG
(
"ELR_EL1 not accessible in EL%u"
,
curel
)
;
armv8.c:319
armv8_read_reg()
LOG_DEBUG
(
"ELR_EL2 not accessible in EL%u"
,
curel
)
;
armv8.c:328
armv8_read_reg()
LOG_DEBUG
(
"ELR_EL3 not accessible in EL%u"
,
curel
)
;
armv8.c:337
armv8_read_reg()
LOG_DEBUG
(
"ESR_EL1 not accessible in EL%u"
,
curel
)
;
armv8.c:346
armv8_read_reg()
LOG_DEBUG
(
"ESR_EL2 not accessible in EL%u"
,
curel
)
;
armv8.c:355
armv8_read_reg()
LOG_DEBUG
(
"ESR_EL3 not accessible in EL%u"
,
curel
)
;
armv8.c:364
armv8_read_reg()
LOG_DEBUG
(
"SPSR_EL1 not accessible in EL%u"
,
curel
)
;
armv8.c:373
armv8_read_reg()
LOG_DEBUG
(
"SPSR_EL2 not accessible in EL%u"
,
curel
)
;
armv8.c:382
armv8_read_reg()
LOG_DEBUG
(
"SPSR_EL3 not accessible in EL%u"
,
curel
)
;
armv8.c:391
armv8_read_reg()
LOG_DEBUG
(
"ELR_EL1 not accessible in EL%u"
,
curel
)
;
armv8.c:480
armv8_write_reg()
LOG_DEBUG
(
"ELR_EL2 not accessible in EL%u"
,
curel
)
;
armv8.c:489
armv8_write_reg()
LOG_DEBUG
(
"ELR_EL3 not accessible in EL%u"
,
curel
)
;
armv8.c:498
armv8_write_reg()
LOG_DEBUG
(
"ESR_EL1 not accessible in EL%u"
,
curel
)
;
armv8.c:507
armv8_write_reg()
LOG_DEBUG
(
"ESR_EL2 not accessible in EL%u"
,
curel
)
;
armv8.c:516
armv8_write_reg()
LOG_DEBUG
(
"ESR_EL3 not accessible in EL%u"
,
curel
)
;
armv8.c:525
armv8_write_reg()
LOG_DEBUG
(
"SPSR_EL1 not accessible in EL%u"
,
curel
)
;
armv8.c:534
armv8_write_reg()
LOG_DEBUG
(
"SPSR_EL2 not accessible in EL%u"
,
curel
)
;
armv8.c:543
armv8_write_reg()
LOG_DEBUG
(
"SPSR_EL3 not accessible in EL%u"
,
curel
)
;
armv8.c:552
armv8_write_reg()
LOG_DEBUG
(
"set CPSR %#8.8x: %s mode, %s state"
,
(
unsigned
)
cpsr
,
armv8.c:964
armv8_set_cpsr()
LOG_DEBUG
(
"found: %s"
,
n
->
name
)
;
armv8.c:1248
armv8_handle_exception_catch_command()
LOG_DEBUG
(
"Creating Aarch64 register list for target %s"
,
target_name
(
target
)
)
;
armv8.c:1967
armv8_get_gdb_reg_list()
LOG_DEBUG
(
"Creating Aarch32 register list for target %s"
,
target_name
(
target
)
)
;
armv8.c:1994
armv8_get_gdb_reg_list()
LOG_DEBUG
(
"cl %"
PRId32
,
cl
)
;
armv8_cache.c:48
armv8_cache_d_inner_flush_level()
LOG_DEBUG
(
"ctr %"
PRIx32
" ctr.iminline %"
PRIu32
" ctr.dminline %"
PRIu32
,
armv8_cache.c:327
armv8_identify_cache()
LOG_DEBUG
(
"Number of cache levels to PoC %"
PRId32
,
cache
->
loc
)
;
armv8_cache.c:337
armv8_identify_cache()
LOG_DEBUG
(
"data/unified cache index %"
PRIu32
" << %"
PRIu32
", way %"
PRIu32
" << %"
PRIu32
,
armv8_cache.c:364
armv8_identify_cache()
LOG_DEBUG
(
"cacheline %"
PRIu32
" bytes %"
PRIu32
" KBytes asso %"
PRIu32
" ways"
,
armv8_cache.c:370
armv8_identify_cache()
LOG_DEBUG
(
"instruction cache index %"
PRIu32
" << %"
PRIu32
", way %"
PRIu32
" << %"
PRIu32
,
armv8_cache.c:384
armv8_identify_cache()
LOG_DEBUG
(
"cacheline %"
PRIu32
" bytes %"
PRIu32
" KBytes asso %"
PRIu32
" ways"
,
armv8_cache.c:390
armv8_identify_cache()
LOG_DEBUG
(
"EL %i -> %"
PRIu32
,
dpm
->
last_el
,
(
dscr
>
>
8
)
&
3
)
;
armv8_dpm.c:247
dpmv8_exec_opcode()
LOG_DEBUG
(
"A: bpwp disable, cr %08x"
,
(
unsigned
)
cr
)
;
armv8_dpm.c:472
dpmv8_bpwp_disable()
LOG_DEBUG
(
"MRC p%d, %d, r0, c%d, c%d, %d"
,
cpnum
,
armv8_dpm.c:495
dpmv8_mrc()
LOG_DEBUG
(
"MCR p%d, %d, r0, c%d, c%d, %d"
,
cpnum
,
armv8_dpm.c:520
dpmv8_mcr()
LOG_DEBUG
(
"restoring mode, cpsr = 0x%08"
PRIx32
,
cpsr
)
;
armv8_dpm.c:551
armv8_dpm_modeswitch()
LOG_DEBUG
(
"setting mode 0x%x"
,
mode
)
;
armv8_dpm.c:554
armv8_dpm_modeswitch()
LOG_DEBUG
(
"target_el = %i, last_el = %i"
,
target_el
,
dpm
->
last_el
)
;
armv8_dpm.c:589
armv8_dpm_modeswitch()
LOG_DEBUG
(
"SPSR = 0x%08"
PRIx32
,
cpsr
)
;
armv8_dpm.c:605
armv8_dpm_modeswitch()
LOG_DEBUG
(
"READ: %s, %16.8llx"
,
r
->
name
,
(
unsigned
long
long
)
value_64
)
;
armv8_dpm.c:659
dpmv8_read_reg()
LOG_DEBUG
(
"READ: %s, %8.8x"
,
r
->
name
,
(
unsigned
int
)
value_64
)
;
armv8_dpm.c:661
dpmv8_read_reg()
LOG_DEBUG
(
"READ: %s, lvalue=%16.8llx"
,
r
->
name
,
(
unsigned
long
long
)
lvalue
)
;
armv8_dpm.c:674
dpmv8_read_reg()
LOG_DEBUG
(
"READ: %s, hvalue=%16.8llx"
,
r
->
name
,
(
unsigned
long
long
)
hvalue
)
;
armv8_dpm.c:675
dpmv8_read_reg()
LOG_DEBUG
(
"Failed to read %s register"
,
r
->
name
)
;
armv8_dpm.c:680
dpmv8_read_reg()
LOG_DEBUG
(
"WRITE: %s, %16.8llx"
,
r
->
name
,
(
unsigned
long
long
)
value_64
)
;
armv8_dpm.c:702
dpmv8_write_reg()
LOG_DEBUG
(
"WRITE: %s, %8.8x"
,
r
->
name
,
(
unsigned
int
)
value_64
)
;
armv8_dpm.c:704
dpmv8_write_reg()
LOG_DEBUG
(
"WRITE: %s, lvalue=%16.8llx"
,
r
->
name
,
(
unsigned
long
long
)
lvalue
)
;
armv8_dpm.c:716
dpmv8_write_reg()
LOG_DEBUG
(
"WRITE: %s, hvalue=%16.8llx"
,
r
->
name
,
(
unsigned
long
long
)
hvalue
)
;
armv8_dpm.c:717
dpmv8_write_reg()
LOG_DEBUG
(
"Failed to write %s register"
,
r
->
name
)
;
armv8_dpm.c:722
dpmv8_write_reg()
LOG_DEBUG
(
"BPWP: addr %8.8"
PRIx32
", control %"
PRIx32
", number %d"
,
armv8_dpm.c:1157
dpmv8_bpwp_setup()
LOG_DEBUG
(
"using HW bkpt, not SW..."
)
;
armv8_dpm.c:1177
dpmv8_add_breakpoint()
LOG_DEBUG
(
"watchpoint values and masking not supported"
)
;
armv8_dpm.c:1221
dpmv8_watchpoint_setup()
LOG_DEBUG
(
"Exception taken to EL %i, DLR=0x%016"
PRIx64
" DSPSR=0x%08"
PRIx32
,
armv8_dpm.c:1327
armv8_dpm_handle_exception()
LOG_DEBUG
(
"Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)"
,
at91sam3.c:2004
efc_get_status()
LOG_DEBUG
(
"Result: 0x%08x"
,
(
(
unsigned
int
)
(
rv
)
)
)
;
at91sam3.c:2027
efc_get_result()
LOG_DEBUG
(
"Command: 0x%08x"
,
(
(
unsigned
int
)
(
v
)
)
)
;
at91sam3.c:2111
efc_start_command()
LOG_DEBUG
(
"Error Write failed"
)
;
at91sam3.c:2115
efc_start_command()
LOG_DEBUG
(
"Begin"
)
;
at91sam3.c:2181
flashd_read_uid()
LOG_DEBUG
(
"End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x"
,
at91sam3.c:2196
flashd_read_uid()
LOG_DEBUG
(
"Here"
)
;
at91sam3.c:2212
flashd_erase_entire_bank()
LOG_DEBUG
(
"Here"
)
;
at91sam3.c:2228
flashd_get_gpnvm()
LOG_DEBUG
(
"Here"
)
;
at91sam3.c:2269
flashd_clr_gpnvm()
LOG_DEBUG
(
"Failed: %d"
,
r
)
;
at91sam3.c:2283
flashd_clr_gpnvm()
LOG_DEBUG
(
"End: %d"
,
r
)
;
at91sam3.c:2287
flashd_clr_gpnvm()
LOG_DEBUG
(
"Here"
)
;
at91sam3.c:2333
flashd_get_lock_bits()
LOG_DEBUG
(
"End: %d"
,
r
)
;
at91sam3.c:2337
flashd_get_lock_bits()
LOG_DEBUG
(
"Start: %s"
,
reg
->
name
)
;
at91sam3.c:2923
sam3_get_info()
LOG_DEBUG
(
"End: %s"
,
reg
->
name
)
;
at91sam3.c:2932
sam3_get_info()
LOG_DEBUG
(
"Begin"
)
;
at91sam3.c:2957
sam3_protect_check()
LOG_DEBUG
(
"Failed: %d"
,
r
)
;
at91sam3.c:2973
sam3_protect_check()
LOG_DEBUG
(
"Done"
)
;
at91sam3.c:2979
sam3_protect_check()
LOG_DEBUG
(
"Begin"
)
;
at91sam3.c:3076
sam3_get_details()
LOG_DEBUG
(
"End"
)
;
at91sam3.c:3124
sam3_get_details()
LOG_DEBUG
(
"Begin: Bank: %u, Noise: %d"
,
bank
->
bank_number
,
noise
)
;
at91sam3.c:3134
_sam3_probe()
LOG_DEBUG
(
"Here"
)
;
at91sam3.c:3150
_sam3_probe()
LOG_DEBUG
(
"Bank = %d, nbanks = %d"
,
at91sam3.c:3189
_sam3_probe()
LOG_DEBUG
(
"Here"
)
;
at91sam3.c:3216
sam3_erase()
LOG_DEBUG
(
"Here,r=%d"
,
r
)
;
at91sam3.c:3224
sam3_erase()
LOG_DEBUG
(
"Here"
)
;
at91sam3.c:3234
sam3_erase()
LOG_DEBUG
(
"Here"
)
;
at91sam3.c:3247
sam3_protect()
LOG_DEBUG
(
"End: r=%d"
,
r
)
;
at91sam3.c:3261
sam3_protect()
LOG_DEBUG
(
"Error Read failed: read flash mode register"
)
;
at91sam3.c:3299
sam3_page_write()
LOG_DEBUG
(
"Flash Mode: 0x%08x"
,
(
(
unsigned
int
)
(
fmr
)
)
)
;
at91sam3.c:3307
sam3_page_write()
LOG_DEBUG
(
"Error Write failed: set flash mode register"
)
;
at91sam3.c:3310
sam3_page_write()
LOG_DEBUG
(
"Wr Page %u @ phys address: 0x%08x"
,
pagenum
,
(
unsigned
int
)
(
adr
)
)
;
at91sam3.c:3312
sam3_page_write()
LOG_DEBUG
(
"Offset: 0x%08x, Count: 0x%08x"
,
(
unsigned
int
)
(
offset
)
,
(
unsigned
int
)
(
count
)
)
;
at91sam3.c:3399
sam3_write()
LOG_DEBUG
(
"Page start: %d, Page End: %d"
,
(
int
)
(
page_cur
)
,
(
int
)
(
page_end
)
)
;
at91sam3.c:3400
sam3_write()
LOG_DEBUG
(
"Special case, all in one page"
)
;
at91sam3.c:3411
sam3_write()
LOG_DEBUG
(
"Not-Aligned start"
)
;
at91sam3.c:3431
sam3_write()
LOG_DEBUG
(
"Full Page Loop: cur=%d, end=%d, count = 0x%08x"
,
at91sam3.c:3460
sam3_write()
LOG_DEBUG
(
"Terminal partial page, count = 0x%08x"
,
(
unsigned
int
)
(
count
)
)
;
at91sam3.c:3475
sam3_write()
LOG_DEBUG
(
"Done!"
)
;
at91sam3.c:3486
sam3_write()
LOG_DEBUG
(
"Sam3Info, Failed %d"
,
r
)
;
at91sam3.c:3543
sam3_handle_info_command()
LOG_DEBUG
(
"Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)"
,
at91sam4.c:1454
efc_get_status()
LOG_DEBUG
(
"Result: 0x%08x"
,
(
(
unsigned
int
)
(
rv
)
)
)
;
at91sam4.c:1477
efc_get_result()
LOG_DEBUG
(
"Command: 0x%08x"
,
(
(
unsigned
int
)
(
v
)
)
)
;
at91sam4.c:1561
efc_start_command()
LOG_DEBUG
(
"Error Write failed"
)
;
at91sam4.c:1565
efc_start_command()
LOG_DEBUG
(
"Begin"
)
;
at91sam4.c:1631
flashd_read_uid()
LOG_DEBUG
(
"End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x"
,
at91sam4.c:1646
flashd_read_uid()
LOG_DEBUG
(
"Here"
)
;
at91sam4.c:1662
flashd_erase_entire_bank()
LOG_DEBUG
(
"Here"
)
;
at91sam4.c:1678
flashd_erase_pages()
LOG_DEBUG
(
"Here"
)
;
at91sam4.c:1724
flashd_get_gpnvm()
LOG_DEBUG
(
"Here"
)
;
at91sam4.c:1765
flashd_clr_gpnvm()
LOG_DEBUG
(
"Failed: %d"
,
r
)
;
at91sam4.c:1779
flashd_clr_gpnvm()
LOG_DEBUG
(
"End: %d"
,
r
)
;
at91sam4.c:1783
flashd_clr_gpnvm()
LOG_DEBUG
(
"Here"
)
;
at91sam4.c:1829
flashd_get_lock_bits()
LOG_DEBUG
(
"End: %d"
,
r
)
;
at91sam4.c:1837
flashd_get_lock_bits()
LOG_DEBUG
(
"Start: %s"
,
reg
->
name
)
;
at91sam4.c:2416
sam4_get_info()
LOG_DEBUG
(
"End: %s"
,
reg
->
name
)
;
at91sam4.c:2425
sam4_get_info()
LOG_DEBUG
(
"Begin"
)
;
at91sam4.c:2450
sam4_protect_check()
LOG_DEBUG
(
"Failed: %d"
,
r
)
;
at91sam4.c:2466
sam4_protect_check()
LOG_DEBUG
(
"Done"
)
;
at91sam4.c:2472
sam4_protect_check()
LOG_DEBUG
(
"Begin"
)
;
at91sam4.c:2562
sam4_get_details()
LOG_DEBUG
(
"SAM4 Found chip %s, CIDR 0x%08"
PRIx32
,
details
->
name
,
details
->
chipid_cidr
)
;
at91sam4.c:2580
sam4_get_details()
LOG_DEBUG
(
"End"
)
;
at91sam4.c:2612
sam4_get_details()
LOG_DEBUG
(
"Begin: Bank: %u"
,
bank
->
bank_number
)
;
at91sam4.c:2640
sam4_probe()
LOG_DEBUG
(
"Here"
)
;
at91sam4.c:2656
sam4_probe()
LOG_DEBUG
(
"SAM4 Set flash bank to "
TARGET_ADDR_FMT
" - "
at91sam4.c:2668
sam4_probe()
LOG_DEBUG
(
"Bank = %d, nbanks = %d"
,
at91sam4.c:2698
sam4_probe()
LOG_DEBUG
(
"Here"
)
;
at91sam4.c:2730
sam4_erase()
LOG_DEBUG
(
"Here,r=%d"
,
r
)
;
at91sam4.c:2738
sam4_erase()
LOG_DEBUG
(
"Here"
)
;
at91sam4.c:2748
sam4_erase()
LOG_DEBUG
(
"Here"
)
;
at91sam4.c:2779
sam4_protect()
LOG_DEBUG
(
"End: r=%d"
,
r
)
;
at91sam4.c:2793
sam4_protect()
LOG_DEBUG
(
"Flash Mode: 0x%08x"
,
(
(
unsigned
int
)
(
fmr
)
)
)
;
at91sam4.c:2836
sam4_set_wait()
LOG_DEBUG
(
"Wr Page %u @ phys address: 0x%08x"
,
pagenum
,
(
unsigned
int
)
(
adr
)
)
;
at91sam4.c:2856
sam4_page_write()
LOG_DEBUG
(
"Offset: 0x%08x, Count: 0x%08x"
,
(
unsigned
int
)
(
offset
)
,
(
unsigned
int
)
(
count
)
)
;
at91sam4.c:2947
sam4_write()
LOG_DEBUG
(
"Page start: %d, Page End: %d"
,
(
int
)
(
page_cur
)
,
(
int
)
(
page_end
)
)
;
at91sam4.c:2948
sam4_write()
LOG_DEBUG
(
"Special case, all in one page"
)
;
at91sam4.c:2959
sam4_write()
LOG_DEBUG
(
"Not-Aligned start"
)
;
at91sam4.c:2979
sam4_write()
LOG_DEBUG
(
"Full Page Loop: cur=%d, end=%d, count = 0x%08x"
,
at91sam4.c:3008
sam4_write()
LOG_DEBUG
(
"Terminal partial page, count = 0x%08x"
,
(
unsigned
int
)
(
count
)
)
;
at91sam4.c:3023
sam4_write()
LOG_DEBUG
(
"Done!"
)
;
at91sam4.c:3034
sam4_write()
LOG_DEBUG
(
"Sam4Info, Failed %d"
,
r
)
;
at91sam4.c:3091
sam4_handle_info_command()
LOG_DEBUG
(
"Erasing the whole chip"
)
;
at91sam4l.c:440
sam4l_erase()
LOG_DEBUG
(
"Erasing sectors %u through %u...\n"
,
first
,
last
)
;
at91sam4l.c:448
sam4l_erase()
LOG_DEBUG
(
"Page %u was not erased."
,
pn
)
;
at91sam4l.c:469
sam4l_erase()
LOG_DEBUG
(
"sam4l_write_page address=%08"
PRIx32
,
address
)
;
at91sam4l.c:486
sam4l_write_page()
LOG_DEBUG
(
"sam4l_write_page_partial address=%08"
PRIx32
" nb=%08"
PRIx32
,
address
,
nb
)
;
at91sam4l.c:524
sam4l_write_page_partial()
LOG_DEBUG
(
"sam4l_write offset=%08"
PRIx32
" count=%08"
PRIx32
,
offset
,
count
)
;
at91sam4l.c:554
sam4l_write()
LOG_DEBUG
(
"fmcn[%i]: %i"
,
bank
->
bank_number
,
(
int
)
(
fmcn
)
)
;
at91sam7.c:280
at91sam7_set_flash_mode()
LOG_DEBUG
(
"status[%i]: 0x%"
PRIx32
""
,
(
int
)
bank
->
bank_number
,
status
)
;
at91sam7.c:294
at91sam7_wait_status_busy()
LOG_DEBUG
(
"status[%i]: 0x%"
PRIx32
""
,
bank
->
bank_number
,
status
)
;
at91sam7.c:298
at91sam7_wait_status_busy()
LOG_DEBUG
(
"Flash command: 0x%"
PRIx32
", flash bank: %i, page number: %u"
,
at91sam7.c:322
at91sam7_flash_command()
LOG_DEBUG
(
"nvptyp: 0x%3.3x, arch: 0x%4.4x"
,
at91sam7.c:630
at91sam7_read_part_info()
LOG_DEBUG
(
"first_page: %i, last_page: %i, count %i"
,
at91sam7.c:930
at91sam7_write()
LOG_DEBUG
(
"Write flash bank:%u page number:%"
PRIu32
,
bank
->
bank_number
,
pagen
)
;
at91sam7.c:957
at91sam7_write()
LOG_DEBUG
(
"at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%"
PRIx32
,
at91sam7.c:1086
at91sam7_handle_gpnvm_command()
LOG_DEBUG
(
"AT91SAM9 NAND Device Command"
)
;
at91sam9.c:488
at91sam9_nand_device_command()
LOG_DEBUG
(
"ath79_spi_bitbang_bytes(%p, %08"
PRIx32
", %p, %d)"
,
ath79.c:266
ath79_spi_bitbang_chunk()
LOG_DEBUG
(
"max code %d => max len %d. to_xfer %d"
,
ath79.c:269
ath79_spi_bitbang_chunk()
LOG_DEBUG
(
"Assembled %d instructions, %d stores"
,
ath79.c:275
ath79_spi_bitbang_chunk()
if
(
LOG_LEVEL_IS
(
LOG_LVL_DEBUG
)
)
{
ath79.c:302
ath79_spi_bitbang_chunk()
LOG_DEBUG
(
"bitbang %02x => %02x"
,
ath79.c:304
ath79_spi_bitbang_chunk()
LOG_DEBUG
(
"%s"
,
__func__
)
;
ath79.c:352
ath79_flash_bank_command()
LOG_DEBUG
(
"%s: from sector %u to sector %u"
,
__func__
,
first
,
last
)
;
ath79.c:496
ath79_erase()
LOG_DEBUG
(
"%s: address=0x%08"
PRIx32
" len=0x%08"
PRIx32
,
ath79.c:610
ath79_write_buffer()
LOG_DEBUG
(
"%s: offset=0x%08"
PRIx32
" count=0x%08"
PRIx32
,
ath79.c:638
ath79_write()
LOG_DEBUG
(
"%s: address=0x%08"
PRIx32
" len=0x%08"
PRIx32
,
ath79.c:679
ath79_read_buffer()
LOG_DEBUG
(
"%s: offset=0x%08"
PRIx32
" count=0x%08"
PRIx32
,
ath79.c:707
ath79_read()
LOG_DEBUG
(
"Found device %s at address "
TARGET_ADDR_FMT
,
ath79.c:782
ath79_probe()
LOG_DEBUG
(
"starting flash command: 0x%08x"
,
(
unsigned
int
)
(
v
)
)
;
atsamv.c:95
samv_efc_start_command()
LOG_DEBUG
(
"write failed"
)
;
atsamv.c:98
samv_efc_start_command()
LOG_DEBUG
(
"get gpnvm failed: %d"
,
r
)
;
atsamv.c:204
samv_clear_gpnvm()
LOG_DEBUG
(
"clear gpnvm result: %d"
,
r
)
;
atsamv.c:208
samv_clear_gpnvm()
LOG_DEBUG
(
"write page %u at address 0x%08x"
,
pagenum
,
(
unsigned
int
)
addr
)
;
atsamv.c:439
samv_page_write()
LOG_DEBUG
(
"offset: 0x%08x, count: 0x%08x"
,
atsamv.c:484
samv_write()
LOG_DEBUG
(
"page start: %d, page end: %d"
,
(
int
)
(
page_cur
)
,
(
int
)
(
page_end
)
)
;
atsamv.c:486
samv_write()
LOG_DEBUG
(
"special case, all in one page"
)
;
atsamv.c:499
samv_write()
LOG_DEBUG
(
"non-aligned start"
)
;
atsamv.c:516
samv_write()
LOG_DEBUG
(
"full page loop: cur=%d, end=%d, count = 0x%08x"
,
atsamv.c:540
samv_write()
LOG_DEBUG
(
"final partial page, count = 0x%08x"
,
(
unsigned
int
)
(
count
)
)
;
atsamv.c:554
samv_write()
LOG_DEBUG
(
"write core reg %i value 0x%"
PRIx32
""
,
num
,
reg_value
)
;
avr32_ap7k.c:120
avr32_write_core_reg()
LOG_DEBUG
(
"target->state: %s"
,
avr32_ap7k.c:260
avr32_ap7k_halt()
LOG_DEBUG
(
"target was already halted"
)
;
avr32_ap7k.c:264
avr32_ap7k_halt()
LOG_DEBUG
(
"unset breakpoint at 0x%8.8"
TARGET_PRIxADDR
""
,
breakpoint
->
address
)
;
avr32_ap7k.c:340
avr32_ap7k_resume()
LOG_DEBUG
(
"target resumed at 0x%"
PRIx32
""
,
resume_pc
)
;
avr32_ap7k.c:375
avr32_ap7k_resume()
LOG_DEBUG
(
"target debug resumed at 0x%"
PRIx32
""
,
resume_pc
)
;
avr32_ap7k.c:379
avr32_ap7k_resume()
LOG_DEBUG
(
"address: 0x%8.8"
TARGET_PRIxADDR
", size: 0x%8.8"
PRIx32
", count: 0x%8.8"
PRIx32
""
,
avr32_ap7k.c:428
avr32_ap7k_read_memory()
LOG_DEBUG
(
"address: 0x%8.8"
TARGET_PRIxADDR
", size: 0x%8.8"
PRIx32
", count: 0x%8.8"
PRIx32
""
,
avr32_ap7k.c:468
avr32_ap7k_write_memory()
LOG_DEBUG
(
"poll_value = 0x%04"
PRIx32
""
,
poll_value
)
;
avrf.c:129
avr_jtagprg_chiperase()
LOG_DEBUG
(
"poll_value = 0x%04"
PRIx32
""
,
poll_value
)
;
avrf.c:190
avr_jtagprg_writeflashpage()
LOG_DEBUG
(
"%s"
,
__func__
)
;
avrf.c:218
avrf_erase()
LOG_DEBUG
(
"offset is 0x%08"
PRIx32
""
,
offset
)
;
avrf.c:256
avrf_write()
LOG_DEBUG
(
"count is %"
PRIu32
""
,
count
)
;
avrf.c:257
avrf_write()
LOG_DEBUG
(
"%s"
,
__func__
)
;
avrf.c:436
avrf_handle_mass_erase_command()
LOG_DEBUG
(
"%s"
,
__func__
)
;
avrt.c:83
avr_init_target()
LOG_DEBUG
(
"%s"
,
__func__
)
;
avrt.c:89
avr_arch_state()
LOG_DEBUG
(
"%s"
,
__func__
)
;
avrt.c:98
avr_poll()
LOG_DEBUG
(
"%s"
,
__func__
)
;
avrt.c:104
avr_halt()
LOG_DEBUG
(
"%s"
,
__func__
)
;
avrt.c:111
avr_resume()
LOG_DEBUG
(
"%s"
,
__func__
)
;
avrt.c:117
avr_step()
LOG_DEBUG
(
"%s"
,
__func__
)
;
avrt.c:125
avr_assert_reset()
LOG_DEBUG
(
"%s"
,
__func__
)
;
avrt.c:133
avr_deassert_reset()
LOG_DEBUG
(
"Ignoring empty batch."
)
;
batch.c:91
riscv_batch_run()
if
(
debug_level
<
LOG_LVL_DEBUG
)
batch.c:197
dump_field()
log_printf_lf
(
LOG_LVL_DEBUG
,
batch.c:212
dump_field()
log_printf_lf
(
LOG_LVL_DEBUG
,
batch.c:218
dump_field()
LOG_DEBUG
(
"address = %08"
PRIx32
", index = %u"
,
address
,
i
)
;
bluenrg-x.c:194
bluenrgx_erase()
LOG_DEBUG
(
"no working area for target algorithm stack"
)
;
bluenrg-x.c:291
bluenrgx_write()
LOG_DEBUG
(
"source->address = "
TARGET_ADDR_FMT
,
source
->
address
)
;
bluenrg-x.c:328
bluenrgx_write()
LOG_DEBUG
(
"source->address+ source->size = "
TARGET_ADDR_FMT
,
source
->
address
+
source
->
size
)
;
bluenrg-x.c:329
bluenrgx_write()
LOG_DEBUG
(
"write_algorithm_stack->address = "
TARGET_ADDR_FMT
,
write_algorithm_stack
->
address
)
;
bluenrg-x.c:330
bluenrgx_write()
LOG_DEBUG
(
"address = %08"
PRIx32
,
address
)
;
bluenrg-x.c:331
bluenrgx_write()
LOG_DEBUG
(
"count = %08"
PRIx32
,
count
)
;
bluenrg-x.c:332
bluenrgx_write()
LOG_TARGET_DEBUG
(
target
,
"added %s breakpoint at "
TARGET_ADDR_FMT
breakpoints.c:93
breakpoint_add_internal()
LOG_TARGET_DEBUG
(
target
,
"added %s Context breakpoint at 0x%8.8"
PRIx32
" of length 0x%8.8x, (BPID: %"
PRIu32
")"
,
breakpoints.c:143
context_breakpoint_add_internal()
LOG_TARGET_DEBUG
(
target
,
breakpoints.c:198
hybrid_breakpoint_add_internal()
LOG_TARGET_DEBUG
(
target
,
"free BPID: %"
PRIu32
" --> %d"
,
breakpoint
->
unique_id
,
retval
)
;
breakpoints.c:300
breakpoint_free()
LOG_TARGET_DEBUG
(
target
,
"Delete all breakpoints"
)
;
breakpoints.c:328
breakpoint_remove_all_internal()
LOG_TARGET_DEBUG
(
target
,
"free WPID: %d --> %d"
,
watchpoint
->
unique_id
,
retval
)
;
breakpoints.c:406
watchpoint_free()
LOG_TARGET_DEBUG
(
target
,
"added %s watchpoint at "
TARGET_ADDR_FMT
breakpoints.c:558
watchpoint_add_internal()
LOG_DEBUG
(
"Delete all watchpoints for target: %s"
,
breakpoints.c:646
watchpoint_clear_target()
LOG_TARGET_DEBUG
(
target
,
"Found hit watchpoint at "
TARGET_ADDR_FMT
" (WPID: %d)"
,
breakpoints.c:675
watchpoint_hit()
LOG_DEBUG
(
"status: 0x%x"
,
status
)
;
cfi.c:337
cfi_intel_wait_status_busy()
LOG_DEBUG
(
"status: 0x%x"
,
status
)
;
cfi.c:391
cfi_spansion_wait_status_busy()
LOG_DEBUG
(
"status: 0x%x"
,
status
)
;
cfi.c:396
cfi_spansion_wait_status_busy()
LOG_DEBUG
(
"pri: '%c%c%c', version: %c.%c"
,
pri_ext
->
pri
[
0
]
,
pri_ext
->
pri
[
1
]
,
cfi.c:449
cfi_read_intel_pri_ext()
LOG_DEBUG
(
"feature_support: 0x%"
PRIx32
", suspend_cmd_support: "
cfi.c:462
cfi_read_intel_pri_ext()
LOG_DEBUG
(
"Vcc opt: %x.%x, Vpp opt: %u.%x"
,
cfi.c:475
cfi_read_intel_pri_ext()
LOG_DEBUG
(
"protection_fields: %i, prot_reg_addr: 0x%x, "
cfi.c:497
cfi_read_intel_pri_ext()
LOG_DEBUG
(
"pri: '%c%c%c', version: %c.%c"
,
pri_ext
->
pri
[
0
]
,
pri_ext
->
pri
[
1
]
,
cfi.c:550
cfi_read_spansion_pri_ext()
LOG_DEBUG
(
"Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x"
,
cfi.c:587
cfi_read_spansion_pri_ext()
LOG_DEBUG
(
"Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, "
cfi.c:590
cfi_read_spansion_pri_ext()
LOG_DEBUG
(
"Burst Mode: 0x%x, Page Mode: 0x%x, "
,
pri_ext
->
burst_mode
,
pri_ext
->
page_mode
)
;
cfi.c:594
cfi_read_spansion_pri_ext()
LOG_DEBUG
(
"Vpp min: %u.%x, Vpp max: %u.%x"
,
cfi.c:597
cfi_read_spansion_pri_ext()
LOG_DEBUG
(
"WP# protection 0x%x"
,
pri_ext
->
top_bottom
)
;
cfi.c:601
cfi_read_spansion_pri_ext()
LOG_DEBUG
(
"pri: '%c%c%c', version: %c.%c"
,
atmel_pri_ext
.
pri
[
0
]
,
cfi.c:660
cfi_read_atmel_pri_ext()
LOG_DEBUG
(
cfi.c:680
cfi_read_atmel_pri_ext()
LOG_DEBUG
(
"Using target buffer at "
TARGET_ADDR_FMT
" and of size 0x%04"
PRIx32
,
cfi.c:1288
cfi_intel_write_block()
LOG_DEBUG
(
"Write 0x%04"
PRIx32
" bytes to flash at 0x%08"
PRIx32
,
cfi.c:1308
cfi_intel_write_block()
LOG_DEBUG
(
"Buffer Writes Not Supported"
)
;
cfi.c:2195
cfi_write_words()
LOG_DEBUG
(
"reading buffer of %i byte at 0x%8.8x"
,
cfi.c:2222
cfi_read()
LOG_DEBUG
(
"swapping reversed erase region information on cmdset 0002 device"
)
;
cfi.c:2467
cfi_fixup_0002_erase_regions()
LOG_DEBUG
(
"CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x"
,
cfi.c:2518
cfi_query_string()
LOG_DEBUG
(
"qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: "
cfi.c:2652
cfi_probe()
LOG_DEBUG
(
"size: 0x%"
PRIx32
", interface desc: %i, max buffer write size: 0x%x"
,
cfi.c:2711
cfi_probe()
LOG_DEBUG
(
cfi.c:2725
cfi_probe()
LOG_DEBUG
(
"Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x"
,
cfi.c:2767
cfi_probe()
LOG_DEBUG
(
"typ. word write timeout: %u us, typ. buf write timeout: %u us, "
cfi.c:2773
cfi_probe()
LOG_DEBUG
(
"max. word write timeout: %u us, max. buf write timeout: %u us, "
cfi.c:2778
cfi_probe()
LOG_DEBUG
(
"calculated word write timeout: %u ms, buf write timeout: %u ms, "
cfi.c:2795
cfi_probe()
LOG_DEBUG
(
"Enabled FPU detected."
)
;
chibios.c:248
chibios_update_stacking()
LOG_DEBUG
(
"Chromium-EC: Symbol \"%s\" found"
,
chromium-ec.c:93
chromium_ec_detect_rtos()
LOG_DEBUG
(
"Current task: %lx tasks_found: %d"
,
chromium-ec.c:207
chromium_ec_update_threads()
LOG_DEBUG
(
"Flushed %u packets"
,
i
)
;
cmsis_dap.c:329
cmsis_dap_flush_read()
LOG_DEBUG_IO
(
"DP write reg TARGETSEL %"
PRIx32
,
instance_id
)
;
cmsis_dap.c:575
cmsis_dap_metacmd_targetsel()
LOG_DEBUG_IO
(
"Executing %d queued transactions from FIFO index %u%s"
,
cmsis_dap.c:790
cmsis_dap_swd_write_from_queue()
LOG_DEBUG
(
"Skipping due to previous errors: %d"
,
queued_retval
)
;
cmsis_dap.c:795
cmsis_dap_swd_write_from_queue()
LOG_DEBUG_IO
(
"%s %s reg %x %"
PRIx32
,
cmsis_dap.c:825
cmsis_dap_swd_write_from_queue()
LOG_DEBUG
(
"refusing to enable sticky overrun detection"
)
;
cmsis_dap.c:845
cmsis_dap_swd_write_from_queue()
LOG_DEBUG
(
"error reading adapter response"
)
;
cmsis_dap.c:909
cmsis_dap_swd_read_process()
LOG_DEBUG
(
"CMSIS-DAP Protocol Error @ %d (wrong parity)"
,
transfer_count
)
;
cmsis_dap.c:939
cmsis_dap_swd_read_process()
LOG_DEBUG
(
"SWD ack not OK @ %d %s"
,
transfer_count
,
cmsis_dap.c:945
cmsis_dap_swd_read_process()
LOG_DEBUG_IO
(
"Received results of %d queued transactions FIFO index %u, %s mode"
,
cmsis_dap.c:960
cmsis_dap_swd_read_process()
LOG_DEBUG_IO
(
"Read result: %"
PRIx32
,
data
)
;
cmsis_dap.c:972
cmsis_dap_swd_read_process()
LOG_DEBUG_IO
(
"SWD line reset"
)
;
cmsis_dap.c:1247
cmsis_dap_swd_switch_seq()
LOG_DEBUG
(
"JTAG-to-SWD"
)
;
cmsis_dap.c:1252
cmsis_dap_swd_switch_seq()
LOG_DEBUG
(
"JTAG-to-DORMANT"
)
;
cmsis_dap.c:1257
cmsis_dap_swd_switch_seq()
LOG_DEBUG
(
"SWD-to-JTAG"
)
;
cmsis_dap.c:1262
cmsis_dap_swd_switch_seq()
LOG_DEBUG
(
"SWD-to-DORMANT"
)
;
cmsis_dap.c:1267
cmsis_dap_swd_switch_seq()
LOG_DEBUG
(
"DORMANT-to-SWD"
)
;
cmsis_dap.c:1272
cmsis_dap_swd_switch_seq()
LOG_DEBUG
(
"DORMANT-to-JTAG"
)
;
cmsis_dap.c:1277
cmsis_dap_swd_switch_seq()
LOG_DEBUG
(
"CMSIS-DAP: Packet Size = %"
PRIu16
,
pkt_sz
)
;
cmsis_dap.c:1369
cmsis_dap_init()
LOG_DEBUG
(
"CMSIS-DAP: Packet Count = %u"
,
pkt_cnt
)
;
cmsis_dap.c:1393
cmsis_dap_init()
LOG_DEBUG
(
"Allocating FIFO for %u pending packets"
,
cmsis_dap_handle
->
packet_count
)
;
cmsis_dap.c:1396
cmsis_dap_init()
tap_set_state
(
TAP_RESET
)
;
cmsis_dap.c:1510
cmsis_dap_execute_tlr_reset()
LOG_DEBUG_IO
(
"Flushing %d queued sequences (%d bytes) with %d pending scan results to capture"
,
cmsis_dap.c:1597
cmsis_dap_flush()
LOG_DEBUG_IO
(
"Copying pending_scan_result %d/%d: %d bits from byte %d -> buffer + %d bits"
,
cmsis_dap.c:1629
cmsis_dap_flush()
LOG_DEBUG_IO
(
"[at %d] %u bits, tms %s, seq offset %u, tdo buf %p, tdo offset %u"
,
cmsis_dap.c:1655
cmsis_dap_add_jtag_sequence()
LOG_DEBUG_IO
(
"START JTAG SEQ SPLIT"
)
;
cmsis_dap.c:1663
cmsis_dap_add_jtag_sequence()
LOG_DEBUG_IO
(
"Splitting long jtag sequence: %u-bit chunk starting at offset %u"
,
len
,
offset
)
;
cmsis_dap.c:1668
cmsis_dap_add_jtag_sequence()
LOG_DEBUG_IO
(
"END JTAG SEQ SPLIT"
)
;
cmsis_dap.c:1678
cmsis_dap_add_jtag_sequence()
LOG_DEBUG_IO
(
"%d bits: %02X"
,
s_len
,
*
sequence
)
;
cmsis_dap.c:1715
cmsis_dap_add_tms_sequence()
LOG_DEBUG_IO
(
"state move from %s to %s: %d clocks, %02X on tms"
,
cmsis_dap.c:1733
cmsis_dap_state_move()
tap_set_state
(
tap_get_end_state
(
)
)
;
cmsis_dap.c:1738
cmsis_dap_state_move()
LOG_DEBUG_IO
(
"%s type:%d"
,
cmd
->
cmd
.
scan
->
ir_scan
?
"IRSCAN"
:
"DRSCAN"
,
cmsis_dap.c:1745
cmsis_dap_execute_scan()
LOG_DEBUG
(
"discarding trailing empty field"
)
;
cmsis_dap.c:1752
cmsis_dap_execute_scan()
LOG_DEBUG
(
"empty scan, doing nothing"
)
;
cmsis_dap.c:1756
cmsis_dap_execute_scan()
LOG_DEBUG_IO
(
"%s%s field %u/%u %u bits"
,
cmsis_dap.c:1779
cmsis_dap_execute_scan()
LOG_DEBUG_IO
(
"Last field and have to move out of SHIFT state"
)
;
cmsis_dap.c:1787
cmsis_dap_execute_scan()
tap_set_state
(
tap_state_transition
(
tap_get_state
(
)
,
1
)
)
;
cmsis_dap.c:1809
cmsis_dap_execute_scan()
tap_set_state
(
tap_state_transition
(
tap_get_state
(
)
,
0
)
)
;
cmsis_dap.c:1819
cmsis_dap_execute_scan()
LOG_DEBUG_IO
(
"Internal field, staying in SHIFT state afterwards"
)
;
cmsis_dap.c:1821
cmsis_dap_execute_scan()
LOG_DEBUG_IO
(
"%s scan, %i bits, end in %s"
,
cmsis_dap.c:1839
cmsis_dap_execute_scan()
tap_set_state
(
path
[
i
]
)
;
cmsis_dap.c:1860
cmsis_dap_pathmove()
LOG_DEBUG_IO
(
"pathmove: %i states, end in %i"
,
cmsis_dap.c:1868
cmsis_dap_execute_pathmove()
LOG_DEBUG_IO
(
"runtest %u cycles, end in %i"
,
cmd
->
cmd
.
runtest
->
num_cycles
,
cmsis_dap.c:1904
cmsis_dap_execute_runtest()
LOG_DEBUG_IO
(
"stableclocks %u cycles"
,
cmd
->
cmd
.
runtest
->
num_cycles
)
;
cmsis_dap.c:1913
cmsis_dap_execute_stableclocks()
LOG_DEBUG_IO
(
"TMS: %u bits"
,
cmd
->
cmd
.
tms
->
num_bits
)
;
cmsis_dap.c:1919
cmsis_dap_execute_tms()
LOG_DEBUG
(
"could not open device 0x%04x:0x%04x: %s"
,
cmsis_dap_usb_bulk.c:124
cmsis_dap_usb_open()
LOG_DEBUG
(
msg
,
dev_desc
.
idVendor
,
dev_desc
.
idProduct
,
cmsis_dap_usb_bulk.c:145
cmsis_dap_usb_open()
LOG_DEBUG
(
"found product string of 0x%04x:0x%04x '%s'"
,
cmsis_dap_usb_bulk.c:169
cmsis_dap_usb_open()
LOG_DEBUG
(
"enumerating interfaces of 0x%04x:0x%04x"
,
cmsis_dap_usb_bulk.c:189
cmsis_dap_usb_open()
LOG_DEBUG
(
"could not read interface string %d for device 0x%04x:0x%04x: %s"
,
cmsis_dap_usb_bulk.c:230
cmsis_dap_usb_open()
LOG_DEBUG
(
"found interface %d string '%s'"
,
cmsis_dap_usb_bulk.c:236
cmsis_dap_usb_open()
LOG_DEBUG
(
"skipping interface %d, has only %d endpoints"
,
cmsis_dap_usb_bulk.c:249
cmsis_dap_usb_open()
LOG_DEBUG
(
"skipping interface %d, endpoint[0] is not bulk out"
,
cmsis_dap_usb_bulk.c:256
cmsis_dap_usb_open()
LOG_DEBUG
(
"skipping interface %d, endpoint[1] is not bulk in"
,
cmsis_dap_usb_bulk.c:263
cmsis_dap_usb_open()
LOG_DEBUG
(
"skipping interface %d, class %"
PRId8
cmsis_dap_usb_bulk.c:295
cmsis_dap_usb_open()
LOG_DEBUG
(
"Cannot read product string of device 0x%x:0x%x"
,
cmsis_dap_usb_hid.c:98
cmsis_dap_hid_open()
if
(
debug_level
<
LOG_LVL_DEBUG
)
command.c:143
script_debug()
LOG_DEBUG
(
"%s"
,
dbg
)
;
command.c:153
script_debug()
LOG_DEBUG
(
"command '%s' is already registered"
,
full_name
)
;
command.c:259
register_command()
LOG_DEBUG
(
"registering '%s'..."
,
full_name
)
;
command.c:271
register_command()
LOG_DEBUG
(
"delete command \"%s\""
,
name
)
;
command.c:370
unregister_commands_match()
LOG_DEBUG
(
"Command '%s' failed with error code %d"
,
command.c:528
exec_command()
LOG_DEBUG_IO
(
"%s num_fields: %u"
,
commands.c:199
jtag_build_buffer()
LOG_DEBUG
(
"fields[%u].out_value[%u]: 0x%s"
,
i
,
commands.c:211
jtag_build_buffer()
LOG_DEBUG_IO
(
"fields[%u].out_value[%u]: NULL"
,
commands.c:218
jtag_build_buffer()
LOG_DEBUG
(
"fields[%u].in_value[%u]: 0x%s"
,
commands.c:253
jtag_read_buffer()
LOG_DEBUG
(
"adding %s"
,
dir
)
;
configuration.c:33
add_script_search_dir()
LOG_DEBUG
(
"found %s"
,
full_path
)
;
configuration.c:88
find_file()
LOG_DEBUG
(
"controller initialization failed"
)
;
core.c:314
nand_probe()
LOG_DEBUG
(
"found %s (%s)"
,
nand
->
device
->
name
,
nand
->
manufacturer
->
name
)
;
core.c:372
nand_probe()
LOG_DEBUG
(
"controller initialization failed"
)
;
core.c:474
nand_probe()
LOG_DEBUG
(
"call flash_driver_read()"
)
;
core.c:107
flash_driver_read()
LOG_DEBUG
(
"addr "
TARGET_ADDR_FMT
", len 0x%08"
PRIx32
", crc 0x%08"
PRIx32
" 0x%08"
PRIx32
,
core.c:156
default_flash_verify()
LOG_DEBUG
(
"iterating over more than one flash bank."
)
;
core.c:596
flash_iterate_address_range()
LOG_DEBUG
(
"Truncate flash run size to the current flash chip."
)
;
core.c:856
flash_write_unlock_verify()
LOG_DEBUG
(
"image_read_section: section = %d, t_section_num = %d, "
core.c:939
flash_write_unlock_verify()
LOG_DEBUG
(
"jtag event: %s"
,
jtag_event_strings
[
event
]
)
;
core.c:328
jtag_call_event_callbacks()
LOG_DEBUG
(
"cur_state=%s goal_state=%s"
,
core.c:556
jtag_add_statemove()
LOG_DEBUG
(
"SRST line asserted"
)
;
core.c:636
adapter_system_reset()
LOG_DEBUG
(
"SRST line released"
)
;
core.c:640
adapter_system_reset()
LOG_DEBUG
(
"SRST line asserted"
)
;
core.c:714
legacy_jtag_add_reset()
LOG_DEBUG
(
"SRST line released"
)
;
core.c:718
legacy_jtag_add_reset()
LOG_DEBUG
(
"JTAG reset with TLR instead of TRST"
)
;
core.c:731
legacy_jtag_add_reset()
LOG_DEBUG
(
"TRST line asserted"
)
;
core.c:737
legacy_jtag_add_reset()
tap_set_state
(
TAP_RESET
)
;
core.c:738
legacy_jtag_add_reset()
LOG_DEBUG
(
"TRST line released"
)
;
core.c:742
legacy_jtag_add_reset()
LOG_DEBUG
(
"SRST line asserted"
)
;
core.c:826
jtag_add_reset()
LOG_DEBUG
(
"SRST line released"
)
;
core.c:830
jtag_add_reset()
LOG_DEBUG
(
"JTAG reset with TLR instead of TRST"
)
;
core.c:843
jtag_add_reset()
LOG_DEBUG
(
"TRST line asserted"
)
;
core.c:850
jtag_add_reset()
tap_set_state
(
TAP_RESET
)
;
core.c:851
jtag_add_reset()
LOG_DEBUG
(
"TRST line released"
)
;
core.c:855
jtag_add_reset()
LOG_DEBUG_IO
(
"JTAG %s SCAN to %s"
,
core.c:960
default_interface_jtag_execute_queue()
LOG_DEBUG_IO
(
" %ub out: %s"
,
field
->
num_bits
,
str
)
;
core.c:967
default_interface_jtag_execute_queue()
LOG_DEBUG_IO
(
" %ub in: %s"
,
field
->
num_bits
,
str
)
;
core.c:972
default_interface_jtag_execute_queue()
LOG_DEBUG_IO
(
"JTAG TLR RESET to %s"
,
core.c:978
default_interface_jtag_execute_queue()
LOG_DEBUG_IO
(
"JTAG RUNTEST %d cycles to %s"
,
core.c:982
default_interface_jtag_execute_queue()
LOG_DEBUG_IO
(
"JTAG RESET %s TRST, %s SRST"
,
core.c:991
default_interface_jtag_execute_queue()
LOG_DEBUG_IO
(
"JTAG PATHMOVE (TODO)"
)
;
core.c:997
default_interface_jtag_execute_queue()
LOG_DEBUG_IO
(
"JTAG SLEEP (TODO)"
)
;
core.c:1000
default_interface_jtag_execute_queue()
LOG_DEBUG_IO
(
"JTAG STABLECLOCKS (TODO)"
)
;
core.c:1003
default_interface_jtag_execute_queue()
LOG_DEBUG_IO
(
"JTAG TMS (TODO)"
)
;
core.c:1006
default_interface_jtag_execute_queue()
LOG_DEBUG
(
"DR scan interrogation for IDCODE/BYPASS"
)
;
core.c:1235
jtag_examine_chain()
LOG_DEBUG
(
"IR capture validation scan"
)
;
core.c:1365
jtag_validate_ircapture()
LOG_DEBUG
(
"%s: IR capture 0x%0*"
PRIx64
,
jtag_tap_name
(
tap
)
,
core.c:1422
jtag_validate_ircapture()
LOG_DEBUG
(
"Created Tap: %s @ abs position %u, "
core.c:1475
jtag_tap_init()
LOG_DEBUG
(
"Init JTAG chain"
)
;
core.c:1510
jtag_init_inner()
LOG_DEBUG
(
"Initializing with hard SRST reset"
)
;
core.c:1592
swd_init_reset()
LOG_DEBUG
(
"Initializing with hard TRST+SRST reset"
)
;
core.c:1607
jtag_init_reset()
LOG_DEBUG
(
"%s, writing cp15 ctrl: %"
PRIx32
,
cortex_a.c:193
cortex_a_mmu_modify()
LOG_DEBUG
(
"exec opcode 0x%08"
PRIx32
,
opcode
)
;
cortex_a.c:292
cortex_a_exec_opcode()
LOG_DEBUG
(
"write DCC 0x%08"
PRIx32
,
data
)
;
cortex_a.c:335
cortex_a_write_dcc()
LOG_DEBUG
(
"A: bpwp enable, vr %08x cr %08x"
,
cortex_a.c:598
cortex_a_bpwp_enable()
LOG_DEBUG
(
"A: bpwp disable, cr %08x"
,
(
unsigned
)
cr
)
;
cortex_a.c:628
cortex_a_bpwp_disable()
LOG_DEBUG
(
"Target halted"
)
;
cortex_a.c:764
cortex_a_poll()
LOG_DEBUG
(
"resume pc = 0x%08"
PRIx32
,
resume_pc
)
;
cortex_a.c:881
cortex_a_internal_restore()
LOG_DEBUG
(
"target resumed at "
TARGET_ADDR_FMT
,
address
)
;
cortex_a.c:1012
cortex_a_resume()
LOG_DEBUG
(
"target debug resumed at "
TARGET_ADDR_FMT
,
address
)
;
cortex_a.c:1016
cortex_a_resume()
LOG_DEBUG
(
"dscr = 0x%08"
PRIx32
,
cortex_a
->
cpudbg_dscr
)
;
cortex_a.c:1030
cortex_a_debug_entry()
LOG_DEBUG
(
"cp15_control_reg: %8.8"
PRIx32
,
cortex_a
->
cp15_control_reg
)
;
cortex_a.c:1114
cortex_a_post_debug_entry()
LOG_DEBUG
(
"cp15_dacr_reg: %8.8"
PRIx32
,
cortex_a.c:1141
cortex_a_post_debug_entry()
LOG_DEBUG
(
"target stepped"
)
;
cortex_a.c:1258
cortex_a_step()
LOG_DEBUG
(
" "
)
;
cortex_a.c:1267
cortex_a_restore_context()
LOG_DEBUG
(
"brp %i control 0x%0"
PRIx32
" value 0x%0"
PRIx32
,
brp_i
,
cortex_a.c:1322
cortex_a_set_breakpoint()
LOG_DEBUG
(
"brp %i control 0x%0"
PRIx32
" value 0x%0"
PRIx32
,
brp_i
,
cortex_a.c:1414
cortex_a_set_context_breakpoint()
LOG_DEBUG
(
"brp(CTX) found num: %d"
,
brp_1
)
;
cortex_a.c:1444
cortex_a_set_hybrid_breakpoint()
LOG_DEBUG
(
"brp(IVA) found num: %d"
,
brp_2
)
;
cortex_a.c:1454
cortex_a_set_hybrid_breakpoint()
LOG_DEBUG
(
"Invalid BRP number in breakpoint"
)
;
cortex_a.c:1519
cortex_a_unset_breakpoint()
LOG_DEBUG
(
"rbp %i control 0x%0"
PRIx32
" value 0x%0"
PRIx32
,
brp_i
,
cortex_a.c:1522
cortex_a_unset_breakpoint()
LOG_DEBUG
(
"Invalid BRP number in breakpoint"
)
;
cortex_a.c:1538
cortex_a_unset_breakpoint()
LOG_DEBUG
(
"rbp %i control 0x%0"
PRIx32
" value 0x%0"
PRIx32
,
brp_j
,
cortex_a.c:1541
cortex_a_unset_breakpoint()
LOG_DEBUG
(
"Invalid BRP number in breakpoint"
)
;
cortex_a.c:1563
cortex_a_unset_breakpoint()
LOG_DEBUG
(
"rbp %i control 0x%0"
PRIx32
" value 0x%0"
PRIx32
,
brp_i
,
cortex_a.c:1566
cortex_a_unset_breakpoint()
LOG_DEBUG
(
"wp %i control 0x%0"
PRIx32
" value 0x%0"
PRIx32
,
wrp_i
,
cortex_a.c:1784
cortex_a_set_watchpoint()
LOG_DEBUG
(
"Invalid WRP number in watchpoint"
)
;
cortex_a.c:1813
cortex_a_unset_watchpoint()
LOG_DEBUG
(
"wrp %i control 0x%0"
PRIx32
" value 0x%0"
PRIx32
,
wrp_i
,
cortex_a.c:1816
cortex_a_unset_watchpoint()
LOG_DEBUG
(
" "
)
;
cortex_a.c:1889
cortex_a_assert_reset()
LOG_DEBUG
(
" "
)
;
cortex_a.c:1930
cortex_a_deassert_reset()
LOG_DEBUG
(
"Writing CPU memory address 0x%"
PRIx32
" size %"
PRIu32
" count %"
PRIu32
,
cortex_a.c:2254
cortex_a_write_cpu_memory()
LOG_DEBUG
(
"Reading CPU memory address 0x%"
PRIx32
" size %"
PRIu32
" count %"
PRIu32
,
cortex_a.c:2571
cortex_a_read_cpu_memory()
LOG_DEBUG
(
"Reading memory at real address "
TARGET_ADDR_FMT
"; size %"
PRIu32
"; count %"
PRIu32
,
cortex_a.c:2720
cortex_a_read_phys_memory()
LOG_DEBUG
(
"Reading memory at address "
TARGET_ADDR_FMT
"; size %"
PRIu32
"; count %"
PRIu32
,
cortex_a.c:2737
cortex_a_read_memory()
LOG_DEBUG
(
"Writing memory to real address "
TARGET_ADDR_FMT
"; size %"
PRIu32
"; count %"
PRIu32
,
cortex_a.c:2756
cortex_a_write_phys_memory()
LOG_DEBUG
(
"Writing memory at address "
TARGET_ADDR_FMT
"; size %"
PRIu32
"; count %"
PRIu32
,
cortex_a.c:2773
cortex_a_write_memory()
LOG_DEBUG
(
"%s's dbgbase is not set, trying to detect using the ROM table"
,
cortex_a.c:2928
cortex_a_examine_first()
LOG_DEBUG
(
"Detected core %"
PRId32
" dbgbase: "
TARGET_ADDR_FMT
,
cortex_a.c:2938
cortex_a_examine_first()
LOG_DEBUG
(
"Examine %s failed"
,
"DIDR"
)
;
cortex_a.c:2950
cortex_a_examine_first()
LOG_DEBUG
(
"Examine %s failed"
,
"CPUID"
)
;
cortex_a.c:2957
cortex_a_examine_first()
LOG_DEBUG
(
"didr = 0x%08"
PRIx32
,
didr
)
;
cortex_a.c:2961
cortex_a_examine_first()
LOG_DEBUG
(
"cpuid = 0x%08"
PRIx32
,
cpuid
)
;
cortex_a.c:2962
cortex_a_examine_first()
LOG_TARGET_DEBUG
(
target
,
"DBGPRSR 0x%"
PRIx32
,
dbg_osreg
)
;
cortex_a.c:2971
cortex_a_examine_first()
LOG_TARGET_DEBUG
(
target
,
"was reset!"
)
;
cortex_a.c:2980
cortex_a_examine_first()
LOG_TARGET_DEBUG
(
target
,
"DBGOSLSR 0x%"
PRIx32
,
dbg_osreg
)
;
cortex_a.c:2987
cortex_a_examine_first()
LOG_TARGET_DEBUG
(
target
,
"OSLock set! Trying to unlock"
)
;
cortex_a.c:2993
cortex_a_examine_first()
LOG_TARGET_DEBUG
(
target
,
"has security extensions"
)
;
cortex_a.c:3017
cortex_a_examine_first()
LOG_TARGET_DEBUG
(
target
,
"has virtualization extensions"
)
;
cortex_a.c:3021
cortex_a_examine_first()
LOG_DEBUG
(
"Configured %i hw breakpoints"
,
cortex_a
->
brp_num
)
;
cortex_a.c:3054
cortex_a_examine_first()
LOG_DEBUG
(
"Configured %i hw watchpoints"
,
cortex_a
->
wrp_num
)
;
cortex_a.c:3068
cortex_a_examine_first()
LOG_TARGET_DEBUG
(
target
,
"Switching back to fast register reads"
)
;
cortex_m.c:251
cortex_m_slow_read_all_regs()
LOG_TARGET_DEBUG
(
target
,
"Register %u was not ready during fast read"
,
i
)
;
cortex_m.c:348
cortex_m_fast_read_all_regs()
LOG_TARGET_DEBUG
(
target
,
"read %u 32-bit registers"
,
wi
)
;
cortex_m.c:359
cortex_m_fast_read_all_regs()
LOG_TARGET_DEBUG
(
target
,
"NVIC_DFSR 0x%"
PRIx32
""
,
cortex_m
->
nvic_dfsr
)
;
cortex_m.c:557
cortex_m_clear_halt()
LOG_TARGET_DEBUG
(
target
,
"single step"
)
;
cortex_m.c:579
cortex_m_single_step_core()
LOG_TARGET_DEBUG
(
target
,
"DCB_DEMCR = 0x%8.8"
PRIx32
""
,
dcb_demcr
)
;
cortex_m.c:619
cortex_m_endreset_event()
LOG_TARGET_DEBUG
(
target
,
"%s SHCSR 0x%"
PRIx32
", SR 0x%"
PRIx32
cortex_m.c:800
cortex_m_examine_exception_reason()
LOG_TARGET_DEBUG
(
target
,
"Erratum 3092511: breakpoint confirmed"
)
;
cortex_m.c:823
cortex_m_erratum_check_breakpoint()
LOG_TARGET_DEBUG
(
target
,
"Erratum 3092511: breakpoint embedded in code confirmed"
)
;
cortex_m.c:836
cortex_m_erratum_check_breakpoint()
LOG_TARGET_DEBUG
(
target
,
"Erratum 3092511: breakpoint not found, proceed with resume"
)
;
cortex_m.c:839
cortex_m_erratum_check_breakpoint()
LOG_TARGET_DEBUG
(
target
,
" "
)
;
cortex_m.c:852
cortex_m_debug_entry()
LOG_TARGET_DEBUG
(
target
,
"Switched to slow register read"
)
;
cortex_m.c:881
cortex_m_debug_entry()
LOG_TARGET_DEBUG
(
target
,
"entered debug state in core mode: %s at PC 0x%"
PRIx32
cortex_m.c:922
cortex_m_debug_entry()
LOG_TARGET_DEBUG
(
target
,
"Exit from reset with dcb_dhcsr 0x%"
PRIx32
,
cortex_m.c:1000
cortex_m_poll_one()
LOG_TARGET_DEBUG
(
target
,
"postpone target event 'halted'"
)
;
cortex_m.c:1044
cortex_m_poll_one()
LOG_TARGET_DEBUG
(
curr
,
"sending postponed target event 'halted'"
)
;
cortex_m.c:1159
cortex_m_poll_smp()
LOG_TARGET_DEBUG
(
target
,
"target->state: %s"
,
target_state_name
(
target
)
)
;
cortex_m.c:1191
cortex_m_halt_one()
LOG_TARGET_DEBUG
(
target
,
"target was already halted"
)
;
cortex_m.c:1199
cortex_m_halt_one()
LOG_TARGET_DEBUG
(
target
,
"soft_reset_halt is discouraged, please use 'reset halt' instead."
)
;
cortex_m.c:1236
cortex_m_soft_reset_halt()
LOG_TARGET_DEBUG
(
target
,
"system reset-halted, DHCSR 0x%08"
PRIx32
", DFSR 0x%08"
PRIx32
,
cortex_m.c:1273
cortex_m_soft_reset_halt()
LOG_TARGET_DEBUG
(
target
,
"waiting for system reset-halt, "
cortex_m.c:1279
cortex_m_soft_reset_halt()
LOG_TARGET_DEBUG
(
target
,
"unset breakpoint at "
TARGET_ADDR_FMT
" (ID: %"
PRIu32
")"
,
cortex_m.c:1380
cortex_m_restore_one()
LOG_TARGET_DEBUG
(
curr
,
"SMP resumed at "
TARGET_ADDR_FMT
,
address
)
;
cortex_m.c:1444
cortex_m_restore_smp()
LOG_TARGET_DEBUG
(
target
,
"%sresumed at "
TARGET_ADDR_FMT
,
cortex_m.c:1470
cortex_m_resume()
LOG_TARGET_DEBUG
(
target
,
"Stepping over next instruction with interrupts disabled"
)
;
cortex_m.c:1567
cortex_m_step()
LOG_TARGET_DEBUG
(
target
,
"Starting core to serve pending interrupts"
)
;
cortex_m.c:1598
cortex_m_step()
LOG_TARGET_DEBUG
(
target
,
"Interrupt handlers didn't complete within time, "
cortex_m.c:1622
cortex_m_step()
LOG_TARGET_DEBUG
(
target
,
"target stepped dcb_dhcsr = 0x%"
PRIx32
cortex_m.c:1657
cortex_m_step()
LOG_TARGET_DEBUG
(
target
,
"target stepped dcb_dhcsr = 0x%"
PRIx32
cortex_m.c:1666
cortex_m_step()
LOG_TARGET_DEBUG
(
target
,
"target->state: %s,%s examined"
,
cortex_m.c:1838
cortex_m_assert_reset()
LOG_TARGET_DEBUG
(
target
,
"Trying to re-examine under reset"
)
;
cortex_m.c:1872
cortex_m_assert_reset()
LOG_TARGET_DEBUG
(
target
,
"Using Cortex-M %s"
,
(
reset_config
==
CORTEX_M_RESET_SYSRESETREQ
)
cortex_m.c:1957
cortex_m_assert_reset()
LOG_TARGET_DEBUG
(
target
,
"Ignoring AP write error right after reset"
)
;
cortex_m.c:1970
cortex_m_assert_reset()
LOG_TARGET_DEBUG
(
target
,
"target->state: %s,%s examined"
,
cortex_m.c:2000
cortex_m_deassert_reset()
LOG_TARGET_DEBUG
(
target
,
"fpc_num %i fpcr_value 0x%"
PRIx32
""
,
cortex_m.c:2062
cortex_m_set_breakpoint()
LOG_TARGET_DEBUG
(
target
,
"FPB wasn't enabled, do it now"
)
;
cortex_m.c:2066
cortex_m_set_breakpoint()
LOG_TARGET_DEBUG
(
target
,
"BPID: %"
PRIu32
", Type: %d, Address: "
TARGET_ADDR_FMT
" Length: %d (n=%u)"
,
cortex_m.c:2098
cortex_m_set_breakpoint()
LOG_TARGET_DEBUG
(
target
,
"BPID: %"
PRIu32
", Type: %d, Address: "
TARGET_ADDR_FMT
" Length: %d (n=%u)"
,
cortex_m.c:2119
cortex_m_unset_breakpoint()
LOG_TARGET_DEBUG
(
target
,
"Invalid FP Comparator number in breakpoint"
)
;
cortex_m.c:2129
cortex_m_unset_breakpoint()
LOG_TARGET_DEBUG
(
target
,
"Using a two byte breakpoint for 32bit Thumb-2 request"
)
;
cortex_m.c:2152
cortex_m_add_breakpoint()
LOG_TARGET_DEBUG
(
target
,
"Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x"
,
cortex_m.c:2248
cortex_m_set_watchpoint()
LOG_TARGET_DEBUG
(
target
,
"Watchpoint (ID %d) DWT%u address: 0x%08x clear"
,
cortex_m.c:2269
cortex_m_unset_watchpoint()
LOG_TARGET_DEBUG
(
target
,
"Invalid DWT Comparator number in watchpoint"
)
;
cortex_m.c:2274
cortex_m_unset_watchpoint()
LOG_TARGET_DEBUG
(
target
,
"no comparators?"
)
;
cortex_m.c:2294
cortex_m_add_watchpoint()
LOG_TARGET_DEBUG
(
target
,
"watchpoint value masks not supported"
)
;
cortex_m.c:2306
cortex_m_add_watchpoint()
LOG_TARGET_DEBUG
(
target
,
"unsupported watchpoint length"
)
;
cortex_m.c:2318
cortex_m_add_watchpoint()
LOG_TARGET_DEBUG
(
target
,
"watchpoint address is unaligned"
)
;
cortex_m.c:2322
cortex_m_add_watchpoint()
LOG_TARGET_DEBUG
(
target
,
"dwt_comp_available: %d"
,
cortex_m
->
dwt_comp_available
)
;
cortex_m.c:2327
cortex_m_add_watchpoint()
LOG_TARGET_DEBUG
(
target
,
"dwt_comp_available: %d"
,
cortex_m
->
dwt_comp_available
)
;
cortex_m.c:2346
cortex_m_remove_watchpoint()
LOG_TARGET_DEBUG
(
target
,
"DWT_CTRL: 0x%"
PRIx32
,
dwtcr
)
;
cortex_m.c:2614
cortex_m_dwt_setup()
LOG_TARGET_DEBUG
(
target
,
"no DWT"
)
;
cortex_m.c:2616
cortex_m_dwt_setup()
LOG_TARGET_DEBUG
(
target
,
"DWT_DEVARCH: 0x%"
PRIx32
,
cm
->
dwt_devarch
)
;
cortex_m.c:2621
cortex_m_dwt_setup()
LOG_TARGET_DEBUG
(
target
,
"DWT dwtcr 0x%"
PRIx32
", comp %d, watch%s"
,
cortex_m.c:2668
cortex_m_dwt_setup()
LOG_TARGET_DEBUG
(
target
,
"cpuid: 0x%8.8"
PRIx32
""
,
cpuid
)
;
cortex_m.c:2820
cortex_m_examine()
LOG_TARGET_DEBUG
(
target
,
"%s floating point feature FPv4_SP found"
,
cortex_m.c:2827
cortex_m_examine()
LOG_TARGET_DEBUG
(
target
,
"%s floating point feature FPv5_DP + MVE-F found"
,
cortex_m.c:2838
cortex_m_examine()
LOG_TARGET_DEBUG
(
target
,
"%s floating point feature FPv5_DP found"
,
cortex_m.c:2842
cortex_m_examine()
LOG_TARGET_DEBUG
(
target
,
"%s floating point feature FPv5_SP found"
,
cortex_m.c:2847
cortex_m_examine()
LOG_TARGET_DEBUG
(
target
,
"%s floating point feature MVE-I found"
,
cortex_m.c:2851
cortex_m_examine()
LOG_TARGET_DEBUG
(
target
,
"reset happened some time ago, ignore"
)
;
cortex_m.c:2889
cortex_m_examine()
LOG_TARGET_DEBUG
(
target
,
"FPB fpcr 0x%"
PRIx32
", numcode %i, numlit %i"
,
cortex_m.c:2936
cortex_m_examine()
LOG_TARGET_DEBUG
(
target
,
"data 0x%x ctrl 0x%x"
,
*
value
,
*
ctrl
)
;
cortex_m.c:2969
cortex_m_dcc_read()
LOG_DEBUG
(
"%s"
,
__func__
)
;
dsp563xx.c:404
dsp563xx_get_core_reg()
LOG_DEBUG
(
"%s"
,
__func__
)
;
dsp563xx.c:414
dsp563xx_set_core_reg()
LOG_DEBUG
(
"%s conditional branch not supported yet (0x%"
PRIx32
" 0x%"
PRIx32
" 0x%"
PRIx32
")"
,
dsp563xx.c:571
dsp563xx_reg_pc_read()
LOG_DEBUG
(
"%s"
,
__func__
)
;
dsp563xx.c:900
dsp563xx_init_target()
LOG_DEBUG
(
"%s"
,
__func__
)
;
dsp563xx.c:940
dsp563xx_arch_state()
LOG_DEBUG
(
"target->state: %s (%"
PRIx32
")"
,
target_state_name
(
target
)
,
once_status
)
;
dsp563xx.c:1070
dsp563xx_poll()
LOG_DEBUG
(
"%s"
,
__func__
)
;
dsp563xx.c:1098
dsp563xx_halt()
LOG_DEBUG
(
"target was already halted"
)
;
dsp563xx.c:1101
dsp563xx_halt()
LOG_DEBUG
(
"%s %08X %08X"
,
__func__
,
current
,
(
unsigned
)
address
)
;
dsp563xx.c:1138
dsp563xx_resume()
LOG_DEBUG
(
"target was not halted"
)
;
dsp563xx.c:1186
dsp563xx_step_ex()
LOG_DEBUG
(
"%s %08X %08X"
,
__func__
,
current
,
(
unsigned
)
address
)
;
dsp563xx.c:1202
dsp563xx_step_ex()
LOG_DEBUG
(
"fetch: %08X"
,
(
unsigned
)
dr_in
&
0x00ffffff
)
;
dsp563xx.c:1263
dsp563xx_step_ex()
LOG_DEBUG
(
"decode: %08X"
,
(
unsigned
)
dr_in
&
0x00ffffff
)
;
dsp563xx.c:1267
dsp563xx_step_ex()
LOG_DEBUG
(
"execute: %08X"
,
(
unsigned
)
dr_in
&
0x00ffffff
)
;
dsp563xx.c:1271
dsp563xx_step_ex()
LOG_DEBUG
(
"%s"
,
__func__
)
;
dsp563xx.c:1341
dsp563xx_assert_reset()
LOG_DEBUG
(
"%s"
,
__func__
)
;
dsp563xx.c:1369
dsp563xx_deassert_reset()
LOG_DEBUG
(
dsp563xx.c:1519
dsp563xx_read_memory_core()
LOG_DEBUG
(
"size is not aligned to 4 byte"
)
;
dsp563xx.c:1614
dsp563xx_read_memory()
LOG_DEBUG
(
dsp563xx.c:1700
dsp563xx_write_memory_core()
LOG_DEBUG
(
"size is not aligned to 4 byte"
)
;
dsp563xx.c:1788
dsp563xx_write_memory()
LOG_DEBUG
(
"debug request: %02X"
,
ir_in
)
;
dsp563xx_once.c:135
dsp563xx_once_request_debug()
LOG_DEBUG
(
"enable once: %02X"
,
ir_in
)
;
dsp563xx_once.c:156
dsp563xx_once_request_debug()
LOG_DEBUG
(
"error"
)
;
dsp563xx_once.c:159
dsp563xx_once_request_debug()
LOG_DEBUG
(
"Data read (%d bits): 0x%04X"
,
len
,
*
d_out
)
;
dsp5680xx.c:97
dsp5680xx_drscan()
LOG_DEBUG
(
"Data read was discarded."
)
;
dsp5680xx.c:99
dsp5680xx_drscan()
LOG_DEBUG
(
"Data read (%d bits): 0x%04X"
,
num_bits
,
*
data_read
)
;
dsp5680xx.c:177
jtag_data_read()
LOG_DEBUG
(
"Reg. data: 0x%02X."
,
*
data_read
)
;
dsp5680xx.c:529
dsp5680xx_read_core_reg()
LOG_DEBUG
(
"EOnCE successfully entered debug mode."
)
;
dsp5680xx.c:676
eonce_enter_debug_mode_without_reset()
LOG_DEBUG
(
"EOnCE successfully entered debug mode."
)
;
dsp5680xx.c:816
eonce_enter_debug_mode()
LOG_DEBUG
(
"target initiated!"
)
;
dsp5680xx.c:872
dsp5680xx_init_target()
LOG_DEBUG
(
"EOnCE status: 0x%02X."
,
eonce_status
)
;
dsp5680xx.c:1031
dsp5680xx_resume()
LOG_DEBUG
(
"%s:Data read from 0x%06"
PRIX32
": 0x%02X%02X"
,
__func__
,
address
,
dsp5680xx.c:1109
dsp5680xx_read_16_single()
LOG_DEBUG
(
"HFM CLK divisor contained incorrect value (0x%02X)."
,
dsp5680xx.c:1731
set_fm_ck_div()
LOG_DEBUG
dsp5680xx.c:1735
set_fm_ck_div()
LOG_DEBUG
(
"HFM CLK divisor set to 0x%02x."
,
i
[
0
]
&
0x7f
)
;
dsp5680xx.c:1756
set_fm_ck_div()
LOG_DEBUG
(
"%s not implemented"
,
__func__
)
;
dsp5680xx_flash.c:157
dsp5680xx_probe()
if
(
debug_level
>=
LOG_LVL_DEBUG
)
{
eCos.c:542
ecos_check_app_info()
LOG_DEBUG
(
"eCos: %s 0x%016"
PRIX64
" %s"
,
eCos.c:544
ecos_check_app_info()
LOG_DEBUG
(
"status: 0x%"
PRIx32
""
,
status
)
;
efm32.c:433
efm32x_wait_status()
LOG_DEBUG
(
"erasing flash page at 0x%08"
PRIx32
,
addr
)
;
efm32.c:465
efm32x_erase_page()
LOG_DEBUG
(
"status 0x%"
PRIx32
,
status
)
;
efm32.c:480
efm32x_erase_page()
LOG_DEBUG
(
"status 0x%"
PRIx32
,
status
)
;
efm32.c:923
efm32x_write_word()
LOG_DEBUG
(
"status: 0x%"
PRIx32
""
,
status
)
;
em357.c:118
em357_wait_status_busy()
LOG_DEBUG
(
"%i: 0x%8.8"
PRIx32
""
,
ice_reg
->
addr
,
value
)
;
embeddedice.c:505
embeddedice_write_reg()
LOG_DEBUG
(
"%s"
,
__func__
)
;
eneispif.c:51
eneispif_flash_bank_command()
LOG_DEBUG
(
"Read address "
TARGET_ADDR_FMT
" = 0x%"
PRIx32
,
eneispif.c:85
eneispif_read_reg()
LOG_DEBUG
(
"Write address "
TARGET_ADDR_FMT
" = 0x%"
PRIx32
,
eneispif.c:95
eneispif_write_reg()
LOG_DEBUG
(
"%s: from sector %u to sector %u"
,
__func__
,
first
,
last
)
;
eneispif.c:166
eneispif_erase()
LOG_DEBUG
(
"bank->size=0x%x offset=0x%08"
PRIx32
" count=0x%08"
PRIx32
,
bank
->
size
,
offset
,
eneispif.c:219
eneispif_write()
LOG_DEBUG
(
"ISPCFG = (0x%08"
PRIx32
")"
,
conf
)
;
eneispif.c:305
eneispif_read_flash_id()
LOG_DEBUG
(
"ISPDAT = (0x%08"
PRIx32
")"
,
value
)
;
eneispif.c:321
eneispif_read_flash_id()
LOG_DEBUG
(
"-"
)
;
esirisc.c:163
esirisc_disable_interrupts()
LOG_DEBUG
(
"-"
)
;
esirisc.c:215
esirisc_save_interrupts()
LOG_DEBUG
(
"-"
)
;
esirisc.c:232
esirisc_restore_interrupts()
LOG_DEBUG
(
"-"
)
;
esirisc.c:268
esirisc_restore_hwdc()
LOG_DEBUG
(
"-"
)
;
esirisc.c:284
esirisc_save_context()
LOG_DEBUG
(
"-"
)
;
esirisc.c:301
esirisc_restore_context()
LOG_DEBUG
(
"-"
)
;
esirisc.c:319
esirisc_flush_caches()
LOG_DEBUG
(
"-"
)
;
esirisc.c:340
esirisc_wait_debug_active()
LOG_DEBUG
(
"-"
)
;
esirisc.c:362
esirisc_read_memory()
LOG_DEBUG
(
"-"
)
;
esirisc.c:411
esirisc_write_memory()
LOG_DEBUG
(
"-"
)
;
esirisc.c:463
esirisc_next_breakpoint()
LOG_DEBUG
(
"-"
)
;
esirisc.c:480
esirisc_add_breakpoint()
LOG_DEBUG
(
"-"
)
;
esirisc.c:531
esirisc_add_breakpoints()
LOG_DEBUG
(
"-"
)
;
esirisc.c:551
esirisc_remove_breakpoint()
LOG_DEBUG
(
"-"
)
;
esirisc.c:579
esirisc_remove_breakpoints()
LOG_DEBUG
(
"-"
)
;
esirisc.c:599
esirisc_next_watchpoint()
LOG_DEBUG
(
"-"
)
;
esirisc.c:616
esirisc_add_watchpoint()
LOG_DEBUG
(
"-"
)
;
esirisc.c:715
esirisc_add_watchpoints()
LOG_DEBUG
(
"-"
)
;
esirisc.c:735
esirisc_remove_watchpoint()
LOG_DEBUG
(
"-"
)
;
esirisc.c:763
esirisc_remove_watchpoints()
LOG_DEBUG
(
"-"
)
;
esirisc.c:782
esirisc_halt()
LOG_DEBUG
(
"-"
)
;
esirisc.c:805
esirisc_disable_step()
LOG_DEBUG
(
"-"
)
;
esirisc.c:831
esirisc_enable_step()
LOG_DEBUG
(
"-"
)
;
esirisc.c:858
esirisc_resume_or_step()
LOG_DEBUG
(
"-"
)
;
esirisc.c:924
esirisc_resume()
LOG_DEBUG
(
"-"
)
;
esirisc.c:933
esirisc_step()
LOG_DEBUG
(
"-"
)
;
esirisc.c:945
esirisc_debug_step()
LOG_DEBUG
(
"-"
)
;
esirisc.c:974
esirisc_debug_reset()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1003
esirisc_debug_enable()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1037
esirisc_debug_entry()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1125
esirisc_assert_reset()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1156
esirisc_reset_entry()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1189
esirisc_deassert_reset()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1255
esirisc_get_gdb_arch()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1275
esirisc_get_gdb_reg_list()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1305
esirisc_read_reg()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1328
esirisc_write_reg()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1350
esirisc_read_csr()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1373
esirisc_write_csr()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1393
esirisc_get_reg()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1408
esirisc_set_reg()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1432
esirisc_build_reg_cache()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1522
esirisc_identify()
LOG_DEBUG
(
"-"
)
;
esirisc.c:1632
esirisc_examine()
LOG_DEBUG
(
"TIMING0: 0x%"
PRIx32
,
value
)
;
esirisc_flash.c:421
esirisc_flash_init()
LOG_DEBUG
(
"TIMING1: 0x%"
PRIx32
,
value
)
;
esirisc_flash.c:426
esirisc_flash_init()
LOG_DEBUG
(
"TIMING2: 0x%"
PRIx32
,
value
)
;
esirisc_flash.c:433
esirisc_flash_init()
LOG_DEBUG
(
"address: 0x%"
PRIx32
", data: 0x%"
PRIx8
,
address
,
*
data
)
;
esirisc_jtag.c:260
esirisc_jtag_read_byte()
LOG_DEBUG
(
"address: 0x%"
PRIx32
", data: 0x%"
PRIx16
,
address
,
*
data
)
;
esirisc_jtag.c:288
esirisc_jtag_read_hword()
LOG_DEBUG
(
"address: 0x%"
PRIx32
", data: 0x%"
PRIx32
,
address
,
*
data
)
;
esirisc_jtag.c:316
esirisc_jtag_read_word()
LOG_DEBUG
(
"address: 0x%"
PRIx32
", data: 0x%"
PRIx8
,
address
,
data
)
;
esirisc_jtag.c:326
esirisc_jtag_write_byte()
LOG_DEBUG
(
"address: 0x%"
PRIx32
", data: 0x%"
PRIx16
,
address
,
data
)
;
esirisc_jtag.c:346
esirisc_jtag_write_hword()
LOG_DEBUG
(
"address: 0x%"
PRIx32
", data: 0x%"
PRIx32
,
address
,
data
)
;
esirisc_jtag.c:367
esirisc_jtag_write_word()
LOG_DEBUG
(
"register: 0x%"
PRIx8
", data: 0x%"
PRIx32
,
reg
,
*
data
)
;
esirisc_jtag.c:404
esirisc_jtag_read_reg()
LOG_DEBUG
(
"register: 0x%"
PRIx8
", data: 0x%"
PRIx32
,
reg
,
data
)
;
esirisc_jtag.c:414
esirisc_jtag_write_reg()
LOG_DEBUG
(
"bank: 0x%"
PRIx8
", csr: 0x%"
PRIx8
", data: 0x%"
PRIx32
,
bank
,
csr
,
*
data
)
;
esirisc_jtag.c:452
esirisc_jtag_read_csr()
LOG_DEBUG
(
"bank: 0x%"
PRIx8
", csr: 0x%"
PRIx8
", data: 0x%"
PRIx32
,
bank
,
csr
,
data
)
;
esirisc_jtag.c:462
esirisc_jtag_write_csr()
LOG_TARGET_DEBUG
(
target
,
"Read debug stubs info %"
PRIx32
" / %d"
,
dbg_stubs
->
base
,
dbg_stubs
->
entries_count
)
;
esp.c:33
esp_dbgstubs_table_read()
LOG_DEBUG
(
"Check dbg stub %d - %x"
,
i
,
dbg_stubs
->
entries
[
i
]
)
;
esp.c:77
esp_dbgstubs_table_read()
LOG_DEBUG
(
"New dbg stub %d at %x"
,
dbg_stubs
->
entries_count
,
dbg_stubs
->
entries
[
i
]
)
;
esp.c:79
esp_dbgstubs_table_read()
LOG_DEBUG
(
"start"
)
;
esp32.c:102
esp32_soc_reset()
LOG_DEBUG
(
"Target not halted before SoC reset, trying to halt it first"
)
;
esp32.c:105
esp32_soc_reset()
LOG_DEBUG
(
"Couldn't halt target before SoC reset, trying to do reset-halt"
)
;
esp32.c:109
esp32_soc_reset()
LOG_TARGET_DEBUG
(
head
->
target
,
"Unstall CPUs before SW reset!"
)
;
esp32.c:145
esp32_soc_reset()
LOG_DEBUG
(
"Loading stub code into RTC RAM"
)
;
esp32.c:158
esp32_soc_reset()
LOG_DEBUG
(
"Resuming the target"
)
;
esp32.c:175
esp32_soc_reset()
LOG_DEBUG
(
"resume done, waiting for the target to come alive"
)
;
esp32.c:184
esp32_soc_reset()
LOG_DEBUG
(
"halting the target"
)
;
esp32.c:202
esp32_soc_reset()
LOG_DEBUG
(
"restoring RTC_SLOW_MEM"
)
;
esp32.c:206
esp32_soc_reset()
LOG_DEBUG
(
"apptrace: Failed to create socket (%d, %d, %d) (%s)"
,
esp32_apptrace.c:222
esp32_apptrace_tcp_dest_init()
LOG_DEBUG
(
"esp32_apptrace_ready_block_put"
)
;
esp32_apptrace.c:353
esp32_apptrace_ready_block_put()
int64_t
timeout
=
timeval_ms
(
)
+
(
LOG_LEVEL_IS
(
LOG_LVL_DEBUG
)
?
70000
:
5000
)
;
esp32_apptrace.c:386
esp32_apptrace_wait_tracing_finished()
LOG_DEBUG
(
"Halt all targets!"
)
;
esp32_apptrace.c:667
esp32_apptrace_safe_halt_targets()
LOG_DEBUG
(
"Read current block statuses"
)
;
esp32_apptrace.c:688
esp32_apptrace_safe_halt_targets()
LOG_DEBUG
(
"Resume targets"
)
;
esp32_apptrace.c:792
esp32_apptrace_connect_targets()
LOG_TARGET_DEBUG
(
ctx
->
cpus
[
i
]
,
"Block %"
PRId32
", len %"
PRId32
" bytes on fired"
,
esp32_apptrace.c:864
esp32_apptrace_get_data_info()
LOG_DEBUG
(
"Got block %"
PRId32
" bytes [%x %x...%x %x]"
,
data_len
,
data
[
12
]
,
data
[
13
]
,
esp32_apptrace.c:881
esp32_apptrace_process_data()
LOG_DEBUG
(
"Got block %"
PRId32
" bytes"
,
block
->
data_len
)
;
esp32_apptrace.c:922
esp32_apptrace_handle_trace_block()
LOG_DEBUG
(
"Process usr block %"
PRId32
"/%"
PRId32
,
processed
,
block
->
data_len
)
;
esp32_apptrace.c:925
esp32_apptrace_handle_trace_block()
LOG_TARGET_DEBUG
(
ctx
->
cpus
[
i
]
,
"Ack empty block %"
PRId32
"!"
,
max_block_id
)
;
esp32_apptrace.c:1069
esp32_apptrace_poll()
LOG_TARGET_DEBUG
(
ctx
->
cpus
[
i
]
,
"Ack block %"
PRId32
,
ctx
->
last_blk_id
)
;
esp32_apptrace.c:1173
esp32_apptrace_poll()
const
float
stop_tmo
=
LOG_LEVEL_IS
(
LOG_LVL_DEBUG
)
?
30.0
:
0.5
;
esp32_apptrace.c:1425
esp32_sysview_stop()
LOG_DEBUG
(
"sysview: evt %d len %d plen %d dlen %d"
,
esp32_sysview.c:321
esp_sysview_parse_packet()
LOG_DEBUG
(
"sysview: Redirect %d bytes of event %d to dest %d"
,
wr_len
,
event_id
,
i
)
;
esp32_sysview.c:421
esp32_sysview_process_packet()
LOG_DEBUG
(
"sysview: Read from target %d bytes [%x %x %x %x]"
,
esp32_sysview.c:449
esp32_sysview_process_data()
LOG_DEBUG
(
"sysview: Process %d sync bytes"
,
SYSVIEW_SYNC_LEN
)
;
esp32_sysview.c:469
esp32_sysview_process_data()
LOG_DEBUG
(
"sysview: Process packet: core %d, %d id, %d bytes [%x %x %x %x]"
,
esp32_sysview.c:513
esp32_sysview_process_data()
LOG_TARGET_DEBUG
(
target
,
"begin"
)
;
esp32s2.c:88
esp32s2_deassert_reset()
LOG_TARGET_DEBUG
(
target
,
"begin"
)
;
esp32s2.c:106
esp32s2_soft_reset_halt()
LOG_TARGET_DEBUG
(
target
,
"begin"
)
;
esp32s2.c:134
esp32s2_stall_set()
LOG_DEBUG
(
"start"
)
;
esp32s2.c:183
esp32s2_soc_reset()
LOG_TARGET_DEBUG
(
target
,
"Target not halted before SoC reset, trying to halt it first"
)
;
esp32s2.c:187
esp32s2_soc_reset()
LOG_TARGET_DEBUG
(
target
,
"Couldn't halt target before SoC reset, trying to do reset-halt"
)
;
esp32s2.c:191
esp32s2_soc_reset()
LOG_DEBUG
(
"start"
)
;
esp32s3.c:99
esp32s3_soc_reset()
LOG_DEBUG
(
"Target not halted before SoC reset, trying to halt it first"
)
;
esp32s3.c:102
esp32s3_soc_reset()
LOG_DEBUG
(
"Couldn't halt target before SoC reset, trying to do reset-halt"
)
;
esp32s3.c:106
esp32s3_soc_reset()
LOG_TARGET_DEBUG
(
head
->
target
,
"Unstall CPUs before SW reset!"
)
;
esp32s3.c:142
esp32s3_soc_reset()
LOG_DEBUG
(
"Loading stub code into RTC RAM"
)
;
esp32s3.c:155
esp32s3_soc_reset()
LOG_DEBUG
(
"Resuming the target"
)
;
esp32s3.c:175
esp32s3_soc_reset()
LOG_DEBUG
(
"resume done, waiting for the target to come alive"
)
;
esp32s3.c:184
esp32s3_soc_reset()
LOG_DEBUG
(
"halting the target"
)
;
esp32s3.c:203
esp32s3_soc_reset()
LOG_DEBUG
(
"restoring RTC_SLOW_MEM"
)
;
esp32s3.c:207
esp32s3_soc_reset()
LOG_DEBUG
(
"Algorithm start @ "
TARGET_ADDR_FMT
", stack %d bytes @ "
TARGET_ADDR_FMT
,
esp_algorithm.c:95
esp_algorithm_run_image()
LOG_DEBUG
(
"Wait algorithm completion"
)
;
esp_algorithm.c:117
esp_algorithm_run_image()
LOG_DEBUG
(
"Got algorithm RC 0x%"
PRIx32
,
run
->
ret_code
)
;
esp_algorithm.c:136
esp_algorithm_run_image()
LOG_DEBUG
(
"Algorithm start @ "
TARGET_ADDR_FMT
", stack %d bytes @ "
TARGET_ADDR_FMT
,
esp_algorithm.c:165
esp_algorithm_run_debug_stub()
LOG_DEBUG
(
"Wait algorithm completion"
)
;
esp_algorithm.c:180
esp_algorithm_run_debug_stub()
LOG_DEBUG
(
"Got algorithm RC 0x%"
PRIx32
,
run
->
ret_code
)
;
esp_algorithm.c:195
esp_algorithm_run_debug_stub()
LOG_DEBUG
(
"stub: base 0x%x, start 0x%"
PRIx32
", %d sections"
,
esp_algorithm.c:321
esp_algorithm_load_func_image()
LOG_DEBUG
(
"addr "
TARGET_ADDR_FMT
", sz %d, flags %"
PRIx64
,
esp_algorithm.c:352
esp_algorithm_load_func_image()
LOG_DEBUG
(
"Write reversed tramp to addr "
TARGET_ADDR_FMT
", sz %zu"
,
run
->
stub
.
tramp_addr
,
al_tramp_size
)
;
esp_algorithm.c:408
esp_algorithm_load_func_image()
LOG_DEBUG
(
"Write tramp to addr "
TARGET_ADDR_FMT
", sz %zu"
,
run
->
stub
.
tramp_addr
,
tramp_sz
)
;
esp_algorithm.c:411
esp_algorithm_load_func_image()
LOG_DEBUG
(
"Tramp mapped to addr "
TARGET_ADDR_FMT
,
run
->
stub
.
tramp_mapped_addr
)
;
esp_algorithm.c:422
esp_algorithm_load_func_image()
LOG_DEBUG
(
"addr "
TARGET_ADDR_FMT
", sz %d, flags %"
PRIx64
,
section
->
base_address
,
section
->
size
,
esp_algorithm.c:446
esp_algorithm_load_func_image()
LOG_DEBUG
(
"DATA sec size %"
PRIu32
" -> %"
PRIu32
,
section
->
size
,
data_sec_sz
)
;
esp_algorithm.c:451
esp_algorithm_load_func_image()
LOG_DEBUG
(
"BSS sec size %"
PRIu32
" -> %"
PRIu32
,
run
->
image
.
bss_size
,
bss_sec_sz
)
;
esp_algorithm.c:453
esp_algorithm_load_func_image()
LOG_DEBUG
(
"Stub loaded in %g ms"
,
duration_elapsed
(
&
algo_time
)
*
1000
)
;
esp_algorithm.c:494
esp_algorithm_load_func_image()
LOG_DEBUG
(
"Stub loaded in %g ms"
,
duration_elapsed
(
&
algo_time
)
*
1000
)
;
esp_algorithm.c:579
esp_algorithm_load_onboard_func()
LOG_TARGET_DEBUG
(
target
,
"lseek(%"
PRIx64
", %"
PRIu32
" %"
PRId64
")=%d"
,
fd
,
pos
,
semihosting
->
result
,
errno
)
;
esp_semihosting.c:34
esp_semihosting_sys_seek()
LOG_TARGET_DEBUG
(
target
,
"op=0x%x, param=0x%"
PRIx64
,
semihosting
->
op
,
semihosting
->
param
)
;
esp_semihosting.c:57
esp_semihosting_common()
LOG_DEBUG
(
"start"
)
;
esp_xtensa.c:89
esp_xtensa_target_deinit()
LOG_TARGET_DEBUG
(
target
,
"Clear debug stubs info"
)
;
esp_xtensa.c:113
esp_xtensa_poll()
LOG_TARGET_DEBUG
(
target
,
"Check stack addr 0x%x"
,
stack_addr
)
;
esp_xtensa_algorithm.c:47
esp_xtensa_algo_regs_init_start()
LOG_TARGET_DEBUG
(
target
,
"Adjust stack addr to 0x%x"
,
stack_addr
)
;
esp_xtensa_algorithm.c:50
esp_xtensa_algo_regs_init_start()
LOG_DEBUG
(
"reg params count %d (%d/%d)."
,
esp_xtensa_algorithm.c:98
esp_xtensa_algo_init()
LOG_DEBUG
(
"Set arg[0] = %d (%s)"
,
arg
,
run
->
reg_args
.
params
[
run
->
reg_args
.
first_user_param
+
0
]
.
reg_name
)
;
esp_xtensa_algorithm.c:116
esp_xtensa_algo_init()
LOG_DEBUG
(
"Set arg[%d] = %d (%s)"
,
i
,
arg
,
run
->
reg_args
.
params
[
run
->
reg_args
.
first_user_param
+
i
]
.
reg_name
)
;
esp_xtensa_algorithm.c:125
esp_xtensa_algo_init()
LOG_DEBUG
(
"ctrl=0x%"
PRIx32
" memadrstart=0x%"
PRIx32
" memadrend=0x%"
PRIx32
" traxadr=0x%"
PRIx32
,
esp_xtensa_apptrace.c:83
esp_xtensa_apptrace_block_max_size_get()
LOG_DEBUG
(
"Read data on target (%s)"
,
target_name
(
target
)
)
;
esp_xtensa_apptrace.c:169
esp_xtensa_apptrace_data_read()
LOG_DEBUG
(
"Ack block %"
PRIu32
" target (%s)!"
,
block_id
,
target_name
(
target
)
)
;
esp_xtensa_apptrace.c:177
esp_xtensa_apptrace_data_read()
LOG_DEBUG
(
"Ack block %"
PRId32
" on target (%s)!"
,
block_id
,
target_name
(
target
)
)
;
esp_xtensa_apptrace.c:487
esp_xtensa_apptrace_buffs_write()
LOG_TARGET_DEBUG
(
target
,
"semihosting enable=%d"
,
enable
)
;
esp_xtensa_semihosting.c:26
esp_xtensa_semihosting_setup()
LOG_TARGET_DEBUG
(
target
,
"Semihosting call 0x%"
PRIx32
" 0x%"
PRIx32
" Base dir '%s'"
,
esp_xtensa_semihosting.c:77
esp_xtensa_semihosting()
LOG_TARGET_DEBUG
(
target
,
"begin"
)
;
esp_xtensa_smp.c:75
esp_xtensa_smp_deassert_reset()
LOG_TARGET_DEBUG
(
target
,
"begin"
)
;
esp_xtensa_smp.c:94
esp_xtensa_smp_soft_reset_halt()
LOG_TARGET_DEBUG
(
target
,
"Check for unexamined cores after reset"
)
;
esp_xtensa_smp.c:186
esp_xtensa_smp_poll()
LOG_DEBUG
(
"Failed to examine!"
)
;
esp_xtensa_smp.c:194
esp_xtensa_smp_poll()
LOG_DEBUG
(
"GDB target '%s'"
,
target_name
(
target
->
gdb_service
->
target
)
)
;
esp_xtensa_smp.c:259
esp_xtensa_smp_update_halt_gdb()
LOG_DEBUG
(
"Check target '%s'"
,
target_name
(
curr
)
)
;
esp_xtensa_smp.c:273
esp_xtensa_smp_update_halt_gdb()
LOG_DEBUG
(
"Poll target '%s'"
,
target_name
(
curr
)
)
;
esp_xtensa_smp.c:287
esp_xtensa_smp_update_halt_gdb()
LOG_DEBUG
(
"exit"
)
;
esp_xtensa_smp.c:318
esp_xtensa_smp_update_halt_gdb()
LOG_TARGET_DEBUG
(
target
,
"begin"
)
;
esp_xtensa_smp.c:343
esp_xtensa_smp_resume_cores()
LOG_TARGET_DEBUG
(
target
,
"smp_break=0x%"
PRIx32
,
smp_break
)
;
esp_xtensa_smp.c:370
esp_xtensa_smp_resume()
LOG_TARGET_DEBUG
(
target
,
"Fake resume"
)
;
esp_xtensa_smp.c:378
esp_xtensa_smp_resume()
LOG_DEBUG
(
"%i"
,
(
int
)
(
etb_reg
->
addr
)
)
;
etb.c:209
etb_read_reg_w_check()
LOG_DEBUG
(
"%i: 0x%8.8"
PRIx32
""
,
(
int
)
(
etb_reg
->
addr
)
,
value
)
;
etb.c:290
etb_write_reg()
LOG_DEBUG
(
"ETM ID: %08x"
,
(
unsigned
)
etm_ctx
->
id
)
;
etm.c:325
etm_build_reg_cache()
LOG_DEBUG
(
"%s (%u)"
,
r
->
name
,
reg_addr
)
;
etm.c:501
etm_read_reg_w_check()
LOG_DEBUG
(
"%s (%u): 0x%8.8"
PRIx32
""
,
r
->
name
,
reg_addr
,
value
)
;
etm.c:588
etm_write_reg()
LOG_DEBUG
(
"out of memory"
)
;
etm.c:1402
handle_etm_config_command()
LOG_DEBUG
(
"ETM SYS CONFIG %08x"
,
(
unsigned
)
config
)
;
etm.c:1498
handle_etm_info_command()
LOG_DEBUG
(
"xpsr: %8.8"
PRIx32
", spsr: %i"
,
xpsr
,
spsr
)
;
fa526.c:126
fa526_write_xpsr()
LOG_DEBUG
(
"xpsr_im: %2.2x, rot: %i, spsr: %i"
,
xpsr_im
,
rot
,
spsr
)
;
fa526.c:163
fa526_write_xpsr_im8()
LOG_DEBUG
(
"xpsr: %8.8"
PRIx32
", spsr: %i"
,
xpsr
,
spsr
)
;
feroceon.c:240
feroceon_write_xpsr()
LOG_DEBUG
(
"xpsr_im: %2.2x, rot: %i, spsr: %i"
,
xpsr_im
,
rot
,
spsr
)
;
feroceon.c:282
feroceon_write_xpsr_im8()
LOG_DEBUG
(
"-"
)
;
feroceon.c:331
feroceon_branch_resume_thumb()
LOG_DEBUG
(
"%s"
,
__func__
)
;
fespi.c:137
fespi_flash_bank_command()
LOG_DEBUG
(
"ASSUMING FESPI device at ctrl_base = "
TARGET_ADDR_FMT
,
fespi.c:153
fespi_flash_bank_command()
LOG_DEBUG
(
"%s: from sector %u to sector %u"
,
__func__
,
first
,
last
)
;
fespi.c:363
fespi_erase()
LOG_DEBUG
(
"bank->size=0x%x offset=0x%08"
PRIx32
" count=0x%08"
PRIx32
,
fespi.c:489
fespi_write()
LOG_DEBUG
(
"Failed to write %d bytes to "
TARGET_ADDR_FMT
": %d"
,
fespi.c:586
fespi_write()
LOG_DEBUG
(
"write(ctrl_base=0x%"
TARGET_PRIxADDR
", page_size=0x%x, "
fespi.c:591
fespi_write()
LOG_DEBUG
(
"Valid FESPI on device %s at address "
TARGET_ADDR_FMT
,
fespi.c:750
fespi_probe()
LOG_DEBUG
(
"Assuming FESPI as specified at address "
TARGET_ADDR_FMT
fespi.c:754
fespi_probe()
LOG_DEBUG
(
"fm3_busy_wait(%"
PRIx32
") needs about %d ms"
,
offset
,
ms
)
;
fm3.c:188
fm3_busy_wait()
LOG_DEBUG
(
"Spansion FM4 erase sectors %u to %u"
,
first
,
last
)
;
fm4.c:121
fm4_flash_erase()
LOG_DEBUG
(
"Spansion FM4 write at 0x%08"
PRIx32
" (%"
PRIu32
" bytes)"
,
fm4.c:216
fm4_flash_write()
LOG_DEBUG
(
"copying %"
PRIu32
" bytes to SRAM "
TARGET_ADDR_FMT
,
fm4.c:276
fm4_flash_write()
LOG_DEBUG
(
"writing 0x%08"
PRIx32
"-0x%08"
PRIx32
" (%"
PRIu32
"x)"
,
fm4.c:287
fm4_flash_write()
LOG_DEBUG
(
"%u sectors"
,
bank
->
num_sectors
)
;
fm4.c:372
mb9bf_probe()
LOG_DEBUG
(
"%u sectors"
,
bank
->
num_sectors
)
;
fm4.c:439
s6e2cc_probe()
LOG_DEBUG_IO
(
"start=%s goal=%s"
,
tap_state_name
(
start_state
)
,
tap_state_name
(
goal_state
)
)
;
ftdi.c:255
move_to_state()
tap_set_state
(
tap_state_transition
(
tap_get_state
(
)
,
(
tms_bits
>
>
i
)
&
1
)
)
;
ftdi.c:259
move_to_state()
LOG_DEBUG
(
"RCLK not supported"
)
;
ftdi.c:294
ftdi_khz()
LOG_DEBUG_IO
(
"runtest %u cycles, end in %s"
,
ftdi.c:316
ftdi_execute_runtest()
LOG_DEBUG_IO
(
"runtest: %u, end in %s"
,
ftdi.c:337
ftdi_execute_runtest()
LOG_DEBUG_IO
(
"statemove end in %s"
,
ftdi.c:344
ftdi_execute_statemove()
LOG_DEBUG_IO
(
"TMS: %u bits"
,
cmd
->
cmd
.
tms
->
num_bits
)
;
ftdi.c:360
ftdi_execute_tms()
LOG_DEBUG_IO
(
"pathmove: %u states, current: %s end: %s"
,
num_states
,
ftdi.c:376
ftdi_execute_pathmove()
LOG_DEBUG_IO
(
"-"
)
;
ftdi.c:384
ftdi_execute_pathmove()
tap_set_state
(
path
[
state_count
]
)
;
ftdi.c:406
ftdi_execute_pathmove()
LOG_DEBUG_IO
(
"%s type:%d"
,
cmd
->
cmd
.
scan
->
ir_scan
?
"IRSCAN"
:
"DRSCAN"
,
ftdi.c:424
ftdi_execute_scan()
LOG_DEBUG_IO
(
"discarding trailing empty field"
)
;
ftdi.c:431
ftdi_execute_scan()
LOG_DEBUG_IO
(
"empty scan, doing nothing"
)
;
ftdi.c:435
ftdi_execute_scan()
LOG_DEBUG_IO
(
"%s%s field %u/%u %u bits"
,
ftdi.c:454
ftdi_execute_scan()
tap_set_state
(
tap_state_transition
(
tap_get_state
(
)
,
1
)
)
;
ftdi.c:487
ftdi_execute_scan()
tap_set_state
(
tap_state_transition
(
tap_get_state
(
)
,
1
)
)
;
ftdi.c:495
ftdi_execute_scan()
tap_set_state
(
tap_state_transition
(
tap_get_state
(
)
,
0
)
)
;
ftdi.c:496
ftdi_execute_scan()
tap_set_state
(
tap_state_transition
(
tap_get_state
(
)
,
0
)
)
;
ftdi.c:504
ftdi_execute_scan()
LOG_DEBUG_IO
(
"%s scan, %i bits, end in %s"
,
ftdi.c:519
ftdi_execute_scan()
LOG_DEBUG_IO
(
"reset trst: %i srst %i"
,
trst
,
srst
)
;
ftdi.c:529
ftdi_reset()
LOG_DEBUG_IO
(
"sleep %"
PRIu32
,
cmd
->
cmd
.
sleep
->
us
)
;
ftdi.c:564
ftdi_execute_sleep()
LOG_DEBUG_IO
(
"sleep %"
PRIu32
" usec while in %s"
,
ftdi.c:568
ftdi_execute_sleep()
LOG_DEBUG_IO
(
"clocks %u while in %s"
,
ftdi.c:592
ftdi_execute_stableclocks()
LOG_DEBUG
(
"ftdi interface using 7 step jtag state transitions"
)
;
ftdi.c:652
ftdi_initialize()
LOG_DEBUG
(
"ftdi interface using shortest path jtag state transitions"
)
;
ftdi.c:654
ftdi_initialize()
LOG_DEBUG_IO
(
"Executing %zu queued transactions"
,
swd_cmd_queue_length
)
;
ftdi.c:1061
ftdi_swd_run_queue()
LOG_DEBUG_IO
(
"Skipping due to previous errors: %d"
,
queued_retval
)
;
ftdi.c:1066
ftdi_swd_run_queue()
LOG_CUSTOM_LEVEL
(
(
check_ack
&&
ack
!=
SWD_ACK_OK
)
?
LOG_LVL_DEBUG
:
LOG_LVL_DEBUG_IO
,
ftdi.c:1090
ftdi_swd_run_queue()
LOG_DEBUG
(
"Increased SWD command queue to %zu elements"
,
swd_cmd_queue_alloced
)
;
ftdi.c:1142
ftdi_swd_queue_cmd()
LOG_DEBUG
(
"SWD line reset"
)
;
ftdi.c:1200
ftdi_swd_switch_seq()
LOG_DEBUG
(
"JTAG-to-SWD"
)
;
ftdi.c:1205
ftdi_swd_switch_seq()
LOG_DEBUG
(
"JTAG-to-DORMANT"
)
;
ftdi.c:1210
ftdi_swd_switch_seq()
LOG_DEBUG
(
"SWD-to-JTAG"
)
;
ftdi.c:1215
ftdi_swd_switch_seq()
LOG_DEBUG
(
"SWD-to-DORMANT"
)
;
ftdi.c:1220
ftdi_swd_switch_seq()
LOG_DEBUG
(
"DORMANT-to-SWD"
)
;
ftdi.c:1225
ftdi_swd_switch_seq()
LOG_DEBUG
(
"DORMANT-to-JTAG"
)
;
ftdi.c:1230
ftdi_swd_switch_seq()
LOG_TARGET_DEBUG
(
target
,
"Debug reason is: %s"
,
gdb_server.c:154
gdb_last_signal()
LOG_DEBUG
(
"GDB connection closed by the remote client"
)
;
gdb_server.c:238
gdb_get_char_inner()
LOG_DEBUG
(
"GDB socket marked as closed, cannot write to it."
)
;
gdb_server.c:342
gdb_write()
if
(
!
LOG_LEVEL_IS
(
LOG_LVL_DEBUG
)
)
gdb_server.c:356
gdb_log_incoming_packet()
LOG_TARGET_DEBUG
(
target
,
"{%d} received packet: %.*s<binary-data-%u-bytes>"
,
gdb_server.c:375
gdb_log_incoming_packet()
LOG_TARGET_DEBUG
(
target
,
"{%d} received packet: <binary-data-%u-bytes>"
,
gdb_server.c:378
gdb_log_incoming_packet()
LOG_TARGET_DEBUG
(
target
,
"{%d} received packet: %s"
,
gdb_connection
->
unique_index
,
packet
)
;
gdb_server.c:383
gdb_log_incoming_packet()
if
(
!
LOG_LEVEL_IS
(
LOG_LVL_DEBUG
)
)
gdb_server.c:390
gdb_log_outgoing_packet()
LOG_TARGET_DEBUG
(
target
,
"{%d} sending packet: $<binary-data-%u-bytes>#%2.2x"
,
gdb_server.c:397
gdb_log_outgoing_packet()
LOG_TARGET_DEBUG
(
target
,
"{%d} sending packet: $%.*s#%2.2x"
,
gdb_server.c:400
gdb_log_outgoing_packet()
LOG_DEBUG
(
"Received first acknowledgment after entering noack mode. Ignoring it."
)
;
gdb_server.c:687
gdb_get_packet_inner()
LOG_TARGET_DEBUG
(
target
,
"Responding with signal 2 (SIGINT) to debugger due to Ctrl-C"
)
;
gdb_server.c:795
gdb_signal_reply()
LOG_DEBUG
(
"Unknown syscall: %s"
,
target
->
fileio_info
->
identifier
)
;
gdb_server.c:908
gdb_fileio_reply()
log_printf_lf
(
all_targets
->
next
?
LOG_LVL_INFO
:
LOG_LVL_DEBUG
,
gdb_server.c:1062
gdb_new_connection()
LOG_TARGET_DEBUG
(
target
,
"{%d} GDB Close, state: %s, gdb_actual_connections=%d"
,
gdb_server.c:1105
gdb_connection_closed()
LOG_DEBUG
(
"Couldn't get register %s."
,
reg_list
[
i
]
->
name
)
;
gdb_server.c:1283
gdb_get_registers_packet()
LOG_DEBUG
(
"Couldn't set register %s."
,
reg_list
[
i
]
->
name
)
;
gdb_server.c:1351
gdb_set_registers_packet()
LOG_DEBUG
(
"Couldn't get register %s."
,
reg_list
[
reg_num
]
->
name
)
;
gdb_server.c:1403
gdb_get_register_packet()
LOG_DEBUG
(
"Couldn't set register %s."
,
reg_list
[
reg_num
]
->
name
)
;
gdb_server.c:1473
gdb_set_register_packet()
LOG_DEBUG
(
"Reporting %i to GDB as generic error"
,
retval
)
;
gdb_server.c:1493
gdb_error()
LOG_DEBUG
(
"addr: 0x%16.16"
PRIx64
", len: 0x%8.8"
PRIx32
""
,
addr
,
len
)
;
gdb_server.c:1531
gdb_read_memory_packet()
LOG_DEBUG
(
"addr: 0x%"
PRIx64
", len: 0x%8.8"
PRIx32
""
,
addr
,
len
)
;
gdb_server.c:1603
gdb_write_memory_packet()
LOG_DEBUG
(
"addr: 0x%"
PRIx64
", len: 0x%8.8"
PRIx32
""
,
addr
,
len
)
;
gdb_server.c:1679
gdb_write_memory_binary_packet()
LOG_DEBUG
(
"-"
)
;
gdb_server.c:1711
gdb_step_continue_packet()
LOG_DEBUG
(
"continue"
)
;
gdb_server.c:1737
gdb_step_continue_packet()
LOG_DEBUG
(
"step"
)
;
gdb_server.c:1741
gdb_step_continue_packet()
LOG_DEBUG
(
"[%s]"
,
target_name
(
target
)
)
;
gdb_server.c:1760
gdb_breakpoint_watchpoint_packet()
LOG_TARGET_DEBUG
(
target
,
"%s not found in combined list"
,
a
->
name
)
;
gdb_server.c:2399
smp_reg_list_noread()
LOG_TARGET_DEBUG
(
target
,
"target continue"
)
;
gdb_server.c:3060
gdb_handle_vcont_packet()
LOG_TARGET_DEBUG
(
target
,
"error polling target after failed resume"
)
;
gdb_server.c:3070
gdb_handle_vcont_packet()
LOG_DEBUG
(
"request to step current core only"
)
;
gdb_server.c:3140
gdb_handle_vcont_packet()
LOG_TARGET_DEBUG
(
ct
,
"single-step thread %"
PRIx64
,
thread_id
)
;
gdb_server.c:3148
gdb_handle_vcont_packet()
LOG_DEBUG
(
"fake step thread %"
PRIx64
,
thread_id
)
;
gdb_server.c:3164
gdb_handle_vcont_packet()
LOG_DEBUG
(
"stepi ignored. GDB will now fetch the register state "
gdb_server.c:3179
gdb_handle_vcont_packet()
LOG_TARGET_DEBUG
(
ct
,
"error polling target after successful step"
)
;
gdb_server.c:3196
gdb_handle_vcont_packet()
LOG_DEBUG
(
"wrote %u bytes from vFlash image to flash"
,
(
unsigned
)
written
)
;
gdb_server.c:3458
gdb_v_packet()
LOG_DEBUG
(
"-"
)
;
gdb_server.c:3498
gdb_fileio_response_packet()
LOG_DEBUG
(
"File-I/O response, retcode: 0x%x, errno: 0x%x, ctrl-c: %s"
,
gdb_server.c:3511
gdb_fileio_response_packet()
LOG_DEBUG
(
"stepi ignored. GDB will now fetch the register state "
gdb_server.c:3676
gdb_input_inner()
LOG_DEBUG
(
"ignoring 0x%2.2x packet"
,
packet
[
0
]
)
;
gdb_server.c:3772
gdb_input_inner()
LOG_TARGET_DEBUG
(
target
,
"skip gdb server"
)
;
gdb_server.c:3919
gdb_target_add_one()
LOG_DEBUG
(
"hl_interface_open"
)
;
hla_interface.c:43
hl_interface_open()
LOG_DEBUG
(
"hl_interface_init_target"
)
;
hla_interface.c:68
hl_interface_init_target()
LOG_DEBUG
(
"hl_interface_init"
)
;
hla_interface.c:110
hl_interface_init()
LOG_DEBUG
(
"hl_interface_quit"
)
;
hla_interface.c:118
hl_interface_quit()
LOG_DEBUG
(
"hl_interface_handle_device_desc_command"
)
;
hla_interface.c:216
hl_interface_handle_device_desc_command()
LOG_DEBUG
(
"hl_interface_handle_layout_command"
)
;
hla_interface.c:229
hl_interface_handle_layout_command()
LOG_DEBUG
(
"hl_layout_open"
)
;
hla_layout.c:28
hl_layout_open()
LOG_DEBUG
(
"failed"
)
;
hla_layout.c:35
hl_layout_open()
LOG_DEBUG
(
"hl_layout_init"
)
;
hla_layout.c:83
hl_layout_init()
LOG_DEBUG
(
"data 0x%x ctrl 0x%x"
,
*
value
,
*
ctrl
)
;
hla_target.c:77
hl_dcc_read()
LOG_DEBUG
(
"%s"
,
__func__
)
;
hla_target.c:163
adapter_init_arch_info()
LOG_DEBUG
(
"%s"
,
__func__
)
;
hla_target.c:183
adapter_init_target()
LOG_DEBUG
(
"%s"
,
__func__
)
;
hla_target.c:193
adapter_target_create()
LOG_DEBUG
(
"entered debug state in core mode: %s at PC 0x%08"
PRIx32
", target->state: %s"
,
hla_target.c:278
adapter_debug_entry()
LOG_DEBUG
(
"halted: PC: 0x%08"
PRIx32
,
buf_get_u32
(
armv7m
->
arm
.
pc
->
value
,
0
,
32
)
)
;
hla_target.c:323
adapter_poll()
LOG_DEBUG
(
"%s"
,
__func__
)
;
hla_target.c:336
hl_assert_reset()
LOG_TARGET_DEBUG
(
target
,
"Trying to re-examine under reset"
)
;
hla_target.c:353
hl_assert_reset()
LOG_DEBUG
(
"%s"
,
__func__
)
;
hla_target.c:402
hl_deassert_reset()
LOG_DEBUG
(
"%s"
,
__func__
)
;
hla_target.c:417
adapter_halt()
LOG_DEBUG
(
"target was already halted"
)
;
hla_target.c:420
adapter_halt()
LOG_DEBUG
(
"%s %d "
TARGET_ADDR_FMT
" %d %d"
,
__func__
,
current
,
hla_target.c:448
adapter_resume()
LOG_DEBUG
(
"unset breakpoint at "
TARGET_ADDR_FMT
" (ID: %"
PRIu32
")"
,
hla_target.c:496
adapter_resume()
LOG_DEBUG
(
"%s"
,
__func__
)
;
hla_target.c:538
adapter_step()
LOG_DEBUG
(
"%s "
TARGET_ADDR_FMT
" %"
PRIu32
" %"
PRIu32
,
hla_target.c:601
adapter_read_memory()
LOG_DEBUG
(
"%s "
TARGET_ADDR_FMT
" %"
PRIu32
" %"
PRIu32
,
hla_target.c:616
adapter_write_memory()
LOG_DEBUG
(
"hl_transport_jtag_command"
)
;
hla_transport.c:26
hl_transport_jtag_command()
LOG_DEBUG
(
"hl_transport_init"
)
;
hla_transport.c:163
hl_transport_init()
LOG_DEBUG
(
"current transport %s"
,
transport
->
name
)
;
hla_transport.c:180
hl_transport_init()
LOG_DEBUG
(
"hl_jtag_transport_select"
)
;
hla_transport.c:200
hl_jtag_transport_select()
LOG_DEBUG
(
"hl_swd_transport_select"
)
;
hla_transport.c:211
hl_swd_transport_select()
LOG_DEBUG
(
"%s current_thread=%i"
,
__func__
,
(
int
)
rtos
->
current_thread
)
;
hwthread.c:209
hwthread_update_threads()
LOG_DEBUG
(
"Less than 9 bytes in the image file found."
)
;
image.c:58
autodetect_image_type()
LOG_DEBUG
(
"BIN image detected."
)
;
image.c:59
autodetect_image_type()
LOG_DEBUG
(
"ELF image detected."
)
;
image.c:69
autodetect_image_type()
LOG_DEBUG
(
"IHEX image detected."
)
;
image.c:80
autodetect_image_type()
LOG_DEBUG
(
"S19 image detected."
)
;
image.c:87
autodetect_image_type()
LOG_DEBUG
(
"BIN image detected."
)
;
image.c:90
autodetect_image_type()
LOG_DEBUG
(
"ELF32 image detected."
)
;
image.c:638
image_elf_read_headers()
LOG_DEBUG
(
"ELF64 image detected."
)
;
image.c:643
image_elf_read_headers()
LOG_DEBUG
(
"load segment %d at 0x%"
TARGET_PRIxADDR
" (sz = 0x%"
PRIx32
")"
,
section
,
offset
,
size
)
;
image.c:667
image_elf32_read_section()
LOG_DEBUG
(
"read elf: size = 0x%zx at 0x%"
TARGET_PRIxADDR
""
,
read_size
,
image.c:673
image_elf32_read_section()
LOG_DEBUG
(
"load segment %d at 0x%"
TARGET_PRIxADDR
" (sz = 0x%"
PRIx32
")"
,
section
,
offset
,
size
)
;
image.c:710
image_elf64_read_section()
LOG_DEBUG
(
"read elf: size = 0x%zx at 0x%"
TARGET_PRIxADDR
""
,
read_size
,
image.c:716
image_elf64_read_section()
LOG_DEBUG
(
image.c:1090
image_read_section()
LOG_DEBUG
(
"Calculating checksum"
)
;
image.c:1271
image_calculate_checksum()
LOG_DEBUG
(
"Calculating checksum done; checksum=0x%"
PRIx32
,
crc
)
;
image.c:1303
image_calculate_checksum()
LOG_DEBUG_IO
(
"TAP/SM: START state: %s"
,
tap_state_name
(
next_state
)
)
;
interface.c:391
jtag_debug_state_machine_()
LOG_DEBUG_IO
(
"TAP/SM: TMS bits: %u (bytes: %u)"
,
tap_bits
,
tap_bytes
)
;
interface.c:397
jtag_debug_state_machine_()
JTAG_DEBUG_STATE_PRINT
(
last_state
,
next_state
,
tms_str
,
tdi_str
)
;
interface.c:428
jtag_debug_state_machine_()
JTAG_DEBUG_STATE_PRINT
(
last_state
,
next_state
,
tms_str
,
tdi_str
)
;
interface.c:439
jtag_debug_state_machine_()
LOG_DEBUG_IO
(
"TAP/SM: FINAL state: %s"
,
tap_state_name
(
next_state
)
)
;
interface.c:442
jtag_debug_state_machine_()
LOG_DEBUG
(
"BUG: Caller passed out-of-range JEP106 ID!"
)
;
jep106.c:22
jep106_table_manufacturer()
LOG_DEBUG_IO
(
"stableclocks %i cycles"
,
cmd
->
cmd
.
runtest
->
num_cycles
)
;
jlink.c:120
jlink_execute_stableclocks()
LOG_DEBUG_IO
(
"runtest %i cycles, end in %i"
,
cmd
->
cmd
.
runtest
->
num_cycles
,
jlink.c:126
jlink_execute_runtest()
LOG_DEBUG_IO
(
"statemove end in %i"
,
cmd
->
cmd
.
statemove
->
end_state
)
;
jlink.c:135
jlink_execute_statemove()
LOG_DEBUG_IO
(
"pathmove: %u states, end in %i"
,
jlink.c:143
jlink_execute_pathmove()
LOG_DEBUG_IO
(
"%s type:%d"
,
cmd
->
cmd
.
scan
->
ir_scan
?
"IRSCAN"
:
"DRSCAN"
,
jlink.c:152
jlink_execute_scan()
LOG_DEBUG
(
"discarding trailing empty field"
)
;
jlink.c:159
jlink_execute_scan()
LOG_DEBUG
(
"empty scan, doing nothing"
)
;
jlink.c:163
jlink_execute_scan()
LOG_DEBUG_IO
(
"%s%s field %u/%u %u bits"
,
jlink.c:186
jlink_execute_scan()
tap_set_state
(
tap_state_transition
(
tap_get_state
(
)
,
1
)
)
;
jlink.c:214
jlink_execute_scan()
tap_set_state
(
tap_state_transition
(
tap_get_state
(
)
,
0
)
)
;
jlink.c:222
jlink_execute_scan()
LOG_DEBUG_IO
(
"%s scan, %i bits, end in %s"
,
jlink.c:238
jlink_execute_scan()
LOG_DEBUG_IO
(
"sleep %"
PRIu32
""
,
cmd
->
cmd
.
sleep
->
us
)
;
jlink.c:245
jlink_execute_sleep()
LOG_DEBUG
(
"Adjusted SWD transaction buffer size to %u bytes"
,
jlink.c:479
adjust_swd_buffer_size()
tmp
=
LOG_LVL_DEBUG
;
jlink.c:505
jaylink_log_handler()
tap_set_state
(
tap_get_end_state
(
)
)
;
jlink.c:899
jlink_state_move()
tap_set_state
(
path
[
i
]
)
;
jlink.c:917
jlink_path_move()
LOG_DEBUG
(
"TRST: %i, SRST: %i"
,
trst
,
srst
)
;
jlink.c:953
jlink_reset()
LOG_DEBUG
(
"Using %"
PRIu32
" bytes device memory for trace capturing"
,
jlink.c:1406
config_trace()
LOG_DEBUG_IO
(
"Pending scan result, length = %d"
,
p
->
length
)
;
jlink.c:2065
jlink_flush()
LOG_DEBUG_IO
(
"SWD line reset"
)
;
jlink.c:2115
jlink_swd_switch_seq()
LOG_DEBUG
(
"JTAG-to-SWD"
)
;
jlink.c:2120
jlink_swd_switch_seq()
LOG_DEBUG
(
"JTAG-to-DORMANT"
)
;
jlink.c:2125
jlink_swd_switch_seq()
LOG_DEBUG
(
"SWD-to-JTAG"
)
;
jlink.c:2130
jlink_swd_switch_seq()
LOG_DEBUG
(
"SWD-to-DORMANT"
)
;
jlink.c:2135
jlink_swd_switch_seq()
LOG_DEBUG
(
"DORMANT-to-SWD"
)
;
jlink.c:2140
jlink_swd_switch_seq()
LOG_DEBUG
(
"DORMANT-to-JTAG"
)
;
jlink.c:2145
jlink_swd_switch_seq()
LOG_DEBUG_IO
(
"Executing %d queued transactions"
,
pending_scan_results_length
)
;
jlink.c:2164
jlink_swd_run_queue()
LOG_DEBUG
(
"Skipping due to previous errors: %d"
,
queued_retval
)
;
jlink.c:2167
jlink_swd_run_queue()
LOG_DEBUG
(
"SWD ack not OK: %d %s"
,
ack
,
jlink.c:2189
jlink_swd_run_queue()
LOG_DEBUG
(
"loading jtagspi ir(0x%"
PRIx32
")"
,
info
->
ir
)
;
jtagspi.c:88
jtagspi_set_user_ir()
LOG_DEBUG
(
"cmd=0x%02x write_len=%d data_len=%d"
,
cmd
,
write_len
,
data_len
)
;
jtagspi.c:111
jtagspi_cmd()
LOG_DEBUG
(
"%s"
,
__func__
)
;
jtagspi.c:218
jtagspi_handle_set()
LOG_DEBUG
(
"%s"
,
__func__
)
;
jtagspi.c:366
jtagspi_handle_cmd()
LOG_DEBUG
(
"%s"
,
__func__
)
;
jtagspi.c:417
jtagspi_handle_always_4byte()
LOG_DEBUG
(
"status=0x%02"
PRIx32
,
*
status
)
;
jtagspi.c:523
jtagspi_read_status()
LOG_DEBUG
(
"waited %"
PRId64
" ms"
,
dt
)
;
jtagspi.c:542
jtagspi_wait()
LOG_DEBUG
(
"erase from sector %u to sector %u"
,
first
,
last
)
;
jtagspi.c:630
jtagspi_erase()
LOG_DEBUG
(
"Trying bulk erase."
)
;
jtagspi.c:652
jtagspi_erase()
LOG_DEBUG
(
"read page at 0x%08"
PRIx32
,
offset
)
;
jtagspi.c:715
jtagspi_read()
LOG_DEBUG
(
"wrote page at 0x%08"
PRIx32
,
offset
)
;
jtagspi.c:768
jtagspi_write()
LOG_DEBUG
(
"MDM_REG[0x%02x] <- %08"
PRIX32
,
reg
,
value
)
;
kinetis.c:430
kinetis_mdm_write_register()
LOG_DEBUG
(
"MDM: failed to get AP"
)
;
kinetis.c:434
kinetis_mdm_write_register()
LOG_DEBUG
(
"MDM: failed to queue a write request"
)
;
kinetis.c:440
kinetis_mdm_write_register()
LOG_DEBUG
(
"MDM: dap_run failed"
)
;
kinetis.c:448
kinetis_mdm_write_register()
LOG_DEBUG
(
"MDM: failed to get AP"
)
;
kinetis.c:460
kinetis_mdm_read_register()
LOG_DEBUG
(
"MDM: failed to queue a read request"
)
;
kinetis.c:466
kinetis_mdm_read_register()
LOG_DEBUG
(
"MDM: dap_run failed"
)
;
kinetis.c:474
kinetis_mdm_read_register()
LOG_DEBUG
(
"MDM_REG[0x%02x]: %08"
PRIX32
,
reg
,
*
result
)
;
kinetis.c:478
kinetis_mdm_read_register()
LOG_DEBUG
(
"MDM: polling timed out"
)
;
kinetis.c:497
kinetis_mdm_poll_register()
LOG_DEBUG
(
"MDM: failed to read MDM_REG_STAT"
)
;
kinetis.c:531
kinetis_mdm_halt()
LOG_DEBUG
(
"MDM: halt succeeded after %d attempts."
,
tries
)
;
kinetis.c:548
kinetis_mdm_halt()
LOG_DEBUG
(
"MDM: dap_run failed when validating secured state"
)
;
kinetis.c:841
kinetis_check_flash_security_status()
LOG_DEBUG
(
"ftfx command failed FSTAT: %02X FCCOB: %02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X"
,
kinetis.c:1557
kinetis_ftfx_command()
LOG_DEBUG
(
"Generated FCF written"
)
;
kinetis.c:1741
kinetis_erase()
LOG_DEBUG
(
"section @ "
TARGET_ADDR_FMT
" aligned begin %"
PRIu32
kinetis.c:1827
kinetis_write_sections()
LOG_DEBUG
(
"write section @ "
TARGET_ADDR_FMT
" with length %"
PRIu32
kinetis.c:1834
kinetis_write_sections()
LOG_DEBUG
(
"flash write @ "
TARGET_ADDR_FMT
,
bank
->
base
+
offset
)
;
kinetis.c:1899
kinetis_write_inner()
LOG_DEBUG
(
"write longword @ %08"
PRIx32
,
(
uint32_t
)
(
bank
->
base
+
offset
)
)
;
kinetis.c:1945
kinetis_write_inner()
LOG_DEBUG
(
"SDID: 0x%08"
PRIX32
" FCFG1: 0x%08"
PRIX32
" FCFG2: 0x%08"
PRIX32
,
k_chip
->
sim_sdid
,
kinetis.c:2723
kinetis_probe_chip()
LOG_DEBUG
(
"Kinetis bank %u: %"
PRIu32
"k PFlash, FTFx base 0x%08"
PRIx32
", sect %"
PRIu32
,
kinetis.c:2938
kinetis_probe()
LOG_DEBUG
(
"FlexNVM bank %u limited to 0x%08"
PRIx32
" due to active EEPROM backup"
,
kinetis.c:2973
kinetis_probe()
LOG_DEBUG
(
"Kinetis bank %u: %"
PRIu32
"k FlexNVM, FTFx base 0x%08"
PRIx32
", sect %"
PRIu32
,
kinetis.c:2978
kinetis_probe()
LOG_DEBUG
(
"Ignoring error on PFlash sector blank-check"
)
;
kinetis.c:3120
kinetis_blank_check()
LOG_DEBUG
(
"MDM_REG[0x%02x] <- %08"
PRIX32
,
reg
,
value
)
;
kinetis_ke.c:139
kinetis_ke_mdm_write_register()
LOG_DEBUG
(
"MDM: failed to get AP"
)
;
kinetis_ke.c:143
kinetis_ke_mdm_write_register()
LOG_DEBUG
(
"MDM: failed to queue a write request"
)
;
kinetis_ke.c:149
kinetis_ke_mdm_write_register()
LOG_DEBUG
(
"MDM: dap_run failed"
)
;
kinetis_ke.c:157
kinetis_ke_mdm_write_register()
LOG_DEBUG
(
"MDM: failed to get AP"
)
;
kinetis_ke.c:168
kinetis_ke_mdm_read_register()
LOG_DEBUG
(
"MDM: failed to queue a read request"
)
;
kinetis_ke.c:174
kinetis_ke_mdm_read_register()
LOG_DEBUG
(
"MDM: dap_run failed"
)
;
kinetis_ke.c:182
kinetis_ke_mdm_read_register()
LOG_DEBUG
(
"MDM_REG[0x%02x]: %08"
PRIX32
,
reg
,
*
result
)
;
kinetis_ke.c:186
kinetis_ke_mdm_read_register()
LOG_DEBUG
(
"MDM: polling timed out"
)
;
kinetis_ke.c:204
kinetis_ke_mdm_poll_register()
LOG_DEBUG
(
"Ignoring error on PFlash sector blank-check"
)
;
kinetis_ke.c:1197
kinetis_ke_blank_check()
LOG_DEBUG
(
"HID write returned %i"
,
ret
)
;
kitprog.c:336
kitprog_hid_command()
LOG_DEBUG
(
"Zero bytes transferred"
)
;
kitprog.c:424
kitprog_set_protocol()
LOG_DEBUG
(
"Programmer did not respond OK"
)
;
kitprog.c:429
kitprog_set_protocol()
LOG_DEBUG
(
"Zero bytes transferred"
)
;
kitprog.c:452
kitprog_get_status()
LOG_DEBUG
(
"Programmer did not respond OK"
)
;
kitprog.c:457
kitprog_get_status()
LOG_DEBUG
(
"Zero bytes transferred"
)
;
kitprog.c:476
kitprog_set_unknown()
LOG_DEBUG
(
"Programmer did not respond OK"
)
;
kitprog.c:481
kitprog_set_unknown()
LOG_DEBUG
(
"Zero bytes transferred"
)
;
kitprog.c:501
kitprog_acquire_psoc()
LOG_DEBUG
(
"Programmer did not respond OK"
)
;
kitprog.c:506
kitprog_acquire_psoc()
LOG_DEBUG
(
"Zero bytes transferred"
)
;
kitprog.c:525
kitprog_reset_target()
LOG_DEBUG
(
"Programmer did not respond OK"
)
;
kitprog.c:530
kitprog_reset_target()
LOG_DEBUG
(
"Zero bytes transferred"
)
;
kitprog.c:549
kitprog_swd_sync()
LOG_DEBUG
(
"Programmer did not respond OK"
)
;
kitprog.c:554
kitprog_swd_sync()
LOG_DEBUG
(
"Zero bytes transferred"
)
;
kitprog.c:573
kitprog_swd_seq()
LOG_DEBUG
(
"Programmer did not respond OK"
)
;
kitprog.c:578
kitprog_swd_seq()
LOG_DEBUG
(
"Acquisition function failed for device 0x%02x."
,
devices
[
j
]
)
;
kitprog.c:608
kitprog_generic_acquire()
LOG_DEBUG
(
"JTAG to SWD"
)
;
kitprog.c:651
kitprog_swd_switch_seq()
LOG_DEBUG
(
"JTAG to SWD not supported"
)
;
kitprog.c:656
kitprog_swd_switch_seq()
LOG_DEBUG
(
"SWD line reset"
)
;
kitprog.c:661
kitprog_swd_switch_seq()
LOG_DEBUG_IO
(
"Executing %d queued transactions"
,
pending_transfer_count
)
;
kitprog.c:683
kitprog_swd_run_queue()
LOG_DEBUG
(
"Skipping due to previous errors: %d"
,
queued_retval
)
;
kitprog.c:686
kitprog_swd_run_queue()
LOG_DEBUG
(
"refusing to enable sticky overrun detection"
)
;
kitprog.c:712
kitprog_swd_run_queue()
LOG_DEBUG_IO
(
"%s %s reg %x %"
PRIx32
,
kitprog.c:716
kitprog_swd_run_queue()
LOG_DEBUG_IO
(
"Read result: %"
PRIx32
,
data
)
;
kitprog.c:773
kitprog_swd_run_queue()
LOG_DEBUG
(
"SWD ack not OK: %d %s"
,
i
,
kitprog.c:783
kitprog_swd_run_queue()
LOG_DEBUG
(
"dr in 0x%02"
PRIx8
,
*
in
)
;
lakemont.c:280
drscan()
LOG_DEBUG
(
"reg=%s, value=0x%08"
PRIx32
,
reg
->
name
,
lakemont.c:335
lakemont_get_core_reg()
LOG_DEBUG
(
"reg=%s, newval=0x%08"
PRIx32
,
reg
->
name
,
value
)
;
lakemont.c:345
lakemont_set_core_reg()
LOG_DEBUG
(
"TS before PM enter = 0x%08"
PRIx32
,
tapstatus
)
;
lakemont.c:439
enter_probemode()
LOG_DEBUG
(
"core already in probemode"
)
;
lakemont.c:441
enter_probemode()
LOG_DEBUG
(
"TS after PM enter = 0x%08"
PRIx32
,
tapstatus
)
;
lakemont.c:453
enter_probemode()
LOG_DEBUG
(
"TS before PM exit = 0x%08"
PRIx32
,
tapstatus
)
;
lakemont.c:466
exit_probemode()
LOG_DEBUG
(
"write %s 0x%08"
PRIx32
,
regs
[
DSB
]
.
name
,
PM_DSB
)
;
lakemont.c:487
halt_prep()
LOG_DEBUG
(
"write %s 0x%08"
PRIx32
,
regs
[
DSL
]
.
name
,
PM_DSL
)
;
lakemont.c:490
halt_prep()
LOG_DEBUG
(
"write DSAR 0x%08"
PRIx32
,
PM_DSAR
)
;
lakemont.c:493
halt_prep()
LOG_DEBUG
(
"write %s 0x%08"
PRIx32
,
regs
[
CSB
]
.
name
,
PM_DSB
)
;
lakemont.c:496
halt_prep()
LOG_DEBUG
(
"write %s 0x%08"
PRIx32
,
regs
[
CSL
]
.
name
,
PM_DSL
)
;
lakemont.c:499
halt_prep()
LOG_DEBUG
(
"write DR7 0x%08"
PRIx32
,
PM_DR7
)
;
lakemont.c:502
halt_prep()
LOG_DEBUG
(
"EFLAGS = 0x%08"
PRIx32
", VM86 = %d, IF = %d"
,
eflags
,
lakemont.c:510
halt_prep()
LOG_DEBUG
(
"EFLAGS now = 0x%08"
PRIx32
", VM86 = %d, IF = %d"
,
lakemont.c:517
halt_prep()
LOG_DEBUG
(
"write CSAR_CPL to 0 0x%08"
PRIx32
,
x86_32
->
pm_regs
[
I
(
CSAR
)
]
)
;
lakemont.c:528
halt_prep()
LOG_DEBUG
(
"write SSAR_CPL to 0 0x%08"
PRIx32
,
x86_32
->
pm_regs
[
I
(
SSAR
)
]
)
;
lakemont.c:534
halt_prep()
LOG_DEBUG
(
"caching enabled CR0 = 0x%08"
PRIx32
,
cr0
)
;
lakemont.c:539
halt_prep()
LOG_DEBUG
(
"cleared paging CR0_PG = 0x%08"
PRIx32
,
x86_32
->
pm_regs
[
I
(
CR0
)
]
)
;
lakemont.c:544
halt_prep()
LOG_DEBUG
(
"set CD, NW and PG, CR0 = 0x%08"
PRIx32
,
x86_32
->
pm_regs
[
I
(
CR0
)
]
)
;
lakemont.c:552
halt_prep()
LOG_DEBUG
(
"read_all_core_hw_regs read %u registers ok"
,
i
)
;
lakemont.c:612
read_all_core_hw_regs()
LOG_DEBUG
(
"write_all_core_hw_regs wrote %u registers ok"
,
i
)
;
lakemont.c:631
write_all_core_hw_regs()
LOG_DEBUG
(
"reg=%s, op=0x%016"
PRIx64
", val=0x%08"
PRIx32
,
lakemont.c:662
read_hw_reg()
LOG_DEBUG
(
"reg=%s, op=0x%016"
PRIx64
", val=0x%08"
PRIx32
,
lakemont.c:680
write_hw_reg()
LOG_DEBUG
(
"reg %s op=0x%016"
PRIx64
,
regs
[
num
]
.
name
,
regs
[
num
]
.
op
)
;
lakemont.c:779
submit_reg_pir()
LOG_DEBUG
(
"%s op=0x%016"
PRIx64
,
instructions
[
num
]
.
name
,
lakemont.c:790
submit_instruction_pir()
LOG_DEBUG
(
"redirect to PM, tapstatus=0x%08"
PRIx32
,
get_tapstatus
(
t
)
)
;
lakemont.c:875
lakemont_poll()
LOG_DEBUG
(
"modifying PMCR = 0x%08"
PRIx32
" and EFLAGS = 0x%08"
PRIx32
,
pmcr
,
eflags
)
;
lakemont.c:1055
lakemont_step()
LOG_DEBUG
(
"EFLAGS [TF] [RF] bits set=0x%08"
PRIx32
", PMCR=0x%08"
PRIx32
", EIP=0x%08"
PRIx32
,
lakemont.c:1059
lakemont_step()
LOG_DEBUG
(
"issuing port 0xcf9 reset"
)
;
lakemont.c:1117
lakemont_reset_break()
LOG_DEBUG
(
" "
)
;
lakemont.c:1171
lakemont_reset_assert()
LOG_DEBUG
(
"target must be halted first"
)
;
lakemont.c:1174
lakemont_reset_assert()
LOG_DEBUG
(
" "
)
;
lakemont.c:1212
lakemont_reset_deassert()
LOG_DEBUG
(
"Device serial number '%s' doesn't match requested serial '%s'"
,
libusb_helper.c:113
string_descriptor_equal()
LOG_DEBUG
(
"Device alternate serial number '%s' doesn't match requested serial '%s'"
,
libusb_helper.c:141
jtag_libusb_match_serial()
LOG_DEBUG
(
"usb ep %s %02x"
,
libusb_helper.c:342
jtag_libusb_choose_interface()
LOG_DEBUG
(
"Claiming interface %d"
,
(
int
)
interdesc
->
bInterfaceNumber
)
;
libusb_helper.c:351
jtag_libusb_choose_interface()
if
(
debug_level
>=
LOG_LVL_DEBUG
)
{
log.c:104
log_puts()
LOG_DEBUG
(
"keep_alive() was not invoked in the "
log.c:408
gdb_timeout_warning()
LOG_DEBUG
(
"IAP command = %i (0x%8.8"
PRIx32
", 0x%8.8"
PRIx32
", 0x%8.8"
PRIx32
", 0x%8.8"
PRIx32
", 0x%8.8"
PRIx32
lpc2000.c:839
lpc2000_iap_call()
LOG_DEBUG
(
"first_sector: %i, last_sector: %i"
,
first_sector
,
last_sector
)
;
lpc2000.c:1079
lpc2000_write()
LOG_DEBUG
(
"Vector 0x%2.2x: 0x%8.8"
PRIx32
,
i
*
4
,
buf_get_u32
(
buffer
+
(
i
*
4
)
,
0
,
32
)
)
;
lpc2000.c:1086
lpc2000_write()
LOG_DEBUG
(
"checksum: 0x%8.8"
PRIx32
,
checksum
)
;
lpc2000.c:1091
lpc2000_write()
LOG_DEBUG
(
"writing 0x%"
PRIx32
" bytes to address "
TARGET_ADDR_FMT
,
lpc2000.c:1180
lpc2000_write()
LOG_DEBUG
(
"Timedout!"
)
;
lpc288x.c:104
lpc288x_wait_status_busy()
LOG_DEBUG
(
"Timeout!"
)
;
lpc2900.c:194
lpc2900_wait_status()
LOG_DEBUG
(
"Skip secured sector %u"
,
lpc2900.c:1223
lpc2900_write()
LOG_DEBUG
(
"LPC3180 HCLK currently clocked at %i kHz"
,
hclk
)
;
lpc3180.c:120
lpc3180_cycle_time()
LOG_DEBUG
(
"no LPC3180 NAND flash controller selected, using default 'mlc'"
)
;
lpc3180.c:167
lpc3180_init()
LOG_DEBUG
(
"lpc3180_controller_ready count start=%d"
,
timeout
)
;
lpc3180.c:1160
lpc3180_controller_ready()
LOG_DEBUG
(
"lpc3180_controller_ready count=%d"
,
lpc3180.c:1170
lpc3180_controller_ready()
LOG_DEBUG
(
"lpc3180_controller_ready count=%d"
,
lpc3180.c:1181
lpc3180_controller_ready()
LOG_DEBUG
(
"lpc3180_nand_ready count start=%d"
,
timeout
)
;
lpc3180.c:1203
lpc3180_nand_ready()
LOG_DEBUG
(
"lpc3180_nand_ready count end=%d"
,
lpc3180.c:1213
lpc3180_nand_ready()
LOG_DEBUG
(
"lpc3180_nand_ready count end=%d"
,
lpc3180.c:1224
lpc3180_nand_ready()
LOG_DEBUG
(
"lpc3180_tc_ready count start=%d"
,
lpc3180.c:1246
lpc3180_tc_ready()
LOG_DEBUG
(
"lpc3180_tc_ready count=%d"
,
lpc3180.c:1256
lpc3180_tc_ready()
LOG_DEBUG
(
"LPC32xx HCLK currently clocked at %i kHz"
,
hclk
)
;
lpc32xx.c:170
lpc32xx_cycle_time()
LOG_DEBUG
(
"no LPC32xx NAND flash controller selected, "
lpc32xx.c:213
lpc32xx_init()
LOG_DEBUG
(
"lpc32xx_dma_ready count start=%d"
,
timeout
)
;
lpc32xx.c:955
lpc32xx_dma_ready()
LOG_DEBUG
(
"lpc32xx_dma_ready count=%d"
,
lpc32xx.c:975
lpc32xx_dma_ready()
LOG_DEBUG
(
"%02x: %02x %02x %02x %02x %02x %02x %02x %02x"
,
addr
,
lpc32xx.c:1009
lpc32xx_dump_oob()
LOG_DEBUG
(
"SLC write page %"
PRIx32
" data=%d, oob=%d, "
lpc32xx.c:1028
lpc32xx_write_page_slc()
LOG_DEBUG
(
"SLC read page %"
PRIx32
" data=%"
PRIu32
", oob=%"
PRIu32
,
lpc32xx.c:1439
lpc32xx_read_page_slc()
LOG_DEBUG
(
"lpc32xx_controller_ready count start=%d"
,
timeout
)
;
lpc32xx.c:1615
lpc32xx_controller_ready()
LOG_DEBUG
(
"lpc32xx_controller_ready count=%d"
,
lpc32xx.c:1629
lpc32xx_controller_ready()
LOG_DEBUG
(
"lpc32xx_controller_ready count=%d"
,
lpc32xx.c:1644
lpc32xx_controller_ready()
LOG_DEBUG
(
"lpc32xx_nand_ready count start=%d"
,
timeout
)
;
lpc32xx.c:1668
lpc32xx_nand_ready()
LOG_DEBUG
(
"lpc32xx_nand_ready count end=%d"
,
lpc32xx.c:1683
lpc32xx_nand_ready()
LOG_DEBUG
(
"lpc32xx_nand_ready count end=%d"
,
lpc32xx.c:1698
lpc32xx_nand_ready()
LOG_DEBUG
(
"lpc32xx_tc_ready count start=%d"
,
timeout
)
;
lpc32xx.c:1714
lpc32xx_tc_ready()
LOG_DEBUG
(
"lpc32xx_tc_ready count=%d"
,
timeout
)
;
lpc32xx.c:1726
lpc32xx_tc_ready()
LOG_DEBUG
(
"Uninitializing LPC43xx SSP"
)
;
lpcspifi.c:133
lpcspifi_set_hw_mode()
LOG_DEBUG
(
"Allocating working area for SPIFI init algorithm"
)
;
lpcspifi.c:164
lpcspifi_set_hw_mode()
LOG_DEBUG
(
"Writing algorithm to working area at "
TARGET_ADDR_FMT
,
lpcspifi.c:178
lpcspifi_set_hw_mode()
LOG_DEBUG
(
"Running SPIFI init algorithm"
)
;
lpcspifi.c:207
lpcspifi_set_hw_mode()
LOG_DEBUG
(
"erase from sector %u to sector %u"
,
first
,
last
)
;
lpcspifi.c:416
lpcspifi_erase()
LOG_DEBUG
(
"Chip supports the bulk erase command."
lpcspifi.c:444
lpcspifi_erase()
LOG_DEBUG
(
"offset=0x%08"
PRIx32
" count=0x%08"
PRIx32
,
lpcspifi.c:582
lpcspifi_write()
LOG_DEBUG
(
"Getting ID"
)
;
lpcspifi.c:773
lpcspifi_read_flash_id()
LOG_DEBUG
(
"%s"
,
__func__
)
;
ls1_sap.c:32
ls1_sap_init_target()
LOG_DEBUG
(
"%s"
,
__func__
)
;
ls1_sap.c:38
ls1_sap_arch_state()
LOG_DEBUG
(
"%s"
,
__func__
)
;
ls1_sap.c:54
ls1_sap_halt()
LOG_DEBUG
(
"%s"
,
__func__
)
;
ls1_sap.c:61
ls1_sap_resume()
LOG_DEBUG
(
"%s"
,
__func__
)
;
ls1_sap.c:68
ls1_sap_step()
LOG_DEBUG
(
"%s"
,
__func__
)
;
ls1_sap.c:76
ls1_sap_assert_reset()
LOG_DEBUG
(
"%s"
,
__func__
)
;
ls1_sap.c:84
ls1_sap_deassert_reset()
LOG_DEBUG
(
"Reading memory at physical address 0x%"
TARGET_PRIxADDR
ls1_sap.c:175
ls1_sap_read_memory()
LOG_DEBUG
(
"Writing memory at physical address 0x%"
TARGET_PRIxADDR
ls1_sap.c:197
ls1_sap_write_memory()
LOG_DEBUG
(
"(bank=%p buffer=%p offset=%08"
PRIx32
" wcount=%08"
PRIx32
""
,
max32xxx.c:369
max32xxx_write_block()
LOG_DEBUG
(
"no working area for block memory writes"
)
;
max32xxx.c:374
max32xxx_write_block()
LOG_DEBUG
(
"retry target_alloc_working_area(%s, size=%u)"
,
max32xxx.c:391
max32xxx_write_block()
LOG_DEBUG
(
"bank=%p buffer=%p offset=%08"
PRIx32
" count=%08"
PRIx32
""
,
max32xxx.c:444
max32xxx_write()
LOG_DEBUG
(
"writing flash word-at-a-time"
)
;
max32xxx.c:477
max32xxx_write()
LOG_DEBUG
(
"Writing @ 0x%08"
PRIx32
,
address
)
;
max32xxx.c:531
max32xxx_write()
LOG_DEBUG
(
"arm_pid = 0x%x"
,
arm_pid
)
;
max32xxx.c:658
max32xxx_probe()
LOG_DEBUG
(
"max326xx_id = 0x%"
PRIx32
,
max326xx_id
)
;
max32xxx.c:663
max32xxx_probe()
LOG_DEBUG
(
"info->max326xx = %d"
,
info
->
max326xx
)
;
max32xxx.c:668
max32xxx_probe()
LOG_DEBUG
(
"%s"
,
__func__
)
;
mem_ap.c:61
mem_ap_init_target()
LOG_DEBUG
(
"%s"
,
__func__
)
;
mem_ap.c:71
mem_ap_deinit_target()
LOG_DEBUG
(
"%s"
,
__func__
)
;
mem_ap.c:83
mem_ap_arch_state()
LOG_DEBUG
(
"%s"
,
__func__
)
;
mem_ap.c:99
mem_ap_halt()
LOG_DEBUG
(
"%s"
,
__func__
)
;
mem_ap.c:109
mem_ap_resume()
LOG_DEBUG
(
"%s"
,
__func__
)
;
mem_ap.c:118
mem_ap_step()
LOG_DEBUG
(
"%s"
,
__func__
)
;
mem_ap.c:130
mem_ap_assert_reset()
LOG_DEBUG
(
"%s"
,
__func__
)
;
mem_ap.c:166
mem_ap_deassert_reset()
LOG_DEBUG
(
"Reading memory at physical address "
TARGET_ADDR_FMT
mem_ap.c:241
mem_ap_read_memory()
LOG_DEBUG
(
"Writing memory at physical address "
TARGET_ADDR_FMT
mem_ap.c:256
mem_ap_write_memory()
LOG_DEBUG
(
"read core reg %i value 0x%"
PRIx64
""
,
num
,
reg_value
)
;
mips32.c:358
mips32_read_core_reg()
LOG_DEBUG
(
"write core reg %i value 0x%"
PRIx64
""
,
num
,
reg_value
)
;
mips32.c:398
mips32_write_core_reg()
LOG_DEBUG
(
"failed algorithm halted at 0x%"
PRIx32
" "
,
pc
)
;
mips32.c:588
mips32_run_and_wait()
LOG_DEBUG
(
"Running algorithm"
)
;
mips32.c:607
mips32_run_algorithm()
LOG_DEBUG
(
"restoring register %s with value 0x%8.8"
PRIx32
,
mips32.c:697
mips32_run_algorithm()
LOG_DEBUG
(
"DCR 0x%"
PRIx32
" numinst %i numdata %i"
,
dcr
,
mips32
->
num_inst_bpoints
,
mips32.c:831
mips32_configure_break_unit()
LOG_DEBUG
(
"CPU: %s (PRId %08x)"
,
entry
->
cpu_name
,
mips32
->
prid
)
;
mips32.c:1024
mips32_cpu_probe()
LOG_DEBUG
(
"read %"
PRIu32
" config registers"
,
ejtag_info
->
config_regs
)
;
mips32.c:1146
mips32_read_config_regs()
LOG_DEBUG
(
"DEBUGMODULE: No memory access in progress!"
)
;
mips32_pracc.c:86
wait_for_pracc_rw()
LOG_DEBUG
(
"restarting code"
)
;
mips32_pracc.c:178
mips32_pracc_exec()
LOG_DEBUG
(
"unexpected write at address %"
PRIx32
,
ejtag_info
->
pa_addr
)
;
mips32_pracc.c:189
mips32_pracc_exec()
LOG_DEBUG
(
"writing at unexpected address %"
PRIx32
,
ejtag_info
->
pa_addr
)
;
mips32_pracc.c:199
mips32_pracc_exec()
LOG_DEBUG
(
"reading at unexpected address %"
PRIx32
", expected %x"
,
mips32_pracc.c:218
mips32_pracc_exec()
LOG_DEBUG
(
"restarting, without clean jump"
)
;
mips32_pracc.c:224
mips32_pracc_exec()
LOG_DEBUG
(
"unexpected second pass through pracc text"
)
;
mips32_pracc.c:255
mips32_pracc_exec()
LOG_DEBUG
(
"unexpected read address in final check: %"
mips32_pracc.c:260
mips32_pracc_exec()
LOG_DEBUG
(
"failed to jump back to pracc text"
)
;
mips32_pracc.c:268
mips32_pracc_exec()
LOG_DEBUG
(
"execution abandoned, store pending: %d"
,
store_pending
)
;
mips32_pracc.c:273
mips32_pracc_exec()
LOG_DEBUG
(
"warning: store access pass pracc text"
)
;
mips32_pracc.c:291
mips32_pracc_exec()
LOG_DEBUG
(
"clsiz must be power of 2"
)
;
mips32_pracc.c:682
mips32_pracc_synchronize_cache()
LOG_DEBUG
(
"Unsupported MIPS Release ( > 5)"
)
;
mips32_pracc.c:848
mips32_pracc_write_mem()
LOG_DEBUG
(
"Unsupported MIPS Release ( > 5)"
)
;
mips32_pracc.c:1210
mips32_pracc_fastdata_xfer_synchronize_cache()
LOG_DEBUG
(
"%s using 0x%.8"
TARGET_PRIxADDR
" for write handler"
,
__func__
,
source
->
address
)
;
mips32_pracc.c:1276
mips32_pracc_fastdata_xfer()
LOG_DEBUG
(
"write core reg %i value 0x%"
PRIx64
""
,
num
,
reg_value
)
;
mips64.c:286
mips64_write_core_reg()
LOG_DEBUG
(
"DCR 0x%"
PRIx64
" numinst %i numdata %i"
,
dcr
,
mips64.c:583
mips64_configure_break_unit()
LOG_DEBUG
(
"DEBUGMODULE: No memory access in progress!\n"
)
;
mips64_pracc.c:55
wait_for_pracc_rw()
LOG_DEBUG
(
"Reading %"
PRIx64
" at %"
PRIx64
,
data
,
address
)
;
mips64_pracc.c:89
mips64_pracc_exec_read()
LOG_DEBUG
(
"Reading %"
PRIx64
" at %"
PRIx64
,
data
,
address
)
;
mips64_pracc.c:101
mips64_pracc_exec_read()
LOG_DEBUG
(
"Running commands %"
PRIx64
" at %"
PRIx64
,
data
,
mips64_pracc.c:111
mips64_pracc_exec_read()
LOG_DEBUG
(
"Reading %"
PRIx64
" at %"
PRIx64
,
data
,
address
)
;
mips64_pracc.c:123
mips64_pracc_exec_read()
LOG_DEBUG
(
"Writing %"
PRIx64
" at %"
PRIx64
,
data
,
address
)
;
mips64_pracc.c:178
mips64_pracc_exec_write()
LOG_DEBUG
(
"%08"
PRIx32
,
code
[
i
]
)
;
mips64_pracc.c:225
mips64_pracc_exec()
LOG_DEBUG
(
"ERROR wait_for_pracc_rw"
)
;
mips64_pracc.c:240
mips64_pracc_exec()
LOG_DEBUG
(
"-> %08"
PRIx32
,
address32
)
;
mips64_pracc.c:251
mips64_pracc_exec()
LOG_DEBUG
(
"@MIPS64_PRACC_TEXT, address_prev=%"
PRIx64
,
address_prev
)
;
mips64_pracc.c:295
mips64_pracc_exec()
LOG_DEBUG
(
"enter mips64_pracc_exec"
)
;
mips64_pracc.c:351
mips64_pracc_read_u64()
LOG_DEBUG
(
"enter mips64_pracc_exec"
)
;
mips64_pracc.c:409
mips64_pracc_read_u32()
LOG_DEBUG
(
"enter mips64_pracc_exec"
)
;
mips64_pracc.c:469
mips64_pracc_read_u16()
LOG_DEBUG
(
"enter mips64_pracc_exec"
)
;
mips64_pracc.c:529
mips64_pracc_read_u8()
LOG_DEBUG
(
"enter mips64_pracc_exec"
)
;
mips64_pracc.c:609
mips64_pracc_write_u64()
LOG_DEBUG
(
"enter mips64_pracc_exec"
)
;
mips64_pracc.c:671
mips64_pracc_write_u32()
LOG_DEBUG
(
"enter mips64_pracc_exec"
)
;
mips64_pracc.c:731
mips64_pracc_write_u16()
LOG_DEBUG
(
"enter mips64_pracc_exec"
)
;
mips64_pracc.c:792
mips64_pracc_write_u8()
LOG_DEBUG
(
"enter mips64_pracc_exec"
)
;
mips64_pracc.c:1032
mips64_pracc_write_regs()
LOG_DEBUG
(
"enter mips64_pracc_exec"
)
;
mips64_pracc.c:1258
mips64_pracc_read_regs()
LOG_DEBUG
(
"%s using "
TARGET_ADDR_FMT
" for write handler"
,
__func__
,
mips64_pracc.c:1351
mips64_pracc_fastdata_xfer()
LOG_DEBUG
(
"daddiu: %08"
PRIx32
,
handler_code
[
11
]
)
;
mips64_pracc.c:1353
mips64_pracc_fastdata_xfer()
LOG_DEBUG
(
"start: "
TARGET_ADDR_FMT
,
val
)
;
mips64_pracc.c:1373
mips64_pracc_fastdata_xfer()
LOG_DEBUG
(
"stop: "
TARGET_ADDR_FMT
,
val
)
;
mips64_pracc.c:1383
mips64_pracc_fastdata_xfer()
LOG_DEBUG
(
"num_clocks=%d"
,
num_clocks
)
;
mips64_pracc.c:1391
mips64_pracc_fastdata_xfer()
LOG_DEBUG
(
"ejtag_ctrl: 0x%8.8"
PRIx32
""
,
ejtag_ctrl
)
;
mips_ejtag.c:248
mips_ejtag_enter_debug()
LOG_DEBUG
(
"EJTAG v2.0: features:%s%s%s%s%s%s%s%s"
,
mips_ejtag.c:314
ejtag_v20_print_imp()
LOG_DEBUG
(
"EJTAG v2.0: Break Channels: %"
PRIu8
,
mips_ejtag.c:323
ejtag_v20_print_imp()
LOG_DEBUG
(
"EJTAG v2.6: features:%s%s"
,
mips_ejtag.c:330
ejtag_v26_print_imp()
LOG_DEBUG
(
"EJTAG main: features:%s%s%s%s%s"
,
mips_ejtag.c:337
ejtag_main_print_imp()
LOG_DEBUG
(
"EJTAG: Version 1 or 2.0 Detected"
)
;
mips_ejtag.c:373
mips_ejtag_init()
LOG_DEBUG
(
"EJTAG: Version 2.5 Detected"
)
;
mips_ejtag.c:376
mips_ejtag_init()
LOG_DEBUG
(
"EJTAG: Version 2.6 Detected"
)
;
mips_ejtag.c:379
mips_ejtag_init()
LOG_DEBUG
(
"EJTAG: Version 3.1 Detected"
)
;
mips_ejtag.c:382
mips_ejtag_init()
LOG_DEBUG
(
"EJTAG: Version 4.1 Detected"
)
;
mips_ejtag.c:385
mips_ejtag_init()
LOG_DEBUG
(
"EJTAG: Version 5.1 Detected"
)
;
mips_ejtag.c:388
mips_ejtag_init()
LOG_DEBUG
(
"EJTAG: Unknown Version Detected"
)
;
mips_ejtag.c:391
mips_ejtag_init()
LOG_DEBUG
(
"EJTAG: DMA Access Mode detected. Disabling to "
mips_ejtag.c:397
mips_ejtag_init()
LOG_DEBUG
(
"enter mips64_pracc_exec"
)
;
mips_ejtag.c:515
mips64_ejtag_exit_debug()
LOG_DEBUG
(
"entered debug state at PC 0x%"
PRIx32
", target->state: %s"
,
mips_m4k.c:114
mips_m4k_debug_entry()
LOG_DEBUG
(
"Reset Detected"
)
;
mips_m4k.c:203
mips_m4k_poll()
LOG_DEBUG
(
"EJTAG_CTRL_BRKST already set during server startup."
)
;
mips_m4k.c:211
mips_m4k_poll()
LOG_DEBUG
(
"target->state: %s"
,
target_state_name
(
target
)
)
;
mips_m4k.c:260
mips_m4k_halt()
LOG_DEBUG
(
"target was already halted"
)
;
mips_m4k.c:263
mips_m4k_halt()
LOG_DEBUG
(
"target->state: %s"
,
mips_m4k.c:304
mips_m4k_assert_reset()
LOG_DEBUG
(
"Using MTAP reset to reset processor..."
)
;
mips_m4k.c:340
mips_m4k_assert_reset()
LOG_DEBUG
(
"Using EJTAG reset (PRRST) to reset processor..."
)
;
mips_m4k.c:352
mips_m4k_assert_reset()
LOG_DEBUG
(
"target->state: %s"
,
target_state_name
(
target
)
)
;
mips_m4k.c:374
mips_m4k_deassert_reset()
LOG_DEBUG
(
"unset breakpoint at "
TARGET_ADDR_FMT
""
,
mips_m4k.c:466
mips_m4k_internal_restore()
LOG_DEBUG
(
"target resumed at 0x%"
PRIx32
""
,
resume_pc
)
;
mips_m4k.c:487
mips_m4k_internal_restore()
LOG_DEBUG
(
"target debug resumed at 0x%"
PRIx32
""
,
resume_pc
)
;
mips_m4k.c:491
mips_m4k_internal_restore()
LOG_DEBUG
(
"target stepped "
)
;
mips_m4k.c:572
mips_m4k_step()
LOG_DEBUG
(
"bpid: %"
PRIu32
", bp_num %i bp_value 0x%"
PRIx32
""
,
mips_m4k.c:639
mips_m4k_set_breakpoint()
LOG_DEBUG
(
"bpid: %"
PRIu32
,
breakpoint
->
unique_id
)
;
mips_m4k.c:643
mips_m4k_set_breakpoint()
LOG_DEBUG
(
"Invalid FP Comparator number in breakpoint (bpid: %"
PRIu32
")"
,
mips_m4k.c:743
mips_m4k_unset_breakpoint()
LOG_DEBUG
(
"bpid: %"
PRIu32
" - releasing hw: %d"
,
mips_m4k.c:747
mips_m4k_unset_breakpoint()
LOG_DEBUG
(
"bpid: %"
PRIu32
,
breakpoint
->
unique_id
)
;
mips_m4k.c:760
mips_m4k_unset_breakpoint()
LOG_DEBUG
(
"wp_num %i bp_value 0x%"
PRIx32
""
,
wp_num
,
comparator_list
[
wp_num
]
.
bp_value
)
;
mips_m4k.c:929
mips_m4k_set_watchpoint()
LOG_DEBUG
(
"Invalid FP Comparator number in watchpoint"
)
;
mips_m4k.c:949
mips_m4k_unset_watchpoint()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", size: 0x%8.8"
PRIx32
", count: 0x%8.8"
PRIx32
""
,
mips_m4k.c:1013
mips_m4k_read_memory()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", size: 0x%8.8"
PRIx32
", count: 0x%8.8"
PRIx32
""
,
mips_m4k.c:1078
mips_m4k_write_memory()
LOG_DEBUG
(
"PIC32 Detected - using EJTAG Interface"
)
;
mips_m4k.c:1183
mips_m4k_examine()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", count: 0x%8.8"
PRIx32
""
,
mips_m4k.c:1205
mips_m4k_bulk_write_memory()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", count: 0x%8.8"
PRIx32
""
,
mips_m4k.c:1271
mips_m4k_bulk_read_memory()
LOG_DEBUG
(
"entered debug state at PC 0x%"
PRIx64
", target->state: %s"
,
mips_mips64.c:64
mips_mips64_debug_entry()
LOG_DEBUG
(
"Reset Detected"
)
;
mips_mips64.c:90
mips_mips64_poll()
LOG_DEBUG
(
"target->state: %s"
,
mips_mips64.c:121
mips_mips64_halt()
LOG_DEBUG
(
"target was already halted"
)
;
mips_mips64.c:125
mips_mips64_halt()
LOG_DEBUG
(
"target->state: %s"
,
mips_mips64.c:160
mips_mips64_assert_reset()
LOG_DEBUG
(
"target->state: %s"
,
mips_mips64.c:199
mips_mips64_deassert_reset()
LOG_DEBUG
(
"ERROR Can not find free FP Comparator(bpid: %"
PRIu32
")"
,
mips_mips64.c:244
mips_mips64_set_hwbp()
LOG_DEBUG
(
"bpid: %"
PRIu32
", bp_num %i bp_value 0x%"
PRIx64
,
bp
->
unique_id
,
mips_mips64.c:271
mips_mips64_set_hwbp()
LOG_DEBUG
(
"bpid: %"
PRIu32
,
bp
->
unique_id
)
;
mips_mips64.c:351
mips_mips64_set_breakpoint()
LOG_DEBUG
(
"wp_num %i bp_value 0x%"
PRIx64
""
,
wp_num
,
c
->
bp_value
)
;
mips_mips64.c:476
mips_mips64_set_watchpoint()
LOG_DEBUG
(
"Invalid FP Comparator number in breakpoint (bpid: %"
PRIu32
")"
,
mips_mips64.c:507
mips_mips64_unset_hwbp()
LOG_DEBUG
(
"bpid: %"
PRIu32
" - releasing hw: %d"
,
bp
->
unique_id
,
bp_num
)
;
mips_mips64.c:512
mips_mips64_unset_hwbp()
LOG_DEBUG
(
"bpid: %"
PRIu32
,
bp
->
unique_id
)
;
mips_mips64.c:572
mips_mips64_unset_breakpoint()
LOG_DEBUG
(
"unset breakpoint at 0x%16.16"
PRIx64
""
,
mips_mips64.c:645
mips_mips64_resume()
LOG_DEBUG
(
"target resumed at 0x%"
PRIx64
""
,
resume_pc
)
;
mips_mips64.c:685
mips_mips64_resume()
LOG_DEBUG
(
"target debug resumed at 0x%"
PRIx64
""
,
resume_pc
)
;
mips_mips64.c:693
mips_mips64_resume()
LOG_DEBUG
(
"target stepped "
)
;
mips_mips64.c:770
mips_mips64_step()
LOG_DEBUG
(
"Invalid FP Comparator number in watchpoint"
)
;
mips_mips64.c:834
mips_mips64_unset_watchpoint()
LOG_DEBUG
(
"address: 0x%16.16"
PRIx64
", size: 0x%8.8"
PRIx32
", count: 0x%8.8"
PRIx32
""
,
mips_mips64.c:914
mips_mips64_read_memory()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", count: 0x%8.8"
PRIx32
""
,
mips_mips64.c:952
mips_mips64_bulk_write_memory()
LOG_DEBUG
(
"address: 0x%16.16"
PRIx64
", size: 0x%8.8"
PRIx32
", count: 0x%8.8"
PRIx32
""
,
mips_mips64.c:1069
mips_mips64_write_memory()
LOG_DEBUG
(
"-"
)
;
mpsse.c:427
mpsse_purge()
LOG_DEBUG_IO
(
"%02x"
,
data
)
;
mpsse.c:460
buffer_write_byte()
LOG_DEBUG_IO
(
"%d bits"
,
bit_count
)
;
mpsse.c:468
buffer_write()
LOG_DEBUG_IO
(
"%d bits, offset %d"
,
bit_count
,
offset
)
;
mpsse.c:478
buffer_add_read()
LOG_DEBUG_IO
(
"%s%s %d bits"
,
in
?
"in"
:
""
,
out
?
"out"
:
""
,
length
)
;
mpsse.c:502
mpsse_clock_data()
LOG_DEBUG_IO
(
"Ignoring command due to previous error"
)
;
mpsse.c:505
mpsse_clock_data()
LOG_DEBUG_IO
(
"%sout %d bits, tdi=%d"
,
in
?
"in"
:
""
,
length
,
tdi
)
;
mpsse.c:578
mpsse_clock_tms_cs()
LOG_DEBUG_IO
(
"Ignoring command due to previous error"
)
;
mpsse.c:582
mpsse_clock_tms_cs()
LOG_DEBUG_IO
(
"-"
)
;
mpsse.c:628
mpsse_set_data_bits_low_byte()
LOG_DEBUG_IO
(
"Ignoring command due to previous error"
)
;
mpsse.c:631
mpsse_set_data_bits_low_byte()
LOG_DEBUG_IO
(
"-"
)
;
mpsse.c:645
mpsse_set_data_bits_high_byte()
LOG_DEBUG_IO
(
"Ignoring command due to previous error"
)
;
mpsse.c:648
mpsse_set_data_bits_high_byte()
LOG_DEBUG_IO
(
"-"
)
;
mpsse.c:662
mpsse_read_data_bits_low_byte()
LOG_DEBUG_IO
(
"Ignoring command due to previous error"
)
;
mpsse.c:665
mpsse_read_data_bits_low_byte()
LOG_DEBUG_IO
(
"-"
)
;
mpsse.c:678
mpsse_read_data_bits_high_byte()
LOG_DEBUG_IO
(
"Ignoring command due to previous error"
)
;
mpsse.c:681
mpsse_read_data_bits_high_byte()
LOG_DEBUG_IO
(
"Ignoring command due to previous error"
)
;
mpsse.c:696
single_byte_boolean_helper()
LOG_DEBUG
(
"%s"
,
enable
?
"on"
:
"off"
)
;
mpsse.c:708
mpsse_loopback_config()
LOG_DEBUG
(
"%d"
,
divisor
)
;
mpsse.c:714
mpsse_set_divisor()
LOG_DEBUG_IO
(
"Ignoring command due to previous error"
)
;
mpsse.c:717
mpsse_set_divisor()
LOG_DEBUG
(
"%s"
,
enable
?
"on"
:
"off"
)
;
mpsse.c:734
mpsse_divide_by_5_config()
LOG_DEBUG
(
"%s"
,
enable
?
"on"
:
"off"
)
;
mpsse.c:745
mpsse_rtck_config()
LOG_DEBUG
(
"target %d Hz"
,
frequency
)
;
mpsse.c:753
mpsse_set_frequency()
LOG_DEBUG
(
"actually %d Hz"
,
frequency
)
;
mpsse.c:777
mpsse_set_frequency()
DEBUG_PRINT_BUF
(
transfer
->
buffer
,
transfer
->
actual_length
)
;
mpsse.c:796
read_cb()
LOG_DEBUG_IO
(
"raw chunk %d, transferred %d of %d"
,
transfer
->
actual_length
,
res
->
transferred
,
mpsse.c:819
read_cb()
LOG_DEBUG_IO
(
"transferred %d of %d"
,
res
->
transferred
,
ctx
->
write_count
)
;
mpsse.c:834
write_cb()
DEBUG_PRINT_BUF
(
transfer
->
buffer
,
transfer
->
actual_length
)
;
mpsse.c:836
write_cb()
LOG_DEBUG_IO
(
"Ignoring flush due to previous error"
)
;
mpsse.c:853
mpsse_flush()
LOG_DEBUG_IO
(
"write %d%s, read %d"
,
ctx
->
write_count
,
ctx
->
read_count
?
"+1"
:
""
,
mpsse.c:859
mpsse_flush()
LOG_DEBUG
(
"status: 0x%08"
PRIx32
,
regval
)
;
mrvlqspi.c:150
mrvlqspi_set_ss_state()
LOG_DEBUG
(
"status: 0x%08"
PRIx32
,
regval
)
;
mrvlqspi.c:205
mrvlqspi_stop_transfer()
LOG_DEBUG
(
"status: 0x%08"
PRIx32
,
regval
)
;
mrvlqspi.c:234
mrvlqspi_stop_transfer()
LOG_DEBUG
(
"status: 0x%08"
PRIX32
,
val
)
;
mrvlqspi.c:275
mrvlqspi_fifo_flush()
LOG_DEBUG
(
"status: 0x%08"
PRIx32
,
val
)
;
mrvlqspi.c:299
mrvlqspi_read_byte()
LOG_DEBUG
(
"Getting ID"
)
;
mrvlqspi.c:407
mrvlqspi_read_id()
LOG_DEBUG
(
"ID is 0x%02"
PRIx8
" 0x%02"
PRIx8
" 0x%02"
PRIx8
,
mrvlqspi.c:444
mrvlqspi_read_id()
LOG_DEBUG
(
"erase from sector %u to sector %u"
,
first
,
last
)
;
mrvlqspi.c:526
mrvlqspi_flash_erase()
LOG_DEBUG
(
"Chip supports the bulk erase command."
mrvlqspi.c:555
mrvlqspi_flash_erase()
LOG_DEBUG
(
"offset=0x%08"
PRIx32
" count=0x%08"
PRIx32
,
mrvlqspi.c:590
mrvlqspi_flash_write()
LOG_DEBUG
(
"part of spare block will be overridden by hardware ECC generator"
)
;
mx3.c:409
imx31_write_page()
LOG_DEBUG
(
"main area read with 1 (correctable) error"
)
;
mx3.c:672
do_data_output()
LOG_DEBUG
(
"main area read with more than 1 (incorrectable) error"
)
;
mx3.c:675
do_data_output()
LOG_DEBUG
(
"spare area read with 1 (correctable) error"
)
;
mx3.c:680
do_data_output()
LOG_DEBUG
(
"main area read with more than 1 (incorrectable) error"
)
;
mx3.c:683
do_data_output()
LOG_DEBUG
(
"BI-swap enabled"
)
;
mxc.c:132
mxc_nand_device_command()
LOG_DEBUG
(
"MXC_NF : bus is 16-bit width"
)
;
mxc.c:241
mxc_init()
LOG_DEBUG
(
"MXC_NF : bus is 8-bit width"
)
;
mxc.c:243
mxc_init()
LOG_DEBUG
(
"MXC_NF : NAND controller can handle pagesize of 2048"
)
;
mxc.c:255
mxc_init()
LOG_DEBUG
(
"part of spare block will be overridden "
mxc.c:497
mxc_write_page()
LOG_DEBUG
(
"MXC_NF : work in Big Endian mode"
)
;
mxc.c:709
initialize_nf_controller()
LOG_DEBUG
(
"MXC_NF : work in Little Endian mode"
)
;
mxc.c:712
initialize_nf_controller()
LOG_DEBUG
(
"MXC_NF : work with ECC mode"
)
;
mxc.c:714
initialize_nf_controller()
LOG_DEBUG
(
"MXC_NF : work without ECC mode"
)
;
mxc.c:717
initialize_nf_controller()
LOG_DEBUG
(
"Timed out waiting for NVMC_READY"
)
;
nrf5.c:401
nrf5_wait_for_nvmc()
LOG_DEBUG
(
"Couldn't read FICR INFO.PART register"
)
;
nrf5.c:721
nrf5_read_ficr_info_part()
LOG_DEBUG
(
"FICR INFO likely not implemented. Invalid PART value 0x%08"
nrf5.c:755
nrf51_52_partno_check()
LOG_DEBUG
(
"Invalid FICR INFO PART value 0x%08"
nrf5.c:774
nrf53_91_partno_check()
LOG_DEBUG
(
"Couldn't read FICR NUMRAMBLOCK register"
)
;
nrf5.c:813
nrf51_get_ram_size()
LOG_DEBUG
(
"FICR NUMRAMBLOCK strange value %"
PRIx32
,
numramblock
)
;
nrf5.c:818
nrf51_get_ram_size()
LOG_DEBUG
(
"Couldn't read FICR NUMRAMBLOCK register"
)
;
nrf5.c:826
nrf51_get_ram_size()
LOG_DEBUG
(
"FICR SIZERAMBLOCK strange value %"
PRIx32
,
sizeramblock
)
;
nrf5.c:830
nrf51_get_ram_size()
LOG_DEBUG
(
"Couldn't read some of FICR INFO registers"
)
;
nrf5.c:916
nrf5_probe_chip()
LOG_DEBUG
(
"Couldn't read FICR CONFIGID register, using FICR INFO"
)
;
nrf5.c:933
nrf5_probe_chip()
LOG_DEBUG
(
"Erasing page at 0x%"
PRIx32
,
sector
->
offset
)
;
nrf5.c:1070
nrf5_erase_page()
LOG_DEBUG
(
"Writing buffer to flash address=0x%"
PRIx32
" bytes=0x%"
PRIx32
,
address
,
bytes
)
;
nrf5.c:1143
nrf5_ll_flash_write()
LOG_DEBUG
(
"NuMicro arm architecture: armv7m\n"
)
;
numicro.c:548
numicro_get_arm_arch()
LOG_DEBUG
(
"NuMicro arm architecture: armv6m\n"
)
;
numicro.c:552
numicro_get_arm_arch()
LOG_DEBUG
(
"protected = 0x%08"
PRIx32
""
,
is_protected
)
;
numicro.c:570
numicro_reg_unlock()
LOG_DEBUG
(
"protection removed"
)
;
numicro.c:589
numicro_reg_unlock()
LOG_DEBUG
(
"still protected!!"
)
;
numicro.c:591
numicro_reg_unlock()
LOG_DEBUG
(
"timed out waiting for flash"
)
;
numicro.c:669
numicro_fmc_cmd()
LOG_DEBUG
(
"CONFIG0: 0x%"
PRIx32
",CONFIG1: 0x%"
PRIx32
""
,
config
[
0
]
,
config
[
1
]
)
;
numicro.c:831
numicro_protect_check()
LOG_DEBUG
(
"erasing sector %u at address "
TARGET_ADDR_FMT
,
i
,
bank
->
base
+
bank
->
sectors
[
i
]
.
offset
)
;
numicro.c:879
numicro_erase()
LOG_DEBUG
(
"timed out waiting for flash"
)
;
numicro.c:900
numicro_erase()
LOG_DEBUG
(
"failure: 0x%"
PRIx32
""
,
status
)
;
numicro.c:911
numicro_erase()
LOG_DEBUG
(
"Erase done."
)
;
numicro.c:920
numicro_erase()
LOG_DEBUG
(
"timed out waiting for flash"
)
;
numicro.c:996
numicro_write()
LOG_DEBUG
(
"failure: 0x%"
PRIx32
""
,
status
)
;
numicro.c:1010
numicro_write()
LOG_DEBUG
(
"Write OK"
)
;
numicro.c:1018
numicro_write()
LOG_DEBUG
(
"Write done."
)
;
numicro.c:1022
numicro_write()
LOG_DEBUG
(
"Nuvoton NuMicro: Probed ..."
)
;
numicro.c:1103
numicro_probe()
LOG_DEBUG
(
"add flash_bank numicro %s"
,
bank
->
name
)
;
numicro.c:1126
numicro_flash_bank_command()
LOG_DEBUG
(
"Hash table size (g_npidhash) = %"
PRId32
,
npidhash
)
;
nuttx.c:216
nuttx_update_threads()
LOG_DEBUG
(
"Hash table address (g_pidhash) = %"
PRIx32
,
pidhashaddr
)
;
nuttx.c:224
nuttx_update_threads()
LOG_DEBUG_IO
(
"runtest %u cycles, end in %i"
,
cmd
->
cmd
.
runtest
->
num_cycles
,
opendous.c:251
opendous_execute_queue()
LOG_DEBUG_IO
(
"statemove end in %i"
,
cmd
->
cmd
.
statemove
->
end_state
)
;
opendous.c:260
opendous_execute_queue()
LOG_DEBUG_IO
(
"pathmove: %u states, end in %i"
,
opendous.c:268
opendous_execute_queue()
LOG_DEBUG_IO
(
"scan end in %i"
,
cmd
->
cmd
.
scan
->
end_state
)
;
opendous.c:276
opendous_execute_queue()
LOG_DEBUG_IO
(
"scan input, length = %d"
,
scan_size
)
;
opendous.c:282
opendous_execute_queue()
LOG_DEBUG_IO
(
"reset trst: %i srst %i"
,
cmd
->
cmd
.
reset
->
trst
,
cmd
->
cmd
.
reset
->
srst
)
;
opendous.c:292
opendous_execute_queue()
tap_set_state
(
TAP_RESET
)
;
opendous.c:297
opendous_execute_queue()
LOG_DEBUG_IO
(
"sleep %"
PRIu32
,
cmd
->
cmd
.
sleep
->
us
)
;
opendous.c:302
opendous_execute_queue()
tap_set_state
(
tap_get_end_state
(
)
)
;
opendous.c:419
opendous_state_move()
tap_set_state
(
path
[
i
]
)
;
opendous.c:435
opendous_path_move()
tap_set_state
(
ir_scan
?
TAP_IRPAUSE
:
TAP_DRPAUSE
)
;
opendous.c:483
opendous_scan()
LOG_DEBUG
(
"trst: %i, srst: %i"
,
trst
,
srst
)
;
opendous.c:491
opendous_reset()
LOG_DEBUG_IO
(
"0x%02x 0x%02x"
,
command
,
_data
)
;
opendous.c:515
opendous_simple_command()
LOG_DEBUG_IO
(
"append scan, length = %d"
,
length
)
;
opendous.c:584
opendous_tap_append_scan()
LOG_DEBUG_IO
(
"pending scan result, length = %d"
,
length
)
;
opendous.c:666
opendous_tap_execute()
LOG_DEBUG_IO
(
"opendous_usb_write, out_length = %d, result = %d"
,
out_length
,
result
)
;
opendous.c:760
opendous_usb_write()
LOG_DEBUG_IO
(
"opendous_usb_read, result = %d"
,
result
)
;
opendous.c:792
opendous_usb_read()
LOG_DEBUG
(
"Debug Adapter init complete"
)
;
openocd.c:133
handle_init_command()
LOG_DEBUG
(
"Examining targets..."
)
;
openocd.c:150
handle_init_command()
LOG_DEBUG
(
"target examination failed"
)
;
openocd.c:152
handle_init_command()
LOG_DEBUG
(
"log_init: complete"
)
;
openocd.c:238
setup_command_handler()
LOG_DEBUG
(
"command registration: complete"
)
;
openocd.c:268
setup_command_handler()
LOG_DEBUG
(
"BINDIR = %s"
,
BINDIR
)
;
options.c:122
find_exe_path()
LOG_DEBUG
(
"bindir=%s"
,
BINDIR
)
;
options.c:234
add_default_dirs()
LOG_DEBUG
(
"pkgdatadir=%s"
,
PKGDATADIR
)
;
options.c:235
add_default_dirs()
LOG_DEBUG
(
"exepath=%s"
,
exepath
)
;
options.c:236
add_default_dirs()
LOG_DEBUG
(
"bin2data=%s"
,
bin2data
)
;
options.c:237
add_default_dirs()
LOG_DEBUG
(
"ARGV[%d] = \"%s\""
,
i
,
argv
[
i
]
)
;
options.c:355
parse_cmdline_args()
LOG_DEBUG
(
"-"
)
;
or1k.c:246
or1k_create_reg_list()
LOG_DEBUG
(
"-"
)
;
or1k.c:311
or1k_jtag_read_regs()
LOG_DEBUG
(
"-"
)
;
or1k.c:322
or1k_jtag_write_regs()
LOG_DEBUG
(
"-"
)
;
or1k.c:336
or1k_save_context()
LOG_DEBUG
(
"-"
)
;
or1k.c:370
or1k_restore_context()
LOG_DEBUG
(
"-"
)
;
or1k.c:407
or1k_read_core_reg()
LOG_DEBUG
(
"Read core reg %i value 0x%08"
PRIx32
,
num
,
reg_value
)
;
or1k.c:415
or1k_read_core_reg()
LOG_DEBUG
(
"Read spr reg %i value 0x%08"
PRIx32
,
num
,
reg_value
)
;
or1k.c:427
or1k_read_core_reg()
LOG_DEBUG
(
"-"
)
;
or1k.c:437
or1k_write_core_reg()
LOG_DEBUG
(
"Write core reg %i value 0x%08"
PRIx32
,
num
,
reg_value
)
;
or1k.c:444
or1k_write_core_reg()
LOG_DEBUG
(
"-"
)
;
or1k.c:456
or1k_get_core_reg()
LOG_DEBUG
(
"-"
)
;
or1k.c:472
or1k_set_core_reg()
LOG_DEBUG
(
"-"
)
;
or1k.c:509
or1k_build_reg_cache()
LOG_DEBUG
(
"-"
)
;
or1k.c:546
or1k_debug_entry()
LOG_DEBUG
(
"target->state: %s"
,
or1k.c:570
or1k_halt()
LOG_DEBUG
(
"Target was already halted"
)
;
or1k.c:574
or1k_halt()
LOG_DEBUG
(
"-"
)
;
or1k.c:714
or1k_assert_reset()
LOG_DEBUG
(
"-"
)
;
or1k.c:730
or1k_deassert_reset()
LOG_DEBUG
(
"-"
)
;
or1k.c:746
or1k_soft_reset_halt()
LOG_DEBUG
(
"-"
)
;
or1k.c:769
is_any_soft_breakpoint()
LOG_DEBUG
(
"Addr: 0x%"
PRIx32
", stepping: %s, handle breakpoints %s\n"
,
or1k.c:788
or1k_resume_or_step()
LOG_DEBUG
(
"Unset breakpoint at 0x%08"
TARGET_PRIxADDR
,
breakpoint
->
address
)
;
or1k.c:853
or1k_resume_or_step()
LOG_DEBUG
(
"Target resumed at 0x%08"
PRIx32
,
resume_pc
)
;
or1k.c:878
or1k_resume_or_step()
LOG_DEBUG
(
"Target debug resumed at 0x%08"
PRIx32
,
resume_pc
)
;
or1k.c:882
or1k_resume_or_step()
LOG_DEBUG
(
"Adding breakpoint: addr 0x%08"
TARGET_PRIxADDR
", len %d, type %d, id: %"
PRIu32
,
or1k.c:915
or1k_add_breakpoint()
LOG_DEBUG
(
"Removing breakpoint: addr 0x%08"
TARGET_PRIxADDR
", len %d, type %d, id: %"
PRIu32
,
or1k.c:973
or1k_remove_breakpoint()
LOG_DEBUG
(
"Read memory at 0x%08"
TARGET_PRIxADDR
", size: %"
PRIu32
", count: 0x%08"
PRIx32
,
address
,
size
,
count
)
;
or1k.c:1026
or1k_read_memory()
LOG_DEBUG
(
"Write memory at 0x%08"
TARGET_PRIxADDR
", size: %"
PRIu32
", count: 0x%08"
PRIx32
,
address
,
size
,
count
)
;
or1k.c:1053
or1k_write_memory()
LOG_DEBUG
(
"Target is halted"
)
;
or1k.c:1140
or1k_examine()
LOG_DEBUG
(
"Add reg \"%s\" @ 0x%08"
PRIx32
", group \"%s\", feature \"%s\""
,
or1k.c:1357
or1k_addreg_command_handler()
LOG_DEBUG
(
"Init done"
)
;
or1k_du_adv.c:183
or1k_adv_jtag_init()
LOG_DEBUG
(
"Select module: %s"
,
chain_name
[
chain
]
)
;
or1k_du_adv.c:202
adbg_select_module()
LOG_DEBUG
(
"Write control register %"
PRId8
": 0x%08"
PRIx32
,
regidx
,
cmd_data
[
0
]
)
;
or1k_du_adv.c:285
adbg_ctrl_write()
LOG_DEBUG
(
"Doing burst read, word size %d, word count %d, start address 0x%08"
PRIx32
,
or1k_du_adv.c:421
adbg_wb_burst_read()
LOG_DEBUG
(
"CRC OK!"
)
;
or1k_du_adv.c:518
adbg_wb_burst_read()
LOG_DEBUG
(
"Doing burst write, word size %d, word count %d,"
or1k_du_adv.c:575
adbg_wb_burst_write()
LOG_DEBUG
(
"Tried WB burst write with invalid word size (%d),"
or1k_du_adv.c:588
adbg_wb_burst_write()
LOG_DEBUG
(
"Tried CPU0 burst write with invalid word size (%d),"
or1k_du_adv.c:597
adbg_wb_burst_write()
LOG_DEBUG
(
"Tried CPU1 burst write with invalid word size (%d),"
or1k_du_adv.c:606
adbg_wb_burst_write()
LOG_DEBUG
(
"CRC OK!\n"
)
;
or1k_du_adv.c:662
adbg_wb_burst_write()
LOG_DEBUG
(
"Reading WB%"
PRIu32
" at 0x%08"
PRIx32
,
size
*
8
,
addr
)
;
or1k_du_adv.c:839
or1k_adv_jtag_read_memory()
LOG_DEBUG
(
"Writing WB%"
PRIu32
" at 0x%08"
PRIx32
,
size
*
8
,
addr
)
;
or1k_du_adv.c:894
or1k_adv_jtag_write_memory()
LOG_DEBUG
(
"JSP transfer"
)
;
or1k_du_adv.c:965
or1k_adv_jtag_jsp_xfer()
LOG_DEBUG
(
"Initialising OpenCores JTAG TAP"
)
;
or1k_tap_mohor.c:21
or1k_tap_mohor_init()
LOG_DEBUG
(
"Initialising Altera Virtual JTAG TAP"
)
;
or1k_tap_vjtag.c:80
or1k_tap_vjtag_init()
LOG_DEBUG
(
"SLD HUB Configuration register"
)
;
or1k_tap_vjtag.c:205
or1k_tap_vjtag_init()
LOG_DEBUG
(
"------------------------------"
)
;
or1k_tap_vjtag.c:206
or1k_tap_vjtag_init()
LOG_DEBUG
(
"m_width = %d"
,
m_width
)
;
or1k_tap_vjtag.c:207
or1k_tap_vjtag_init()
LOG_DEBUG
(
"manufacturer_id = 0x%02"
PRIx32
,
MANUF
(
hub_info
)
)
;
or1k_tap_vjtag.c:208
or1k_tap_vjtag_init()
LOG_DEBUG
(
"nb_of_node = %d"
,
nb_nodes
)
;
or1k_tap_vjtag.c:209
or1k_tap_vjtag_init()
LOG_DEBUG
(
"version = %"
PRIu32
,
VER
(
hub_info
)
)
;
or1k_tap_vjtag.c:210
or1k_tap_vjtag_init()
LOG_DEBUG
(
"VIR length = %d"
,
guess_addr_width
(
nb_nodes
)
+
m_width
)
;
or1k_tap_vjtag.c:211
or1k_tap_vjtag_init()
LOG_DEBUG
(
"Node info register"
)
;
or1k_tap_vjtag.c:247
or1k_tap_vjtag_init()
LOG_DEBUG
(
"--------------------"
)
;
or1k_tap_vjtag.c:248
or1k_tap_vjtag_init()
LOG_DEBUG
(
"instance_id = %"
PRIu32
,
ID
(
node_info
)
)
;
or1k_tap_vjtag.c:249
or1k_tap_vjtag_init()
LOG_DEBUG
(
"manufacturer_id = 0x%02"
PRIx32
,
MANUF
(
node_info
)
)
;
or1k_tap_vjtag.c:250
or1k_tap_vjtag_init()
LOG_DEBUG
(
"node_id = %"
PRIu32
" (%s)"
,
ID
(
node_info
)
,
or1k_tap_vjtag.c:251
or1k_tap_vjtag_init()
LOG_DEBUG
(
"version = %"
PRIu32
,
VER
(
node_info
)
)
;
or1k_tap_vjtag.c:253
or1k_tap_vjtag_init()
LOG_DEBUG
(
"Initialising Xilinx Internal JTAG TAP"
)
;
or1k_tap_xilinx_bscan.c:21
or1k_tap_xilinx_bscan_init()
tap_set_state
(
path
[
i
]
)
;
osbdm.c:407
osbdm_add_pathmove()
tap_set_state
(
tap_get_end_state
(
)
)
;
osbdm.c:448
osbdm_add_statemove()
LOG_DEBUG
(
"OSBDM init"
)
;
osbdm.c:669
osbdm_init()
LOG_DEBUG
(
"status: 0x%"
PRIx32
,
status
)
;
pic32mm.c:235
pic32mm_wait_status_busy()
LOG_DEBUG
(
"timeout: status: 0x%"
PRIx32
,
status
)
;
pic32mm.c:239
pic32mm_wait_status_busy()
LOG_DEBUG
(
"Erasing entire program flash"
)
;
pic32mm.c:398
pic32mm_erase()
LOG_DEBUG
(
"timeout waiting for unlock: 0x%"
PRIx8
""
,
mchip_cmd
)
;
pic32mm.c:1040
pic32mm_handle_unlock_command()
LOG_DEBUG
(
"status: 0x%"
PRIx32
,
status
)
;
pic32mx.c:225
pic32mx_wait_status_busy()
LOG_DEBUG
(
"timeout: status: 0x%"
PRIx32
,
status
)
;
pic32mx.c:229
pic32mx_wait_status_busy()
LOG_DEBUG
(
"Erasing entire program flash"
)
;
pic32mx.c:327
pic32mx_erase()
LOG_DEBUG
(
"writing to flash at address "
TARGET_ADDR_FMT
" at offset 0x%8.8"
PRIx32
pic32mx.c:610
pic32mx_write()
LOG_DEBUG
(
"timeout waiting for unlock: 0x%"
PRIx8
""
,
mchip_cmd
)
;
pic32mx.c:903
pic32mx_handle_unlock_command()
LOG_DEBUG_IO
(
"Flush %d transactions"
,
(
int
)
picoprobe_queue_length
)
;
picoprobe.c:113
picoprobe_flush()
LOG_DEBUG_IO
(
"Read %d bytes from probe"
,
ret
)
;
picoprobe.c:182
picoprobe_flush()
LOG_DEBUG_IO
(
"Processing read of %d bits"
,
read_hdr
->
bits
)
;
picoprobe.c:208
picoprobe_flush()
LOG_DEBUG_IO
(
"Picoprobe queue len %d -> %d"
,
(
int
)
picoprobe_queue_length
,
picoprobe.c:233
picoprobe_read_write_bits()
LOG_DEBUG_IO
(
"Write %d bits @ offset %d"
,
length
,
offset
)
;
picoprobe.c:249
picoprobe_write_bits()
LOG_DEBUG_IO
(
"Read %d bits @ offset %d"
,
length
,
offset
)
;
picoprobe.c:255
picoprobe_read_bits()
LOG_DEBUG_IO
(
"Executing %zu queued transactions"
,
swd_cmd_queue_length
)
;
picoprobe.c:265
picoprobe_swd_run_queue()
LOG_DEBUG_IO
(
"Skipping due to previous errors: %d"
,
queued_retval
)
;
picoprobe.c:271
picoprobe_swd_run_queue()
LOG_DEBUG_IO
(
"trn_ack_data_parity_trn:"
)
;
picoprobe.c:283
picoprobe_swd_run_queue()
LOG_DEBUG_IO
(
"BYTE %d 0x%x"
,
(
int
)
y
,
swd_cmd_queue
[
i
]
.
trn_ack_data_parity_trn
[
y
]
)
;
picoprobe.c:285
picoprobe_swd_run_queue()
LOG_DEBUG_IO
(
"%s %s %s reg %X = %08"
PRIx32
,
picoprobe.c:289
picoprobe_swd_run_queue()
LOG_DEBUG
(
"Add %d idle cycles"
,
ap_delay_clk
)
;
picoprobe.c:363
picoprobe_swd_queue_cmd()
LOG_DEBUG_IO
(
"SWD line reset"
)
;
picoprobe.c:440
picoprobe_swd_switch_seq()
LOG_DEBUG
(
"JTAG-to-SWD"
)
;
picoprobe.c:444
picoprobe_swd_switch_seq()
LOG_DEBUG
(
"SWD-to-JTAG"
)
;
picoprobe.c:448
picoprobe_swd_switch_seq()
LOG_DEBUG
(
"DORMANT-to-SWD"
)
;
picoprobe.c:452
picoprobe_swd_switch_seq()
LOG_DEBUG
(
"SWD-to-DORMANT"
)
;
picoprobe.c:456
picoprobe_swd_switch_seq()
LOG_DEBUG
(
"Initializing PLDs..."
)
;
pld.c:337
handle_pld_init_command()
LOG_DEBUG
(
"debug_buffer[%02x] = DASM(0x%08x)"
,
i
,
program
->
debug_buffer
[
i
]
)
;
program.c:35
riscv_program_write()
LOG_DEBUG
(
"Saving register %d as used by program"
,
(
int
)
i
)
;
program.c:51
riscv_program_exec()
LOG_DEBUG
(
"Unable to execute program %p"
,
p
)
;
program.c:70
riscv_program_exec()
LOG_DEBUG
(
"no working area for sysreq code"
)
;
psoc4.c:252
psoc4_sysreq()
LOG_DEBUG
(
"SYSREQ %02"
PRIx8
" %04"
PRIx16
" %08"
PRIx32
" size %"
PRIu32
,
psoc4.c:268
psoc4_sysreq()
LOG_DEBUG
(
"SYSREQ %02"
PRIx8
" %04"
PRIx16
" %08"
PRIx32
,
psoc4.c:295
psoc4_sysreq()
LOG_DEBUG
(
"offset / row: 0x%08"
PRIx32
" / %"
PRIu32
", size %"
PRIu32
""
,
psoc4.c:661
psoc4_write()
LOG_DEBUG
(
"SPCIF geometry: %"
PRIu32
" KiB flash, row %"
PRIu32
" bytes."
,
psoc4.c:772
psoc4_probe()
LOG_DEBUG
(
"flash bank set %"
PRIu32
" rows"
,
num_rows
)
;
psoc4.c:816
psoc4_probe()
LOG_DEBUG
(
"PANTHER_DEVICE_ID = 0x%08"
PRIX32
,
device_id
)
;
psoc5lp.c:256
psoc5lp_find_device()
LOG_DEBUG
(
"Get_Temp: sign 0x%02"
PRIx8
", magnitude 0x%02"
PRIx8
,
psoc5lp.c:870
psoc5lp_eeprom_write()
LOG_DEBUG
(
"Padding %"
PRIu32
" bytes"
,
EEPROM_ROW_SIZE
-
byte_count
)
;
psoc5lp.c:895
psoc5lp_eeprom_write()
LOG_DEBUG
(
"Skipping duplicate erase of sectors %u to %u"
,
psoc5lp.c:1033
psoc5lp_erase()
LOG_DEBUG
(
"Get_Temp: sign 0x%02"
PRIx8
", magnitude 0x%02"
PRIx8
,
psoc5lp.c:1152
psoc5lp_write()
LOG_DEBUG
(
"Writing load command for array %u row %u at "
TARGET_ADDR_FMT
,
psoc5lp.c:1188
psoc5lp_write()
LOG_DEBUG
(
"Padding %d bytes"
,
ROW_SIZE
-
len
)
;
psoc5lp.c:1211
psoc5lp_write()
LOG_DEBUG
(
"row[%u][%02u] = 0x%02"
PRIx8
,
i
,
k
,
row_data
[
k
]
)
;
psoc5lp.c:1345
psoc5lp_protect_check()
LOG_DEBUG
(
"NVL[%d] = 0x%02"
PRIx8
,
3
,
nvl
[
3
]
)
;
psoc5lp.c:1434
psoc5lp_probe()
LOG_DEBUG
(
"Erasing SECTOR @%08"
PRIX32
,
addr
)
;
psoc6.c:644
psoc6_erase_sector()
LOG_DEBUG
(
"Erasing ROW @%08"
PRIX32
,
addr
)
;
psoc6.c:673
psoc6_erase_row()
LOG_DEBUG
(
"Programming ROW @%08"
PRIX32
,
addr
)
;
psoc6.c:772
psoc6_program_row()
LOG_DEBUG
(
"Error reading reg at "
TARGET_ADDR_FMT
qn908x.c:246
qn908x_update_reg()
LOG_DEBUG
(
"Error writing reg at "
TARGET_ADDR_FMT
" with 0x%08"
qn908x.c:254
qn908x_update_reg()
LOG_DEBUG
(
"Updated reg at "
TARGET_ADDR_FMT
": ?? -> 0x%.08"
qn908x.c:259
qn908x_update_reg()
LOG_DEBUG
(
"Updated reg at "
TARGET_ADDR_FMT
": 0x%.08"
PRIx32
qn908x.c:262
qn908x_update_reg()
LOG_DEBUG
(
"LOCK_STAT_%d = 0x%08"
PRIx32
,
i
,
lock_stat
)
;
qn908x.c:291
qn908x_load_lock_stat()
LOG_DEBUG
(
"Clock clk_sel=0x%08"
PRIu32
,
clk_sel
)
;
qn908x.c:307
qn908x_init_flash()
LOG_DEBUG
(
"Core freq: %"
PRIu32
" Hz | AHB freq: %"
PRIu32
" Hz"
,
qn908x.c:338
qn908x_init_flash()
LOG_DEBUG
(
"Flash protection = 0x%02"
PRIx8
,
qn908x.c:409
qn908x_read_page_lock()
LOG_DEBUG
(
"Erasing page %"
PRIu32
" of block %"
PRIu32
,
qn908x.c:547
qn908x_erase()
LOG_DEBUG
(
"protect set=%d bits[%d] with mask=0x%02x"
,
set
,
i
,
mask
)
;
qn908x.c:646
qn908x_protect()
LOG_DEBUG
(
"computed image checksum: 0x%8.8"
PRIx32
,
checksum
)
;
qn908x.c:691
qn908x_write()
LOG_DEBUG
(
"Code Read Protection = 0x%08"
PRIx32
,
crp
)
;
qn908x.c:713
qn908x_write()
LOG_DEBUG
(
"auto_probe"
)
;
qn908x.c:920
qn908x_auto_probe()
LOG_DEBUG
(
"LOCK_STAT_8 before erasing: 0x%"
PRIx32
,
lock_stat_8
)
;
qn908x.c:1062
qn908x_handle_mass_erase_command()
LOG_DEBUG
(
"Erasing both blocks with command 0x%"
PRIx32
,
erase_cmd
)
;
qn908x.c:1083
qn908x_handle_mass_erase_command()
LOG_DEBUG
(
"reading buffer of %"
PRIu32
" byte at 0x%8.8"
PRIx32
,
renesas_rpchf.c:616
rpchf_read()
LOG_DEBUG
(
"DTMCONTROL: 0x%x -> 0x%x"
,
out
,
in
)
;
riscv-011.c:307
dtmcontrol_scan()
LOG_DEBUG
(
"IDCODE: 0x0 -> 0x%x"
,
in
)
;
riscv-011.c:334
idcode_scan()
LOG_DEBUG
(
"dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d"
,
riscv-011.c:343
increase_dbus_busy_delay()
LOG_DEBUG
(
"dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d"
,
riscv-011.c:354
increase_interrupt_high_delay()
if
(
debug_level
<
LOG_LVL_DEBUG
)
riscv-011.c:397
dump_field()
log_printf_lf
(
LOG_LVL_DEBUG
,
riscv-011.c:413
dump_field()
LOG_DEBUG
(
"cache[0x%x] = 0x%08x: DASM(0x%x) (hit)"
,
index
,
data
,
data
)
;
riscv-011.c:772
cache_set32()
LOG_DEBUG
(
"cache[0x%x] = 0x%08x: DASM(0x%x)"
,
index
,
data
,
data
)
;
riscv-011.c:775
cache_set32()
LOG_DEBUG
(
"enter"
)
;
riscv-011.c:864
cache_write()
LOG_DEBUG
(
"exit"
)
;
riscv-011.c:986
cache_write()
LOG_DEBUG
(
"csr 0x%x = 0x%"
PRIx64
,
csr
,
*
value
)
;
riscv-011.c:1046
read_remote_csr()
LOG_DEBUG
(
"csr 0x%x <- 0x%"
PRIx64
,
csr
,
value
)
;
riscv-011.c:1061
write_remote_csr()
LOG_DEBUG
(
"step=%d"
,
step
)
;
riscv-011.c:1114
execute_resume()
LOG_DEBUG
(
"%s = 0x%"
PRIx64
,
r
->
name
,
value
)
;
riscv-011.c:1213
reg_cache_get()
LOG_DEBUG
(
"%s <= 0x%"
PRIx64
,
r
->
name
,
value
)
;
riscv-011.c:1221
reg_cache_set()
LOG_DEBUG
(
"reg[%d]=0x%"
PRIx64
,
regnum
,
*
value
)
;
riscv-011.c:1265
register_read()
LOG_DEBUG
(
"riscv_halt()"
)
;
riscv-011.c:1392
halt()
LOG_DEBUG
(
"riscv_deinit_target()"
)
;
riscv-011.c:1410
deinit_target()
LOG_DEBUG
(
"enter"
)
;
riscv-011.c:1421
strict_step()
LOG_DEBUG
(
"dtmcontrol=0x%x"
,
dtmcontrol
)
;
riscv-011.c:1473
examine()
LOG_DEBUG
(
" addrbits=%d"
,
get_field
(
dtmcontrol
,
DTMCONTROL_ADDRBITS
)
)
;
riscv-011.c:1474
examine()
LOG_DEBUG
(
" version=%d"
,
get_field
(
dtmcontrol
,
DTMCONTROL_VERSION
)
)
;
riscv-011.c:1475
examine()
LOG_DEBUG
(
" idle=%d"
,
get_field
(
dtmcontrol
,
DTMCONTROL_IDLE
)
)
;
riscv-011.c:1476
examine()
LOG_DEBUG
(
"dminfo: 0x%08x"
,
dminfo
)
;
riscv-011.c:1500
examine()
LOG_DEBUG
(
" abussize=0x%x"
,
get_field
(
dminfo
,
DMINFO_ABUSSIZE
)
)
;
riscv-011.c:1501
examine()
LOG_DEBUG
(
" serialcount=0x%x"
,
get_field
(
dminfo
,
DMINFO_SERIALCOUNT
)
)
;
riscv-011.c:1502
examine()
LOG_DEBUG
(
" access128=%d"
,
get_field
(
dminfo
,
DMINFO_ACCESS128
)
)
;
riscv-011.c:1503
examine()
LOG_DEBUG
(
" access64=%d"
,
get_field
(
dminfo
,
DMINFO_ACCESS64
)
)
;
riscv-011.c:1504
examine()
LOG_DEBUG
(
" access32=%d"
,
get_field
(
dminfo
,
DMINFO_ACCESS32
)
)
;
riscv-011.c:1505
examine()
LOG_DEBUG
(
" access16=%d"
,
get_field
(
dminfo
,
DMINFO_ACCESS16
)
)
;
riscv-011.c:1506
examine()
LOG_DEBUG
(
" access8=%d"
,
get_field
(
dminfo
,
DMINFO_ACCESS8
)
)
;
riscv-011.c:1507
examine()
LOG_DEBUG
(
" dramsize=0x%x"
,
get_field
(
dminfo
,
DMINFO_DRAMSIZE
)
)
;
riscv-011.c:1508
examine()
LOG_DEBUG
(
" authenticated=0x%x"
,
get_field
(
dminfo
,
DMINFO_AUTHENTICATED
)
)
;
riscv-011.c:1509
examine()
LOG_DEBUG
(
" authbusy=0x%x"
,
get_field
(
dminfo
,
DMINFO_AUTHBUSY
)
)
;
riscv-011.c:1510
examine()
LOG_DEBUG
(
" authtype=0x%x"
,
get_field
(
dminfo
,
DMINFO_AUTHTYPE
)
)
;
riscv-011.c:1511
examine()
LOG_DEBUG
(
" version=0x%x"
,
get_field
(
dminfo
,
DMINFO_VERSION
)
)
;
riscv-011.c:1512
examine()
LOG_DEBUG
(
"Discovered XLEN is %d"
,
riscv_xlen
(
target
)
)
;
riscv-011.c:1569
examine()
if
(
debug_level
>=
LOG_LVL_DEBUG
)
riscv-011.c:1906
poll_target()
LOG_DEBUG
(
"debug running"
)
;
riscv-011.c:1913
poll_target()
LOG_DEBUG
(
"halting"
)
;
riscv-011.c:1919
poll_target()
LOG_DEBUG
(
"j=%d status=%d data=%09"
PRIx64
,
j
,
status
,
data
)
;
riscv-011.c:2092
read_memory()
LOG_DEBUG
(
"t0 is 0x%"
PRIx64
,
t0
)
;
riscv-011.c:2172
write_memory()
LOG_DEBUG
(
"init"
)
;
riscv-011.c:2374
init_target()
LOG_DEBUG
(
"[%d] Allocating new DM"
,
target
->
coreid
)
;
riscv-013.c:251
get_dm()
if
(
debug_level
<
LOG_LVL_DEBUG
)
riscv-013.c:377
dump_field()
log_printf_lf
(
LOG_LVL_DEBUG
,
riscv-013.c:390
dump_field()
log_printf_lf
(
LOG_LVL_DEBUG
,
__FILE__
,
__LINE__
,
"scan"
,
"%s -> %s"
,
riscv-013.c:401
dump_field()
LOG_DEBUG
(
"DTMCS: 0x%x -> 0x%x"
,
out
,
in
)
;
riscv-013.c:445
dtmcontrol_scan()
LOG_DEBUG
(
"dtmcs_idle=%d, dmi_busy_delay=%d, ac_busy_delay=%d"
,
riscv-013.c:454
increase_dmi_busy_delay()
LOG_DEBUG
(
"dtmcs_idle=%d, dmi_busy_delay=%d, ac_busy_delay=%d"
,
riscv-013.c:715
increase_ac_busy_delay()
if
(
debug_level
>=
LOG_LVL_DEBUG
)
{
riscv-013.c:775
execute_abstract_command()
LOG_DEBUG
(
"command=0x%x; access register, size=%d, postexec=%d, "
riscv-013.c:778
execute_abstract_command()
LOG_DEBUG
(
"command=0x%x"
,
command
)
;
riscv-013.c:788
execute_abstract_command()
LOG_DEBUG
(
"command 0x%x failed; abstractcs=0x%x"
,
command
,
abstractcs
)
;
riscv-013.c:801
execute_abstract_command()
LOG_DEBUG
(
"{%d} %s <- 0x%"
PRIx64
,
riscv_current_hartid
(
target
)
,
riscv-013.c:1299
register_write_direct()
LOG_DEBUG
(
"{%d} %s = 0x%"
PRIx64
,
riscv_current_hartid
(
target
)
,
riscv-013.c:1488
register_read_direct()
LOG_DEBUG
(
"riscv_deinit_target()"
)
;
riscv-013.c:1522
deinit_target()
LOG_DEBUG
(
"dtmcontrol=0x%x"
,
dtmcontrol
)
;
riscv-013.c:1567
examine()
LOG_DEBUG
(
" dmireset=%d"
,
get_field
(
dtmcontrol
,
DTM_DTMCS_DMIRESET
)
)
;
riscv-013.c:1568
examine()
LOG_DEBUG
(
" idle=%d"
,
get_field
(
dtmcontrol
,
DTM_DTMCS_IDLE
)
)
;
riscv-013.c:1569
examine()
LOG_DEBUG
(
" dmistat=%d"
,
get_field
(
dtmcontrol
,
DTM_DTMCS_DMISTAT
)
)
;
riscv-013.c:1570
examine()
LOG_DEBUG
(
" abits=%d"
,
get_field
(
dtmcontrol
,
DTM_DTMCS_ABITS
)
)
;
riscv-013.c:1571
examine()
LOG_DEBUG
(
" version=%d"
,
get_field
(
dtmcontrol
,
DTM_DTMCS_VERSION
)
)
;
riscv-013.c:1572
examine()
LOG_DEBUG
(
"dmstatus: 0x%08x"
,
dmstatus
)
;
riscv-013.c:1617
examine()
LOG_DEBUG
(
"hartsellen=%d"
,
info
->
hartsellen
)
;
riscv-013.c:1633
examine()
LOG_DEBUG
(
"Detected %d harts."
,
dm
->
hart_count
)
;
riscv-013.c:1702
examine()
LOG_DEBUG
(
" hart %d: XLEN=%d, misa=0x%"
PRIx64
,
r
->
current_hartid
,
r
->
xlen
,
riscv-013.c:1752
examine()
LOG_DEBUG
(
"init"
)
;
riscv-013.c:2277
init_target()
LOG_DEBUG
(
"Waiting for hart %d to come out of reset."
,
index
)
;
riscv-013.c:2417
deassert_reset()
LOG_DEBUG
(
"Unable to execute pre-fence"
)
;
riscv-013.c:2472
execute_fence()
if
(
debug_level
<
LOG_LVL_DEBUG
)
riscv-013.c:2481
log_memory_access()
LOG_DEBUG
(
fmt
,
value
)
;
riscv-013.c:2502
log_memory_access()
LOG_DEBUG
(
"System Bus Access: size: %d\tcount:%d\tstart address: 0x%08"
riscv-013.c:2596
read_memory_bus_v0()
LOG_DEBUG
(
"\r\nread_memory: sab: access: 0x%08x"
,
access
)
;
riscv-013.c:2618
read_memory_bus_v0()
LOG_DEBUG
(
"\r\nread_memory: sab: value: 0x%08x"
,
value
)
;
riscv-013.c:2624
read_memory_bus_v0()
LOG_DEBUG
(
"reading block until final address 0x%"
PRIx64
,
fin_addr
)
;
riscv-013.c:2633
read_memory_bus_v0()
LOG_DEBUG
(
"\r\naccess: 0x%08x"
,
access
)
;
riscv-013.c:2644
read_memory_bus_v0()
LOG_DEBUG
(
"\r\nsab:autoincrement: \r\n size: %d\tcount:%d\taddress: 0x%08"
riscv-013.c:2648
read_memory_bus_v0()
LOG_DEBUG
(
"%s"
,
msg
)
;
riscv-013.c:2843
log_mem_access_result()
LOG_DEBUG
(
"Skipping mem %s via progbuf - insufficient progbuf size."
,
riscv-013.c:2852
mem_should_skip_progbuf()
LOG_DEBUG
(
"Skipping mem %s via progbuf - target not halted."
,
riscv-013.c:2858
mem_should_skip_progbuf()
LOG_DEBUG
(
"Skipping mem %s via progbuf - XLEN (%d) is too short for %d-bit memory access."
,
riscv-013.c:2864
mem_should_skip_progbuf()
LOG_DEBUG
(
"Skipping mem %s via progbuf - unsupported size."
,
riscv-013.c:2870
mem_should_skip_progbuf()
LOG_DEBUG
(
"Skipping mem %s via progbuf - progbuf only supports %u-bit address."
,
riscv-013.c:2876
mem_should_skip_progbuf()
LOG_DEBUG
(
"Skipping mem %s via system bus - unsupported size."
,
riscv-013.c:2892
mem_should_skip_sysbus()
LOG_DEBUG
(
"Skipping mem %s via system bus - sba only supports %u-bit address."
,
riscv-013.c:2899
mem_should_skip_sysbus()
LOG_DEBUG
(
"Skipping mem read via system bus - "
riscv-013.c:2905
mem_should_skip_sysbus()
LOG_DEBUG
(
"Skipping mem %s via abstract access - unsupported size: %d bits"
,
riscv-013.c:2922
mem_should_skip_abstract()
LOG_DEBUG
(
"Skipping mem %s via abstract access - abstract access only supports %u-bit address."
,
riscv-013.c:2928
mem_should_skip_abstract()
LOG_DEBUG
(
"reading %d words of %d bytes from 0x%"
TARGET_PRIxADDR
,
count
,
riscv-013.c:2956
read_memory_abstract()
LOG_DEBUG
(
"aampostincrement is supported on this target."
)
;
riscv-013.c:2990
read_memory_abstract()
LOG_DEBUG
(
"aampostincrement is not supported on this target."
)
;
riscv-013.c:3001
read_memory_abstract()
LOG_DEBUG
(
"writing %d words of %d bytes from 0x%"
TARGET_PRIxADDR
,
count
,
riscv-013.c:3034
write_memory_abstract()
LOG_DEBUG
(
"aampostincrement is supported on this target."
)
;
riscv-013.c:3073
write_memory_abstract()
LOG_DEBUG
(
"aampostincrement is not supported on this target."
)
;
riscv-013.c:3084
write_memory_abstract()
LOG_DEBUG
(
"i=%d, count=%d, read_addr=0x%"
PRIx64
,
index
,
count
,
read_addr
)
;
riscv-013.c:3151
read_memory_progbuf_inner()
LOG_DEBUG
(
"successful (partial?) memory read"
)
;
riscv-013.c:3193
read_memory_progbuf_inner()
LOG_DEBUG
(
"memory read resulted in busy response"
)
;
riscv-013.c:3197
read_memory_progbuf_inner()
LOG_DEBUG
(
"error when reading memory, abstractcs=0x%08lx"
,
(
long
)
abstractcs
)
;
riscv-013.c:3250
read_memory_progbuf_inner()
LOG_DEBUG
(
"index=%d, reads=%d, next_index=%d, ignore_last=%d, j=%d"
,
riscv-013.c:3263
read_memory_progbuf_inner()
LOG_DEBUG
(
"reading %d words of %d bytes from 0x%"
TARGET_PRIxADDR
,
count
,
riscv-013.c:3427
read_memory_progbuf()
LOG_DEBUG
(
"error reading single word of %d bytes from 0x%"
TARGET_PRIxADDR
,
riscv-013.c:3510
read_memory_progbuf()
LOG_DEBUG
(
"System Bus Access: size: %d\tcount:%d\tstart address: 0x%08"
riscv-013.c:3600
write_memory_bus_v0()
LOG_DEBUG
(
"\r\naccess: 0x%08"
PRIx64
,
access
)
;
riscv-013.c:3616
write_memory_bus_v0()
LOG_DEBUG
(
"\r\nwrite_memory:SAB: ONE OFF: value 0x%08"
PRIx64
,
value
)
;
riscv-013.c:3617
write_memory_bus_v0()
LOG_DEBUG
(
"\r\naccess: 0x%08"
PRIx64
,
access
)
;
riscv-013.c:3627
write_memory_bus_v0()
LOG_DEBUG
(
"SAB:autoincrement: expected address: 0x%08x value: 0x%08x"
riscv-013.c:3638
write_memory_bus_v0()
LOG_DEBUG
(
"transferring burst starting at address 0x%"
TARGET_PRIxADDR
,
riscv-013.c:3664
write_memory_bus_v1()
LOG_DEBUG
(
"DMI busy encountered during system bus write."
)
;
riscv-013.c:3725
write_memory_bus_v1()
LOG_DEBUG
(
"Sbbusyerror encountered during system bus write."
)
;
riscv-013.c:3742
write_memory_bus_v1()
LOG_DEBUG
(
"unexpected sbaddress=0x%"
TARGET_PRIxADDR
riscv-013.c:3755
write_memory_bus_v1()
LOG_DEBUG
(
"System bus access failed with sberror=%u (sbaddress=0x%"
TARGET_PRIxADDR
")"
,
riscv-013.c:3771
write_memory_bus_v1()
LOG_DEBUG
(
"unexpected sbaddress=0x%"
TARGET_PRIxADDR
riscv-013.c:3776
write_memory_bus_v1()
LOG_DEBUG
(
"writing %d words of %d bytes to 0x%08lx"
,
count
,
size
,
(
long
)
address
)
;
riscv-013.c:3800
write_memory_progbuf()
LOG_DEBUG
(
"writing until final address 0x%016"
PRIx64
,
fin_addr
)
;
riscv-013.c:3857
write_memory_progbuf()
LOG_DEBUG
(
"transferring burst starting at address 0x%016"
PRIx64
,
riscv-013.c:3859
write_memory_progbuf()
LOG_DEBUG
(
"successful (partial?) memory write"
)
;
riscv-013.c:3940
write_memory_progbuf()
LOG_DEBUG
(
"Memory write resulted in abstract command busy response."
)
;
riscv-013.c:3943
write_memory_progbuf()
LOG_DEBUG
(
"Memory write resulted in DMI busy response."
)
;
riscv-013.c:3945
write_memory_progbuf()
LOG_DEBUG
(
"[%s] reading register %s"
,
target_name
(
target
)
,
riscv-013.c:4070
riscv013_get_register()
LOG_DEBUG
(
"[%d] read PC from DPC: 0x%"
PRIx64
,
target
->
coreid
,
*
value
)
;
riscv-013.c:4080
riscv013_get_register()
LOG_DEBUG
(
"[%d] writing 0x%"
PRIx64
" to register %s"
,
riscv-013.c:4099
riscv013_set_register()
LOG_DEBUG
(
"[%d] writing PC to DPC: 0x%"
PRIx64
,
target
->
coreid
,
value
)
;
riscv-013.c:4105
riscv013_set_register()
LOG_DEBUG
(
"[%d] actual DPC written: 0x%016"
PRIx64
,
target
->
coreid
,
actual_value
)
;
riscv-013.c:4109
riscv013_set_register()
LOG_DEBUG
(
"index=%d, coreid=%d, prepped=%d"
,
index
,
t
->
coreid
,
r
->
prepped
)
;
riscv-013.c:4175
select_prepped_harts()
LOG_DEBUG
(
"halting hart %d"
,
r
->
current_hartid
)
;
riscv-013.c:4214
riscv013_halt_go()
LOG_DEBUG
(
"dcsr.cause: 0x%"
PRIx64
,
get_field
(
dcsr
,
CSR_DCSR_CAUSE
)
)
;
riscv-013.c:4323
riscv013_halt_reason()
LOG_DEBUG
(
"{%d} halted because of trigger"
,
target
->
coreid
)
;
riscv-013.c:4333
riscv013_halt_reason()
LOG_DEBUG
(
"cache hit for 0x%"
PRIx32
" @%d"
,
data
,
index
)
;
riscv-013.c:4359
riscv013_write_debug_buffer()
LOG_DEBUG
(
"resuming hart %d (for step?=%d)"
,
r
->
current_hartid
,
step
)
;
riscv-013.c:4441
riscv013_step_or_resume_current_hart()
LOG_DEBUG
(
"DTMCS: 0x%x -> 0x%x"
,
out
,
in
)
;
riscv.c:372
dtmcontrol_scan_via_bscan()
LOG_DEBUG
(
"DTMCONTROL: 0x%x -> 0x%x"
,
out
,
in
)
;
riscv.c:406
dtmcontrol_scan()
LOG_DEBUG
(
"riscv_create_target()"
)
;
riscv.c:432
riscv_create_target()
LOG_DEBUG
(
"riscv_init_target()"
)
;
riscv.c:445
riscv_init_target()
LOG_DEBUG
(
"riscv_deinit_target()"
)
;
riscv.c:491
riscv_deinit_target()
LOG_DEBUG
(
"tdata1=0x%"
PRIx64
,
tdata1_rb
)
;
riscv.c:572
maybe_add_trigger_t1()
LOG_DEBUG
(
"Trigger doesn't support what we need; After writing 0x%"
riscv.c:575
maybe_add_trigger_t1()
LOG_DEBUG
(
"tdata1=0x%"
PRIx64
,
tdata1_rb
)
;
riscv.c:622
maybe_add_trigger_t2()
LOG_DEBUG
(
"Trigger doesn't support what we need; After writing 0x%"
riscv.c:625
maybe_add_trigger_t2()
LOG_DEBUG
(
"tdata1=0x%"
PRIx64
,
tdata1_rb
)
;
riscv.c:674
maybe_add_trigger_t6()
LOG_DEBUG
(
"Trigger doesn't support what we need; After writing 0x%"
riscv.c:677
maybe_add_trigger_t6()
LOG_DEBUG
(
"trigger %d has unknown type %d"
,
i
,
type
)
;
riscv.c:724
add_trigger()
LOG_DEBUG
(
"[%d] Using trigger %d (type %d) for bp %d"
,
target
->
coreid
,
riscv.c:731
add_trigger()
LOG_DEBUG
(
"[%d] @0x%"
TARGET_PRIxADDR
,
target
->
coreid
,
breakpoint
->
address
)
;
riscv.c:867
riscv_add_breakpoint()
LOG_DEBUG
(
"[%d] Stop using resource %d for bp %d"
,
target
->
coreid
,
i
,
riscv.c:930
remove_trigger()
LOG_DEBUG
(
"[%d] @0x%"
TARGET_PRIxADDR
,
target
->
coreid
,
watchpoint
->
address
)
;
riscv.c:1004
riscv_remove_watchpoint()
LOG_DEBUG
(
"Current hartid = %d"
,
riscv_current_hartid
(
target
)
)
;
riscv.c:1027
riscv_hit_watchpoint()
LOG_DEBUG
(
"dpc is 0x%"
PRIx64
,
dpc
)
;
riscv.c:1036
riscv_hit_watchpoint()
LOG_DEBUG
(
"Next byte is %x"
,
buffer
[
i
]
)
;
riscv.c:1048
riscv_hit_watchpoint()
LOG_DEBUG
(
"Full instruction is %x"
,
instruction
)
;
riscv.c:1051
riscv_hit_watchpoint()
LOG_DEBUG
(
"%x is store instruction"
,
instruction
)
;
riscv.c:1065
riscv_hit_watchpoint()
LOG_DEBUG
(
"%x is load instruction"
,
instruction
)
;
riscv.c:1068
riscv_hit_watchpoint()
LOG_DEBUG
(
"memory address=0x%"
PRIx64
,
mem_addr
)
;
riscv.c:1075
riscv_hit_watchpoint()
LOG_DEBUG
(
"%x is not a RV32I load or store"
,
instruction
)
;
riscv.c:1077
riscv_hit_watchpoint()
LOG_DEBUG
(
"Hit address=%"
TARGET_PRIxADDR
,
wp
->
address
)
;
riscv.c:1085
riscv_hit_watchpoint()
LOG_DEBUG
(
"handle_breakpoints=%d"
,
handle_breakpoints
)
;
riscv.c:1111
old_or_new_riscv_step()
LOG_DEBUG
(
"riscv_examine()"
)
;
riscv.c:1121
riscv_examine()
LOG_DEBUG
(
"Target was already examined."
)
;
riscv.c:1123
riscv_examine()
LOG_DEBUG
(
"dtmcontrol=0x%x"
,
dtmcontrol
)
;
riscv.c:1131
riscv_examine()
LOG_DEBUG
(
" version=0x%x"
,
info
->
dtm_version
)
;
riscv.c:1133
riscv_examine()
LOG_DEBUG
(
"[%s] prep hart, debug_reason=%d"
,
target_name
(
target
)
,
riscv.c:1170
halt_prep()
LOG_DEBUG
(
"[%s] Hart is already halted (reason=%d)."
,
riscv.c:1175
halt_prep()
LOG_DEBUG
(
"[%s] Hart is already halted."
,
target_name
(
target
)
)
;
riscv.c:1193
riscv_halt_go_all_harts()
LOG_DEBUG
(
"[%d] halting all harts"
,
target
->
coreid
)
;
riscv.c:1235
riscv_halt()
LOG_DEBUG
(
"[%d]"
,
target
->
coreid
)
;
riscv.c:1275
riscv_assert_reset()
LOG_DEBUG
(
"[%d]"
,
target
->
coreid
)
;
riscv.c:1283
riscv_deassert_reset()
LOG_DEBUG
(
"[%s] prep hart"
,
target_name
(
target
)
)
;
riscv.c:1292
riscv_resume_prep_all_harts()
LOG_DEBUG
(
"[%s] hart requested resume, but was already resumed"
,
riscv.c:1299
riscv_resume_prep_all_harts()
LOG_DEBUG
(
"[%s] mark as prepped"
,
target_name
(
target
)
)
;
riscv.c:1303
riscv_resume_prep_all_harts()
LOG_DEBUG
(
"deal with triggers"
)
;
riscv.c:1314
disable_triggers()
LOG_DEBUG
(
"watchpoint %d: set=%d"
,
i
,
watchpoint
->
is_set
)
;
riscv.c:1344
disable_triggers()
LOG_DEBUG
(
"watchpoint %d: cleared=%"
PRId64
,
i
,
state
[
i
]
)
;
riscv.c:1382
enable_triggers()
LOG_DEBUG
(
"[%d]"
,
target
->
coreid
)
;
riscv.c:1402
resume_prep()
LOG_DEBUG
(
"[%d] mark as prepped"
,
target
->
coreid
)
;
riscv.c:1427
resume_prep()
LOG_DEBUG
(
"handle_breakpoints=%d"
,
handle_breakpoints
)
;
riscv.c:1474
riscv_resume()
LOG_DEBUG
(
"SATP/MMU ignored in Machine mode (mstatus=0x%"
PRIx64
")."
,
mstatus
)
;
riscv.c:1546
riscv_mmu()
LOG_DEBUG
(
"Couldn't read SATP."
)
;
riscv.c:1553
riscv_mmu()
LOG_DEBUG
(
"MMU is disabled."
)
;
riscv.c:1560
riscv_mmu()
LOG_DEBUG
(
"MMU is enabled."
)
;
riscv.c:1563
riscv_mmu()
LOG_DEBUG
(
"virtual=0x%"
TARGET_PRIxADDR
"; mode=%s"
,
virtual
,
info
->
name
)
;
riscv.c:1607
riscv_address_translate()
LOG_DEBUG
(
"i=%d; PTE @0x%"
TARGET_PRIxADDR
" = 0x%"
PRIx64
,
i
,
riscv.c:1639
riscv_address_translate()
LOG_DEBUG
(
"0x%"
TARGET_PRIxADDR
" -> 0x%"
TARGET_PRIxADDR
,
virtual
,
riscv.c:1671
riscv_address_translate()
LOG_DEBUG
(
"[%s] {%d} reg_class=%d, read=%d"
,
riscv.c:1764
riscv_get_gdb_reg_list_internal()
LOG_DEBUG
(
"saved_pc=0x%"
PRIx64
,
saved_pc
)
;
riscv.c:1852
riscv_run_algorithm()
LOG_DEBUG
(
"save %s"
,
reg_params
[
i
]
.
reg_name
)
;
riscv.c:1856
riscv_run_algorithm()
LOG_DEBUG
(
"Disabling Interrupts"
)
;
riscv.c:1889
riscv_run_algorithm()
LOG_DEBUG
(
"resume at 0x%"
TARGET_PRIxADDR
,
entry_point
)
;
riscv.c:1906
riscv_run_algorithm()
LOG_DEBUG
(
"poll()"
)
;
riscv.c:1912
riscv_run_algorithm()
LOG_DEBUG
(
"Restoring Interrupts"
)
;
riscv.c:1959
riscv_run_algorithm()
LOG_DEBUG
(
"restore %s"
,
reg_params
[
i
]
.
reg_name
)
;
riscv.c:1979
riscv_run_algorithm()
LOG_DEBUG
(
"address=0x%"
TARGET_PRIxADDR
"; count=0x%"
PRIx32
,
address
,
count
)
;
riscv.c:1999
riscv_checksum_memory()
LOG_DEBUG
(
"checksum=0x%"
PRIx32
", result=%d"
,
*
checksum
,
retval
)
;
riscv.c:2072
riscv_checksum_memory()
LOG_DEBUG
(
"polling hart %d, target->state=%d"
,
hartid
,
target
->
state
)
;
riscv.c:2091
riscv_poll_hart()
LOG_DEBUG
(
" triggered a halt"
)
;
riscv.c:2097
riscv_poll_hart()
LOG_DEBUG
(
" triggered running"
)
;
riscv.c:2101
riscv_poll_hart()
LOG_DEBUG
(
"[%s] debug_reason=%d"
,
target_name
(
target
)
,
target
->
debug_reason
)
;
riscv.c:2132
set_debug_reason()
LOG_DEBUG
(
"buf used/size: %d/%d"
,
r
->
sample_buf
.
used
,
r
->
sample_buf
.
size
)
;
riscv.c:2143
sample_memory()
LOG_DEBUG
(
"polling all harts"
)
;
riscv.c:2186
riscv_openocd_poll()
LOG_DEBUG
(
"should_remain_halted=%d, should_resume=%d"
,
riscv.c:2237
riscv_openocd_poll()
LOG_DEBUG
(
"halt all"
)
;
riscv.c:2244
riscv_openocd_poll()
LOG_DEBUG
(
"resume all"
)
;
riscv.c:2247
riscv_openocd_poll()
LOG_DEBUG
(
" hart %d halted"
,
halted_hart
)
;
riscv.c:2274
riscv_openocd_poll()
LOG_DEBUG
(
"stepping rtos hart"
)
;
riscv.c:2306
riscv_openocd_step()
LOG_DEBUG
(
"[%s] resuming hart"
,
target_name
(
target
)
)
;
riscv.c:3153
riscv_resume_go_all_harts()
LOG_DEBUG
(
"[%s] hart requested resume, but was already resumed"
,
riscv.c:3160
riscv_resume_go_all_harts()
LOG_DEBUG
(
"[%s] stepping"
,
target_name
(
target
)
)
;
riscv.c:3175
riscv_step_rtos_hart()
LOG_DEBUG
(
"setting hartid to %d, was %d"
,
hartid
,
previous_hartid
)
;
riscv.c:3221
riscv_set_current_hartid()
LOG_DEBUG
(
"[%d]"
,
target
->
coreid
)
;
riscv.c:3231
riscv_invalidate_register_cache()
LOG_DEBUG
(
"[%s] %s <- %"
PRIx64
,
target_name
(
target
)
,
gdb_regno_name
(
regid
)
,
value
)
;
riscv.c:3311
riscv_set_register()
LOG_DEBUG
(
"[%s] wrote 0x%"
PRIx64
" to %s valid=%d"
,
riscv.c:3329
riscv_set_register()
LOG_DEBUG
(
"[%s] %s does not exist."
,
riscv.c:3343
riscv_get_register()
LOG_DEBUG
(
"[%s] %s: %"
PRIx64
" (cached)"
,
target_name
(
target
)
,
riscv.c:3350
riscv_get_register()
LOG_DEBUG
(
"[%s] %s: %"
PRIx64
,
target_name
(
target
)
,
riscv.c:3367
riscv_get_register()
LOG_DEBUG
(
"[%s] Cannot access tselect register. "
riscv.c:3462
riscv_enumerate_triggers()
LOG_DEBUG
(
"[%s] read 0x%s from %s (valid=%d)"
,
target_name
(
target
)
,
riscv.c:3721
register_get()
LOG_DEBUG
(
"[%s] write 0x%s to %s (valid=%d)"
,
target_name
(
target
)
,
riscv.c:3734
register_set()
LOG_DEBUG
(
"create register cache for %d registers"
,
riscv.c:3808
riscv_init_registers()
LOG_DEBUG
(
"Exposing additional CSR %d (name=%s)"
,
riscv.c:4350
riscv_init_registers()
LOG_DEBUG
(
"Exposing additional custom register %d (name=%s)"
,
riscv.c:4395
riscv_init_registers()
LOG_DEBUG
(
" -> NONE (!semihosting)"
)
;
riscv_semihosting.c:60
riscv_semihosting()
LOG_DEBUG
(
" -> NONE (!semihosting->is_active)"
)
;
riscv_semihosting.c:65
riscv_semihosting()
LOG_DEBUG
(
"check %08x %08x %08x from 0x%"
PRIx64
"-4"
,
pre
,
ebreak
,
post
,
pc
)
;
riscv_semihosting.c:95
riscv_semihosting()
LOG_DEBUG
(
" -> NONE (no magic)"
)
;
riscv_semihosting.c:99
riscv_semihosting()
LOG_DEBUG
(
" -> ERROR (couldn't read a0)"
)
;
riscv_semihosting.c:114
riscv_semihosting()
LOG_DEBUG
(
" -> ERROR (couldn't read a1)"
)
;
riscv_semihosting.c:120
riscv_semihosting()
LOG_DEBUG
(
" -> NONE (unknown operation number)"
)
;
riscv_semihosting.c:139
riscv_semihosting()
LOG_DEBUG
(
" -> HANDLED"
)
;
riscv_semihosting.c:154
riscv_semihosting()
LOG_DEBUG
(
" -> WAITING"
)
;
riscv_semihosting.c:158
riscv_semihosting()
LOG_DEBUG
(
"[%s] enable=%d"
,
target_name
(
target
)
,
enable
)
;
riscv_semihosting.c:171
riscv_semihosting_setup()
LOG_DEBUG
(
"0x%"
PRIx64
,
semihosting
->
result
)
;
riscv_semihosting.c:188
riscv_semihosting_post_result()
LOG_DEBUG
(
"%d/%d"
,
command_buffer_size
,
reply_buffer_size
)
;
rlink.c:472
dtc_run_download()
tap_set_state
(
tap_get_end_state
(
)
)
;
rlink.c:867
rlink_state_move()
tap_set_state
(
cmd
->
path
[
state_count
]
)
;
rlink.c:891
rlink_path_move()
tap_set_state
(
ir_scan
?
TAP_IRPAUSE
:
TAP_DRPAUSE
)
;
rlink.c:1256
rlink_scan()
LOG_DEBUG_IO
(
"reset trst: %i srst %i"
,
rlink.c:1300
rlink_execute_queue()
tap_set_state
(
TAP_RESET
)
;
rlink.c:1306
rlink_execute_queue()
LOG_DEBUG_IO
(
"runtest %i cycles, end in %i"
,
rlink.c:1310
rlink_execute_queue()
LOG_DEBUG_IO
(
"statemove end in %i"
,
cmd
->
cmd
.
statemove
->
end_state
)
;
rlink.c:1318
rlink_execute_queue()
LOG_DEBUG_IO
(
"pathmove: %u states, end in %i"
,
rlink.c:1324
rlink_execute_queue()
LOG_DEBUG_IO
(
"%s scan end in %i"
,
rlink.c:1330
rlink_execute_queue()
LOG_DEBUG_IO
(
"sleep %"
PRIu32
,
cmd
->
cmd
.
sleep
->
us
)
;
rlink.c:1341
rlink_execute_queue()
LOG_DEBUG
(
"Opened device, hdev = %p"
,
hdev
)
;
rlink.c:1471
rlink_init()
LOG_DEBUG
(
"interface claimed!"
)
;
rlink.c:1485
rlink_init()
LOG_DEBUG
(
INTERFACE_NAME
" firmware version: %d.%d.%d"
,
rlink.c:1531
rlink_init()
LOG_TARGET_DEBUG
(
target
,
"Calling ROM func @0x%"
PRIx16
" with %u arguments"
,
func_offset
,
n_args
)
;
rp2040.c:106
rp2040_call_rom_func()
LOG_DEBUG
(
"Set %s = 0x%"
PRIx32
,
args
[
i
]
.
reg_name
,
buf_get_u32
(
args
[
i
]
.
value
,
0
,
32
)
)
;
rp2040.c:124
rp2040_call_rom_func()
LOG_DEBUG
(
"Flushing flash cache after write behind"
)
;
rp2040.c:161
rp2040_finalize_stack_free()
LOG_DEBUG
(
"Configuring SSI for execute-in-place"
)
;
rp2040.c:168
rp2040_finalize_stack_free()
LOG_DEBUG
(
"Connecting internal flash"
)
;
rp2040.c:197
rp2040_stack_grab_and_prep()
LOG_DEBUG
(
"Kicking flash out of XIP mode"
)
;
rp2040.c:204
rp2040_stack_grab_and_prep()
LOG_DEBUG
(
"Writing %d bytes starting at 0x%"
PRIx32
,
count
,
offset
)
;
rp2040.c:216
rp2040_flash_write()
LOG_DEBUG
(
"Allocated flash bounce buffer @"
TARGET_ADDR_FMT
,
bounce
->
address
)
;
rp2040.c:243
rp2040_flash_write()
LOG_DEBUG
(
"Writing %d bytes to offset 0x%"
PRIx32
,
write_size
,
offset
)
;
rp2040.c:247
rp2040_flash_write()
LOG_DEBUG
(
"RP2040 erase %d bytes starting at 0x%"
PRIx32
,
length
,
start_addr
)
;
rp2040.c:290
rp2040_flash_erase()
LOG_DEBUG
(
"Remote call flash_range_erase"
)
;
rp2040.c:296
rp2040_flash_erase()
LOG_DEBUG
(
"SPI flash autodetection disabled, using configured size"
)
;
rp2040.c:442
rp2040_flash_probe()
LOG_DEBUG
(
"Running flash init algorithm"
)
;
rs14100.c:167
rs14100_init()
LOG_DEBUG
(
"Running flash erase algorithm"
)
;
rs14100.c:280
rs14100_erase()
LOG_DEBUG
(
"erasing buffer flash address=0x%"
PRIx32
,
address
)
;
rsl10.c:345
rsl10_ll_flash_erase()
LOG_DEBUG
(
"Writing 0x%"
PRIx32
" to flash address=0x%"
PRIx32
" bytes=0x%"
PRIx32
,
data
,
address
,
bytes
)
;
rsl10.c:405
rsl10_ll_flash_write()
LOG_DEBUG
(
"Writing buffer to flash address=0x%"
PRIx32
" bytes=0x%"
PRIx32
,
address
,
bytes
)
;
rsl10.c:407
rsl10_ll_flash_write()
LOG_DEBUG
(
rsl10.c:463
rsl10_ll_flash_write()
LOG_DEBUG
(
"task name at 0x%"
PRIx32
", value \"%s\""
,
name
,
tmp_str
)
;
rtkernel.c:131
rtkernel_add_task()
LOG_DEBUG
(
"task state 0x%"
PRIx16
,
state
)
;
rtkernel.c:146
rtkernel_add_task()
LOG_DEBUG
(
"current task is 0x%"
PRIx32
,
current_task
)
;
rtkernel.c:227
rtkernel_update_threads()
LOG_DEBUG
(
"chain start at 0x%"
PRIx32
,
chain
)
;
rtkernel.c:237
rtkernel_update_threads()
LOG_DEBUG
(
"next entry at 0x%"
PRIx32
,
next
)
;
rtkernel.c:246
rtkernel_update_threads()
LOG_DEBUG
(
"end of chain detected"
)
;
rtkernel.c:248
rtkernel_update_threads()
LOG_DEBUG
(
"found task at 0x%"
PRIx32
,
task
)
;
rtkernel.c:252
rtkernel_update_threads()
LOG_DEBUG
(
"stack pointer at 0x%"
PRIx64
", value 0x%"
PRIx32
,
rtkernel.c:291
rtkernel_get_thread_reg_list()
LOG_DEBUG
(
"cm3 stacking"
)
;
rtkernel.c:321
rtkernel_get_thread_reg_list()
LOG_DEBUG
(
"cm4f_fpu stacking"
)
;
rtkernel.c:334
rtkernel_get_thread_reg_list()
LOG_DEBUG
(
"cm4f stacking"
)
;
rtkernel.c:338
rtkernel_get_thread_reg_list()
LOG_DEBUG
(
"RTOS: Address of symbol '%s%s' is 0x%"
PRIx64
,
cur_sym
,
cur_suffix
,
addr
)
;
rtos.c:274
rtos_qsymbol()
LOG_DEBUG
(
"RTOS: Requesting symbol lookup of '%s%s' from the debugger"
,
next_sym
->
symbol_name
,
next_suffix
)
;
rtos.c:316
rtos_qsymbol()
LOG_DEBUG
(
"RTOS: GDB requested to set current thread to 0x%"
PRIx64
,
threadid
)
;
rtos.c:465
rtos_thread_packet()
LOG_DEBUG
(
"getting register %d for thread 0x%"
PRIx64
rtos.c:514
rtos_get_gdb_reg()
LOG_DEBUG
(
"RTOS: getting register list for thread 0x%"
PRIx64
rtos.c:566
rtos_get_gdb_reg_list()
LOG_DEBUG
(
"RTOS: Read stack frame at 0x%"
PRIx32
,
address
)
;
rtos.c:629
rtos_generic_stack_read()
LOG_DEBUG
(
"XPSR(0x%08"
PRIx32
") indicated stack alignment was necessary\r\n"
,
rtos_standard_stackings.c:165
rtos_cortex_m_stack_align()
LOG_DEBUG
(
"rtt: Registering sink for channel %u"
,
channel_index
)
;
rtt.c:216
rtt_register_sink()
LOG_DEBUG
(
"rtt: Unregistering sink for channel %u"
,
channel_index
)
;
rtt.c:237
rtt_unregister_sink()
LOG_DEBUG
(
"rtt: Wrote %zu bytes into down-channel %u"
,
*
length
,
rtt.c:214
target_rtt_write_callback()
LOG_DEBUG
(
"rtt: New connection for channel %u"
,
service
->
channel
)
;
rtt_server.c:62
rtt_new_connection()
LOG_DEBUG
(
"rtt: Connection for channel %u closed"
,
service
->
channel
)
;
rtt_server.c:82
rtt_connection_closed()
LOG_DEBUG
(
" "
)
;
semihosting_common.c:107
semihosting_common_init()
LOG_DEBUG
(
"op=0x%x (%s), param=0x%"
PRIx64
,
semihosting
->
op
,
semihosting_common.c:390
semihosting_common()
LOG_DEBUG
(
"ignoring semihosting attempt to close %s"
,
semihosting_common.c:452
semihosting_common()
LOG_DEBUG
(
"close(%d)=%"
PRId64
,
fd
,
semihosting
->
result
)
;
semihosting_common.c:468
semihosting_common()
LOG_DEBUG
(
"fstat(%d)=%"
PRId64
,
fd
,
semihosting
->
result
)
;
semihosting_common.c:693
semihosting_common()
LOG_DEBUG
(
"fstat(%d)=%"
PRId64
,
fd
,
semihosting
->
result
)
;
semihosting_common.c:696
semihosting_common()
LOG_DEBUG
(
"SYS_GET_CMDLINE=[%s], %"
PRId64
,
arg
,
semihosting
->
result
)
;
semihosting_common.c:753
semihosting_common()
LOG_DEBUG
(
"isatty(%d)=%"
PRId64
,
fd
,
semihosting
->
result
)
;
semihosting_common.c:847
semihosting_common()
LOG_DEBUG
(
"dup(STDIN)=%d"
,
fd
)
;
semihosting_common.c:966
semihosting_common()
LOG_DEBUG
(
"dup(STDOUT)=%d"
,
fd
)
;
semihosting_common.c:970
semihosting_common()
LOG_DEBUG
(
"dup(STDERR)=%d"
,
fd
)
;
semihosting_common.c:974
semihosting_common()
LOG_DEBUG
(
"open('%s')=%"
PRId64
,
fn
,
semihosting
->
result
)
;
semihosting_common.c:988
semihosting_common()
LOG_DEBUG
(
"read(%d, 0x%"
PRIx64
", %zu)=%"
PRId64
,
semihosting_common.c:1051
semihosting_common()
LOG_DEBUG
(
"getchar()=%"
PRId64
,
semihosting
->
result
)
;
semihosting_common.c:1091
semihosting_common()
LOG_DEBUG
(
"remove('%s')=%"
PRId64
,
fn
,
semihosting
->
result
)
;
semihosting_common.c:1138
semihosting_common()
LOG_DEBUG
(
"rename('%s', '%s')=%"
PRId64
" %d"
,
fn1
,
fn2
,
semihosting
->
result
,
errno
)
;
semihosting_common.c:1209
semihosting_common()
LOG_DEBUG
(
"lseek(%d, %d)=%"
PRId64
,
fd
,
(
int
)
pos
,
semihosting
->
result
)
;
semihosting_common.c:1255
semihosting_common()
LOG_DEBUG
(
"system('%s')=%"
PRId64
,
cmd
,
semihosting
->
result
)
;
semihosting_common.c:1314
semihosting_common()
LOG_DEBUG
(
"write(%d, 0x%"
PRIx64
", %zu)=%"
PRId64
,
semihosting_common.c:1392
semihosting_common()
LOG_DEBUG
(
"Terminating on Signal %d"
,
sig
)
;
server.c:608
sig_handler()
LOG_DEBUG
(
"Ignored extra Signal %d"
,
sig
)
;
server.c:610
sig_handler()
LOG_DEBUG
(
"header 0x%08"
PRIx32
" 0x%08"
PRIx32
,
header
.
signature
,
header
.
revision
)
;
sfdp.c:76
spi_sfdp()
LOG_DEBUG
(
"parameter headers: %d"
,
nph
)
;
sfdp.c:89
spi_sfdp()
LOG_DEBUG
(
"pheader %d len=0x%02"
PRIx8
" id=0x%04"
PRIx16
sfdp.c:106
spi_sfdp()
LOG_DEBUG
(
"word %02d 0x%08X"
,
j
+
1
,
ptable
[
j
]
)
;
sfdp.c:121
spi_sfdp()
LOG_DEBUG
(
"basic flash parameter table"
)
;
sfdp.c:133
spi_sfdp()
LOG_DEBUG
(
"unimplemented parameter table id=0x%04"
PRIx16
,
id
)
;
sfdp.c:233
spi_sfdp()
LOG_DEBUG
(
"%s: from sector %u to sector %u"
,
__func__
,
first
,
last
)
;
sh_qspi.c:448
sh_qspi_erase()
LOG_DEBUG
(
"%s: offset=0x%08"
PRIx32
" count=0x%08"
PRIx32
,
sh_qspi.c:498
sh_qspi_write()
LOG_DEBUG
(
"%s: offset=0x%08"
PRIx32
" count=0x%08"
PRIx32
,
sh_qspi.c:531
sh_qspi_write()
LOG_DEBUG
(
"%s: offset=0x%08"
PRIx32
" count=0x%08"
PRIx32
,
sh_qspi.c:602
sh_qspi_read()
LOG_DEBUG
(
"Found device %s at address "
TARGET_ADDR_FMT
,
sh_qspi.c:776
sh_qspi_probe()
LOG_DEBUG
(
"%s"
,
__func__
)
;
sh_qspi.c:878
sh_qspi_flash_bank_command()
LOG_DEBUG
(
"DAP_REG[0x%02x] <- %08"
PRIX32
,
reg
,
value
)
;
sim3x.c:864
ap_write_register()
LOG_DEBUG
(
"DAP: failed to get AP"
)
;
sim3x.c:868
ap_write_register()
LOG_DEBUG
(
"DAP: failed to queue a write request"
)
;
sim3x.c:874
ap_write_register()
LOG_DEBUG
(
"DAP: dap_run failed"
)
;
sim3x.c:882
ap_write_register()
LOG_DEBUG
(
"DAP: failed to get AP"
)
;
sim3x.c:893
ap_read_register()
LOG_DEBUG
(
"DAP: failed to queue a read request"
)
;
sim3x.c:899
ap_read_register()
LOG_DEBUG
(
"DAP: dap_run failed"
)
;
sim3x.c:907
ap_read_register()
LOG_DEBUG
(
"DAP_REG[0x%02x]: %08"
PRIX32
,
reg
,
*
result
)
;
sim3x.c:911
ap_read_register()
LOG_DEBUG
(
"DAP: polling timed out"
)
;
sim3x.c:928
ap_poll_register()
LOG_DEBUG
(
"usecrl = %i"
,
(
int
)
(
usecrl
)
)
;
stellaris.c:529
stellaris_set_flash_timing()
LOG_DEBUG
(
"Stellaris RCC %"
PRIx32
""
,
rcc
)
;
stellaris.c:576
stellaris_read_clock_info()
LOG_DEBUG
(
"Stellaris RCC2 %"
PRIx32
""
,
rcc
)
;
stellaris.c:579
stellaris_read_clock_info()
LOG_DEBUG
(
"Stellaris PLLCFG %"
PRIx32
""
,
pllcfg
)
;
stellaris.c:582
stellaris_read_clock_info()
LOG_DEBUG
(
"did0 0x%"
PRIx32
", did1 0x%"
PRIx32
", dc0 0x%"
PRIx32
", dc1 0x%"
PRIx32
""
,
stellaris.c:662
stellaris_read_part_info()
LOG_DEBUG
(
"(bank=%p buffer=%p offset=%08"
PRIx32
" wcount=%08"
PRIx32
""
,
stellaris.c:1038
stellaris_write_block()
LOG_DEBUG
(
"no working area for block memory writes"
)
;
stellaris.c:1044
stellaris_write_block()
LOG_DEBUG
(
"retry target_alloc_working_area(%s, size=%u)"
,
stellaris.c:1059
stellaris_write_block()
LOG_DEBUG
(
"(bank=%p buffer=%p offset=%08"
PRIx32
" count=%08"
PRIx32
""
,
stellaris.c:1118
stellaris_write()
LOG_DEBUG
(
"writing flash word-at-a-time"
)
;
stellaris.c:1151
stellaris_write()
LOG_DEBUG
(
"0x%"
PRIx32
""
,
address
)
;
stellaris.c:1168
stellaris_write()
LOG_DEBUG
(
"0x%"
PRIx32
""
,
address
)
;
stellaris.c:1192
stellaris_write()
LOG_DEBUG
(
"flash_cris 0x%"
PRIx32
""
,
flash_cris
)
;
stellaris.c:1208
stellaris_write()
LOG_DEBUG
(
"ERROR, failed to alloc usb transfers"
)
;
stlink_usb.c:669
jtag_libusb_bulk_transfer_n()
LOG_DEBUG
(
"ERROR, failed to submit transfer %zu, error %d"
,
i
,
retval
)
;
stlink_usb.c:686
jtag_libusb_bulk_transfer_n()
LOG_DEBUG
(
"ERROR, transfer %zu failed, error %d"
,
i
,
retval
)
;
stlink_usb.c:709
jtag_libusb_bulk_transfer_n()
LOG_DEBUG
(
"get sense"
)
;
stlink_usb.c:904
stlink_usb_usb_xfer_noerrcheck()
LOG_DEBUG
(
"socket send error: %s (errno %d)"
,
strerror
(
errno
)
,
errno
)
;
stlink_usb.c:927
stlink_tcp_send_cmd()
LOG_DEBUG
(
"sent size %d (expected %d)"
,
sent_size
,
send_size
)
;
stlink_usb.c:929
stlink_tcp_send_cmd()
LOG_DEBUG
(
"received size %d (expected %d)"
,
recv_size
-
remaining_bytes
,
recv_size
)
;
stlink_usb.c:941
stlink_tcp_send_cmd()
LOG_DEBUG
(
"socket recv error: %s (errno %d)"
,
strerror
(
errno
)
,
errno
)
;
stlink_usb.c:950
stlink_tcp_send_cmd()
LOG_DEBUG
(
"TCP busy"
)
;
stlink_usb.c:968
stlink_tcp_send_cmd()
LOG_DEBUG
(
"unknown/unexpected STLINK status code 0x%x"
,
h
->
databuf
[
0
]
)
;
stlink_usb.c:1066
stlink_usb_error_check()
LOG_DEBUG
(
"SWD fault response (0x%x)"
,
STLINK_DEBUG_ERR_FAULT
)
;
stlink_usb.c:1079
stlink_usb_error_check()
LOG_DEBUG
(
"wait status SWD_AP_WAIT (0x%x)"
,
STLINK_SWD_AP_WAIT
)
;
stlink_usb.c:1082
stlink_usb_error_check()
LOG_DEBUG
(
"wait status SWD_DP_WAIT (0x%x)"
,
STLINK_SWD_DP_WAIT
)
;
stlink_usb.c:1085
stlink_usb_error_check()
LOG_DEBUG
(
"STLINK_JTAG_GET_IDCODE_ERROR"
)
;
stlink_usb.c:1088
stlink_usb_error_check()
LOG_DEBUG
(
"Write error"
)
;
stlink_usb.c:1091
stlink_usb_error_check()
LOG_DEBUG
(
"Write verify error, ignoring"
)
;
stlink_usb.c:1094
stlink_usb_error_check()
LOG_DEBUG
(
"STLINK_SWD_AP_FAULT"
)
;
stlink_usb.c:1102
stlink_usb_error_check()
LOG_DEBUG
(
"STLINK_SWD_AP_ERROR"
)
;
stlink_usb.c:1105
stlink_usb_error_check()
LOG_DEBUG
(
"STLINK_SWD_AP_PARITY_ERROR"
)
;
stlink_usb.c:1108
stlink_usb_error_check()
LOG_DEBUG
(
"STLINK_SWD_DP_FAULT"
)
;
stlink_usb.c:1111
stlink_usb_error_check()
LOG_DEBUG
(
"STLINK_SWD_DP_ERROR"
)
;
stlink_usb.c:1114
stlink_usb_error_check()
LOG_DEBUG
(
"STLINK_SWD_DP_PARITY_ERROR"
)
;
stlink_usb.c:1117
stlink_usb_error_check()
LOG_DEBUG
(
"STLINK_SWD_AP_WDATA_ERROR"
)
;
stlink_usb.c:1120
stlink_usb_error_check()
LOG_DEBUG
(
"STLINK_SWD_AP_STICKY_ERROR"
)
;
stlink_usb.c:1123
stlink_usb_error_check()
LOG_DEBUG
(
"STLINK_SWD_AP_STICKYORUN_ERROR"
)
;
stlink_usb.c:1126
stlink_usb_error_check()
LOG_DEBUG
(
"STLINK_BAD_AP_ERROR"
)
;
stlink_usb.c:1129
stlink_usb_error_check()
LOG_DEBUG
(
"unknown/unexpected STLINK status code 0x%x"
,
h
->
databuf
[
0
]
)
;
stlink_usb.c:1132
stlink_usb_error_check()
LOG_DEBUG
(
"stlink_cmd_allow_retry ERROR_WAIT, retry %d, delaying %u microseconds"
,
retries
,
delay_us
)
;
stlink_usb.c:1183
stlink_cmd_allow_retry()
LOG_DEBUG
(
"MODE: 0x%02X"
,
mode
)
;
stlink_usb.c:1696
stlink_usb_exit_mode()
LOG_DEBUG
(
"MODE: 0x%02X"
,
mode
)
;
stlink_usb.c:1764
stlink_usb_init_mode()
LOG_DEBUG
(
"MODE: 0x%02X"
,
mode
)
;
stlink_usb.c:1824
stlink_usb_init_mode()
LOG_DEBUG
(
"IDCODE: 0x%08"
PRIX32
,
*
idcode
)
;
stlink_usb.c:2057
stlink_usb_idcode()
LOG_DEBUG
(
"Tracing: disable"
)
;
stlink_usb.c:2230
stlink_usb_trace_disable()
LOG_DEBUG
(
"Tracing: recording at %"
PRIu32
"Hz"
,
h
->
trace
.
source_hz
)
;
stlink_usb.c:2264
stlink_usb_trace_enable()
LOG_DEBUG
(
"max buffer (%d) length exceeded"
,
stlink_usb_block
(
h
)
)
;
stlink_usb.c:2502
stlink_usb_read_mem8()
LOG_DEBUG
(
"max buffer length (%d) exceeded"
,
stlink_usb_block
(
h
)
)
;
stlink_usb.c:2546
stlink_usb_write_mem8()
LOG_DEBUG
(
"max buffer (%d) length exceeded"
,
STLINK_MAX_RW16_32
)
;
stlink_usb.c:2586
stlink_usb_read_mem16()
LOG_DEBUG
(
"Invalid data alignment"
)
;
stlink_usb.c:2592
stlink_usb_read_mem16()
LOG_DEBUG
(
"max buffer (%d) length exceeded"
,
STLINK_MAX_RW16_32
)
;
stlink_usb.c:2634
stlink_usb_write_mem16()
LOG_DEBUG
(
"Invalid data alignment"
)
;
stlink_usb.c:2640
stlink_usb_write_mem16()
LOG_DEBUG
(
"max buffer (%d) length exceeded"
,
STLINK_MAX_RW16_32
)
;
stlink_usb.c:2677
stlink_usb_read_mem32()
LOG_DEBUG
(
"Invalid data alignment"
)
;
stlink_usb.c:2683
stlink_usb_read_mem32()
LOG_DEBUG
(
"max buffer (%d) length exceeded"
,
STLINK_MAX_RW16_32
)
;
stlink_usb.c:2722
stlink_usb_write_mem32()
LOG_DEBUG
(
"Invalid data alignment"
)
;
stlink_usb.c:2728
stlink_usb_write_mem32()
LOG_DEBUG
(
"max buffer (%d) length exceeded"
,
STLINK_MAX_RW16_32
)
;
stlink_usb.c:2763
stlink_usb_read_mem32_noaddrinc()
LOG_DEBUG
(
"Invalid data alignment"
)
;
stlink_usb.c:2769
stlink_usb_read_mem32_noaddrinc()
LOG_DEBUG
(
"max buffer (%d) length exceeded"
,
STLINK_MAX_RW16_32
)
;
stlink_usb.c:2805
stlink_usb_write_mem32_noaddrinc()
LOG_DEBUG
(
"Invalid data alignment"
)
;
stlink_usb.c:2811
stlink_usb_write_mem32_noaddrinc()
LOG_DEBUG
(
"Supported clock speeds are:"
)
;
stlink_usb.c:3130
stlink_dump_speed_map()
LOG_DEBUG
(
"%d kHz"
,
map
[
i
]
.
speed
)
;
stlink_usb.c:3133
stlink_dump_speed_map()
LOG_DEBUG
(
"claim interface failed"
)
;
stlink_usb.c:3418
stlink_usb_usb_open()
LOG_DEBUG
(
"libusb_get_pid failed"
)
;
stlink_usb.c:3427
stlink_usb_usb_open()
LOG_DEBUG
(
"socket : %x"
,
h
->
tcp_backend_priv
.
fd
)
;
stlink_usb.c:3540
stlink_tcp_open()
LOG_DEBUG
(
"%d ST-LINK detected"
,
connected_stlinks
)
;
stlink_usb.c:3614
stlink_tcp_open()
LOG_DEBUG
(
"Device serial number '%s' doesn't match requested serial '%s'"
,
stlink_usb.c:3676
stlink_tcp_open()
LOG_DEBUG
(
"transport: vid: 0x%04x pid: 0x%04x serial: %s"
,
h
->
vid
,
h
->
pid
,
serial
)
;
stlink_usb.c:3698
stlink_tcp_open()
LOG_DEBUG
(
"stlink_open"
)
;
stlink_usb.c:3732
stlink_open()
LOG_DEBUG
(
"malloc failed"
)
;
stlink_usb.c:3737
stlink_open()
LOG_DEBUG
(
"transport: %d vid: 0x%04x pid: 0x%04x serial: %s"
,
stlink_usb.c:3744
stlink_open()
LOG_DEBUG
(
"Using TAR autoincrement: %"
PRIu32
,
h
->
max_mem_packet
)
;
stlink_usb.c:3820
stlink_open()
LOG_DEBUG_IO
(
"init ap_num = %d"
,
ap_num
)
;
stlink_usb.c:3910
stlink_usb_init_access_port()
LOG_DEBUG_IO
(
"close ap_num = %d"
,
ap_num
)
;
stlink_usb.c:3929
stlink_usb_close_access_port()
LOG_DEBUG_IO
(
"%s(%"
PRIu32
")"
,
__func__
,
items
)
;
stlink_usb.c:3948
stlink_usb_rw_misc_out()
LOG_DEBUG_IO
(
"%s(%"
PRIu32
")"
,
__func__
,
items
)
;
stlink_usb.c:3969
stlink_usb_rw_misc_in()
LOG_DEBUG_IO
(
"dap_port_read = %d, addr = 0x%x, value = 0x%"
PRIx32
,
dap_port
,
addr
,
*
val
)
;
stlink_usb.c:4010
stlink_read_dap_register()
LOG_DEBUG_IO
(
"dap_write port = %d, addr = 0x%x, value = 0x%"
PRIx32
,
dap_port
,
addr
,
val
)
;
stlink_usb.c:4025
stlink_write_dap_register()
LOG_DEBUG
(
"AP %d enabled"
,
apsel
)
;
stlink_usb.c:4127
stlink_usb_open_ap()
LOG_DEBUG
(
"Ignoring DPBANKSEL while write SELECT"
)
;
stlink_usb.c:4297
stlink_dap_dp_write()
LOG_DEBUG
(
"Queue: %u commands in %u items"
,
len
,
items
)
;
stlink_usb.c:4377
stlink_usb_misc_rw_segment()
LOG_DEBUG_IO
(
"read at 0x%08"
PRIx32
" len %"
PRIu32
"*0x%08"
PRIx32
,
addr
,
size
,
count
)
;
stlink_usb.c:4921
stlink_swim_op_read_mem()
LOG_DEBUG_IO
(
"write at 0x%08"
PRIx32
" len %"
PRIu32
"*0x%08"
PRIx32
,
addr
,
size
,
count
)
;
stlink_usb.c:4944
stlink_swim_op_write_mem()
LOG_DEBUG
(
"stlink_dap_init()"
)
;
stlink_usb.c:5120
stlink_dap_init()
LOG_DEBUG
(
"stlink_dap_quit()"
)
;
stlink_usb.c:5155
stlink_dap_quit()
LOG_DEBUG
(
"stlink_dap_reset(%d)"
,
req_srst
)
;
stlink_usb.c:5163
stlink_dap_reset()
LOG_DEBUG
(
"status: 0x%"
PRIx32
""
,
status
)
;
stm32f1x.c:173
stm32x_wait_status_busy()
LOG_DEBUG
(
"status: 0x%"
PRIx32
,
status
)
;
stm32f2x.c:284
stm32x_wait_status_busy()
LOG_DEBUG
(
"unable to read option bytes"
)
;
stm32f2x.c:573
stm32x_protect_check()
LOG_DEBUG
(
"unable to read option bytes"
)
;
stm32f2x.c:677
stm32x_protect()
LOG_DEBUG
(
"sector %u: %ukBytes"
,
i
,
size
>
>
10
)
;
stm32f2x.c:902
setup_sector()
LOG_DEBUG
(
"unable to read option bytes"
)
;
stm32f2x.c:1150
stm32x_probe()
LOG_DEBUG
(
"unable to read option bytes"
)
;
stm32f2x.c:1167
stm32x_probe()
LOG_DEBUG
(
"allocated %u sectors"
,
num_pages
)
;
stm32f2x.c:1192
stm32x_probe()
LOG_DEBUG
(
"allocated %u prot blocks"
,
num_prot_blocks
)
;
stm32f2x.c:1202
stm32x_probe()
LOG_DEBUG
(
"status: 0x%"
PRIx32
""
,
status
)
;
stm32g0x.c:207
stm32x_wait_status_busy()
LOG_DEBUG
(
"status: 0x%"
PRIx32
""
,
status
)
;
stm32g4x.c:387
stm32l4_wait_status_busy()
LOG_DEBUG
(
"unable to read WPSN_CUR register"
)
;
stm32h7x.c:453
stm32x_protect_check()
LOG_DEBUG
(
"erase sector %u"
,
i
)
;
stm32h7x.c:490
stm32x_erase()
LOG_DEBUG
(
"unable to read WPSN_CUR register"
)
;
stm32h7x.c:534
stm32x_protect()
LOG_DEBUG
(
"stm32x_protect, option_bytes written WPSN 0x%"
PRIx32
,
protection
)
;
stm32h7x.c:548
stm32x_protect()
LOG_DEBUG
(
"target_alloc_working_area_try : buffer_size -> 0x%"
PRIx32
,
buffer_size
)
;
stm32h7x.c:604
stm32x_write_block()
LOG_DEBUG
(
"device id = 0x%08"
PRIx32
,
stm32x_info
->
idcode
)
;
stm32h7x.c:768
stm32x_probe()
LOG_DEBUG
(
"flash_regs_base: 0x%"
PRIx32
,
stm32x_info
->
flash_regs_base
)
;
stm32h7x.c:792
stm32x_probe()
LOG_DEBUG
(
"unable to read FLASH_OPTSR_PRG register"
)
;
stm32h7x.c:973
stm32x_set_rdp()
LOG_DEBUG
(
"status: 0x%"
PRIx32
""
,
status
)
;
stm32l4x.c:878
stm32l4_wait_status_busy()
LOG_DEBUG
(
"setting secure block-based areas registers (SECBBxRy) to 0x%08x"
,
value
)
;
stm32l4x.c:924
stm32l4_set_secbb()
LOG_DEBUG
(
"current protected areas: %s"
,
ranges_str
)
;
stm32l4x.c:1355
stm32l4_protect_same_bank()
LOG_DEBUG
(
"current protected areas: none"
)
;
stm32l4x.c:1358
stm32l4_protect_same_bank()
LOG_DEBUG
(
"requested areas for protection: %s"
,
ranges_str
)
;
stm32l4x.c:1374
stm32l4_protect_same_bank()
LOG_DEBUG
(
"requested areas for protection: none"
)
;
stm32l4x.c:1377
stm32l4_protect_same_bank()
LOG_DEBUG
(
"data: 0x%08"
PRIx32
" - 0x%08"
PRIx32
", sectors: 0x%08"
PRIx32
" - 0x%08"
PRIx32
,
stm32l4x.c:1647
stm32l4_write()
LOG_DEBUG
(
"WRPxxR mask 0x%04"
PRIx16
,
(
uint16_t
)
stm32l4_info
->
wrpxxr_mask
)
;
stm32l4x.c:2129
stm32l4_probe()
LOG_DEBUG
(
"status: 0x%"
PRIx32
""
,
status
)
;
stm32l5x.c:247
stm32l4_wait_status_busy()
LOG_DEBUG
(
"no working area for block memory writes"
)
;
stm32lx.c:444
stm32lx_write_half_pages()
LOG_DEBUG
(
"device id = 0x%08"
PRIx32
""
,
device_id
)
;
stm32lx.c:748
stm32lx_probe()
LOG_DEBUG
(
"status: 0x%"
PRIx32
""
,
status
)
;
stm32lx.c:1207
stm32lx_wait_until_bsy_clear_timeout()
LOG_DEBUG
(
"DM_BKR1E=%"
PRIx32
,
data
)
;
stm8.c:326
stm8_set_hwbreak()
LOG_DEBUG
(
"DM_BKR2E=%"
PRIx32
,
data
)
;
stm8.c:329
stm8_set_hwbreak()
LOG_DEBUG
(
"addr=%"
PRIu32
,
addr
)
;
stm8.c:331
stm8_set_hwbreak()
LOG_DEBUG
(
"DM_CR1=%"
PRIx8
,
buf
[
0
]
)
;
stm8.c:340
stm8_set_hwbreak()
LOG_DEBUG
(
"hw breakpoints: numinst %i numdata %i"
,
stm8
->
num_hw_bpoints
,
stm8.c:418
stm8_configure_break_unit()
LOG_DEBUG
(
"csr1 = 0x%02X csr2 = 0x%02X"
,
csr1
,
csr2
)
;
stm8.c:433
stm8_examine_debug_reason()
LOG_DEBUG
(
"entered debug state at PC 0x%"
PRIx32
", target->state: %s"
,
stm8.c:473
stm8_debug_entry()
LOG_DEBUG
(
"address: 0x%8.8"
TARGET_PRIxADDR
stm8.c:742
stm8_write_memory()
LOG_DEBUG
(
"address: 0x%8.8"
TARGET_PRIxADDR
stm8.c:773
stm8_read_memory()
LOG_DEBUG
(
"stm8_speed: %d"
,
speed
)
;
stm8.c:795
stm8_speed()
LOG_DEBUG
(
"writing B0 to SWIM_CSR (SAFE_MASK + SWIM_DM + HS:%d)"
,
csr
&
HS
?
1
:
0
)
;
stm8.c:801
stm8_speed()
LOG_DEBUG
(
"stm8_read_dm_csrx failed retval=%d"
,
retval
)
;
stm8.c:836
stm8_poll()
LOG_DEBUG
(
"DM_CSR2_STALL already set during server startup."
)
;
stm8.c:848
stm8_poll()
LOG_DEBUG
(
"stm8_debug_entry failed retval=%d"
,
retval
)
;
stm8.c:852
stm8_poll()
LOG_DEBUG
(
"target->state: %s"
,
target_state_name
(
target
)
)
;
stm8.c:874
stm8_halt()
LOG_DEBUG
(
"target was already halted"
)
;
stm8.c:877
stm8_halt()
LOG_DEBUG
(
"Hardware srst not supported, falling back to swim reset"
)
;
stm8.c:921
stm8_reset_assert()
LOG_DEBUG
(
"%d "
TARGET_ADDR_FMT
" %d %d"
,
current
,
address
,
stm8.c:993
stm8_resume()
LOG_DEBUG
(
"unset breakpoint at "
TARGET_ADDR_FMT
,
stm8.c:1032
stm8_resume()
LOG_DEBUG
(
"target resumed at 0x%"
PRIx32
""
,
resume_pc
)
;
stm8.c:1054
stm8_resume()
LOG_DEBUG
(
"target debug resumed at 0x%"
PRIx32
""
,
resume_pc
)
;
stm8.c:1058
stm8_resume()
LOG_DEBUG
(
"read core reg %i value 0x%"
PRIx32
""
,
num
,
reg_value
)
;
stm8.c:1134
stm8_read_core_reg()
LOG_DEBUG
(
"write core reg %i value 0x%"
PRIx32
""
,
num
,
reg_value
)
;
stm8.c:1154
stm8_write_core_reg()
LOG_DEBUG
(
"%x "
TARGET_ADDR_FMT
" %x"
,
stm8.c:1298
stm8_step()
LOG_DEBUG
(
"target stepped "
)
;
stm8.c:1345
stm8_step()
LOG_DEBUG
(
"bpid: %"
PRIu32
", bp_num %i bp_value 0x%"
PRIx32
""
,
stm8.c:1399
stm8_set_breakpoint()
LOG_DEBUG
(
"bpid: %"
PRIu32
,
breakpoint
->
unique_id
)
;
stm8.c:1403
stm8_set_breakpoint()
LOG_DEBUG
(
"Invalid comparator number in breakpoint (bpid: %"
PRIu32
")"
,
stm8.c:1476
stm8_unset_breakpoint()
LOG_DEBUG
(
"bpid: %"
PRIu32
" - releasing hw: %d"
,
stm8.c:1480
stm8_unset_breakpoint()
LOG_DEBUG
(
"bpid: %"
PRIu32
,
breakpoint
->
unique_id
)
;
stm8.c:1489
stm8_unset_breakpoint()
LOG_DEBUG
(
"wp_num %i bp_value 0x%"
PRIx32
""
,
stm8.c:1587
stm8_set_watchpoint()
LOG_DEBUG
(
"Invalid hw comparator number in watchpoint"
)
;
stm8.c:1639
stm8_unset_watchpoint()
LOG_DEBUG
(
"failed algorithm halted at 0x%"
PRIx32
" "
,
pc
)
;
stm8.c:1812
stm8_run_and_wait()
LOG_DEBUG
(
"Running algorithm"
)
;
stm8.c:1829
stm8_run_algorithm()
LOG_DEBUG
(
"restoring register %s with value 0x%8.8"
PRIx32
,
stm8.c:1923
stm8_run_algorithm()
LOG_DEBUG
(
"blocksize=%8.8"
PRIx32
,
stm8
->
blocksize
)
;
stm8.c:1959
stm8_jim_configure()
LOG_DEBUG
(
"flashstart=%8.8"
PRIx32
,
stm8
->
flashstart
)
;
stm8.c:1978
stm8_jim_configure()
LOG_DEBUG
(
"flashend=%8.8"
PRIx32
,
stm8
->
flashend
)
;
stm8.c:1997
stm8_jim_configure()
LOG_DEBUG
(
"eepromstart=%8.8"
PRIx32
,
stm8
->
eepromstart
)
;
stm8.c:2016
stm8_jim_configure()
LOG_DEBUG
(
"eepromend=%8.8"
PRIx32
,
stm8
->
eepromend
)
;
stm8.c:2035
stm8_jim_configure()
LOG_DEBUG
(
"optionstart=%8.8"
PRIx32
,
stm8
->
optionstart
)
;
stm8.c:2054
stm8_jim_configure()
LOG_DEBUG
(
"optionend=%8.8"
PRIx32
,
stm8
->
optionend
)
;
stm8.c:2073
stm8_jim_configure()
LOG_DEBUG
(
"enable_step_irq=%8.8x"
,
stm8
->
enable_step_irq
)
;
stm8.c:2082
stm8_jim_configure()
LOG_DEBUG
(
"enable_stm8l=%8.8x"
,
stm8
->
enable_stm8l
)
;
stm8.c:2091
stm8_jim_configure()
LOG_DEBUG
(
"%s"
,
__func__
)
;
stmqspi.c:210
stmqspi_flash_bank_command()
LOG_DEBUG
(
"busy: 0x%08X"
,
spi_sr
)
;
stmqspi.c:253
poll_busy()
LOG_DEBUG
(
"flash status regs: 0x%04"
PRIx16
,
*
status
)
;
stmqspi.c:388
read_status_reg()
LOG_DEBUG
(
"%s"
,
__func__
)
;
stmqspi.c:496
stmqspi_handle_mass_erase_command()
LOG_DEBUG
(
"%s"
,
__func__
)
;
stmqspi.c:617
stmqspi_handle_set()
LOG_DEBUG
(
"FSIZE = 0x%04x"
,
fsize
)
;
stmqspi.c:727
stmqspi_handle_set()
LOG_DEBUG
(
"FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1."
)
;
stmqspi.c:729
stmqspi_handle_set()
LOG_DEBUG
(
"FSIZE in DCR(1) is off by one regarding actual capacity. Fix for silicon bug?"
)
;
stmqspi.c:731
stmqspi_handle_set()
LOG_DEBUG
(
"%s"
,
__func__
)
;
stmqspi.c:781
stmqspi_handle_cmd()
LOG_DEBUG
(
"erase status regs: 0x%04"
PRIx16
,
status
)
;
stmqspi.c:960
qspi_erase_sector()
LOG_DEBUG
(
"erasing sector %4u"
,
sector
)
;
stmqspi.c:986
qspi_erase_sector()
LOG_DEBUG
(
"%s: from sector %u to sector %u"
,
__func__
,
first
,
last
)
;
stmqspi.c:1002
stmqspi_erase()
LOG_DEBUG
(
"checking sectors %u to %u"
,
sector
,
sector
+
count
-
1
)
;
stmqspi.c:1193
stmqspi_blank_check()
LOG_DEBUG
(
"Flash sector %u checked: 0x%04x"
,
sector
+
index
,
result
&
0xFFFFU
)
;
stmqspi.c:1220
stmqspi_blank_check()
LOG_DEBUG
(
"addr "
TARGET_ADDR_FMT
", len 0x%08"
PRIx32
", crc 0x%08"
PRIx32
" 0x%08"
PRIx32
,
stmqspi.c:1346
qspi_verify()
LOG_DEBUG
(
"%s: offset=0x%08"
PRIx32
" len=0x%08"
PRIx32
,
stmqspi.c:1381
qspi_read_write_block()
LOG_DEBUG
(
"%s: offset=0x%08"
PRIx32
" count=0x%08"
PRIx32
,
stmqspi.c:1576
stmqspi_read()
LOG_DEBUG
(
"%s: offset=0x%08"
PRIx32
" count=0x%08"
PRIx32
,
stmqspi.c:1616
stmqspi_write()
LOG_DEBUG
(
"%s: offset=0x%08"
PRIx32
" count=0x%08"
PRIx32
,
stmqspi.c:1677
stmqspi_verify()
LOG_DEBUG
(
"%s: len=%d, dual=%u, flash1=%d"
,
stmqspi.c:1731
find_sfdp_dummy()
LOG_DEBUG
(
"start of SFDP header for flash%c after %u dummy bytes"
,
stmqspi.c:1782
find_sfdp_dummy()
LOG_DEBUG
(
"no start of SFDP header even after %u dummy bytes"
,
count
)
;
stmqspi.c:1799
find_sfdp_dummy()
LOG_DEBUG
(
"%s: addr=0x%08"
PRIx32
" words=0x%08x dummy=%u"
,
stmqspi.c:1851
read_sfdp_block()
LOG_DEBUG
(
"raw SFDP data 0x%08"
PRIx32
,
*
buffer
)
;
stmqspi.c:1923
read_sfdp_block()
LOG_DEBUG
(
"QSPI_ABR register present"
)
;
stmqspi.c:2110
stmqspi_probe()
LOG_DEBUG
(
"OCTOSPI_MAGIC present"
)
;
stmqspi.c:2118
stmqspi_probe()
LOG_DEBUG
(
"OCTOSPI at 0x%08"
PRIx64
", io_base at 0x%08"
PRIx32
", OCTOSPI_CR 0x%08"
stmqspi.c:2162
stmqspi_probe()
LOG_DEBUG
(
"QSPI at 0x%08"
PRIx64
", io_base at 0x%08"
PRIx32
", QSPI_CR 0x%08"
stmqspi.c:2167
stmqspi_probe()
LOG_DEBUG
(
"id1 0x%06"
PRIx32
", id2 0x%06"
PRIx32
,
id1
,
id2
)
;
stmqspi.c:2189
stmqspi_probe()
LOG_DEBUG
(
"FSIZE = 0x%04x"
,
fsize
)
;
stmqspi.c:2325
stmqspi_probe()
LOG_DEBUG
(
"FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1."
)
;
stmqspi.c:2327
stmqspi_probe()
LOG_DEBUG
(
"FSIZE in DCR(1) is off by one regarding actual capacity. Fix for silicon bug?"
)
;
stmqspi.c:2329
stmqspi_probe()
LOG_DEBUG
(
"%s"
,
__func__
)
;
stmsmi.c:130
stmsmi_flash_bank_command()
LOG_DEBUG
(
"%s: from sector %u to sector %u"
,
__func__
,
first
,
last
)
;
stmsmi.c:312
stmsmi_erase()
LOG_DEBUG
(
"%s: address=0x%08"
PRIx32
" len=0x%08"
PRIx32
,
stmsmi.c:367
smi_write_buffer()
LOG_DEBUG
(
"%s: offset=0x%08"
PRIx32
" count=0x%08"
PRIx32
,
stmsmi.c:393
stmsmi_write()
LOG_DEBUG
(
"Valid SMI on device %s at address "
TARGET_ADDR_FMT
,
stmsmi.c:553
stmsmi_probe()
LOG_DEBUG
(
"sectors: 0x%"
PRIx32
""
,
sectors
)
;
str7x.c:338
str7x_erase()
LOG_DEBUG
(
"status: 0x%2.2x"
,
status
)
;
str9xpec.c:109
str9xpec_isc_status()
LOG_DEBUG
(
"ISC_MODE Enabled"
)
;
str9xpec.c:137
str9xpec_isc_enable()
LOG_DEBUG
(
"ISC_MODE Disabled"
)
;
str9xpec.c:165
str9xpec_isc_disable()
LOG_DEBUG
(
"ISC_CONFIGURATION"
)
;
str9xpec.c:181
str9xpec_read_config()
LOG_DEBUG
(
"blank check: first_bank: %u, last_bank: %u"
,
first
,
last
)
;
str9xpec.c:316
str9xpec_blank_check()
LOG_DEBUG
(
"erase: first_bank: %u, last_bank: %u"
,
first
,
last
)
;
str9xpec.c:397
str9xpec_erase_area()
LOG_DEBUG
(
"ISC_ERASE"
)
;
str9xpec.c:411
str9xpec_erase_area()
LOG_DEBUG
(
"protect: first_bank: %u, last_bank: %u"
,
first
,
last
)
;
str9xpec.c:509
str9xpec_protect()
LOG_DEBUG
(
"first_sector: %i, last_sector: %i"
,
first_sector
,
last_sector
)
;
str9xpec.c:607
str9xpec_write()
LOG_DEBUG
(
"ISC_PROGRAM"
)
;
str9xpec.c:611
str9xpec_write()
LOG_DEBUG
(
"\tIR end_state = %s"
,
svf.c:1024
svf_run_command()
LOG_DEBUG
(
"\tDR end_state = %s"
,
svf.c:1028
svf_run_command()
LOG_DEBUG
(
"\tfrequency = %f"
,
svf_para
.
frequency
)
;
svf.c:1058
svf_run_command()
LOG_DEBUG
(
"\tlength = %d"
,
xxr_para_tmp
->
len
)
;
svf.c:1117
svf_run_command()
SVF_BUF_LOG
(
DEBUG
,
*
pbuffer_tmp
,
xxr_para_tmp
->
len
,
argus
[
i
]
)
;
svf.c:1153
svf_run_command()
LOG_DEBUG
(
"\trun_state = %s"
,
tap_state_name
(
i_tmp
)
)
;
svf.c:1403
svf_run_command()
LOG_DEBUG
(
"\trun_count@TCK = %d"
,
run_count
)
;
svf.c:1416
svf_run_command()
LOG_DEBUG
(
"\tmin_time = %fs"
,
min_time
)
;
svf.c:1426
svf_run_command()
LOG_DEBUG
(
"\tmax_time = %fs"
,
max_time
)
;
svf.c:1434
svf_run_command()
LOG_DEBUG
(
"\tend_state = %s"
,
tap_state_name
(
i_tmp
)
)
;
svf.c:1443
svf_run_command()
LOG_DEBUG
(
"\tmove to %s by path_move"
,
svf.c:1534
svf_run_command()
LOG_DEBUG
(
"\tmove to %s by svf_add_statemove"
,
svf.c:1551
svf_run_command()
LOG_DEBUG
(
"\ttrst_mode = %s"
,
svf_trst_mode_name
[
svf_para
.
trst_mode
]
)
;
svf.c:1591
svf_run_command()
if
(
debug_level
>=
LOG_LVL_DEBUG
)
{
svf.c:1607
svf_run_command()
SVF_BUF_LOG
(
DEBUG
,
svf_tdi_buffer
,
svf_check_tdo_para
[
0
]
.
bit_len
,
"TDO read"
)
;
svf.c:1617
svf_run_command()
LOG_DEBUG
(
"Creating new SWIM \"tap\", Chip: %s, Tap: %s, Dotted: %s"
,
swim.c:81
handle_swim_newtap_command()
LOG_DEBUG
(
__func__
)
;
swim.c:116
swim_transport_select()
LOG_DEBUG
(
__func__
)
;
swim.c:125
swim_transport_init()
LOG_TARGET_DEBUG
(
target
,
"Examination started"
)
;
target.c:674
target_examine_one()
LOG_TARGET_DEBUG
(
target
,
"examine() returned error code %d"
,
retval
)
;
target.c:681
target_examine_one()
LOG_DEBUG
(
"offs 0x%zx count 0x%"
PRIx32
" wp 0x%"
PRIx32
" rp 0x%"
PRIx32
,
target.c:986
target_run_flash_async_algorithm()
LOG_DEBUG
(
"offs 0x%zx count 0x%"
PRIx32
" wp 0x%"
PRIx32
" rp 0x%"
PRIx32
,
target.c:1141
target_run_read_async_algorithm()
LOG_DEBUG
(
"Initializing targets..."
)
;
target.c:1598
handle_target_init_command()
LOG_DEBUG
(
"target event %i (%s) for core %s"
,
event
,
target.c:1784
target_call_event_callbacks()
LOG_DEBUG
(
"target reset %i (%s)"
,
reset_mode
,
target.c:1803
target_call_reset_callbacks()
LOG_DEBUG
(
"%c%c "
TARGET_ADDR_FMT
"-"
TARGET_ADDR_FMT
" (%"
PRIu32
" bytes)"
,
target.c:1910
print_wa_layout()
LOG_DEBUG
(
"MMU disabled, using physical "
target.c:1989
target_alloc_working_area_try()
LOG_DEBUG
(
"MMU enabled, using virtual "
target.c:2000
target_alloc_working_area_try()
LOG_DEBUG
(
"allocated new working area of %"
PRIu32
" bytes at address "
TARGET_ADDR_FMT
,
target.c:2043
target_alloc_working_area_try()
LOG_DEBUG
(
"freed %"
PRIu32
" bytes of working area at address "
TARGET_ADDR_FMT
,
target.c:2111
target_free_working_area_restore()
LOG_DEBUG
(
"freeing all working areas"
)
;
target.c:2140
target_free_all_working_areas_restore()
LOG_DEBUG
(
"writing buffer of %"
PRIu32
" byte at "
TARGET_ADDR_FMT
,
target.c:2354
target_write_buffer()
LOG_DEBUG
(
"reading buffer of %"
PRIu32
" byte at "
TARGET_ADDR_FMT
,
target.c:2419
target_read_buffer()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", value: 0x%16.16"
PRIx64
""
,
target.c:2548
target_read_u64()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
" failed"
,
target.c:2553
target_read_u64()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", value: 0x%8.8"
PRIx32
""
,
target.c:2572
target_read_u32()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
" failed"
,
target.c:2577
target_read_u32()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", value: 0x%4.4"
PRIx16
,
target.c:2596
target_read_u16()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
" failed"
,
target.c:2601
target_read_u16()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", value: 0x%2.2"
PRIx8
,
target.c:2618
target_read_u8()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
" failed"
,
target.c:2623
target_read_u8()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", value: 0x%16.16"
PRIx64
""
,
target.c:2639
target_write_u64()
LOG_DEBUG
(
"failed: %i"
,
retval
)
;
target.c:2646
target_write_u64()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", value: 0x%8.8"
PRIx32
""
,
target.c:2660
target_write_u32()
LOG_DEBUG
(
"failed: %i"
,
retval
)
;
target.c:2667
target_write_u32()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", value: 0x%8.8"
PRIx16
,
target.c:2681
target_write_u16()
LOG_DEBUG
(
"failed: %i"
,
retval
)
;
target.c:2688
target_write_u16()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", value: 0x%2.2"
PRIx8
,
target.c:2701
target_write_u8()
LOG_DEBUG
(
"failed: %i"
,
retval
)
;
target.c:2706
target_write_u8()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", value: 0x%16.16"
PRIx64
""
,
target.c:2720
target_write_phys_u64()
LOG_DEBUG
(
"failed: %i"
,
retval
)
;
target.c:2727
target_write_phys_u64()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", value: 0x%8.8"
PRIx32
""
,
target.c:2741
target_write_phys_u32()
LOG_DEBUG
(
"failed: %i"
,
retval
)
;
target.c:2748
target_write_phys_u32()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", value: 0x%8.8"
PRIx16
,
target.c:2762
target_write_phys_u16()
LOG_DEBUG
(
"failed: %i"
,
retval
)
;
target.c:2769
target_write_phys_u16()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", value: 0x%2.2"
PRIx8
,
target.c:2782
target_write_phys_u8()
LOG_DEBUG
(
"failed: %i"
,
retval
)
;
target.c:2787
target_write_phys_u8()
LOG_DEBUG
(
"-"
)
;
target.c:3033
handle_reg_command()
LOG_DEBUG
(
"waiting for target %s..."
,
target.c:3240
target_wait_state()
LOG_DEBUG
(
"-"
)
;
target.c:3262
handle_halt_command()
LOG_DEBUG
(
"-"
)
;
target.c:3339
handle_step_command()
LOG_DEBUG
(
"read_memory: read at "
TARGET_ADDR_FMT
" with width=%u and count=%zu failed"
,
target.c:4591
handle_target_read_memory()
LOG_DEBUG
(
"target: %s (%s) event: %d (%s) action: %s"
,
target.c:4781
target_handle_event()
LOG_DEBUG
(
"target_create failed"
)
;
target.c:5985
target_create()
LOG_DEBUG
(
"%s "
,
targetname
)
;
target.c:6085
create_target_list_node()
LOG_DEBUG
(
"Empty SMP target"
)
;
target.c:6123
handle_target_smp()
LOG_DEBUG
(
"%d"
,
CMD_ARGC
)
;
target.c:6126
handle_target_smp()
LOG_DEBUG
(
"%s"
,
msg
)
;
target_request.c:45
target_asciimsg()
LOG_DEBUG
(
"size: %i, length: %i"
,
(
int
)
size
,
(
int
)
length
)
;
target_request.c:70
target_hexmsg()
LOG_DEBUG
(
"%s"
,
line
)
;
target_request.c:89
target_hexmsg()
LOG_DEBUG
(
"Initializing NAND devices..."
)
;
tcl.c:484
handle_nand_init_command()
LOG_DEBUG
(
"'%s' driver usage field missing"
,
controller
->
name
)
;
tcl.c:549
create_nand_device()
LOG_DEBUG
(
"'%s' driver usage field missing"
,
driver_name
)
;
tcl.c:1307
handle_flash_bank_command()
LOG_DEBUG
(
"Initializing flash devices..."
)
;
tcl.c:1364
handle_flash_init_command()
LOG_DEBUG
(
"Creating New Tap, Chip: %s, Tap: %s, Dotted: %s, %d params"
,
tcl.c:404
handle_jtag_newtap_args()
LOG_DEBUG
(
"JTAG tap: %s event: %d (%s)\n\taction: %s"
,
tcl.c:546
jtag_tap_handle_event()
LOG_DEBUG
(
"Initializing jtag devices..."
)
;
tcl.c:685
handle_jtag_init_command()
LOG_DEBUG
(
"unhandled nonprintable: %2.2x"
,
*
buf_p
)
;
telnet_server.c:822
telnet_input()
LOG_DEBUG
(
"Error TX Data %d"
,
result
)
;
ti_icdi_usb.c:154
icdi_send_packet()
LOG_DEBUG
(
"Error RX Data %d"
,
result
)
;
ti_icdi_usb.c:162
icdi_send_packet()
LOG_DEBUG
(
"Resending packet %d"
,
++
retry
)
;
ti_icdi_usb.c:171
icdi_send_packet()
LOG_DEBUG
(
"Unexpected Reply from ICDI: %c"
,
h
->
read_buffer
[
0
]
)
;
ti_icdi_usb.c:174
icdi_send_packet()
LOG_DEBUG
(
"maximum nack retries attempted"
)
;
ti_icdi_usb.c:179
icdi_send_packet()
LOG_DEBUG
(
"Error RX timeout %d"
,
result
)
;
ti_icdi_usb.c:201
icdi_send_packet()
LOG_DEBUG
(
"Error RX Data %d"
,
result
)
;
ti_icdi_usb.c:203
icdi_send_packet()
LOG_DEBUG
(
"maximum data retries attempted"
)
;
ti_icdi_usb.c:221
icdi_send_packet()
LOG_DEBUG
(
"max packet supported : %i bytes"
,
h
->
max_packet
)
;
ti_icdi_usb.c:372
icdi_usb_query()
LOG_DEBUG
(
"icdi_usb_open"
)
;
ti_icdi_usb.c:671
icdi_usb_open()
LOG_DEBUG
(
"transport: %d vid: 0x%04x pid: 0x%04x serial: %s"
,
param
->
transport
,
ti_icdi_usb.c:681
icdi_usb_open()
LOG_DEBUG
(
"claim interface failed"
)
;
ti_icdi_usb.c:694
icdi_usb_open()
LOG_DEBUG
(
"malloc failed"
)
;
ti_icdi_usb.c:724
icdi_usb_open()
LOG_DEBUG
(
"set fmmac2 = 0x%04"
PRIx32
""
,
fmmac2
)
;
tms470.c:503
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmmac1 = 0x%04"
PRIx32
""
,
fmmac1
)
;
tms470.c:511
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmtcreg = 0x2fc0"
)
;
tms470.c:517
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmmaxpp = 50"
)
;
tms470.c:523
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmmaxcp = 0x%04x"
,
0xf000
+
2000
)
;
tms470.c:529
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmptr3 = 0x9964"
)
;
tms470.c:538
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmptr3 = 0x9b64"
)
;
tms470.c:542
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmmaxep = 0x%04"
PRIx32
""
,
fmmaxep
)
;
tms470.c:545
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmptr4 = 0xa000"
)
;
tms470.c:551
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmpsetup = 0x%04"
PRIx32
""
,
(
delay
<
<
4
)
|
(
delay
<
<
8
)
)
;
tms470.c:565
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmpvevaccess = 0x%04"
PRIx32
""
,
k
)
;
tms470.c:572
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmpchold = 0x%04"
PRIx32
""
,
k
)
;
tms470.c:579
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmpvevhold = 0x%04"
PRIx32
""
,
k
)
;
tms470.c:581
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmpvevsetup = 0x%04"
PRIx32
""
,
k
)
;
tms470.c:583
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmcvaccess = 0x%04"
PRIx32
""
,
k
)
;
tms470.c:590
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmcsetup = 0x%04"
PRIx32
""
,
k
)
;
tms470.c:597
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmehold = 0x%04"
PRIx32
""
,
k
)
;
tms470.c:604
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmpwidth = 0x%04"
PRIx32
""
,
delay
*
8
)
;
tms470.c:610
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmcwidth = 0x%04"
PRIx32
""
,
delay
*
1000
)
;
tms470.c:612
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmewidth = 0x%04"
PRIx32
""
,
delay
*
5400
)
;
tms470.c:614
tms470_flash_initialize_internal_state_machine()
LOG_DEBUG
(
"set fmmstat = 0x%04"
PRIx32
""
,
fmmstat
)
;
tms470.c:628
tms470_flash_status()
LOG_DEBUG
(
"set glbctrl = 0x%08"
PRIx32
""
,
glbctrl
|
0x10
)
;
tms470.c:683
tms470_erase_sector()
LOG_DEBUG
(
"set fmregopt = 0x%08x"
,
0
)
;
tms470.c:688
tms470_erase_sector()
LOG_DEBUG
(
"set fmbsea = 0x%04"
PRIx32
""
,
fmbsea
|
(
1
<
<
sector
)
)
;
tms470.c:700
tms470_erase_sector()
LOG_DEBUG
(
"set fmbseb = 0x%04"
PRIx32
""
,
fmbseb
|
(
1
<
<
(
sector
-
16
)
)
)
;
tms470.c:704
tms470_erase_sector()
LOG_DEBUG
(
"write *(uint16_t *)0x%08"
PRIx32
"=0x0040"
,
flash_addr
)
;
tms470.c:712
tms470_erase_sector()
LOG_DEBUG
(
"write *(uint16_t *)0x%08"
PRIx32
"=0x0020"
,
flash_addr
)
;
tms470.c:714
tms470_erase_sector()
LOG_DEBUG
(
"write *(uint16_t *)0x%08"
PRIx32
"=0xffff"
,
flash_addr
)
;
tms470.c:716
tms470_erase_sector()
LOG_DEBUG
(
"set fmbsea = 0x%04"
PRIx32
""
,
fmbsea
)
;
tms470.c:732
tms470_erase_sector()
LOG_DEBUG
(
"set fmbseb = 0x%04"
PRIx32
""
,
fmbseb
)
;
tms470.c:736
tms470_erase_sector()
LOG_DEBUG
(
"set fmregopt = 0x%08"
PRIx32
""
,
orig_fmregopt
)
;
tms470.c:740
tms470_erase_sector()
LOG_DEBUG
(
"set glbctrl = 0x%08"
PRIx32
""
,
glbctrl
)
;
tms470.c:742
tms470_erase_sector()
LOG_DEBUG
(
"bank %u sector %u is %s"
,
tms470.c:1096
tms470_protect_check()
LOG_DEBUG
(
"tracepoint: %i"
,
(
int
)
number
)
;
trace.c:20
trace_point()
LOG_DEBUG
(
"register '%s'"
,
new_transport
->
name
)
;
transport.c:146
transport_register()
LOG_DEBUG
(
"%s"
,
__func__
)
;
transport.c:219
handle_transport_init()
LOG_DEBUG
(
"section %02i at addr 0x%04x (size 0x%04x)"
,
section_index
,
addr
,
ublast2_access_libusb.c:76
ublast2_write_firmware_section()
LOG_DEBUG
(
"section %02i at addr 0x%04x (size 0x%04x)"
,
section_index
,
addr
,
ulink.c:442
ulink_write_firmware_section()
tap_set_state
(
tap_get_end_state
(
)
)
;
ulink.c:1429
ulink_queue_statemove()
tap_set_state
(
TAP_IRSHIFT
)
;
ulink.c:1496
ulink_queue_scan()
tap_set_state
(
TAP_DRSHIFT
)
;
ulink.c:1511
ulink_queue_scan()
tap_set_state
(
cmd
->
cmd
.
scan
->
end_state
)
;
ulink.c:1608
ulink_queue_scan()
tap_set_state
(
TAP_RESET
)
;
ulink.c:1628
ulink_queue_tlr_reset()
tap_set_state
(
TAP_RESET
)
;
ulink.c:1681
ulink_queue_reset()
tap_set_state
(
path
[
state_count
]
)
;
ulink.c:1739
ulink_queue_pathmove()
LOG_DEBUG_IO
(
"ULINK TCK setup: delay_tck = %i (%li Hz),"
,
ulink.c:2023
ulink_khz()
LOG_DEBUG_IO
(
" delay_tms = %i (%li Hz),"
,
ulink.c:2026
ulink_khz()
LOG_DEBUG_IO
(
" delay_scan_in = %i (%li Hz),"
,
ulink.c:2029
ulink_khz()
LOG_DEBUG_IO
(
" delay_scan_out = %i (%li Hz),"
,
ulink.c:2032
ulink_khz()
LOG_DEBUG_IO
(
" delay_scan_io = %i (%li Hz),"
,
ulink.c:2035
ulink_khz()
LOG_DEBUG_IO
(
"(size=%d, buf=[%s]) -> %"
PRIu32
,
size
,
str
,
usb_blaster.c:166
ublast_buf_read()
LOG_DEBUG_IO
(
"(size=%d, buf=[%s]) -> %"
PRIu32
,
size
,
str
,
usb_blaster.c:177
ublast_buf_write()
LOG_DEBUG_IO
(
"(byte=0x%02x)"
,
abyte
)
;
usb_blaster.c:258
ublast_queue_byte()
LOG_DEBUG_IO
(
"(tms=%d)"
,
!!
tms
)
;
usb_blaster.c:329
ublast_clock_tms()
LOG_DEBUG_IO
(
"."
)
;
usb_blaster.c:346
ublast_idle_clock()
LOG_DEBUG_IO
(
"(tdi=%d)"
,
!!
tdi
)
;
usb_blaster.c:367
ublast_clock_tdi()
LOG_DEBUG_IO
(
"(tdi=%d)"
,
!!
tdi
)
;
usb_blaster.c:392
ublast_clock_tdi_flip_tms()
LOG_DEBUG_IO
(
"(nb_bytes=%d, bytes=[0x%02x, ...])"
,
nb_bytes
,
usb_blaster.c:422
ublast_queue_bytes()
LOG_DEBUG_IO
(
"(bits=%02x..., nb_bits=%d)"
,
bits
[
0
]
,
nb_bits
)
;
usb_blaster.c:449
ublast_tms_seq()
LOG_DEBUG_IO
(
"(num_bits=%d)"
,
cmd
->
num_bits
)
;
usb_blaster.c:461
ublast_tms()
LOG_DEBUG_IO
(
"(num_states=%u, last_state=%d)"
,
usb_blaster.c:477
ublast_path_move()
tap_set_state
(
cmd
->
path
[
i
]
)
;
usb_blaster.c:484
ublast_path_move()
LOG_DEBUG_IO
(
"(from %s to %s)"
,
tap_state_name
(
tap_get_state
(
)
)
,
usb_blaster.c:502
ublast_state_move()
tap_set_state
(
state
)
;
usb_blaster.c:509
ublast_state_move()
LOG_DEBUG_IO
(
"%s(buf=%p, num_bits=%d)"
,
__func__
,
buf
,
nb_bytes
*
8
)
;
usb_blaster.c:531
ublast_read_byteshifted_tdos()
LOG_DEBUG_IO
(
"%s(buf=%p, num_bits=%d)"
,
__func__
,
buf
,
nb_bits
)
;
usb_blaster.c:563
ublast_read_bitbang_tdos()
LOG_DEBUG_IO
(
"%s(cycles=%u, end_state=%d)"
,
__func__
,
num_cycles
,
state
)
;
usb_blaster.c:678
ublast_runtest()
LOG_DEBUG_IO
(
"%s(cycles=%u)"
,
__func__
,
num_cycles
)
;
usb_blaster.c:687
ublast_stableclocks()
LOG_DEBUG_IO
(
"%s(scan=%s, type=%s, bits=%d, buf=[%s], end_state=%d)"
,
__func__
,
usb_blaster.c:717
ublast_scan()
LOG_DEBUG_IO
(
"%s(us=%d)"
,
__func__
,
us
)
;
usb_blaster.c:738
ublast_usleep()
tap_set_state
(
TAP_RESET
)
;
usb_blaster.c:763
ublast_initial_wipeout()
tap_set_state
(
TAP_RESET
)
;
usb_blaster.c:874
ublast_init()
LOG_DEBUG_IO
(
"reset trst: %i srst %i"
,
usbprog.c:96
usbprog_execute_queue()
tap_set_state
(
TAP_RESET
)
;
usbprog.c:100
usbprog_execute_queue()
LOG_DEBUG_IO
(
"runtest %u cycles, end in %i"
,
usbprog.c:104
usbprog_execute_queue()
LOG_DEBUG_IO
(
"statemove end in %i"
,
cmd
->
cmd
.
statemove
->
end_state
)
;
usbprog.c:111
usbprog_execute_queue()
LOG_DEBUG_IO
(
"pathmove: %u states, end in %i"
,
usbprog.c:116
usbprog_execute_queue()
LOG_DEBUG_IO
(
"scan end in %i"
,
cmd
->
cmd
.
scan
->
end_state
)
;
usbprog.c:122
usbprog_execute_queue()
LOG_DEBUG_IO
(
"sleep %"
PRIu32
,
cmd
->
cmd
.
sleep
->
us
)
;
usbprog.c:132
usbprog_execute_queue()
tap_set_state
(
tap_get_end_state
(
)
)
;
usbprog.c:187
usbprog_state_move()
tap_set_state
(
cmd
->
path
[
state_count
]
)
;
usbprog.c:217
usbprog_path_move()
LOG_DEBUG_IO
(
"runtest: cur_state %s end_state %s"
,
tap_state_name
(
usbprog.c:247
usbprog_runtest()
tap_set_state
(
TAP_IRPAUSE
)
;
usbprog.c:294
usbprog_scan()
tap_set_state
(
TAP_DRPAUSE
)
;
usbprog.c:296
usbprog_scan()
LOG_DEBUG
(
"trst: %i, srst: %i"
,
trst
,
srst
)
;
usbprog.c:321
usbprog_reset()
LOG_DEBUG
(
"status: 0x%8.8"
PRIx32
,
*
status
)
;
virtex2.c:141
virtex2_read_stat()
LOG_DEBUG_IO
(
"-------------------------------------"
vsllink.c:94
vsllink_execute_queue()
LOG_DEBUG_IO
(
"runtest %u cycles, end in %s"
,
vsllink.c:101
vsllink_execute_queue()
LOG_DEBUG_IO
(
"statemove end in %s"
,
vsllink.c:110
vsllink_execute_queue()
LOG_DEBUG_IO
(
"pathmove: %u states, end in %s"
,
vsllink.c:118
vsllink_execute_queue()
LOG_DEBUG_IO
(
"JTAG Scan..."
)
;
vsllink.c:126
vsllink_execute_queue()
LOG_DEBUG_IO
(
vsllink.c:134
vsllink_execute_queue()
LOG_DEBUG_IO
(
vsllink.c:141
vsllink_execute_queue()
LOG_DEBUG_IO
(
"sleep %"
PRIu32
,
cmd
->
cmd
.
sleep
->
us
)
;
vsllink.c:158
vsllink_execute_queue()
LOG_DEBUG_IO
(
"add %u clocks"
,
vsllink.c:164
vsllink_execute_queue()
LOG_DEBUG_IO
(
"add %d jtag tms"
,
vsllink.c:194
vsllink_execute_queue()
LOG_DEBUG
(
"vsllink found on %04X:%04X"
,
vsllink.c:286
vsllink_interface_init()
tap_set_state
(
tap_get_end_state
(
)
)
;
vsllink.c:371
vsllink_state_move()
tap_set_state
(
path
[
i
]
)
;
vsllink.c:388
vsllink_path_move()
tap_set_state
(
ir_scan
?
TAP_IRPAUSE
:
TAP_DRPAUSE
)
;
vsllink.c:448
vsllink_scan()
LOG_DEBUG
(
"trst: %i, srst: %i"
,
trst
,
srst
)
;
vsllink.c:456
vsllink_reset()
LOG_DEBUG_IO
(
vsllink.c:638
vsllink_jtag_execute()
LOG_DEBUG
(
"SWD delay: %d, retry count: %d"
,
delay
,
retry_count
)
;
vsllink.c:705
vsllink_swd_frequency()
LOG_DEBUG
(
"SWD line reset"
)
;
vsllink.c:717
vsllink_swd_switch_seq()
LOG_DEBUG
(
"JTAG-to-SWD"
)
;
vsllink.c:722
vsllink_swd_switch_seq()
LOG_DEBUG
(
"SWD-to-JTAG"
)
;
vsllink.c:727
vsllink_swd_switch_seq()
LOG_DEBUG_IO
(
"%s"
,
line
)
;
vsllink.c:862
vsllink_debug_buffer()
LOG_DEBUG
(
"WRITE CMD: 0x%08"
PRIx32
""
,
cmd
)
;
w600.c:131
w600_start_do()
LOG_DEBUG
(
"WRITE START: 0x%08"
PRIx32
""
,
addr
)
;
w600.c:137
w600_start_do()
LOG_DEBUG
(
"DELAY %dms"
,
timeout
)
;
w600.c:142
w600_start_do()
LOG_DEBUG
(
"READ START..."
)
;
w600.c:148
w600_start_do()
LOG_DEBUG
(
"READ START: 0x%08"
PRIx32
""
,
status
)
;
w600.c:151
w600_start_do()
LOG_DEBUG
(
"READ START FAILED"
)
;
w600.c:153
w600_start_do()
LOG_DEBUG
(
"num_regs=%d, reg_class=%d"
,
(
*
reg_list_size
)
,
reg_class
)
;
x86_32_common.c:65
x86_32_get_gdb_reg_list()
LOG_DEBUG
(
"value %s = %08"
PRIx32
,
x86_32
->
cache
->
reg_list
[
i
]
.
name
,
x86_32_common.c:74
x86_32_get_gdb_reg_list()
LOG_DEBUG
(
"addr=0x%08"
PRIx32
", size=%"
PRIu32
", count=0x%"
PRIx32
", buf=%p"
,
x86_32_common.c:164
read_phys_mem()
LOG_DEBUG
(
"addr=0x%08"
PRIx32
", size=%"
PRIu32
", count=0x%"
PRIx32
", buf=%p"
,
x86_32_common.c:269
write_phys_mem()
LOG_DEBUG
(
"invalid read size"
)
;
x86_32_common.c:305
write_phys_mem()
LOG_DEBUG
(
"addr="
TARGET_ADDR_FMT
", size=%"
PRIu32
", count=0x%"
PRIx32
", buf=%p"
,
x86_32_common.c:573
x86_32_common_read_memory()
LOG_DEBUG
(
"addr="
TARGET_ADDR_FMT
", size=%"
PRIu32
", count=0x%"
PRIx32
", buf=%p"
,
x86_32_common.c:630
x86_32_common_write_memory()
LOG_DEBUG
(
"addr=0x%08"
PRIx32
", size=%"
PRIu32
", buf=%p"
,
addr
,
size
,
buf
)
;
x86_32_common.c:688
x86_32_common_read_io()
LOG_DEBUG
(
"addr=0x%08"
PRIx32
", size=%"
PRIu32
", buf=%p"
,
addr
,
size
,
buf
)
;
x86_32_common.c:766
x86_32_common_write_io()
LOG_DEBUG
(
"type=%d, addr="
TARGET_ADDR_FMT
,
bp
->
type
,
bp
->
address
)
;
x86_32_common.c:861
x86_32_common_add_breakpoint()
LOG_DEBUG
(
"type=%d, addr="
TARGET_ADDR_FMT
,
bp
->
type
,
bp
->
address
)
;
x86_32_common.c:872
x86_32_common_remove_breakpoint()
LOG_DEBUG
(
"addr=0x%08"
PRIx32
", bp_num=%"
PRIu8
", bp_type=%"
PRIu8
", pb_length=%"
PRIu8
,
x86_32_common.c:885
set_debug_regs()
LOG_DEBUG
(
"bp_num=%"
PRIu8
,
bp_num
)
;
x86_32_common.c:945
unset_debug_regs()
LOG_DEBUG
(
"id %"
PRIx32
,
bp
->
unique_id
)
;
x86_32_common.c:1020
set_swbp()
LOG_DEBUG
(
"set software breakpoint - orig byte=0x%02"
PRIx8
""
,
*
bp
->
orig_instr
)
;
x86_32_common.c:1030
set_swbp()
LOG_DEBUG
(
"id %"
PRIx32
,
bp
->
unique_id
)
;
x86_32_common.c:1076
unset_swbp()
LOG_DEBUG
(
"type=%d, addr="
TARGET_ADDR_FMT
,
bp
->
type
,
bp
->
address
)
;
x86_32_common.c:1125
set_breakpoint()
LOG_DEBUG
(
"type=%d, addr="
TARGET_ADDR_FMT
,
bp
->
type
,
bp
->
address
)
;
x86_32_common.c:1155
unset_breakpoint()
LOG_DEBUG
(
"type=%d, addr="
TARGET_ADDR_FMT
,
wp
->
rw
,
wp
->
address
)
;
x86_32_common.c:1183
set_watchpoint()
LOG_DEBUG
(
"type=%d, addr="
TARGET_ADDR_FMT
,
wp
->
rw
,
wp
->
address
)
;
x86_32_common.c:1239
unset_watchpoint()
LOG_DEBUG
(
"Invalid FP Comparator number in watchpoint"
)
;
x86_32_common.c:1247
unset_watchpoint()
LOG_DEBUG
(
"reg %s value 0x%08"
PRIx32
,
x86_32_common.c:1310
read_hw_reg_to_cache()
LOG_DEBUG
(
"reg %s value 0x%08"
PRIx32
,
x86_32
->
cache
->
reg_list
[
num
]
.
name
,
x86_32_common.c:1326
write_hw_reg_from_cache()
LOG_DEBUG
(
"address=0x%08"
PRIx32
", data_size=%u, b=0x%08"
PRIx32
,
x86_32_common.c:1432
target_fill_io()
LOG_DEBUG
(
"written %d bytes from %d"
,
dbg_written
,
dbg_count
)
;
xcf.c:470
read_write_data()
LOG_DEBUG
(
"XDS110: command 0x%02x return %"
PRIu32
" bytes, expected %"
PRIu32
,
xds110.c:633
xds_execute()
LOG_DEBUG
(
"XDS110: command 0x%02x returned error %d"
,
xds110.c:640
xds_execute()
LOG_DEBUG
(
"JTAG-to-SWD"
)
;
xds110.c:1101
xds110_swd_switch_seq()
LOG_DEBUG
(
"SWD-to-JTAG"
)
;
xds110.c:1118
xds110_swd_switch_seq()
LOG_DEBUG
(
"XDS110: refusing to enable sticky overrun detection"
)
;
xds110.c:1333
xds110_swd_queue_cmd()
LOG_DEBUG
(
"bit_file: %s %s %s,%s %"
PRIu32
""
,
bit_file
->
source_file
,
bit_file
->
part_name
,
xilinx_bit.c:116
xilinx_read_bit_file()
LOG_DEBUG
(
"Infineon XMC1000 erase sectors %u to %u"
,
first
,
last
)
;
xmc1xxx.c:93
xmc1xxx_erase()
LOG_DEBUG
(
"Erase-checking 0x%08"
PRIx32
,
start
)
;
xmc1xxx.c:203
xmc1xxx_erase_check()
LOG_DEBUG
(
"Infineon XMC1000 write at 0x%08"
PRIx32
" (%"
PRIu32
" bytes)"
,
xmc1xxx.c:254
xmc1xxx_write()
LOG_DEBUG
(
"copying %"
PRIu32
" bytes to SRAM "
TARGET_ADDR_FMT
,
xmc1xxx.c:307
xmc1xxx_write()
LOG_DEBUG
(
"writing 0x%08"
PRIx32
"-0x%08"
PRIx32
" (%"
PRIu32
"x)"
,
xmc1xxx.c:330
xmc1xxx_write()
LOG_DEBUG
(
"NVMCONF = %08"
PRIx32
,
nvmconf
)
;
xmc1xxx.c:394
xmc1xxx_protect_check()
LOG_DEBUG
(
"ID[%d] = %08"
PRIX32
,
i
,
chipid
[
i
]
)
;
xmc1xxx.c:421
xmc1xxx_get_info_command()
LOG_DEBUG
(
"ID[7] = %08"
PRIX32
,
chipid
[
7
]
)
;
xmc1xxx.c:428
xmc1xxx_get_info_command()
LOG_DEBUG
(
"IDCHIP = %08"
PRIx32
,
idchip
)
;
xmc1xxx.c:467
xmc1xxx_probe()
LOG_DEBUG
(
"%u sectors"
,
bank
->
num_sectors
)
;
xmc4xxx.c:272
xmc4xxx_load_bank_layout()
LOG_DEBUG
(
"\t%d: %uk"
,
i
,
capacity
[
i
]
)
;
xmc4xxx.c:306
xmc4xxx_load_bank_layout()
LOG_DEBUG
(
"Found XMC4xxx with devid: 0x%08"
PRIx32
,
devid
)
;
xmc4xxx.c:348
xmc4xxx_probe()
LOG_DEBUG
(
"XMC4xxx: XMC4100/4200 detected."
)
;
xmc4xxx.c:365
xmc4xxx_probe()
LOG_DEBUG
(
"XMC4xxx: XMC4400 detected."
)
;
xmc4xxx.c:369
xmc4xxx_probe()
LOG_DEBUG
(
"XMC4xxx: XMC4500 detected."
)
;
xmc4xxx.c:373
xmc4xxx_probe()
LOG_DEBUG
(
"XMC4xxx: XMC4700/4800 detected."
)
;
xmc4xxx.c:377
xmc4xxx_probe()
LOG_DEBUG
(
"Erasing sector %u @ 0x%08"
PRIx32
,
i
,
tmp_addr
)
;
xmc4xxx.c:556
xmc4xxx_erase()
LOG_DEBUG
(
"WLO: %08"
PRIx32
,
w_lo
)
;
xmc4xxx.c:655
xmc4xxx_write_page()
LOG_DEBUG
(
"WHI: %08"
PRIx32
,
w_hi
)
;
xmc4xxx.c:656
xmc4xxx_write_page()
LOG_DEBUG
(
"Setting flash protection with procon:"
)
;
xmc4xxx.c:1082
xmc4xxx_flash_protect()
LOG_DEBUG
(
"PROCON: %"
PRIx32
,
procon
)
;
xmc4xxx.c:1083
xmc4xxx_flash_protect()
LOG_DEBUG
(
"waiting 100ms"
)
;
xscale.c:403
xscale_read_tx()
LOG_DEBUG
(
"polling RX"
)
;
xscale.c:452
xscale_write_rx()
LOG_DEBUG
(
"waiting 100ms"
)
;
xscale.c:474
xscale_write_rx()
LOG_DEBUG
(
"loading miniIC at 0x%8.8"
PRIx32
""
,
va
)
;
xscale.c:642
xscale_load_ic()
LOG_DEBUG
(
"r0: 0x%8.8"
PRIx32
""
,
buffer
[
0
]
)
;
xscale.c:862
xscale_debug_entry()
LOG_DEBUG
(
"pc: 0x%8.8"
PRIx32
""
,
buffer
[
1
]
)
;
xscale.c:868
xscale_debug_entry()
LOG_DEBUG
(
"r%i: 0x%8.8"
PRIx32
""
,
i
,
buffer
[
i
+
1
]
)
;
xscale.c:875
xscale_debug_entry()
LOG_DEBUG
(
"cpsr: 0x%8.8"
PRIx32
""
,
buffer
[
9
]
)
;
xscale.c:879
xscale_debug_entry()
LOG_DEBUG
(
"target entered debug state in %s mode"
,
xscale.c:886
xscale_debug_entry()
LOG_DEBUG
(
"target->state: %s"
,
xscale.c:1012
xscale_halt()
LOG_DEBUG
(
"target was already halted"
)
;
xscale.c:1016
xscale_halt()
LOG_DEBUG
(
"target->state == TARGET_RESET"
)
;
xscale.c:1023
xscale_halt()
LOG_DEBUG
(
"-"
)
;
xscale.c:1118
xscale_resume()
LOG_DEBUG
(
"unset breakpoint at "
TARGET_ADDR_FMT
""
,
xscale.c:1155
xscale_resume()
LOG_DEBUG
(
"enable single-step"
)
;
xscale.c:1169
xscale_resume()
LOG_DEBUG
(
"writing cpsr with value 0x%8.8"
PRIx32
,
xscale.c:1183
xscale_resume()
LOG_DEBUG
(
"writing r%i with value 0x%8.8"
PRIx32
""
,
xscale.c:1190
xscale_resume()
LOG_DEBUG
(
"writing PC with value 0x%8.8"
PRIx32
,
xscale.c:1197
xscale_resume()
LOG_DEBUG
(
"disable single-step"
)
;
xscale.c:1210
xscale_resume()
LOG_DEBUG
(
"set breakpoint at "
TARGET_ADDR_FMT
""
,
xscale.c:1213
xscale_resume()
LOG_DEBUG
(
"writing cpsr with value 0x%8.8"
PRIx32
,
xscale.c:1248
xscale_resume()
LOG_DEBUG
(
"writing r%i with value 0x%8.8"
PRIx32
""
,
xscale.c:1254
xscale_resume()
LOG_DEBUG
(
"wrote PC with value 0x%8.8"
PRIx32
,
xscale.c:1260
xscale_resume()
LOG_DEBUG
(
"target resumed"
)
;
xscale.c:1275
xscale_resume()
LOG_DEBUG
(
"enable single-step"
)
;
xscale.c:1304
xscale_step_inner()
LOG_DEBUG
(
"writing cpsr with value 0x%8.8"
PRIx32
,
xscale.c:1334
xscale_step_inner()
LOG_DEBUG
(
"writing r%i with value 0x%8.8"
PRIx32
""
,
i
,
xscale.c:1343
xscale_step_inner()
LOG_DEBUG
(
"wrote PC with value 0x%8.8"
PRIx32
,
xscale.c:1352
xscale_step_inner()
LOG_DEBUG
(
"disable single-step"
)
;
xscale.c:1365
xscale_step_inner()
LOG_DEBUG
(
"current pc %"
PRIx32
,
current_pc
)
;
xscale.c:1401
xscale_step()
LOG_DEBUG
(
"target stepped"
)
;
xscale.c:1426
xscale_step()
LOG_DEBUG
(
"target->state: %s"
,
xscale.c:1443
xscale_assert_reset()
LOG_DEBUG
(
"-"
)
;
xscale.c:1485
xscale_deassert_reset()
LOG_DEBUG
(
"-"
)
;
xscale.c:1632
xscale_full_context()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", size: 0x%8.8"
PRIx32
", count: 0x%8.8"
PRIx32
,
xscale.c:1778
xscale_read_memory()
LOG_DEBUG
(
"address: "
TARGET_ADDR_FMT
", size: 0x%8.8"
PRIx32
", count: 0x%8.8"
PRIx32
,
xscale.c:1877
xscale_write_memory()
LOG_DEBUG
(
"no trace data collected"
)
;
xscale.c:2529
xscale_read_trace()
LOG_DEBUG
(
"XSTATE 0x%02X %s"
,
uc
,
xsvf.c:297
handle_xsvf_command()
LOG_DEBUG
(
"XCOMPLETE"
)
;
xsvf.c:349
handle_xsvf_command()
LOG_DEBUG
(
"XTDOMASK"
)
;
xsvf.c:359
handle_xsvf_command()
LOG_DEBUG
(
"XRUNTEST %d 0x%08X"
,
xruntest
,
xruntest
)
;
xsvf.c:375
handle_xsvf_command()
LOG_DEBUG
(
"XREPEAT %d"
,
xrepeat
)
;
xsvf.c:387
handle_xsvf_command()
LOG_DEBUG
(
"XSDRSIZE %d"
,
xsdrsize
)
;
xsvf.c:402
handle_xsvf_command()
LOG_DEBUG
(
"%s %d"
,
op_name
,
xsdrsize
)
;
xsvf.c:439
handle_xsvf_command()
LOG_DEBUG
(
"XSTATE 0x%02X %s"
,
uc
,
tap_state_name
(
mystate
)
)
;
xsvf.c:575
handle_xsvf_command()
LOG_DEBUG
(
"XENDIR 0x%02X %s"
,
uc
,
tap_state_name
(
xendir
)
)
;
xsvf.c:627
handle_xsvf_command()
LOG_DEBUG
(
"XENDDR %02X %s"
,
uc
,
tap_state_name
(
xenddr
)
)
;
xsvf.c:648
handle_xsvf_command()
LOG_DEBUG
(
"XSIR %d"
,
bitcount
)
;
xsvf.c:666
handle_xsvf_command()
LOG_DEBUG
(
"XSIR2 %d"
,
bitcount
)
;
xsvf.c:673
handle_xsvf_command()
LOG_DEBUG
(
"XWAIT %s %s usecs:%d"
,
tap_state_name
(
xsvf.c:762
handle_xsvf_command()
LOG_DEBUG
(
"XWAITSTATE %s %s clocks:%i usecs:%i"
,
xsvf.c:810
handle_xsvf_command()
LOG_DEBUG
(
"LCOUNT %d"
,
loop_count
)
;
xsvf.c:854
handle_xsvf_command()
LOG_DEBUG
(
"LDELAY %s clocks:%d usecs:%d"
,
tap_state_name
(
xsvf.c:879
handle_xsvf_command()
LOG_DEBUG
(
"LSDR"
)
;
xsvf.c:893
handle_xsvf_command()
LOG_DEBUG
(
"xsvf failed, setting taps to reasonable state"
)
;
xsvf.c:983
handle_xsvf_command()
LOG_DEBUG
(
"Scratch reg %s [0x%08"
PRIx32
"] set from gdb"
,
reg
->
name
,
xtensa.c:474
xtensa_core_reg_set()
LOG_DEBUG
(
"scratch_ars mapping: a3/%s, a4/%s"
,
xtensa.c:476
xtensa_core_reg_set()
LOG_TARGET_DEBUG
(
target
,
"PPTLB("
TARGET_ADDR_FMT
") -> 0x%08"
PRIx32
" exec_acc %d"
,
xtensa.c:580
xtensa_region_ar_exec()
LOG_TARGET_DEBUG
(
target
,
"Clearing %s (0x%08"
PRIx32
" -> 0x%08"
PRIx32
")"
,
xtensa.c:617
xtensa_window_state_save()
LOG_TARGET_DEBUG
(
target
,
"Restored %s (0x%08"
PRIx32
")"
,
xtensa.c:636
xtensa_window_state_restore()
LOG_DEBUG
(
"AR conflict: a%d -> ar%d"
,
a_name
,
j
-
XT_REG_IDX_AR0
)
;
xtensa.c:654
xtensa_scratch_regs_fixup()
LOG_DEBUG
(
"AR conflict: ar%d -> a%d"
,
j
-
XT_REG_IDX_AR0
,
a_name
)
;
xtensa.c:657
xtensa_scratch_regs_fixup()
LOG_TARGET_DEBUG
(
target
,
"start"
)
;
xtensa.c:679
xtensa_write_dirty_registers()
LOG_TARGET_DEBUG
(
target
,
"Writing back reg %s (%d) val %08"
PRIX32
,
xtensa.c:696
xtensa_write_dirty_registers()
LOG_TARGET_DEBUG
(
target
,
"Delaying MS write: 0x%x"
,
ms
)
;
xtensa.c:724
xtensa_write_dirty_registers()
LOG_TARGET_DEBUG
(
target
,
"Writing back reg cpenable (224) val %08"
PRIX32
,
regval
)
;
xtensa.c:738
xtensa_write_dirty_registers()
LOG_TARGET_DEBUG
(
target
,
"Writing back reg %s value %08"
PRIX32
", num =%i"
,
xtensa.c:804
xtensa_write_dirty_registers()
LOG_TARGET_DEBUG
(
xtensa.c:830
xtensa_write_dirty_registers()
LOG_TARGET_DEBUG
(
target
,
"Delayed MS (0x%x) write complete: 0x%x"
,
ms_regno
,
ms
)
;
xtensa.c:866
xtensa_write_dirty_registers()
LOG_TARGET_DEBUG
(
target
,
""
)
;
xtensa.c:891
xtensa_examine()
LOG_DEBUG
(
"OCD_ID = %08"
PRIx32
,
xtensa
->
dbg_mod
.
device_id
)
;
xtensa.c:909
xtensa_examine()
LOG_TARGET_DEBUG
(
xtensa
->
target
,
"write smpbreak set=0x%"
PRIx32
" clear=0x%"
PRIx32
,
set
,
clear
)
;
xtensa.c:936
xtensa_smpbreak_write()
LOG_TARGET_DEBUG
(
target
,
"set smpbreak=%"
PRIx32
", state=%i"
,
set
,
target
->
state
)
;
xtensa.c:952
xtensa_smpbreak_set()
LOG_TARGET_DEBUG
(
target
,
"Imprecise exception: %s: 0x%x"
,
xtensa.c:994
xtensa_imprecise_exception_occurred()
LOG_TARGET_DEBUG
(
target
,
"Imprecise exception: clearing %s (0x%x)"
,
xtensa.c:1011
xtensa_imprecise_exception_clear()
LOG_TARGET_DEBUG
(
target
,
"DSR (%08"
PRIX32
")"
,
dsr
)
;
xtensa.c:1024
xtensa_core_status_check()
LOG_TARGET_DEBUG
(
target
,
" begin"
)
;
xtensa.c:1165
xtensa_assert_reset()
LOG_TARGET_DEBUG
(
target
,
"halt=%d"
,
target
->
reset_halt
)
;
xtensa.c:1186
xtensa_deassert_reset()
LOG_TARGET_DEBUG
(
target
,
"begin"
)
;
xtensa.c:1206
xtensa_soft_reset_halt()
bool
debug_dsrs
=
!
xtensa
->
regs_fetched
||
LOG_LEVEL_IS
(
LOG_LVL_DEBUG
)
;
xtensa.c:1220
xtensa_fetch_all_regs()
LOG_TARGET_DEBUG
(
target
,
"start"
)
;
xtensa.c:1234
xtensa_fetch_all_regs()
LOG_TARGET_DEBUG
(
target
,
"Overriding MS (0x%x): 0x%x"
,
ms_regno
,
XT_MS_DISPST_DBG
)
;
xtensa.c:1252
xtensa_fetch_all_regs()
LOG_TARGET_DEBUG
(
target
,
"CPENABLE: was 0x%"
PRIx32
", all enabled"
,
cpenable
)
;
xtensa.c:1318
xtensa_fetch_all_regs()
LOG_DEBUG
(
"%s = 0x%x"
,
rlist
[
ridx
]
.
name
,
regval
)
;
xtensa.c:1426
xtensa_fetch_all_regs()
LOG_TARGET_DEBUG
(
target
,
"Caching MS: 0x%x"
,
ms
)
;
xtensa.c:1439
xtensa_fetch_all_regs()
LOG_DEBUG
(
"reg_class=%i, num_regs=%d"
,
(
int
)
reg_class
,
num_regs
)
;
xtensa.c:1508
xtensa_get_gdb_reg_list()
LOG_DEBUG
(
"SPARSE GDB reg 0x%x getting EPS%d 0x%x"
,
xtensa.c:1537
xtensa_get_gdb_reg_list()
LOG_TARGET_DEBUG
(
target
,
"start"
)
;
xtensa.c:1570
xtensa_halt()
LOG_TARGET_DEBUG
(
target
,
"target was already halted"
)
;
xtensa.c:1572
xtensa_halt()
LOG_TARGET_DEBUG
(
target
,
"Core status 0x%"
PRIx32
,
xtensa_dm_core_status_get
(
&
xtensa
->
dbg_mod
)
)
;
xtensa.c:1581
xtensa_halt()
LOG_TARGET_DEBUG
(
target
,
xtensa.c:1602
xtensa_prepare_resume()
LOG_TARGET_DEBUG
(
target
,
"DEBUGCAUSE 0x%x (watchpoint %lu) (break %lu)"
,
xtensa.c:1619
xtensa_prepare_resume()
LOG_TARGET_DEBUG
(
target
,
"start"
)
;
xtensa.c:1660
xtensa_do_resume()
LOG_TARGET_DEBUG
(
target
,
"start"
)
;
xtensa.c:1679
xtensa_resume()
LOG_TARGET_DEBUG
(
target
,
"current=%d, address="
TARGET_ADDR_FMT
", handle_breakpoints=%i"
,
xtensa.c:1732
xtensa_do_step()
LOG_TARGET_DEBUG
(
target
,
"oldps=%"
PRIx32
", oldpc=%"
PRIx32
" dbg_cause=%"
PRIx32
" exc_cause=%"
PRIx32
,
xtensa.c:1751
xtensa_do_step()
LOG_TARGET_DEBUG
(
target
,
"Increment PC to pass break instruction..."
)
;
xtensa.c:1758
xtensa_do_step()
LOG_TARGET_DEBUG
(
xtensa.c:1802
xtensa_do_step()
LOG_TARGET_DEBUG
(
target
,
xtensa.c:1821
xtensa_do_step()
LOG_TARGET_DEBUG
(
target
,
"Finish stepping. dsr=0x%08"
PRIx32
,
xtensa.c:1864
xtensa_do_step()
LOG_TARGET_DEBUG
(
target
,
xtensa.c:1879
xtensa_do_step()
LOG_DEBUG
(
"Stepping out of window exception, PC=%"
PRIX32
,
cur_pc
)
;
xtensa.c:1893
xtensa_do_step()
LOG_DEBUG
(
"Stepped from %"
PRIX32
" to %"
PRIX32
,
oldpc
,
cur_pc
)
;
xtensa.c:1903
xtensa_do_step()
LOG_DEBUG
(
"Done stepping, PC=%"
PRIX32
,
cur_pc
)
;
xtensa.c:1909
xtensa_do_step()
LOG_TARGET_DEBUG
(
target
,
"...Done, re-installing watchpoints."
)
;
xtensa.c:1912
xtensa_do_step()
LOG_DEBUG
(
"Restoring %s after stepping: 0x%08"
PRIx32
,
xtensa.c:1920
xtensa_do_step()
LOG_DEBUG
(
"address "
TARGET_ADDR_FMT
" not readable"
,
address
)
;
xtensa.c:2017
xtensa_read_memory()
LOG_TARGET_DEBUG
(
target
,
"Disabling LDDR32.P/SDDR32.P"
)
;
xtensa.c:2064
xtensa_read_memory()
LOG_TARGET_DEBUG
(
target
,
"Cache OPs: IHI %d, DHWBI %d"
,
issue_ihi
,
issue_dhwbi
)
;
xtensa.c:2247
xtensa_write_memory()
LOG_TARGET_DEBUG
(
target
,
"PWRSTAT: read 0x%08"
PRIx32
", clear 0x%08lx, reread 0x%08"
PRIx32
,
xtensa.c:2315
xtensa_poll()
LOG_TARGET_DEBUG
(
target
,
xtensa.c:2341
xtensa_poll()
LOG_TARGET_DEBUG
(
target
,
"not powered 0x%"
PRIX32
"%ld"
,
xtensa.c:2349
xtensa_poll()
LOG_TARGET_DEBUG
(
target
,
"Target halted, pc=0x%08"
PRIx32
xtensa.c:2380
xtensa_poll()
LOG_TARGET_DEBUG
(
target
,
"Halt reason=0x%08"
PRIX32
", exc_cause=%"
PRId32
", dsr=0x%08"
PRIx32
,
xtensa.c:2385
xtensa_poll()
LOG_TARGET_DEBUG
(
target
,
"Enabling PS.DIEXC: 0x%08x -> 0x%08x"
,
ps
,
newps
)
;
xtensa.c:2399
xtensa_poll()
LOG_TARGET_DEBUG
(
target
,
"IHI %d, DHWBI %d for address "
TARGET_ADDR_FMT
,
xtensa.c:2460
xtensa_update_instruction()
LOG_TARGET_DEBUG
(
target
,
xtensa.c:2465
xtensa_update_instruction()
LOG_TARGET_DEBUG
(
target
,
xtensa.c:2474
xtensa_update_instruction()
LOG_DEBUG
(
"DHWB dcache line for address "
TARGET_ADDR_FMT
,
address
)
;
xtensa.c:2502
xtensa_update_instruction()
LOG_TARGET_DEBUG
(
target
,
"DHWB second dcache line for address "
TARGET_ADDR_FMT
,
address
+
4
)
;
xtensa.c:2504
xtensa_update_instruction()
LOG_TARGET_DEBUG
(
target
,
"placed SW breakpoint %u @ "
TARGET_ADDR_FMT
,
xtensa.c:2574
xtensa_breakpoint_add()
LOG_TARGET_DEBUG
(
target
,
"placed HW breakpoint %u @ "
TARGET_ADDR_FMT
,
xtensa.c:2591
xtensa_breakpoint_add()
LOG_TARGET_DEBUG
(
target
,
"cleared SW breakpoint %u @ "
TARGET_ADDR_FMT
,
slot
,
breakpoint
->
address
)
;
xtensa.c:2617
xtensa_breakpoint_remove()
LOG_TARGET_DEBUG
(
target
,
"cleared HW breakpoint %u @ "
TARGET_ADDR_FMT
,
slot
,
breakpoint
->
address
)
;
xtensa.c:2632
xtensa_breakpoint_remove()
LOG_TARGET_DEBUG
(
target
,
"placed HW watchpoint @ "
TARGET_ADDR_FMT
,
xtensa.c:2687
xtensa_watchpoint_add()
LOG_TARGET_DEBUG
(
target
,
"cleared HW watchpoint @ "
TARGET_ADDR_FMT
,
xtensa.c:2707
xtensa_watchpoint_remove()
LOG_DEBUG
(
"setting core_mode: 0x%x"
,
algorithm_info
->
core_mode
)
;
xtensa.c:2789
xtensa_start_algorithm()
LOG_DEBUG
(
"Read mem params"
)
;
xtensa.c:2853
xtensa_wait_algorithm()
LOG_DEBUG
(
"Check mem param @ "
TARGET_ADDR_FMT
,
mem_params
[
i
]
.
address
)
;
xtensa.c:2855
xtensa_wait_algorithm()
LOG_DEBUG
(
"Read mem param @ "
TARGET_ADDR_FMT
,
mem_params
[
i
]
.
address
)
;
xtensa.c:2857
xtensa_wait_algorithm()
LOG_DEBUG
(
"Skip restoring register %s: 0x%8.8"
PRIx32
" -> 0x%8.8"
PRIx32
,
xtensa.c:2874
xtensa_wait_algorithm()
LOG_DEBUG
(
"restoring register %s: 0x%8.8"
PRIx32
" -> 0x%8.8"
PRIx32
,
xtensa.c:2883
xtensa_wait_algorithm()
LOG_DEBUG
(
"restoring register %s: 0x%8.8"
PRIx64
" -> 0x%8.8"
PRIx64
,
xtensa.c:2888
xtensa_wait_algorithm()
LOG_DEBUG
(
"restoring register %s %u-bits"
,
xtensa
->
core_cache
->
reg_list
[
i
]
.
name
,
reg
->
size
)
;
xtensa.c:2893
xtensa_wait_algorithm()
LOG_TARGET_DEBUG
(
target
,
xtensa.c:2981
xtensa_build_reg_cache()
LOG_TARGET_DEBUG
(
target
,
"xtensa->total_regs_num %d reg_list_size %d xtensa->dbregs_num %d"
,
xtensa.c:2997
xtensa_build_reg_cache()
LOG_TARGET_DEBUG
(
target
,
xtensa.c:3041
xtensa_build_reg_cache()
LOG_TARGET_DEBUG
(
target
,
"%s"
,
insn_buf
)
;
xtensa.c:3119
xtensa_gdbqc_parse_exec_tie_ops()
LOG_DEBUG
(
"TIE reg 0x%08"
PRIx32
" %s (%d bytes)"
,
regnum
,
iswrite
?
"write"
:
"read"
,
reglen
)
;
xtensa.c:3157
xtensa_gdbqc_qxtreg()
LOG_TARGET_DEBUG
(
target
,
"TIE response: %s"
,
*
response_p
)
;
xtensa.c:3240
xtensa_gdbqc_qxtreg()
LOG_TARGET_DEBUG
(
target
,
"memcheck: %dB @ 0x%08x"
,
size
,
base
)
;
xtensa.c:3304
xtensa_gdb_query_custom()
LOG_TARGET_DEBUG
(
target
,
"Set spill 0x%08"
PRIx32
" (%d)"
,
xtensa
->
spill_loc
,
xtensa
->
spill_bytes
)
;
xtensa.c:3352
xtensa_gdb_query_custom()
LOG_DEBUG
(
"start"
)
;
xtensa.c:3489
xtensa_target_deinit()
LOG_TARGET_DEBUG
(
target
,
"execute stub: %s"
,
CMD_ARGV
[
0
]
)
;
xtensa.c:3570
xtensa_cmd_exe_do()
LOG_DEBUG
(
"Setting PS (%s) index to %d"
,
rptr
->
name
,
xtensa
->
eps_dbglevel_idx
)
;
xtensa.c:3980
xtensa_cmd_xtreg_do()
LOG_DEBUG
(
"NX reg %s: index %d (%d)"
,
xtensa.c:4005
xtensa_cmd_xtreg_do()
LOG_DEBUG
(
"Added %s register %-16s: 0x%04x/0x%02x t%d (%d of %d)"
,
xtensa.c:4020
xtensa_cmd_xtreg_do()
LOG_DEBUG
(
"DAP: ap_num %"
PRId64
" DAP %p\n"
,
pc
->
ap_num
,
pc
->
dap
)
;
xtensa_chip.c:103
xtensa_chip_target_create()
LOG_DEBUG
(
"JTAG: %s:%s pos %u"
,
target
->
tap
->
chip
,
target
->
tap
->
tapname
,
xtensa_chip.c:106
xtensa_chip_target_create()
LOG_DEBUG
(
"DM examine: DAP AP select %d"
,
dm
->
debug_apsel
)
;
xtensa_debug_module.c:120
xtensa_dm_examine()
LOG_DEBUG
(
"DM examine: search for APB-type MEM-AP..."
)
;
xtensa_debug_module.c:126
xtensa_dm_examine()
LOG_DEBUG
(
"DM examine: Setting apsel to %d"
,
dm
->
debug_apsel
)
;
xtensa_debug_module.c:139
xtensa_dm_examine()
LOG_TARGET_DEBUG
(
target
,
"File-I/O: syscall breakpoint found at 0x%x"
,
pc
)
;
xtensa_fileio.c:64
xtensa_fileio_detect_proc()
LOG_TARGET_DEBUG
(
target
,
"File-I/O: syscall 0x%x 0x%x 0x%x 0x%x 0x%x"
,
xtensa_fileio.c:88
xtensa_get_gdb_fileio_info()
LOG_TARGET_DEBUG
(
target
,
"File-I/O: syscall unknown (%d), pc=0x%08X"
,
xtensa_fileio.c:160
xtensa_get_gdb_fileio_info()
LOG_TARGET_DEBUG
(
target
,
"File-I/O: syscall return code: 0x%x, errno: 0x%x , ctrl_c: %s"
,
xtensa_fileio.c:177
xtensa_gdb_fileio_end()
CHECK_RETVAL
(
arc_jtag_read_aux_reg_one
(
&
arc
->
jtag_info
,
ARC_AUX_SEC_BUILD_REG
,
&
value
)
)
;
zephyr.c:434
zephyr_create()
LOG_DEBUG
(
"ARC EM board has security subsystem, changing offsets"
)
;
zephyr.c:436
zephyr_create()
LOG_DEBUG
(
"Fetched thread%"
PRIx32
": {entry@0x%"
PRIx32
zephyr.c:560
zephyr_fetch_thread()
LOG_DEBUG
(
"Got information for %zu threads"
,
thread_array
.
elements
)
;
zephyr.c:611
zephyr_fetch_thread_list()
LOG_DEBUG
(
"Zephyr OpenOCD support version %"
PRId32
,
zephyr.c:726
zephyr_update_threads()
Call Tree
from
examples
All items filtered out
All items filtered out
Data Use
from
examples
LOG_LVL_DEBUG
is read by 1497 functions:
All items filtered out
LOG_LVL_DEBUG
loaded_plugin_load()
find_exe_path()
add_default_dirs()
parse_cmdline_args()
add_script_search_dir()
find_file()
log_puts()
gdb_timeout_warning()
script_debug()
register_command()
unregister_commands_match()
exec_command()
jep106_table_manufacturer()
adapter_khz_to_speed()
adapter_rclk_to_speed()
adapter_config_khz()
adapter_config_rclk()
adapter_gpio_config_handler()
jtag_call_event_callbacks()
jtag_add_statemove()
adapter_system_reset()
legacy_jtag_add_reset()
jtag_add_reset()
default_interface_jtag_execute_queue()
jtag_examine_chain()
jtag_validate_ircapture()
jtag_tap_init()
jtag_init_inner()
swd_init_reset()
jtag_init_reset()
dap_dp_poll_register()
jtag_debug_state_machine_()
handle_jtag_newtap_args()
jtag_tap_handle_event()
handle_jtag_init_command()
jtag_build_buffer()
jtag_read_buffer()
handle_swim_newtap_command()
swim_transport_select()
swim_transport_init()
arm_code_to_working_area()
at91sam9_nand_device_command()
nand_probe()
lpc3180_cycle_time()
lpc3180_init()
lpc3180_controller_ready()
lpc3180_nand_ready()
lpc3180_tc_ready()
lpc32xx_cycle_time()
lpc32xx_init()
lpc32xx_dma_ready()
lpc32xx_dump_oob()
lpc32xx_write_page_slc()
lpc32xx_read_page_slc()
lpc32xx_controller_ready()
lpc32xx_nand_ready()
lpc32xx_tc_ready()
imx31_write_page()
do_data_output()
mxc_nand_device_command()
mxc_init()
mxc_write_page()
initialize_nf_controller()
handle_nand_init_command()
create_nand_device()
aduc702x_erase()
aduc702x_write_single()
aducm360_write_block_sync()
aducm360_write_block_async()
aducm360_write_modified()
ambiqmicro_read_part_info()
check_flash_status()
ambiqmicro_exec_command()
ambiqmicro_write_block()
efc_get_status()
efc_get_result()
efc_start_command()
flashd_read_uid()
flashd_erase_entire_bank()
flashd_get_gpnvm()
flashd_clr_gpnvm()
flashd_get_lock_bits()
sam3_get_info()
sam3_protect_check()
sam3_get_details()
_sam3_probe()
sam3_erase()
sam3_protect()
sam3_page_write()
sam3_write()
sam3_handle_info_command()
efc_get_status()
efc_get_result()
efc_start_command()
flashd_read_uid()
flashd_erase_entire_bank()
flashd_erase_pages()
flashd_get_gpnvm()
flashd_clr_gpnvm()
flashd_get_lock_bits()
sam4_get_info()
sam4_protect_check()
sam4_get_details()
sam4_probe()
sam4_erase()
sam4_protect()
sam4_set_wait()
sam4_page_write()
sam4_write()
sam4_handle_info_command()
sam4l_erase()
sam4l_write_page()
sam4l_write_page_partial()
sam4l_write()
at91sam7_set_flash_mode()
at91sam7_wait_status_busy()
at91sam7_flash_command()
at91sam7_read_part_info()
at91sam7_write()
at91sam7_handle_gpnvm_command()
ath79_spi_bitbang_chunk()
ath79_flash_bank_command()
ath79_erase()
ath79_write_buffer()
ath79_write()
ath79_read_buffer()
ath79_read()
ath79_probe()
samv_efc_start_command()
samv_clear_gpnvm()
samv_page_write()
samv_write()
avr_jtagprg_chiperase()
avr_jtagprg_writeflashpage()
avrf_erase()
avrf_write()
avrf_handle_mass_erase_command()
cfi_intel_wait_status_busy()
cfi_spansion_wait_status_busy()
cfi_read_intel_pri_ext()
cfi_read_spansion_pri_ext()
cfi_read_atmel_pri_ext()
cfi_intel_write_block()
cfi_write_words()
cfi_read()
cfi_fixup_0002_erase_regions()
cfi_query_string()
cfi_probe()
flash_driver_read()
default_flash_verify()
flash_iterate_address_range()
flash_write_unlock_verify()
dsp5680xx_probe()
efm32x_wait_status()
efm32x_erase_page()
efm32x_write_word()
em357_wait_status_busy()
fm3_busy_wait()
fm4_flash_erase()
fm4_flash_write()
mb9bf_probe()
s6e2cc_probe()
jtagspi_set_user_ir()
jtagspi_cmd()
jtagspi_handle_set()
jtagspi_handle_cmd()
jtagspi_handle_always_4byte()
jtagspi_read_status()
jtagspi_wait()
jtagspi_erase()
jtagspi_read()
jtagspi_write()
kinetis_mdm_write_register()
kinetis_mdm_read_register()
kinetis_mdm_poll_register()
kinetis_mdm_halt()
kinetis_check_flash_security_status()
kinetis_ftfx_command()
kinetis_erase()
kinetis_write_sections()
kinetis_write_inner()
kinetis_probe_chip()
kinetis_probe()
kinetis_blank_check()
kinetis_ke_mdm_write_register()
kinetis_ke_mdm_read_register()
kinetis_ke_mdm_poll_register()
kinetis_ke_blank_check()
lpc2000_iap_call()
lpc2000_write()
lpc288x_wait_status_busy()
lpc2900_wait_status()
lpc2900_write()
lpcspifi_set_hw_mode()
lpcspifi_erase()
lpcspifi_write()
lpcspifi_read_flash_id()
mrvlqspi_set_ss_state()
mrvlqspi_stop_transfer()
mrvlqspi_fifo_flush()
mrvlqspi_read_byte()
mrvlqspi_read_id()
mrvlqspi_flash_erase()
mrvlqspi_flash_write()
nrf5_wait_for_nvmc()
nrf5_read_ficr_info_part()
nrf51_52_partno_check()
nrf53_91_partno_check()
nrf51_get_ram_size()
nrf5_probe_chip()
nrf5_erase_page()
nrf5_ll_flash_write()
numicro_get_arm_arch()
numicro_reg_unlock()
numicro_fmc_cmd()
numicro_protect_check()
numicro_erase()
numicro_write()
numicro_probe()
numicro_flash_bank_command()
pic32mx_wait_status_busy()
pic32mx_erase()
pic32mx_write()
pic32mx_handle_unlock_command()
psoc4_sysreq()
psoc4_write()
psoc4_probe()
ap_write_register()
ap_read_register()
ap_poll_register()
stellaris_set_flash_timing()
stellaris_read_clock_info()
stellaris_read_part_info()
stellaris_write_block()
stellaris_write()
stm32x_wait_status_busy()
stm32x_wait_status_busy()
stm32x_protect_check()
stm32x_protect()
setup_sector()
stm32x_probe()
stm32x_protect_check()
stm32x_erase()
stm32x_protect()
stm32x_write_block()
stm32x_probe()
stm32x_set_rdp()
stm32l4_wait_status_busy()
stm32l4_set_secbb()
stm32l4_protect_same_bank()
stm32l4_write()
stm32l4_probe()
stm32lx_write_half_pages()
stm32lx_probe()
stm32lx_wait_until_bsy_clear_timeout()
stmqspi_flash_bank_command()
poll_busy()
read_status_reg()
stmqspi_handle_mass_erase_command()
stmqspi_handle_set()
stmqspi_handle_cmd()
qspi_erase_sector()
stmqspi_erase()
stmqspi_blank_check()
qspi_verify()
qspi_read_write_block()
stmqspi_read()
stmqspi_write()
stmqspi_verify()
find_sfdp_dummy()
read_sfdp_block()
stmqspi_probe()
stmsmi_flash_bank_command()
stmsmi_erase()
smi_write_buffer()
stmsmi_write()
stmsmi_probe()
str7x_erase()
str9xpec_isc_status()
str9xpec_isc_enable()
str9xpec_isc_disable()
str9xpec_read_config()
str9xpec_blank_check()
str9xpec_erase_area()
str9xpec_protect()
str9xpec_write()
handle_flash_bank_command()
handle_flash_init_command()
tms470_flash_initialize_internal_state_machine()
tms470_flash_status()
tms470_erase_sector()
tms470_protect_check()
read_write_data()
xmc1xxx_erase()
xmc1xxx_erase_check()
xmc1xxx_write()
xmc1xxx_protect_check()
xmc1xxx_get_info_command()
xmc1xxx_probe()
xmc4xxx_load_bank_layout()
xmc4xxx_probe()
xmc4xxx_erase()
xmc4xxx_write_page()
xmc4xxx_flash_protect()
bluenrgx_erase()
bluenrgx_write()
psoc6_erase_sector()
psoc6_erase_row()
psoc6_program_row()
psoc5lp_find_device()
psoc5lp_eeprom_write()
psoc5lp_erase()
psoc5lp_write()
psoc5lp_protect_check()
psoc5lp_probe()
max32xxx_write_block()
max32xxx_write()
max32xxx_probe()
esirisc_flash_init()
aducm302x_probe()
aducm302x_erase()
aducm302x_protect()
aducm302x_write_block()
aducm302x_write()
fespi_flash_bank_command()
fespi_erase()
fespi_write()
fespi_probe()
w600_start_do()
stm32x_wait_status_busy()
stm32l4_wait_status_busy()
stm32l4_wait_status_busy()
rpchf_read()
spi_sfdp()
sh_qspi_erase()
sh_qspi_write()
sh_qspi_read()
sh_qspi_probe()
sh_qspi_flash_bank_command()
rs14100_init()
rs14100_erase()
rp2040_call_rom_func()
rp2040_finalize_stack_free()
rp2040_stack_grab_and_prep()
rp2040_flash_write()
rp2040_flash_erase()
rp2040_flash_probe()
pic32mm_wait_status_busy()
pic32mm_erase()
pic32mm_handle_unlock_command()
rsl10_ll_flash_erase()
rsl10_ll_flash_write()
qn908x_update_reg()
qn908x_load_lock_stat()
qn908x_init_flash()
qn908x_read_page_lock()
qn908x_erase()
qn908x_protect()
qn908x_write()
qn908x_auto_probe()
qn908x_handle_mass_erase_command()
eneispif_flash_bank_command()
eneispif_read_reg()
eneispif_write_reg()
eneispif_erase()
eneispif_write()
eneispif_read_flash_id()
hl_transport_jtag_command()
hl_transport_init()
hl_jtag_transport_select()
hl_swd_transport_select()
hl_interface_open()
hl_interface_init_target()
hl_interface_init()
hl_interface_quit()
hl_interface_handle_device_desc_command()
hl_interface_handle_layout_command()
hl_layout_open()
hl_layout_init()
jlink_execute_stableclocks()
jlink_execute_runtest()
jlink_execute_statemove()
jlink_execute_pathmove()
jlink_execute_scan()
jlink_execute_sleep()
adjust_swd_buffer_size()
jaylink_log_handler()
jlink_state_move()
jlink_path_move()
jlink_reset()
config_trace()
jlink_flush()
jlink_swd_switch_seq()
jlink_swd_run_queue()
move_to_state()
ftdi_khz()
ftdi_execute_runtest()
ftdi_execute_statemove()
ftdi_execute_tms()
ftdi_execute_pathmove()
ftdi_execute_scan()
ftdi_reset()
ftdi_execute_sleep()
ftdi_execute_stableclocks()
ftdi_initialize()
ftdi_swd_run_queue()
ftdi_swd_queue_cmd()
ftdi_swd_switch_seq()
mpsse_purge()
buffer_write_byte()
buffer_write()
buffer_add_read()
mpsse_clock_data()
mpsse_clock_tms_cs()
mpsse_set_data_bits_low_byte()
mpsse_set_data_bits_high_byte()
mpsse_read_data_bits_low_byte()
mpsse_read_data_bits_high_byte()
single_byte_boolean_helper()
mpsse_loopback_config()
mpsse_set_divisor()
mpsse_divide_by_5_config()
mpsse_rtck_config()
mpsse_set_frequency()
read_cb()
write_cb()
mpsse_flush()
usbprog_execute_queue()
usbprog_state_move()
usbprog_path_move()
usbprog_runtest()
usbprog_scan()
usbprog_reset()
dtc_run_download()
rlink_state_move()
rlink_path_move()
rlink_scan()
rlink_execute_queue()
rlink_init()
ulink_write_firmware_section()
ulink_queue_statemove()
ulink_queue_scan()
ulink_queue_tlr_reset()
ulink_queue_reset()
ulink_queue_pathmove()
ulink_khz()
vsllink_execute_queue()
vsllink_interface_init()
vsllink_state_move()
vsllink_path_move()
vsllink_scan()
vsllink_reset()
vsllink_jtag_execute()
vsllink_swd_frequency()
vsllink_swd_switch_seq()
vsllink_debug_buffer()
armjtagew_execute_queue()
armjtagew_state_move()
armjtagew_path_move()
armjtagew_scan()
armjtagew_reset()
armjtagew_tap_execute()
armjtagew_usb_write()
armjtagew_usb_read()
jtag_libusb_bulk_transfer_n()
stlink_usb_usb_xfer_noerrcheck()
stlink_tcp_send_cmd()
stlink_usb_error_check()
stlink_cmd_allow_retry()
stlink_usb_exit_mode()
stlink_usb_init_mode()
stlink_usb_idcode()
stlink_usb_trace_disable()
stlink_usb_trace_enable()
stlink_usb_read_mem8()
stlink_usb_write_mem8()
stlink_usb_read_mem16()
stlink_usb_write_mem16()
stlink_usb_read_mem32()
stlink_usb_write_mem32()
stlink_usb_read_mem32_noaddrinc()
stlink_usb_write_mem32_noaddrinc()
stlink_dump_speed_map()
stlink_usb_usb_open()
stlink_tcp_open()
stlink_open()
stlink_usb_init_access_port()
stlink_usb_close_access_port()
stlink_usb_rw_misc_out()
stlink_usb_rw_misc_in()
stlink_read_dap_register()
stlink_write_dap_register()
stlink_usb_open_ap()
stlink_dap_dp_write()
stlink_usb_misc_rw_segment()
stlink_swim_op_read_mem()
stlink_swim_op_write_mem()
stlink_dap_init()
stlink_dap_quit()
stlink_dap_reset()
icdi_send_packet()
icdi_usb_query()
icdi_usb_open()
osbdm_add_pathmove()
osbdm_add_statemove()
osbdm_init()
kitprog_hid_command()
kitprog_set_protocol()
kitprog_get_status()
kitprog_set_unknown()
kitprog_acquire_psoc()
kitprog_reset_target()
kitprog_swd_sync()
kitprog_swd_seq()
kitprog_generic_acquire()
kitprog_swd_switch_seq()
kitprog_swd_run_queue()
opendous_execute_queue()
opendous_state_move()
opendous_path_move()
opendous_scan()
opendous_reset()
opendous_simple_command()
opendous_tap_append_scan()
opendous_tap_execute()
opendous_usb_write()
opendous_usb_read()
cmsis_dap_flush_read()
cmsis_dap_metacmd_targetsel()
cmsis_dap_swd_write_from_queue()
cmsis_dap_swd_read_process()
cmsis_dap_swd_switch_seq()
cmsis_dap_init()
cmsis_dap_execute_tlr_reset()
cmsis_dap_flush()
cmsis_dap_add_jtag_sequence()
cmsis_dap_add_tms_sequence()
cmsis_dap_state_move()
cmsis_dap_execute_scan()
cmsis_dap_pathmove()
cmsis_dap_execute_pathmove()
cmsis_dap_execute_runtest()
cmsis_dap_execute_stableclocks()
cmsis_dap_execute_tms()
cmsis_dap_usb_open()
cmsis_dap_hid_open()
xds_execute()
xds110_swd_switch_seq()
xds110_swd_queue_cmd()
picoprobe_flush()
picoprobe_read_write_bits()
picoprobe_write_bits()
picoprobe_read_bits()
picoprobe_swd_run_queue()
picoprobe_swd_queue_cmd()
picoprobe_swd_switch_seq()
string_descriptor_equal()
jtag_libusb_match_serial()
jtag_libusb_choose_interface()
ublast_buf_read()
ublast_buf_write()
ublast_queue_byte()
ublast_clock_tms()
ublast_idle_clock()
ublast_clock_tdi()
ublast_clock_tdi_flip_tms()
ublast_queue_bytes()
ublast_tms_seq()
ublast_tms()
ublast_path_move()
ublast_state_move()
ublast_read_byteshifted_tdos()
ublast_read_bitbang_tdos()
ublast_runtest()
ublast_stableclocks()
ublast_scan()
ublast_usleep()
ublast_initial_wipeout()
ublast_init()
ublast2_write_firmware_section()
handle_init_command()
setup_command_handler()
or1k_create_reg_list()
or1k_jtag_read_regs()
or1k_jtag_write_regs()
or1k_save_context()
or1k_restore_context()
or1k_read_core_reg()
or1k_write_core_reg()
or1k_get_core_reg()
or1k_set_core_reg()
or1k_build_reg_cache()
or1k_debug_entry()
or1k_halt()
or1k_assert_reset()
or1k_deassert_reset()
or1k_soft_reset_halt()
is_any_soft_breakpoint()
or1k_resume_or_step()
or1k_add_breakpoint()
or1k_remove_breakpoint()
or1k_read_memory()
or1k_write_memory()
or1k_examine()
or1k_addreg_command_handler()
or1k_adv_jtag_init()
adbg_select_module()
adbg_ctrl_write()
adbg_wb_burst_read()
adbg_wb_burst_write()
or1k_adv_jtag_read_memory()
or1k_adv_jtag_write_memory()
or1k_adv_jtag_jsp_xfer()
or1k_tap_mohor_init()
or1k_tap_vjtag_init()
or1k_tap_xilinx_bscan_init()
handle_pld_init_command()
xilinx_read_bit_file()
virtex2_read_stat()
rtos_qsymbol()
rtos_thread_packet()
rtos_get_gdb_reg()
rtos_get_gdb_reg_list()
rtos_generic_stack_read()
rtos_cortex_m_stack_align()
freertos_update_threads()
freertos_get_thread_reg_list()
get_stacking_info_arm926ejs()
ecos_check_app_info()
chibios_update_stacking()
nuttx_update_threads()
chromium_ec_detect_rtos()
chromium_ec_update_threads()
hwthread_update_threads()
zephyr_create()
zephyr_fetch_thread()
zephyr_fetch_thread_list()
zephyr_update_threads()
rtkernel_add_task()
rtkernel_update_threads()
rtkernel_get_thread_reg_list()
rtt_register_sink()
rtt_unregister_sink()
sig_handler()
telnet_input()
gdb_last_signal()
gdb_get_char_inner()
gdb_write()
gdb_log_incoming_packet()
gdb_log_outgoing_packet()
gdb_get_packet_inner()
gdb_signal_reply()
gdb_fileio_reply()
gdb_new_connection()
gdb_connection_closed()
gdb_get_registers_packet()
gdb_set_registers_packet()
gdb_get_register_packet()
gdb_set_register_packet()
gdb_error()
gdb_read_memory_packet()
gdb_write_memory_packet()
gdb_write_memory_binary_packet()
gdb_step_continue_packet()
gdb_breakpoint_watchpoint_packet()
smp_reg_list_noread()
gdb_handle_vcont_packet()
gdb_v_packet()
gdb_fileio_response_packet()
gdb_input_inner()
gdb_target_add_one()
rtt_new_connection()
rtt_connection_closed()
svf_run_command()
adi_jtag_dp_scan_u32()
jtagdp_overrun_check()
jtagdp_transaction_endcheck()
jtag_ap_q_bankselect()
swd_queue_dp_bankselect()
swd_multidrop_select_inner()
swd_multidrop_select()
swd_queue_ap_bankselect()
swd_select()
arm11_check_init()
arm11_debug_entry()
arm11_leave_debug_state()
arm11_poll()
arm11_halt()
arm11_resume()
arm11_step()
arm11_assert_reset()
arm11_deassert_reset()
arm11_read_memory_inner()
arm11_write_memory_inner()
arm11_add_breakpoint()
arm11_examine()
arm11_add_ir()
arm11_add_debug_scan_n()
arm11_add_debug_inst()
arm11_read_dscr()
arm11_write_dscr()
arm11_run_instr_no_data()
arm11_run_instr_data_to_core()
arm11_run_instr_data_from_core()
arm11_sc7_run()
arm11_read_memory_word()
arm720t_scan_cp15()
arm720t_post_debug_entry()
arm7tdmi_write_xpsr()
arm7tdmi_write_xpsr_im8()
arm7tdmi_branch_resume_thumb()
arm7_9_clear_watchpoints()
arm7_9_assign_wp()
arm7_9_set_software_breakpoints()
arm7_9_set_breakpoint()
arm7_9_unset_breakpoint()
arm7_9_poll()
arm7_9_assert_reset()
arm7_9_deassert_reset()
arm7_9_soft_reset_halt()
arm7_9_halt()
arm7_9_debug_entry()
arm7_9_full_context()
arm7_9_restore_context()
arm7_9_resume()
arm7_9_step()
arm7_9_read_memory()
arm920t_post_debug_entry()
arm920t_write_memory()
arm920t_handle_read_cache_command()
arm920t_handle_read_mmu_command()
arm926ejs_examine_debug_reason()
arm926ejs_post_debug_entry()
arm946e_invalidate_whole_dcache()
arm946e_invalidate_whole_icache()
arm946e_post_debug_entry()
arm946e_pre_restore_context()
arm946e_invalidate_dcache()
arm946e_invalidate_icache()
arm946e_write_memory()
arm946e_read_memory()
arm9tdmi_write_xpsr()
arm9tdmi_write_xpsr_im8()
arm9tdmi_branch_resume_thumb()
arm_set_cpsr()
armv4_5_set_core_reg()
armv4_5_run_algorithm_inner()
armv4_5_mmu_translate_va()
armv7a_read_midr()
armv7a_read_ttbcr()
armv7a_read_mpidr()
armv7a_identify_cache()
armv7a_l1_d_cache_sanity_check()
armv7a_l1_i_cache_sanity_check()
armv7a_l1_d_cache_flush_level()
arm7a_l2x_sanity_check()
armv7m_restore_context()
armv7m_read_core_reg()
armv7m_write_core_reg()
armv7m_start_algorithm()
armv7m_wait_algorithm()
armv7m_blank_check_memory()
armv7m_maybe_skip_bkpt_inst()
armv8_read_ttbcr32()
armv8_read_reg()
armv8_write_reg()
armv8_set_cpsr()
armv8_handle_exception_catch_command()
armv8_get_gdb_reg_list()
armv8_cache_d_inner_flush_level()
armv8_identify_cache()
dpmv8_exec_opcode()
dpmv8_bpwp_disable()
dpmv8_mrc()
dpmv8_mcr()
armv8_dpm_modeswitch()
dpmv8_read_reg()
dpmv8_write_reg()
dpmv8_bpwp_setup()
dpmv8_add_breakpoint()
dpmv8_watchpoint_setup()
armv8_dpm_handle_exception()
mem_ap_setup_transfer_verify_size_packing()
dap_dp_init()
dap_dp_init_or_reconnect()
mem_ap_init()
dap_to_swd()
dap_to_jtag()
dap_find_get_ap()
dap_get_ap()
dap_get_config_ap()
dap_put_ap()
rtp_read_cs_regs()
rtp_rom_loop()
dap_lookup_cs_component()
dpm_mrc()
dpm_mrrc()
dpm_mcr()
dpm_mcrr()
dpm_read_reg_u64()
arm_dpm_read_reg()
dpm_write_reg_u64()
dpm_write_reg()
dpm_bpwp_setup()
dpm_add_breakpoint()
dpm_watchpoint_setup()
arm_tpiu_swo_handle_event()
handle_arm_tpiu_swo_enable()
handle_arm_tpiu_swo_init()
avr32_write_core_reg()
avr32_ap7k_halt()
avr32_ap7k_resume()
avr32_ap7k_read_memory()
avr32_ap7k_write_memory()
avr_init_target()
avr_arch_state()
avr_poll()
avr_halt()
avr_resume()
avr_step()
avr_assert_reset()
avr_deassert_reset()
breakpoint_add_internal()
context_breakpoint_add_internal()
hybrid_breakpoint_add_internal()
breakpoint_free()
breakpoint_remove_all_internal()
watchpoint_free()
watchpoint_add_internal()
watchpoint_clear_target()
watchpoint_hit()
cortex_a_mmu_modify()
cortex_a_exec_opcode()
cortex_a_write_dcc()
cortex_a_bpwp_enable()
cortex_a_bpwp_disable()
cortex_a_poll()
cortex_a_internal_restore()
cortex_a_resume()
cortex_a_debug_entry()
cortex_a_post_debug_entry()
cortex_a_step()
cortex_a_restore_context()
cortex_a_set_breakpoint()
cortex_a_set_context_breakpoint()
cortex_a_set_hybrid_breakpoint()
cortex_a_unset_breakpoint()
cortex_a_set_watchpoint()
cortex_a_unset_watchpoint()
cortex_a_assert_reset()
cortex_a_deassert_reset()
cortex_a_write_cpu_memory()
cortex_a_read_cpu_memory()
cortex_a_read_phys_memory()
cortex_a_read_memory()
cortex_a_write_phys_memory()
cortex_a_write_memory()
cortex_a_examine_first()
cortex_m_slow_read_all_regs()
cortex_m_fast_read_all_regs()
cortex_m_clear_halt()
cortex_m_single_step_core()
cortex_m_endreset_event()
cortex_m_examine_exception_reason()
cortex_m_erratum_check_breakpoint()
cortex_m_debug_entry()
cortex_m_poll_one()
cortex_m_poll_smp()
cortex_m_halt_one()
cortex_m_soft_reset_halt()
cortex_m_restore_one()
cortex_m_restore_smp()
cortex_m_resume()
cortex_m_step()
cortex_m_assert_reset()
cortex_m_deassert_reset()
cortex_m_set_breakpoint()
cortex_m_unset_breakpoint()
cortex_m_add_breakpoint()
cortex_m_set_watchpoint()
cortex_m_unset_watchpoint()
cortex_m_add_watchpoint()
cortex_m_remove_watchpoint()
cortex_m_dwt_setup()
cortex_m_examine()
cortex_m_dcc_read()
dsp563xx_get_core_reg()
dsp563xx_set_core_reg()
dsp563xx_reg_pc_read()
dsp563xx_init_target()
dsp563xx_arch_state()
dsp563xx_poll()
dsp563xx_halt()
dsp563xx_resume()
dsp563xx_step_ex()
dsp563xx_assert_reset()
dsp563xx_deassert_reset()
dsp563xx_read_memory_core()
dsp563xx_read_memory()
dsp563xx_write_memory_core()
dsp563xx_write_memory()
dsp563xx_once_request_debug()
dsp5680xx_drscan()
jtag_data_read()
dsp5680xx_read_core_reg()
eonce_enter_debug_mode_without_reset()
eonce_enter_debug_mode()
dsp5680xx_init_target()
dsp5680xx_resume()
dsp5680xx_read_16_single()
set_fm_ck_div()
embeddedice_write_reg()
etb_read_reg_w_check()
etb_write_reg()
etm_build_reg_cache()
etm_read_reg_w_check()
etm_write_reg()
handle_etm_config_command()
handle_etm_info_command()
fa526_write_xpsr()
fa526_write_xpsr_im8()
feroceon_write_xpsr()
feroceon_write_xpsr_im8()
feroceon_branch_resume_thumb()
hl_dcc_read()
adapter_init_arch_info()
adapter_init_target()
adapter_target_create()
adapter_debug_entry()
adapter_poll()
hl_assert_reset()
hl_deassert_reset()
adapter_halt()
adapter_resume()
adapter_step()
adapter_read_memory()
adapter_write_memory()
autodetect_image_type()
image_elf_read_headers()
image_elf32_read_section()
image_elf64_read_section()
image_read_section()
image_calculate_checksum()
drscan()
lakemont_get_core_reg()
lakemont_set_core_reg()
enter_probemode()
exit_probemode()
halt_prep()
read_all_core_hw_regs()
write_all_core_hw_regs()
read_hw_reg()
write_hw_reg()
submit_reg_pir()
submit_instruction_pir()
lakemont_poll()
lakemont_step()
lakemont_reset_break()
lakemont_reset_assert()
lakemont_reset_deassert()
ls1_sap_init_target()
ls1_sap_arch_state()
ls1_sap_halt()
ls1_sap_resume()
ls1_sap_step()
ls1_sap_assert_reset()
ls1_sap_deassert_reset()
ls1_sap_read_memory()
ls1_sap_write_memory()
mips32_read_core_reg()
mips32_write_core_reg()
mips32_run_and_wait()
mips32_run_algorithm()
mips32_configure_break_unit()
mips32_cpu_probe()
mips32_read_config_regs()
wait_for_pracc_rw()
mips32_pracc_exec()
mips32_pracc_synchronize_cache()
mips32_pracc_write_mem()
mips32_pracc_fastdata_xfer_synchronize_cache()
mips32_pracc_fastdata_xfer()
mips_ejtag_enter_debug()
ejtag_v20_print_imp()
ejtag_v26_print_imp()
ejtag_main_print_imp()
mips_ejtag_init()
mips64_ejtag_exit_debug()
mips_m4k_debug_entry()
mips_m4k_poll()
mips_m4k_halt()
mips_m4k_assert_reset()
mips_m4k_deassert_reset()
mips_m4k_internal_restore()
mips_m4k_step()
mips_m4k_set_breakpoint()
mips_m4k_unset_breakpoint()
mips_m4k_set_watchpoint()
mips_m4k_unset_watchpoint()
mips_m4k_read_memory()
mips_m4k_write_memory()
mips_m4k_examine()
mips_m4k_bulk_write_memory()
mips_m4k_bulk_read_memory()
target_rtt_write_callback()
target_examine_one()
target_run_flash_async_algorithm()
target_run_read_async_algorithm()
handle_target_init_command()
target_call_event_callbacks()
target_call_reset_callbacks()
print_wa_layout()
target_alloc_working_area_try()
target_free_working_area_restore()
target_free_all_working_areas_restore()
target_write_buffer()
target_read_buffer()
target_read_u64()
target_read_u32()
target_read_u16()
target_read_u8()
target_write_u64()
target_write_u32()
target_write_u16()
target_write_u8()
target_write_phys_u64()
target_write_phys_u32()
target_write_phys_u16()
target_write_phys_u8()
handle_reg_command()
target_wait_state()
handle_halt_command()
handle_step_command()
handle_target_read_memory()
target_handle_event()
target_create()
create_target_list_node()
handle_target_smp()
target_asciimsg()
target_hexmsg()
trace_point()
x86_32_get_gdb_reg_list()
read_phys_mem()
write_phys_mem()
x86_32_common_read_memory()
x86_32_common_write_memory()
x86_32_common_read_io()
x86_32_common_write_io()
x86_32_common_add_breakpoint()
x86_32_common_remove_breakpoint()
set_debug_regs()
unset_debug_regs()
set_swbp()
unset_swbp()
set_breakpoint()
unset_breakpoint()
set_watchpoint()
unset_watchpoint()
read_hw_reg_to_cache()
write_hw_reg_from_cache()
target_fill_io()
xscale_read_tx()
xscale_write_rx()
xscale_load_ic()
xscale_debug_entry()
xscale_halt()
xscale_resume()
xscale_step_inner()
xscale_step()
xscale_assert_reset()
xscale_deassert_reset()
xscale_full_context()
xscale_read_memory()
xscale_write_memory()
xscale_read_trace()
aarch64_mmu_modify()
aarch64_init_debug_access()
aarch64_wait_halt_one()
aarch64_prepare_halt_smp()
aarch64_halt_one()
update_halt_gdb()
aarch64_poll()
aarch64_restore_one()
aarch64_prepare_restart_one()
aarch64_do_restart_one()
aarch64_restart_one()
aarch64_step_restart_smp()
aarch64_resume()
aarch64_debug_entry()
aarch64_post_debug_entry()
aarch64_step()
aarch64_restore_context()
aarch64_set_breakpoint()
aarch64_set_context_breakpoint()
aarch64_set_hybrid_breakpoint()
aarch64_unset_breakpoint()
aarch64_set_watchpoint()
aarch64_unset_watchpoint()
aarch64_enable_reset_catch()
aarch64_clear_reset_catch()
aarch64_assert_reset()
aarch64_deassert_reset()
aarch64_read_cpu_memory()
aarch64_examine_first()
stm8_set_hwbreak()
stm8_configure_break_unit()
stm8_examine_debug_reason()
stm8_debug_entry()
stm8_write_memory()
stm8_read_memory()
stm8_speed()
stm8_poll()
stm8_halt()
stm8_reset_assert()
stm8_resume()
stm8_read_core_reg()
stm8_write_core_reg()
stm8_step()
stm8_set_breakpoint()
stm8_unset_breakpoint()
stm8_set_watchpoint()
stm8_unset_watchpoint()
stm8_run_and_wait()
stm8_run_algorithm()
stm8_jim_configure()
dap_init_all()
semihosting_common_init()
semihosting_common()
riscv_batch_run()
dump_field()
riscv_program_write()
riscv_program_exec()
dtmcontrol_scan_via_bscan()
dtmcontrol_scan()
riscv_create_target()
riscv_init_target()
riscv_deinit_target()
maybe_add_trigger_t1()
maybe_add_trigger_t2()
maybe_add_trigger_t6()
add_trigger()
riscv_add_breakpoint()
remove_trigger()
riscv_remove_watchpoint()
riscv_hit_watchpoint()
old_or_new_riscv_step()
riscv_examine()
halt_prep()
riscv_halt_go_all_harts()
riscv_halt()
riscv_assert_reset()
riscv_deassert_reset()
riscv_resume_prep_all_harts()
disable_triggers()
enable_triggers()
resume_prep()
riscv_resume()
riscv_mmu()
riscv_address_translate()
riscv_get_gdb_reg_list_internal()
riscv_run_algorithm()
riscv_checksum_memory()
riscv_poll_hart()
set_debug_reason()
sample_memory()
riscv_openocd_poll()
riscv_openocd_step()
riscv_resume_go_all_harts()
riscv_step_rtos_hart()
riscv_set_current_hartid()
riscv_invalidate_register_cache()
riscv_set_register()
riscv_get_register()
riscv_enumerate_triggers()
register_get()
register_set()
riscv_init_registers()
riscv_semihosting()
riscv_semihosting_setup()
riscv_semihosting_post_result()
dtmcontrol_scan()
idcode_scan()
increase_dbus_busy_delay()
increase_interrupt_high_delay()
dump_field()
cache_set32()
cache_write()
read_remote_csr()
write_remote_csr()
execute_resume()
reg_cache_get()
reg_cache_set()
register_read()
halt()
deinit_target()
strict_step()
examine()
poll_target()
read_memory()
write_memory()
init_target()
get_dm()
dump_field()
dtmcontrol_scan()
increase_dmi_busy_delay()
increase_ac_busy_delay()
execute_abstract_command()
register_write_direct()
register_read_direct()
deinit_target()
examine()
init_target()
deassert_reset()
execute_fence()
log_memory_access()
read_memory_bus_v0()
log_mem_access_result()
mem_should_skip_progbuf()
mem_should_skip_sysbus()
mem_should_skip_abstract()
read_memory_abstract()
write_memory_abstract()
read_memory_progbuf_inner()
read_memory_progbuf()
write_memory_bus_v0()
write_memory_bus_v1()
write_memory_progbuf()
riscv013_get_register()
riscv013_set_register()
select_prepped_harts()
riscv013_halt_go()
riscv013_halt_reason()
riscv013_write_debug_buffer()
riscv013_step_or_resume_current_hart()
mem_ap_init_target()
mem_ap_deinit_target()
mem_ap_arch_state()
mem_ap_halt()
mem_ap_resume()
mem_ap_step()
mem_ap_assert_reset()
mem_ap_deassert_reset()
mem_ap_read_memory()
mem_ap_write_memory()
esirisc_disable_interrupts()
esirisc_save_interrupts()
esirisc_restore_interrupts()
esirisc_restore_hwdc()
esirisc_save_context()
esirisc_restore_context()
esirisc_flush_caches()
esirisc_wait_debug_active()
esirisc_read_memory()
esirisc_write_memory()
esirisc_next_breakpoint()
esirisc_add_breakpoint()
esirisc_add_breakpoints()
esirisc_remove_breakpoint()
esirisc_remove_breakpoints()
esirisc_next_watchpoint()
esirisc_add_watchpoint()
esirisc_add_watchpoints()
esirisc_remove_watchpoint()
esirisc_remove_watchpoints()
esirisc_halt()
esirisc_disable_step()
esirisc_enable_step()
esirisc_resume_or_step()
esirisc_resume()
esirisc_step()
esirisc_debug_step()
esirisc_debug_reset()
esirisc_debug_enable()
esirisc_debug_entry()
esirisc_assert_reset()
esirisc_reset_entry()
esirisc_deassert_reset()
esirisc_get_gdb_arch()
esirisc_get_gdb_reg_list()
esirisc_read_reg()
esirisc_write_reg()
esirisc_read_csr()
esirisc_write_csr()
esirisc_get_reg()
esirisc_set_reg()
esirisc_build_reg_cache()
esirisc_identify()
esirisc_examine()
esirisc_jtag_read_byte()
esirisc_jtag_read_hword()
esirisc_jtag_read_word()
esirisc_jtag_write_byte()
esirisc_jtag_write_hword()
esirisc_jtag_write_word()
esirisc_jtag_read_reg()
esirisc_jtag_write_reg()
esirisc_jtag_read_csr()
esirisc_jtag_write_csr()
armv7a_mmu_dump_table()
mips_mips64_debug_entry()
mips_mips64_poll()
mips_mips64_halt()
mips_mips64_assert_reset()
mips_mips64_deassert_reset()
mips_mips64_set_hwbp()
mips_mips64_set_breakpoint()
mips_mips64_set_watchpoint()
mips_mips64_unset_hwbp()
mips_mips64_unset_breakpoint()
mips_mips64_resume()
mips_mips64_step()
mips_mips64_unset_watchpoint()
mips_mips64_read_memory()
mips_mips64_bulk_write_memory()
mips_mips64_write_memory()
mips64_write_core_reg()
mips64_configure_break_unit()
wait_for_pracc_rw()
mips64_pracc_exec_read()
mips64_pracc_exec_write()
mips64_pracc_exec()
mips64_pracc_read_u64()
mips64_pracc_read_u32()
mips64_pracc_read_u16()
mips64_pracc_read_u8()
mips64_pracc_write_u64()
mips64_pracc_write_u32()
mips64_pracc_write_u16()
mips64_pracc_write_u8()
mips64_pracc_write_regs()
mips64_pracc_read_regs()
mips64_pracc_fastdata_xfer()
dapdirect_jtag_empty_command()
dapdirect_jtag_select()
dapdirect_swd_select()
dapdirect_init()
arc_reg_data_type_add()
arc_reset_caches_states()
arc_reg_add()
arc_get_register()
arc_set_register()
arc_build_reg_cache()
arc_build_bcr_reg_cache()
arc_get_gdb_reg_list()
arc_reg_get_field()
arc_get_register_value()
arc_set_register_value()
arc_configure_dccm()
arc_configure_iccm()
arc_configure()
arc_examine()
arc_exit_debug()
arc_halt()
arc_save_context()
get_current_actionpoint()
arc_examine_debug_reason()
arc_debug_entry()
arc_poll()
arc_assert_reset()
arc_deassert_reset()
arc_arch_state()
arc_restore_context()
arc_enable_interrupts()
arc_resume()
arc_init_target()
arc_deinit_target()
arc_target_create()
arc_write_instruction_u32()
arc_read_instruction_u32()
arc_configure_actionpoint()
arc_set_breakpoint()
arc_unset_breakpoint()
arc_enable_breakpoints()
arc_remove_breakpoint()
arc_set_actionpoints_num()
arc_set_watchpoint()
arc_unset_watchpoint()
arc_enable_watchpoints()
arc_add_watchpoint()
arc_remove_watchpoint()
arc_hit_watchpoint()
arc_config_step()
arc_single_step_core()
arc_step()
arc_icache_invalidate()
arc_dcache_invalidate()
arc_l2cache_invalidate()
arc_cache_invalidate()
arc_dcache_flush()
arc_l2cache_flush()
arc_cache_flush()
arc_handle_add_reg_type_flags()
arc_handle_set_aux_reg()
arc_handle_get_aux_reg()
arc_handle_get_core_reg()
arc_handle_set_core_reg()
arc_handle_add_reg_type_struct()
arc_handle_actionpoints_num()
arc_jtag_status()
arc_jtag_write_registers()
arc_jtag_read_registers()
arc_jtag_write_memory()
arc_jtag_read_memory()
arc_mem_write_block32()
arc_mem_write_block16()
arc_mem_write_block8()
arc_mem_write()
arc_mem_read_block()
arc_mem_read()
esp_semihosting_sys_seek()
esp_semihosting_common()
esp_xtensa_target_deinit()
esp_xtensa_poll()
esp_xtensa_semihosting_setup()
esp_xtensa_semihosting()
esp_xtensa_smp_deassert_reset()
esp_xtensa_smp_soft_reset_halt()
esp_xtensa_smp_poll()
esp_xtensa_smp_update_halt_gdb()
esp_xtensa_smp_resume_cores()
esp_xtensa_smp_resume()
esp32_soc_reset()
esp32s2_deassert_reset()
esp32s2_soft_reset_halt()
esp32s2_stall_set()
esp32s2_soc_reset()
esp32s3_soc_reset()
xtensa_core_reg_set()
xtensa_region_ar_exec()
xtensa_window_state_save()
xtensa_window_state_restore()
xtensa_scratch_regs_fixup()
xtensa_write_dirty_registers()
xtensa_examine()
xtensa_smpbreak_write()
xtensa_smpbreak_set()
xtensa_imprecise_exception_occurred()
xtensa_imprecise_exception_clear()
xtensa_core_status_check()
xtensa_assert_reset()
xtensa_deassert_reset()
xtensa_soft_reset_halt()
xtensa_fetch_all_regs()
xtensa_get_gdb_reg_list()
xtensa_halt()
xtensa_prepare_resume()
xtensa_do_resume()
xtensa_resume()
xtensa_do_step()
xtensa_read_memory()
xtensa_write_memory()
xtensa_poll()
xtensa_update_instruction()
xtensa_breakpoint_add()
xtensa_breakpoint_remove()
xtensa_watchpoint_add()
xtensa_watchpoint_remove()
xtensa_start_algorithm()
xtensa_wait_algorithm()
xtensa_build_reg_cache()
xtensa_gdbqc_parse_exec_tie_ops()
xtensa_gdbqc_qxtreg()
xtensa_gdb_query_custom()
xtensa_target_deinit()
xtensa_cmd_exe_do()
xtensa_cmd_xtreg_do()
xtensa_chip_target_create()
xtensa_dm_examine()
esp_xtensa_apptrace_block_max_size_get()
esp_xtensa_apptrace_data_read()
esp_xtensa_apptrace_buffs_write()
esp32_apptrace_tcp_dest_init()
esp32_apptrace_ready_block_put()
esp32_apptrace_wait_tracing_finished()
esp32_apptrace_safe_halt_targets()
esp32_apptrace_connect_targets()
esp32_apptrace_get_data_info()
esp32_apptrace_process_data()
esp32_apptrace_handle_trace_block()
esp32_apptrace_poll()
esp32_sysview_stop()
esp_sysview_parse_packet()
esp32_sysview_process_packet()
esp32_sysview_process_data()
xtensa_fileio_detect_proc()
xtensa_get_gdb_fileio_info()
xtensa_gdb_fileio_end()
esp_dbgstubs_table_read()
esp_algorithm_run_image()
esp_algorithm_run_debug_stub()
esp_algorithm_load_func_image()
esp_algorithm_load_onboard_func()
esp_xtensa_algo_regs_init_start()
esp_xtensa_algo_init()
transport_register()
handle_transport_init()
handle_xsvf_command()
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