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// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* Copyright (C) 2006 by Magnus Lundin *
* lundin@mlu.mine.nu *
* *
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* *
* Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
* *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "jtag/interface.h"
#include "breakpoints.h"
#include "cortex_m.h"
#include "target_request.h"
#include "target_type.h"
#include "arm_adi_v5.h"
#include "arm_disassembler.h"
#include "register.h"
#include "arm_opcodes.h"
#include "arm_semihosting.h"
#include "smp.h"
#include <helper/nvp.h>
#include <helper/time_support.h>
#include <rtt/rtt.h>
/* NOTE: most of this should work fine for the Cortex-M1 and
* Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
* Some differences: M0/M1 doesn't have FPB remapping or the
* DWT tracing/profiling support. (So the cycle counter will
* not be usable; the other stuff isn't currently used here.)
*
* Although there are some workarounds for errata seen only in r0p0
* silicon, such old parts are hard to find and thus not much tested
* any longer.
*/
/* Timeout for register r/w */
#define DHCSR_S_REGRDY_TIMEOUT (500)
/* Supported Cortex-M Cores */
static const struct cortex_m_part_info cortex_m_parts[] = {
{
.impl_part = CORTEX_M0_PARTNO,
.name = "Cortex-M0",
.arch = ARM_ARCH_V6M,
},
{
.impl_part = CORTEX_M0P_PARTNO,
.name = "Cortex-M0+",
.arch = ARM_ARCH_V6M,
},
{
.impl_part = CORTEX_M1_PARTNO,
.name = "Cortex-M1",
.arch = ARM_ARCH_V6M,
},
{
.impl_part = CORTEX_M3_PARTNO,
.name = "Cortex-M3",
.arch = ARM_ARCH_V7M,
.flags = CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K,
},
{
.impl_part = CORTEX_M4_PARTNO,
.name = "Cortex-M4",
.arch = ARM_ARCH_V7M,
.flags = CORTEX_M_F_HAS_FPV4 | CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K,
},
{
.impl_part = CORTEX_M7_PARTNO,
.name = "Cortex-M7",
.arch = ARM_ARCH_V7M,
.flags = CORTEX_M_F_HAS_FPV5,
},
{
.impl_part = CORTEX_M23_PARTNO,
.name = "Cortex-M23",
.arch = ARM_ARCH_V8M,
},
{
.impl_part = CORTEX_M33_PARTNO,
.name = "Cortex-M33",
.arch = ARM_ARCH_V8M,
.flags = CORTEX_M_F_HAS_FPV5,
},
{
.impl_part = CORTEX_M35P_PARTNO,
.name = "Cortex-M35P",
.arch = ARM_ARCH_V8M,
.flags = CORTEX_M_F_HAS_FPV5,
},
{
.impl_part = CORTEX_M52_PARTNO,
.name = "Cortex-M52",
.arch = ARM_ARCH_V8M,
.flags = CORTEX_M_F_HAS_FPV5,
},
{
.impl_part = CORTEX_M55_PARTNO,
.name = "Cortex-M55",
.arch = ARM_ARCH_V8M,
.flags = CORTEX_M_F_HAS_FPV5,
},
{
.impl_part = CORTEX_M85_PARTNO,
.name = "Cortex-M85",
.arch = ARM_ARCH_V8M,
.flags = CORTEX_M_F_HAS_FPV5,
},
{
.impl_part = STAR_MC1_PARTNO,
.name = "STAR-MC1",
.arch = ARM_ARCH_V8M,
.flags = CORTEX_M_F_HAS_FPV5,
},
{
.impl_part = INFINEON_SLX2_PARTNO,
.name = "Infineon-SLx2",
.arch = ARM_ARCH_V8M,
},
{
.impl_part = REALTEK_M200_PARTNO,
.name = "Real-M200 (KM0)",
.arch = ARM_ARCH_V8M,
},
{
.impl_part = REALTEK_M300_PARTNO,
.name = "Real-M300 (KM4)",
.arch = ARM_ARCH_V8M,
.flags = CORTEX_M_F_HAS_FPV5,
},
};
/* forward declarations */
static int cortex_m_store_core_reg_u32(struct target *target,
uint32_t num, uint32_t value);
static void cortex_m_dwt_free(struct target *target);
/** DCB DHCSR register contains S_RETIRE_ST and S_RESET_ST bits cleared
* on a read. Call this helper function each time DHCSR is read
* to preserve S_RESET_ST state in case of a reset event was detected.
*/
static inline void cortex_m_cumulate_dhcsr_sticky(struct cortex_m_common *cortex_m,
uint32_t dhcsr)
{
cortex_m->dcb_dhcsr_cumulated_sticky |= dhcsr;
}
/** Read DCB DHCSR register to cortex_m->dcb_dhcsr and cumulate
* sticky bits in cortex_m->dcb_dhcsr_cumulated_sticky
*/
static int cortex_m_read_dhcsr_atomic_sticky(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = target_to_armv7m(target);
int retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
&cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
return ERROR_OK;
}
static int cortex_m_load_core_reg_u32(struct target *target,
uint32_t regsel, uint32_t *value)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = target_to_armv7m(target);
int retval;
uint32_t dcrdr, tmp_value;
int64_t then;
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
if (target->dbg_msg_enabled) {
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
if (retval != ERROR_OK)
return retval;
}
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
if (retval != ERROR_OK)
return retval;
/* check if value from register is ready and pre-read it */
then = timeval_ms();
while (1) {
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DHCSR,
&cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR,
&tmp_value);
if (retval != ERROR_OK)
return retval;
cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
if (cortex_m->dcb_dhcsr & S_REGRDY)
break;
cortex_m->slow_register_read = true; /* Polling (still) needed. */
if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
LOG_TARGET_ERROR(target, "Timeout waiting for DCRDR transfer ready");
return ERROR_TIMEOUT_REACHED;
}
keep_alive();
}
*value = tmp_value;
if (target->dbg_msg_enabled) {
/* restore DCB_DCRDR - this needs to be in a separate
* transaction otherwise the emulated DCC channel breaks */
if (retval == ERROR_OK)
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
}
return retval;
}
static int cortex_m_slow_read_all_regs(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = target_to_armv7m(target);
const unsigned int num_regs = armv7m->arm.core_cache->num_regs;
/* Opportunistically restore fast read, it'll revert to slow
* if any register needed polling in cortex_m_load_core_reg_u32(). */
cortex_m->slow_register_read = false;
for (unsigned int reg_id = 0; reg_id < num_regs; reg_id++) {
struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
if (r->exist) {
int retval = armv7m->arm.read_core_reg(target, r, reg_id, ARM_MODE_ANY);
if (retval != ERROR_OK)
return retval;
}
}
if (!cortex_m->slow_register_read)
LOG_TARGET_DEBUG(target, "Switching back to fast register reads");
return ERROR_OK;
}
static int cortex_m_queue_reg_read(struct target *target, uint32_t regsel,
uint32_t *reg_value, uint32_t *dhcsr)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
int retval;
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DHCSR, dhcsr);
if (retval != ERROR_OK)
return retval;
return mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, reg_value);
}
static int cortex_m_fast_read_all_regs(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = target_to_armv7m(target);
int retval;
uint32_t dcrdr;
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
bool dbg_msg_enabled = target->dbg_msg_enabled;
if (dbg_msg_enabled) {
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
if (retval != ERROR_OK)
return retval;
}
const unsigned int num_regs = armv7m->arm.core_cache->num_regs;
const unsigned int n_r32 = ARMV7M_LAST_REG - ARMV7M_CORE_FIRST_REG + 1
+ ARMV7M_FPU_LAST_REG - ARMV7M_FPU_FIRST_REG + 1;
/* we need one 32-bit word for each register except FP D0..D15, which
* need two words */
uint32_t r_vals[n_r32];
uint32_t dhcsr[n_r32];
unsigned int wi = 0; /* write index to r_vals and dhcsr arrays */
unsigned int reg_id; /* register index in the reg_list, ARMV7M_R0... */
for (reg_id = 0; reg_id < num_regs; reg_id++) {
struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
if (!r->exist)
continue; /* skip non existent registers */
if (r->size <= 8) {
/* Any 8-bit or shorter register is unpacked from a 32-bit
* container register. Skip it now. */
continue;
}
uint32_t regsel = armv7m_map_id_to_regsel(reg_id);
retval = cortex_m_queue_reg_read(target, regsel, &r_vals[wi],
&dhcsr[wi]);
if (retval != ERROR_OK)
return retval;
wi++;
assert(r->size == 32 || r->size == 64);
if (r->size == 32)
continue; /* done with 32-bit register */
assert(reg_id >= ARMV7M_FPU_FIRST_REG && reg_id <= ARMV7M_FPU_LAST_REG);
/* the odd part of FP register (S1, S3...) */
retval = cortex_m_queue_reg_read(target, regsel + 1, &r_vals[wi],
&dhcsr[wi]);
if (retval != ERROR_OK)
return retval;
wi++;
}
assert(wi <= n_r32);
retval = dap_run(armv7m->debug_ap->dap);
if (retval != ERROR_OK)
return retval;
if (dbg_msg_enabled) {
/* restore DCB_DCRDR - this needs to be in a separate
* transaction otherwise the emulated DCC channel breaks */
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
if (retval != ERROR_OK)
return retval;
}
bool not_ready = false;
for (unsigned int i = 0; i < wi; i++) {
if ((dhcsr[i] & S_REGRDY) == 0) {
not_ready = true;
LOG_TARGET_DEBUG(target, "Register %u was not ready during fast read", i);
}
cortex_m_cumulate_dhcsr_sticky(cortex_m, dhcsr[i]);
}
if (not_ready) {
/* Any register was not ready,
* fall back to slow read with S_REGRDY polling */
return ERROR_TIMEOUT_REACHED;
}
LOG_TARGET_DEBUG(target, "read %u 32-bit registers", wi);
unsigned int ri = 0; /* read index from r_vals array */
for (reg_id = 0; reg_id < num_regs; reg_id++) {
struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
if (!r->exist)
continue; /* skip non existent registers */
r->dirty = false;
unsigned int reg32_id;
uint32_t offset;
if (armv7m_map_reg_packing(reg_id, ®32_id, &offset)) {
/* Unpack a partial register from 32-bit container register */
struct reg *r32 = &armv7m->arm.core_cache->reg_list[reg32_id];
/* The container register ought to precede all regs unpacked
* from it in the reg_list. So the value should be ready
* to unpack */
assert(r32->valid);
buf_cpy(r32->value + offset, r->value, r->size);
} else {
assert(r->size == 32 || r->size == 64);
buf_set_u32(r->value, 0, 32, r_vals[ri++]);
if (r->size == 64) {
assert(reg_id >= ARMV7M_FPU_FIRST_REG && reg_id <= ARMV7M_FPU_LAST_REG);
/* the odd part of FP register (S1, S3...) */
buf_set_u32(r->value + 4, 0, 32, r_vals[ri++]);
}
}
r->valid = true;
}
assert(ri == wi);
return retval;
}
static int cortex_m_store_core_reg_u32(struct target *target,
uint32_t regsel, uint32_t value)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = target_to_armv7m(target);
int retval;
uint32_t dcrdr;
int64_t then;
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
if (target->dbg_msg_enabled) {
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
if (retval != ERROR_OK)
return retval;
}
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WNR);
if (retval != ERROR_OK)
return retval;
/* check if value is written into register */
then = timeval_ms();
while (1) {
retval = cortex_m_read_dhcsr_atomic_sticky(target);
if (retval != ERROR_OK)
return retval;
if (cortex_m->dcb_dhcsr & S_REGRDY)
break;
if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
LOG_TARGET_ERROR(target, "Timeout waiting for DCRDR transfer ready");
return ERROR_TIMEOUT_REACHED;
}
keep_alive();
}
if (target->dbg_msg_enabled) {
/* restore DCB_DCRDR - this needs to be in a separate
* transaction otherwise the emulated DCC channel breaks */
if (retval == ERROR_OK)
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
}
return retval;
}
static int cortex_m_write_debug_halt_mask(struct target *target,
uint32_t mask_on, uint32_t mask_off)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
/* mask off status bits */
cortex_m->dcb_dhcsr &= ~((0xFFFFul << 16) | mask_off);
/* create new register mask */
cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
}
static int cortex_m_set_maskints(struct target *target, bool mask)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
else
return ERROR_OK;
}
static int cortex_m_set_maskints_for_halt(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
switch (cortex_m->isrmasking_mode) {
case CORTEX_M_ISRMASK_AUTO:
/* interrupts taken at resume, whether for step or run -> no mask */
return cortex_m_set_maskints(target, false);
case CORTEX_M_ISRMASK_OFF:
/* interrupts never masked */
return cortex_m_set_maskints(target, false);
case CORTEX_M_ISRMASK_ON:
/* interrupts always masked */
return cortex_m_set_maskints(target, true);
case CORTEX_M_ISRMASK_STEPONLY:
/* interrupts masked for single step only -> mask now if MASKINTS
* erratum, otherwise only mask before stepping */
return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
}
return ERROR_OK;
}
static int cortex_m_set_maskints_for_run(struct target *target)
{
switch (target_to_cm(target)->isrmasking_mode) {
case CORTEX_M_ISRMASK_AUTO:
/* interrupts taken at resume, whether for step or run -> no mask */
return cortex_m_set_maskints(target, false);
case CORTEX_M_ISRMASK_OFF:
/* interrupts never masked */
return cortex_m_set_maskints(target, false);
case CORTEX_M_ISRMASK_ON:
/* interrupts always masked */
return cortex_m_set_maskints(target, true);
case CORTEX_M_ISRMASK_STEPONLY:
/* interrupts masked for single step only -> no mask */
return cortex_m_set_maskints(target, false);
}
return ERROR_OK;
}
static int cortex_m_set_maskints_for_step(struct target *target)
{
switch (target_to_cm(target)->isrmasking_mode) {
case CORTEX_M_ISRMASK_AUTO:
/* the auto-interrupt should already be done -> mask */
return cortex_m_set_maskints(target, true);
case CORTEX_M_ISRMASK_OFF:
/* interrupts never masked */
return cortex_m_set_maskints(target, false);
case CORTEX_M_ISRMASK_ON:
/* interrupts always masked */
return cortex_m_set_maskints(target, true);
case CORTEX_M_ISRMASK_STEPONLY:
/* interrupts masked for single step only -> mask */
return cortex_m_set_maskints(target, true);
}
return ERROR_OK;
}
static int cortex_m_clear_halt(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
int retval;
/* clear step if any */
cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
/* Read Debug Fault Status Register */
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
/* Clear Debug Fault Status */
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
LOG_TARGET_DEBUG(target, "NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
return ERROR_OK;
}
static int cortex_m_single_step_core(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
int retval;
/* Mask interrupts before clearing halt, if not done already. This avoids
* Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
* HALT can put the core into an unknown state.
*/
if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
retval = cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
if (retval != ERROR_OK)
return retval;
}
retval = cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
if (retval != ERROR_OK)
return retval;
LOG_TARGET_DEBUG(target, "single step");
/* restore dhcsr reg */
cortex_m_clear_halt(target);
return ERROR_OK;
}
static int cortex_m_enable_fpb(struct target *target)
{
int retval = target_write_u32(target, FP_CTRL, 3);
if (retval != ERROR_OK)
return retval;
/* check the fpb is actually enabled */
uint32_t fpctrl;
retval = target_read_u32(target, FP_CTRL, &fpctrl);
if (retval != ERROR_OK)
return retval;
if (fpctrl & 1)
return ERROR_OK;
return ERROR_FAIL;
}
static int cortex_m_endreset_event(struct target *target)
{
int retval;
uint32_t dcb_demcr;
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
/* REVISIT The four debug monitor bits are currently ignored... */
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
if (retval != ERROR_OK)
return retval;
LOG_TARGET_DEBUG(target, "DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
/* this register is used for emulated dcc channel */
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
if (retval != ERROR_OK)
return retval;
retval = cortex_m_read_dhcsr_atomic_sticky(target);
if (retval != ERROR_OK)
return retval;
if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
/* Enable debug requests */
retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
if (retval != ERROR_OK)
return retval;
}
/* Restore proper interrupt masking setting for running CPU. */
cortex_m_set_maskints_for_run(target);
/* Enable features controlled by ITM and DWT blocks, and catch only
* the vectors we were told to pay attention to.
*
* Target firmware is responsible for all fault handling policy
* choices *EXCEPT* explicitly scripted overrides like "vector_catch"
* or manual updates to the NVIC SHCSR and CCR registers.
*/
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
if (retval != ERROR_OK)
return retval;
/* Paranoia: evidently some (early?) chips don't preserve all the
* debug state (including FPB, DWT, etc) across reset...
*/
/* Enable FPB */
retval = cortex_m_enable_fpb(target);
if (retval != ERROR_OK) {
LOG_TARGET_ERROR(target, "Failed to enable the FPB");
return retval;
}
cortex_m->fpb_enabled = true;
/* Restore FPB registers */
for (unsigned int i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
if (retval != ERROR_OK)
return retval;
}
/* Restore DWT registers */
for (unsigned int i = 0; i < cortex_m->dwt_num_comp; i++) {
retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
dwt_list[i].comp);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
dwt_list[i].mask);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
dwt_list[i].function);
if (retval != ERROR_OK)
return retval;
}
retval = dap_run(swjdp);
if (retval != ERROR_OK)
return retval;
register_cache_invalidate(armv7m->arm.core_cache);
/* TODO: invalidate also working areas (needed in the case of detected reset).
* Doing so will require flash drivers to test if working area
* is still valid in all target algo calling loops.
*/
/* make sure we have latest dhcsr flags */
retval = cortex_m_read_dhcsr_atomic_sticky(target);
if (retval != ERROR_OK)
return retval;
return retval;
}
static int cortex_m_examine_debug_reason(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
/* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP)) {
if (cortex_m->nvic_dfsr & DFSR_BKPT) {
target->debug_reason = DBG_REASON_BREAKPOINT;
if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
target->debug_reason = DBG_REASON_WPTANDBKPT;
} else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
target->debug_reason = DBG_REASON_WATCHPOINT;
else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
target->debug_reason = DBG_REASON_BREAKPOINT;
else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
target->debug_reason = DBG_REASON_DBGRQ;
else /* HALTED */
target->debug_reason = DBG_REASON_UNDEFINED;
}
return ERROR_OK;
}
static int cortex_m_examine_exception_reason(struct target *target)
{
uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval;
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
if (retval != ERROR_OK)
return retval;
switch (armv7m->exception_number) {
case 2: /* NMI */
break;
case 3: /* Hard Fault */
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
if (except_sr & 0x40000000) {
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
if (retval != ERROR_OK)
return retval;
}
break;
case 4: /* Memory Management */
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
if (retval != ERROR_OK)
return retval;
break;
case 5: /* Bus Fault */
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
if (retval != ERROR_OK)
return retval;
break;
case 6: /* Usage Fault */
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
break;
case 7: /* Secure Fault */
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
if (retval != ERROR_OK)
return retval;
break;
case 11: /* SVCall */
break;
case 12: /* Debug Monitor */
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
break;
case 14: /* PendSV */
break;
case 15: /* SysTick */
break;
default:
except_sr = 0;
break;
}
retval = dap_run(swjdp);
if (retval == ERROR_OK)
LOG_TARGET_DEBUG(target, "%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
armv7m_exception_string(armv7m->exception_number),
shcsr, except_sr, cfsr, except_ar);
return retval;
}
/* Errata 3092511 workaround
* Cortex-M7 can halt in an incorrect address when breakpoint
* and exception occurs simultaneously */
static int cortex_m_erratum_check_breakpoint(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
struct arm *arm = &armv7m->arm;
uint32_t pc = buf_get_u32(arm->pc->value, 0, 32);
/* To reduce the workaround processing cost we assume FPB is in sync
* with OpenOCD breakpoints. If the target app writes to FPB
* OpenOCD will resume after the break set by app */
struct breakpoint *bkpt = breakpoint_find(target, pc);
if (bkpt) {
LOG_TARGET_DEBUG(target, "Erratum 3092511: breakpoint confirmed");
return ERROR_OK;
}
if (pc >= 0xe0000000u)
/* not executable area, do not read instruction @ pc */
return ERROR_OK;
uint16_t insn;
int retval = target_read_u16(target, pc, &insn);
if (retval != ERROR_OK)
return ERROR_OK; /* do not propagate the error, just avoid workaround */
if ((insn & 0xff00) == (ARMV5_T_BKPT(0) & 0xff00)) {
LOG_TARGET_DEBUG(target, "Erratum 3092511: breakpoint embedded in code confirmed");
return ERROR_OK;
}
LOG_TARGET_DEBUG(target, "Erratum 3092511: breakpoint not found, proceed with resume");
return ERROR_TARGET_HALTED_DO_RESUME;
}
static int cortex_m_debug_entry(struct target *target)
{
uint32_t xpsr;
int retval;
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
struct arm *arm = &armv7m->arm;
struct reg *r;
LOG_TARGET_DEBUG(target, " ");
/* Do this really early to minimize the window where the MASKINTS erratum
* can pile up pending interrupts. */
cortex_m_set_maskints_for_halt(target);
cortex_m_clear_halt(target);
retval = cortex_m_read_dhcsr_atomic_sticky(target);
if (retval != ERROR_OK)
return retval;
retval = armv7m->examine_debug_reason(target);
if (retval != ERROR_OK)
return retval;
/* examine PE security state */
uint32_t dscsr = 0;
if (armv7m->arm.arch == ARM_ARCH_V8M) {
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
if (retval != ERROR_OK)
return retval;
}
/* Load all registers to arm.core_cache */
if (!cortex_m->slow_register_read) {
retval = cortex_m_fast_read_all_regs(target);
if (retval == ERROR_TIMEOUT_REACHED) {
cortex_m->slow_register_read = true;
LOG_TARGET_DEBUG(target, "Switched to slow register read");
}
}
if (cortex_m->slow_register_read)
retval = cortex_m_slow_read_all_regs(target);
if (retval != ERROR_OK)
return retval;
r = arm->cpsr;
xpsr = buf_get_u32(r->value, 0, 32);
/* Are we in an exception handler */
if (xpsr & 0x1FF) {
armv7m->exception_number = (xpsr & 0x1FF);
arm->core_mode = ARM_MODE_HANDLER;
arm->map = armv7m_msp_reg_map;
} else {
unsigned control = buf_get_u32(arm->core_cache
->reg_list[ARMV7M_CONTROL].value, 0, 3);
/* is this thread privileged? */
arm->core_mode = control & 1
? ARM_MODE_USER_THREAD
: ARM_MODE_THREAD;
/* which stack is it using? */
if (control & 2)
arm->map = armv7m_psp_reg_map;
else
arm->map = armv7m_msp_reg_map;
armv7m->exception_number = 0;
}
if (armv7m->exception_number)
cortex_m_examine_exception_reason(target);
bool secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
LOG_TARGET_DEBUG(target, "entered debug state in core mode: %s at PC 0x%" PRIx32
", cpu in %s state, target->state: %s",
arm_mode_name(arm->core_mode),
buf_get_u32(arm->pc->value, 0, 32),
secure_state ? "Secure" : "Non-Secure",
target_state_name(target));
/* Errata 3092511 workaround
* Cortex-M7 can halt in an incorrect address when breakpoint
* and exception occurs simultaneously */
if (cortex_m->incorrect_halt_erratum
&& armv7m->exception_number
&& cortex_m->nvic_dfsr == (DFSR_BKPT | DFSR_HALTED)) {
retval = cortex_m_erratum_check_breakpoint(target);
if (retval != ERROR_OK)
return retval;
}
if (armv7m->post_debug_entry) {
retval = armv7m->post_debug_entry(target);
if (retval != ERROR_OK)
return retval;
}
return ERROR_OK;
}
static int cortex_m_poll_one(struct target *target)
{
int detected_failure = ERROR_OK;
int retval = ERROR_OK;
enum target_state prev_target_state = target->state;
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
/* Read from Debug Halting Control and Status Register */
retval = cortex_m_read_dhcsr_atomic_sticky(target);
if (retval != ERROR_OK) {
target->state = TARGET_UNKNOWN;
return retval;
}
/* Recover from lockup. See ARMv7-M architecture spec,
* section B1.5.15 "Unrecoverable exception cases".
*/
if (cortex_m->dcb_dhcsr & S_LOCKUP) {
LOG_TARGET_ERROR(target, "clearing lockup after double fault")