Outline ![]()
Files ![]()
loading...
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* Copyright (C) 2006 by Magnus Lundin *
* lundin@mlu.mine.nu *
* *
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2007,2008 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2018 by Liviu Ionescu *
* <ilg@livius.net> *
* *
* Copyright (C) 2019 by Tomas Vanek *
* vanekt@fbl.cz *
* *
* ARMv7-M Architecture, Application Level Reference Manual *
* ARM DDI 0405C (September 2008) *
* *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "breakpoints.h"
#include "armv7m.h"
#include "algorithm.h"
#include "register.h"
#include "semihosting_common.h"
#include <helper/log.h>
#include <helper/binarybuffer.h>
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
static const char * const armv7m_exception_strings[] = {
"", "Reset", "NMI", "HardFault",
"MemManage", "BusFault", "UsageFault", "SecureFault",
"RESERVED", "RESERVED", "RESERVED", "SVCall",
"DebugMonitor", "RESERVED", "PendSV", "SysTick"
};
/* PSP is used in some thread modes */
const int armv7m_psp_reg_map[ARMV7M_NUM_CORE_REGS] = {
ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
ARMV7M_XPSR,
};
/* MSP is used in handler and some thread modes */
const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS] = {
ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
ARMV7M_XPSR,
};
/*
* These registers are not memory-mapped. The ARMv7-M profile includes
* memory mapped registers too, such as for the NVIC (interrupt controller)
* and SysTick (timer) modules; those can mostly be treated as peripherals.
*
* The ARMv6-M profile is almost identical in this respect, except that it
* doesn't include basepri or faultmask registers.
*/
static const struct {
unsigned id;
const char *name;
unsigned bits;
enum reg_type type;
const char *group;
const char *feature;
} armv7m_regs[] = {
{ ARMV7M_R0, "r0", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R1, "r1", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R2, "r2", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R3, "r3", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R4, "r4", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R5, "r5", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R6, "r6", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R7, "r7", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R8, "r8", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R9, "r9", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R10, "r10", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R11, "r11", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R12, "r12", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R13, "sp", 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R14, "lr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_PC, "pc", 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_XPSR, "xpsr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_MSP, "msp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
{ ARMV7M_PSP, "psp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
/* A working register for packing/unpacking special regs, hidden from gdb */
{ ARMV7M_PMSK_BPRI_FLTMSK_CTRL, "pmsk_bpri_fltmsk_ctrl", 32, REG_TYPE_INT, NULL, NULL },
/* WARNING: If you use armv7m_write_core_reg() on one of 4 following
* special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
* cache only and are not flushed to CPU HW register.
* To trigger write to CPU HW register, add
* armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
*/
{ ARMV7M_PRIMASK, "primask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
{ ARMV7M_BASEPRI, "basepri", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
{ ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
{ ARMV7M_CONTROL, "control", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
/* ARMv8-M security extension (TrustZone) specific registers */
{ ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
{ ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
{ ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
{ ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
{ ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
{ ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
{ ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
{ ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, "pmsk_bpri_fltmsk_ctrl_s", 32, REG_TYPE_INT, NULL, NULL },
{ ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
{ ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
{ ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
{ ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS, "pmsk_bpri_fltmsk_ctrl_ns", 32, REG_TYPE_INT, NULL, NULL },
{ ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
{ ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
{ ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
{ ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
/* FPU registers */
{ ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D1, "d1", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D2, "d2", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D3, "d3", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D4, "d4", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D5, "d5", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D6, "d6", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D7, "d7", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D8, "d8", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D9, "d9", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D10, "d10", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D11, "d11", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D12, "d12", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D13, "d13", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D14, "d14", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D15, "d15", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_FPSCR, "fpscr", 32, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp" },
};
#define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
/**
* Restores target context using the cache of core registers set up
* by armv7m_build_reg_cache(), calling optional core-specific hooks.
*/
int armv7m_restore_context(struct target *target)
{
int i;
struct armv7m_common *armv7m = target_to_armv7m(target);
struct reg_cache *cache = armv7m->arm.core_cache;
LOG_DEBUG(" ");
if (armv7m->pre_restore_context)
armv7m->pre_restore_context(target);
/* The descending order of register writes is crucial for correct
* packing of ARMV7M_PMSK_BPRI_FLTMSK_CTRL!
* See also comments in the register table above */
for (i = cache->num_regs - 1; i >= 0; i--) {
struct reg *r = &cache->reg_list[i];
if (r->exist && r->dirty) {
int retval = armv7m->arm.write_core_reg(target, r, i, ARM_MODE_ANY, r->value);
if (retval != ERROR_OK)
return retval;
}
}
return ERROR_OK;
}
/* Core state functions */
/**
* Maps ISR number (from xPSR) to name.
* Note that while names and meanings for the first sixteen are standardized
* (with zero not a true exception), external interrupts are only numbered.
* They are assigned by vendors, which generally assign different numbers to
* peripherals (such as UART0 or a USB peripheral controller).
*/
const char *armv7m_exception_string(int number)
{
static char enamebuf[32];
if ((number < 0) | (number > 511))
return "Invalid exception";
if (number < 16)
return armv7m_exception_strings[number];
sprintf(enamebuf, "External Interrupt(%i)", number - 16);
return enamebuf;
}
static int armv7m_get_core_reg(struct reg *reg)
{
int retval;
struct arm_reg *armv7m_reg = reg->arch_info;
struct target *target = armv7m_reg->target;
struct arm *arm = target_to_arm(target);
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
retval = arm->read_core_reg(target, reg, reg->number, arm->core_mode);
return retval;
}
static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
{
struct arm_reg *armv7m_reg = reg->arch_info;
struct target *target = armv7m_reg->target;
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
buf_cpy(buf, reg->value, reg->size);
reg->dirty = true;
reg->valid = true;
return ERROR_OK;
}
uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
{
switch (arm_reg_id) {
case ARMV7M_R0 ... ARMV7M_R14:
case ARMV7M_PC:
case ARMV7M_XPSR:
case ARMV7M_MSP:
case ARMV7M_PSP:
/* NOTE: we "know" here that the register identifiers
* match the Cortex-M DCRSR.REGSEL selectors values
* for R0..R14, PC, xPSR, MSP, and PSP.
*/
return arm_reg_id;
case ARMV7M_PMSK_BPRI_FLTMSK_CTRL:
return ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL;
case ARMV8M_MSP_NS...ARMV8M_PSPLIM_NS:
return arm_reg_id - ARMV8M_MSP_NS + ARMV8M_REGSEL_MSP_NS;
case ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S:
return ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S;
case ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS:
return ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS;
case ARMV7M_FPSCR:
return ARMV7M_REGSEL_FPSCR;
case ARMV7M_D0 ... ARMV7M_D15:
return ARMV7M_REGSEL_S0 + 2 * (arm_reg_id - ARMV7M_D0);
default:
LOG_ERROR("Bad register ID %u", arm_reg_id);
return arm_reg_id;
}
}
bool armv7m_map_reg_packing(unsigned int arm_reg_id,
unsigned int *reg32_id, uint32_t *offset)
{
switch (arm_reg_id) {
case ARMV7M_PRIMASK...ARMV7M_CONTROL:
*reg32_id = ARMV7M_PMSK_BPRI_FLTMSK_CTRL;
*offset = arm_reg_id - ARMV7M_PRIMASK;
return true;
case ARMV8M_PRIMASK_S...ARMV8M_CONTROL_S:
*reg32_id = ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S;
*offset = arm_reg_id - ARMV8M_PRIMASK_S;
return true;
case ARMV8M_PRIMASK_NS...ARMV8M_CONTROL_NS:
*reg32_id = ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS;
*offset = arm_reg_id - ARMV8M_PRIMASK_NS;
return true;
default:
return false;
}
}
static int armv7m_read_core_reg(struct target *target, struct reg *r,
int num, enum arm_mode mode)
{
uint32_t reg_value;
int retval;
struct armv7m_common *armv7m = target_to_armv7m(target);
assert(num < (int)armv7m->arm.core_cache->num_regs);
assert(num == (int)r->number);
/* If a code calls read_reg, it expects the cache is no more dirty.
* Clear the dirty flag regardless of the later read succeeds or not
* to prevent unwanted cache flush after a read error */
r->dirty = false;
if (r->size <= 8) {
/* any 8-bit or shorter register is packed */
uint32_t offset;
unsigned int reg32_id;
bool is_packed = armv7m_map_reg_packing(num, ®32_id, &offset);
if (!is_packed) {
/* We should not get here as all 8-bit or shorter registers
* are packed */
assert(false);
/* assert() does nothing if NDEBUG is defined */
return ERROR_FAIL;
}
struct reg *r32 = &armv7m->arm.core_cache->reg_list[reg32_id];
/* Read 32-bit container register if not cached */
if (!r32->valid) {
retval = armv7m_read_core_reg(target, r32, reg32_id, mode);
if (retval != ERROR_OK)
return retval;
}
/* Copy required bits of 32-bit container register */
buf_cpy(r32->value + offset, r->value, r->size);
} else {
assert(r->size == 32 || r->size == 64);
struct arm_reg *armv7m_core_reg = r->arch_info;
uint32_t regsel = armv7m_map_id_to_regsel(armv7m_core_reg->num);
retval = armv7m->load_core_reg_u32(target, regsel, ®_value);
if (retval != ERROR_OK)
return retval;
buf_set_u32(r->value, 0, 32, reg_value);
if (r->size == 64) {
retval = armv7m->load_core_reg_u32(target, regsel + 1, ®_value);
if (retval != ERROR_OK) {
r->valid = false;
return retval;
}
buf_set_u32(r->value + 4, 0, 32, reg_value);
uint64_t q = buf_get_u64(r->value, 0, 64);
LOG_DEBUG("read %s value 0x%016" PRIx64, r->name, q);
} else {
LOG_DEBUG("read %s value 0x%08" PRIx32, r->name, reg_value);
}
}
r->valid = true;
return ERROR_OK;
}
static int armv7m_write_core_reg(struct target *target, struct reg *r,
int num, enum arm_mode mode, uint8_t *value)
{
int retval;
uint32_t t;
struct armv7m_common *armv7m = target_to_armv7m(target);
assert(num < (int)armv7m->arm.core_cache->num_regs);
assert(num == (int)r->number);
if (value != r->value) {
/* If we are not flushing the cache, store the new value to the cache */
buf_cpy(value, r->value, r->size);
}
if (r->size <= 8) {
/* any 8-bit or shorter register is packed */
uint32_t offset;
unsigned int reg32_id;
bool is_packed = armv7m_map_reg_packing(num, ®32_id, &offset);
if (!is_packed) {
/* We should not get here as all 8-bit or shorter registers
* are packed */
assert(false);
/* assert() does nothing if NDEBUG is defined */
return ERROR_FAIL;
}
struct reg *r32 = &armv7m->arm.core_cache->reg_list[reg32_id];
if (!r32->valid) {
/* Before merging with other parts ensure the 32-bit register is valid */
retval = armv7m_read_core_reg(target, r32, reg32_id, mode);
if (retval != ERROR_OK)
return retval;
}
/* Write a part to the 32-bit container register */
buf_cpy(value, r32->value + offset, r->size);
r32->dirty = true;
} else {
assert(r->size == 32 || r->size == 64);
struct arm_reg *armv7m_core_reg = r->arch_info;
uint32_t regsel = armv7m_map_id_to_regsel(armv7m_core_reg->num);
t = buf_get_u32(value, 0, 32);
retval = armv7m->store_core_reg_u32(target, regsel, t);
if (retval != ERROR_OK)
goto out_error;
if (r->size == 64) {
t = buf_get_u32(value + 4, 0, 32);
retval = armv7m->store_core_reg_u32(target, regsel + 1, t);
if (retval != ERROR_OK)
goto out_error;
uint64_t q = buf_get_u64(value, 0, 64);
LOG_DEBUG("write %s value 0x%016" PRIx64, r->name, q);
} else {
LOG_DEBUG("write %s value 0x%08" PRIx32, r->name, t);
}
}
r->valid = true;
r->dirty = false;
return ERROR_OK;
out_error:
r->dirty = true;
LOG_ERROR("Error setting register %s", r->name);
return retval;
}
/**
* Returns generic ARM userspace registers to GDB.
*/
int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
int *reg_list_size, enum target_register_class reg_class)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
int i, size;
if (reg_class == REG_CLASS_ALL)
size = armv7m->arm.core_cache->num_regs;
else
size = ARMV7M_NUM_CORE_REGS;
*reg_list = malloc(sizeof(struct reg *) * size);
if (!*reg_list)
return ERROR_FAIL;
for (i = 0; i < size; i++)
(*reg_list)[i] = &armv7m->arm.core_cache->reg_list[i];
*reg_list_size = size;
return ERROR_OK;
}
/** Runs a Thumb algorithm in the target. */
int armv7m_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
target_addr_t entry_point, target_addr_t exit_point,
unsigned int timeout_ms, void *arch_info)
{
int retval;
retval = armv7m_start_algorithm(target,
num_mem_params, mem_params,
num_reg_params, reg_params,
entry_point, exit_point,
arch_info);
if (retval == ERROR_OK)
retval = armv7m_wait_algorithm(target,
num_mem_params, mem_params,
num_reg_params, reg_params,
exit_point, timeout_ms,
arch_info);
return retval;
}
/** Starts a Thumb algorithm in the target. */
int armv7m_start_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
target_addr_t entry_point, target_addr_t exit_point,
void *arch_info)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
enum arm_mode core_mode = armv7m->arm.core_mode;
int retval = ERROR_OK;
/* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
* at the exit point */
if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
LOG_ERROR("current target isn't an ARMV7M target");
return ERROR_TARGET_INVALID;
}
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted (start target algo)");
return ERROR_TARGET_NOT_HALTED;
}
/* Store all non-debug execution registers to armv7m_algorithm_info context */
for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
if (!reg->exist)
continue;
if (!reg->valid)
armv7m_get_core_reg(reg);
if (!reg->valid)
LOG_TARGET_WARNING(target, "Storing invalid register %s", reg->name);
armv7m_algorithm_info->context[i] = buf_get_u32(reg->value, 0, 32);
}
for (int i = 0; i < num_mem_params; i++) {
if (mem_params[i].direction == PARAM_IN)
continue;
retval = target_write_buffer(target, mem_params[i].address,
mem_params[i].size,
mem_params[i].value);
if (retval != ERROR_OK)
return retval;
}
for (int i = 0; i < num_reg_params; i++) {
if (reg_params[i].direction == PARAM_IN)
continue;
struct reg *reg =
register_get_by_name(armv7m->arm.core_cache, reg_params[i].reg_name, false);
/* uint32_t regvalue; */
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
return ERROR_COMMAND_SYNTAX_ERROR;
}
if (reg->size != reg_params[i].size) {
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
reg_params[i].reg_name);
return ERROR_COMMAND_SYNTAX_ERROR;
}
/* regvalue = buf_get_u32(reg_params[i].value, 0, 32); */
armv7m_set_core_reg(reg, reg_params[i].value);
}
{
/*
* Ensure xPSR.T is set to avoid trying to run things in arm
* (non-thumb) mode, which armv7m does not support.
*
* We do this by setting the entirety of xPSR, which should
* remove all the unknowns about xPSR state.
*
* Because xPSR.T is populated on reset from the vector table,
* it might be 0 if the vector table has "bad" data in it.
*/
struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_XPSR];
buf_set_u32(reg->value, 0, 32, 0x01000000);
reg->valid = true;
reg->dirty = true;
}
if (armv7m_algorithm_info->core_mode != ARM_MODE_ANY &&
armv7m_algorithm_info->core_mode != core_mode) {
/* we cannot set ARM_MODE_HANDLER, so use ARM_MODE_THREAD instead */
if (armv7m_algorithm_info->core_mode == ARM_MODE_HANDLER) {
armv7m_algorithm_info->core_mode = ARM_MODE_THREAD;
LOG_INFO("ARM_MODE_HANDLER not currently supported, using ARM_MODE_THREAD instead");
}
LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
0, 1, armv7m_algorithm_info->core_mode);
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
}
/* save previous core mode */
armv7m_algorithm_info->core_mode = core_mode;
retval = target_resume(target, 0, entry_point, 1, 1);
return retval;
}
/** Waits for an algorithm in the target. */
int armv7m_wait_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
target_addr_t exit_point, unsigned int timeout_ms,
void *arch_info)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
int retval = ERROR_OK;
/* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
* at the exit point */
if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
LOG_ERROR("current target isn't an ARMV7M target");
return ERROR_TARGET_INVALID;
}
retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
/* If the target fails to halt due to the breakpoint, force a halt */
if (retval != ERROR_OK || target->state != TARGET_HALTED) {
retval = target_halt(target);
if (retval != ERROR_OK)
return retval;
retval = target_wait_state(target, TARGET_HALTED, 500);
if (retval != ERROR_OK)
return retval;
return ERROR_TARGET_TIMEOUT;
}
if (exit_point) {
/* PC value has been cached in cortex_m_debug_entry() */
uint32_t pc = buf_get_u32(armv7m->arm.pc->value, 0, 32);
if (pc != exit_point) {
LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
pc, exit_point);
return ERROR_TARGET_ALGO_EXIT;
}
}
/* Read memory values to mem_params[] */
for (int i = 0; i < num_mem_params; i++) {
if (mem_params[i].direction != PARAM_OUT) {
retval = target_read_buffer(target, mem_params[i].address,
mem_params[i].size,
mem_params[i].value);
if (retval != ERROR_OK)
return retval;
}
}
/* Copy core register values to reg_params[] */
for (int i = 0; i < num_reg_params; i++) {
if (reg_params[i].direction != PARAM_OUT) {
struct reg *reg = register_get_by_name(armv7m->arm.core_cache,
reg_params[i].reg_name,
false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
return ERROR_COMMAND_SYNTAX_ERROR;
}
if (reg->size != reg_params[i].size) {
LOG_ERROR(
"BUG: register '%s' size doesn't match reg_params[i].size",
reg_params[i].reg_name);
return ERROR_COMMAND_SYNTAX_ERROR;
}
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
}
}
for (int i = armv7m->arm.core_cache->num_regs - 1; i >= 0; i--) {
struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
if (!reg->exist)
continue;
uint32_t regvalue;
regvalue = buf_get_u32(reg->value, 0, 32);
if (regvalue != armv7m_algorithm_info->context[i]) {
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
reg->name, armv7m_algorithm_info->context[i]);
buf_set_u32(reg->value,
0, 32, armv7m_algorithm_info->context[i]);
reg->valid = true;
reg->dirty = true;
}
}
/* restore previous core mode */
if (armv7m_algorithm_info->core_mode != armv7m->arm.core_mode) {
LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
0, 1, armv7m_algorithm_info->core_mode);
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
}
armv7m->arm.core_mode = armv7m_algorithm_info->core_mode;
return retval;
}
/** Logs summary of ARMv7-M state for a halted target. */
int armv7m_arch_state(struct target *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct arm *arm = &armv7m->arm;
uint32_t ctrl, sp;
/* avoid filling log waiting for fileio reply */
if (target->semihosting && target->semihosting->hit_fileio)
return ERROR_OK;
ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
LOG_USER("[%s] halted due to %s, current mode: %s %s\n"
"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s%s",
target_name(target),
debug_reason_name(target),
arm_mode_name(arm->core_mode),
armv7m_exception_string(armv7m->exception_number),
buf_get_u32(arm->cpsr->value, 0, 32),
buf_get_u32(arm->pc->value, 0, 32),
(ctrl & 0x02) ? 'p' : 'm',
sp,
(target->semihosting && target->semihosting->is_active) ? ", semihosting" : "",
(target->semihosting && target->semihosting->is_fileio) ? " fileio" : "");
return ERROR_OK;
}
static const struct reg_arch_type armv7m_reg_type = {
.get = armv7m_get_core_reg,
.set = armv7m_set_core_reg,
};
/** Builds cache of architecturally defined registers. */
struct reg_cache *armv7m_build_reg_cache(struct target *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct arm *arm = &armv7m->arm;
int num_regs = ARMV7M_NUM_REGS;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
struct reg_feature *feature;
int i;
/* Build the process context cache */
cache->name = "arm v7m registers";
cache->next = NULL;
cache->reg_list = reg_list;
cache->num_regs = num_regs;
(*cache_p) = cache;
for (i = 0; i < num_regs; i++) {
arch_info[i].num = armv7m_regs[i].id;
arch_info[i].target = target;
arch_info[i].arm = arm;
reg_list[i].name = armv7m_regs[i].name;
reg_list[i].size = armv7m_regs[i].bits;
reg_list[i].value = arch_info[i].value;
reg_list[i].dirty = false;
reg_list[i].valid = false;
reg_list[i].hidden = (i == ARMV7M_PMSK_BPRI_FLTMSK_CTRL ||
i == ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS || i == ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S);
reg_list[i].type = &armv7m_reg_type;
reg_list[i].arch_info = &arch_info[i];
reg_list[i].group = armv7m_regs[i].group;
reg_list[i].number = i;
reg_list[i].exist = true;
reg_list[i].caller_save = true; /* gdb defaults to true */
if (reg_list[i].hidden)
continue;
feature = calloc(1, sizeof(struct reg_feature));
if (feature) {
feature->name = armv7m_regs[i].feature;
reg_list[i].feature = feature;
} else
LOG_ERROR("unable to allocate feature list");
reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
if (reg_list[i].reg_data_type)
reg_list[i].reg_data_type->type = armv7m_regs[i].type;
else
LOG_ERROR("unable to allocate reg type list");
}
arm->cpsr = reg_list + ARMV7M_XPSR;
arm->pc = reg_list + ARMV7M_PC;
arm->core_cache = cache;
return cache;
}
void armv7m_free_reg_cache(struct target *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct arm *arm = &armv7m->arm;
struct reg_cache *cache;
struct reg *reg;
unsigned int i;
cache = arm->core_cache;
if (!cache)
return;
for (i = 0; i < cache->num_regs; i++) {
reg = &cache->reg_list[i];
free(reg->feature);
free(reg->reg_data_type);
}
free(cache->reg_list[0].arch_info);
free(cache->reg_list);
free(cache);
arm->core_cache = NULL;
}
static int armv7m_setup_semihosting(struct target *target, int enable)
{
/* nothing todo for armv7m */
return ERROR_OK;
}
/** Sets up target as a generic ARMv7-M core */
int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
{
struct arm *arm = &armv7m->arm;
armv7m->common_magic = ARMV7M_COMMON_MAGIC;
armv7m->fp_feature = FP_NONE;
armv7m->trace_config.trace_bus_id = 1;
/* Enable stimulus port #0 by default */
armv7m->trace_config.itm_ter[0] = 1;
arm->core_state = ARM_STATE_THUMB;
arm->core_type = ARM_CORE_TYPE_M_PROFILE;
arm->arch_info = armv7m;
arm->setup_semihosting = armv7m_setup_semihosting;
arm->read_core_reg = armv7m_read_core_reg;
arm->write_core_reg = armv7m_write_core_reg;
return arm_init_arch_info(target, arm);
}
/** Generates a CRC32 checksum of a memory region. */
int armv7m_checksum_memory(struct target *target,
target_addr_t address, uint32_t count, uint32_t *checksum)
{
struct working_area *crc_algorithm;
struct armv7m_algorithm armv7m_info;
struct reg_param reg_params[2];
int retval;
static const uint8_t cortex_m_crc_code[] = {
#include "../../contrib/loaders/checksum/armv7m_crc.inc"
};
retval = target_alloc_working_area(target, sizeof(cortex_m_crc_code), &crc_algorithm);
if (retval != ERROR_OK)
return retval;
retval = target_write_buffer(target, crc_algorithm->address,
sizeof(cortex_m_crc_code), (uint8_t *)cortex_m_crc_code);
if (retval != ERROR_OK)
goto cleanup;
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARM_MODE_THREAD;
init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
buf_set_u32(reg_params[0].value, 0, 32, address);
buf_set_u32(reg_params[1].value, 0, 32, count);
unsigned int timeout = 20000 * (1 + (count / (1024 * 1024)));
retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address,
crc_algorithm->address + (sizeof(cortex_m_crc_code) - 6),
timeout, &armv7m_info);
if (retval == ERROR_OK)
*checksum = buf_get_u32(reg_params[0].value, 0, 32);
else
LOG_ERROR("error executing cortex_m crc algorithm");
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
cleanup:
target_free_working_area(target, crc_algorithm);
return retval;
}
/** Checks an array of memory regions whether they are erased. */
int armv7m_blank_check_memory(struct target *target,
struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
{
struct working_area *erase_check_algorithm;
struct working_area *erase_check_params;
struct reg_param reg_params[2];
struct armv7m_algorithm armv7m_info;
int retval;
static bool timed_out;
static const uint8_t erase_check_code[] = {
#include "../../contrib/loaders/erase_check/armv7m_erase_check.inc"
};
const uint32_t code_size = sizeof(erase_check_code);
/* make sure we have a working area */
if (target_alloc_working_area(target, code_size,
&erase_check_algorithm) != ERROR_OK)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
retval = target_write_buffer(target, erase_check_algorithm->address,
code_size, erase_check_code);
if (retval != ERROR_OK)
goto cleanup1;
/* prepare blocks array for algo */
struct algo_block {
union {
uint32_t size;
uint32_t result;
};
uint32_t address;
};
uint32_t avail = target_get_working_area_avail(target);
int blocks_to_check = avail / sizeof(struct algo_block) - 1;
if (num_blocks < blocks_to_check)
blocks_to_check = num_blocks;
struct algo_block *params = malloc((blocks_to_check+1)*sizeof(struct algo_block));
if (!params) {
retval = ERROR_FAIL;
goto cleanup1;
}
int i;
uint32_t total_size = 0;
for (i = 0; i < blocks_to_check; i++) {
total_size += blocks[i].size;
target_buffer_set_u32(target, (uint8_t *)&(params[i].size),
blocks[i].size / sizeof(uint32_t));
target_buffer_set_u32(target, (uint8_t *)&(params[i].address),
blocks[i].address);
}
target_buffer_set_u32(target, (uint8_t *)&(params[blocks_to_check].size), 0);
uint32_t param_size = (blocks_to_check + 1) * sizeof(struct algo_block);
if (target_alloc_working_area(target, param_size,
&erase_check_params) != ERROR_OK) {
retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
goto cleanup2;
}
retval = target_write_buffer(target, erase_check_params->address,
param_size, (uint8_t *)params);
if (retval != ERROR_OK)
goto cleanup3;
uint32_t erased_word = erased_value | (erased_value << 8)
| (erased_value << 16) | (erased_value << 24);
LOG_DEBUG("Starting erase check of %d blocks, parameters@"
TARGET_ADDR_FMT, blocks_to_check, erase_check_params->address);
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARM_MODE_THREAD;
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
buf_set_u32(reg_params[0].value, 0, 32, erase_check_params->address);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
buf_set_u32(reg_params[1].value, 0, 32, erased_word);
/* assume CPU clk at least 1 MHz */
unsigned int timeout = (timed_out ? 30000 : 2000) + total_size * 3 / 1000;
retval = target_run_algorithm(target,
0, NULL,
ARRAY_SIZE(reg_params), reg_params,
erase_check_algorithm->address,
erase_check_algorithm->address + (code_size - 2),
timeout,
&armv7m_info);
timed_out = retval == ERROR_TARGET_TIMEOUT;
if (retval != ERROR_OK && !timed_out)
goto cleanup4;
retval = target_read_buffer(target, erase_check_params->address,
param_size, (uint8_t *)params);
if (retval != ERROR_OK)
goto cleanup4;
for (i = 0; i < blocks_to_check; i++) {
uint32_t result = target_buffer_get_u32(target,
(uint8_t *)&(params[i].result));
if (result != 0 && result != 1)
break;
blocks[i].result = result;
}
if (i && timed_out)
LOG_INFO("Slow CPU clock: %d blocks checked, %d remain. Continuing...", i, num_blocks-i);
retval = i; /* return number of blocks really checked */
cleanup4:
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
cleanup3:
target_free_working_area(target, erase_check_params);
cleanup2:
free(params);
cleanup1:
target_free_working_area(target, erase_check_algorithm);
return retval;
}
int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct reg *r = armv7m->arm.pc;
bool result = false;
/* if we halted last time due to a bkpt instruction
* then we have to manually step over it, otherwise
* the core will break again */
if (target->debug_reason == DBG_REASON_BREAKPOINT) {
uint16_t op;
uint32_t pc = buf_get_u32(r->value, 0, 32);
pc &= ~1;
if (target_read_u16(target, pc, &op) == ERROR_OK) {
if ((op & 0xFF00) == 0xBE00) {
pc = buf_get_u32(r->value, 0, 32) + 2;
buf_set_u32(r->value, 0, 32, pc);
r->dirty = true;
r->valid = true;
result = true;
LOG_DEBUG("Skipping over BKPT instruction");
}
}
}
if (inst_found)
*inst_found = result;
return ERROR_OK;
}
const struct command_registration armv7m_command_handlers[] = {
{
.name = "arm",
.mode = COMMAND_ANY,
.help = "ARM command group",
.usage = "",
.chain = arm_all_profiles_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
Details ![]()
Show: from Types: Columns: ![]( "Show Project Names")
![]( "Show Locations")
![]( "Show Referring Symbols")
![]( "Show Scope")
Click anywhere in the source to view detailed information here...