mips32_cpu_probe() function

The target CPU to probe.

Register one or more commands, as register_commands(), plus specify that command should override the current target

Returns a description of the endianness for the specified target.

Returns the instance-specific name of the specified target.

Sets the @c examined flag for the given target. Use in target->type->examine() after one-time setup is done.

Convert target handle to generic ARM target state handle.

Returns true only if the target has a handler for the specified event.

Make the target (re)start executing using its saved execution context (possibly with some modifications). @todo Resolve the ambiguity about what the "debug_execution" flag signifies. For example, Target implementations don't agree on how it relates to invalidation of the register cache, or to whether breakpoints and watchpoints should be enabled. (It would seem wrong to enable breakpoints when running downloaded "helper" algorithms (debug_execution true), since the breakpoints would be set to match target firmware being debugged, not the helper algorithm.... and enabling them could cause such helpers to malfunction (for example, by overwriting data with a breakpoint instruction. On the other hand the infrastructure for running such helpers might use this procedure but rely on hardware breakpoint to detect termination.)

Get the target type name. This routine is a wrapper for the target->type->name field. Note that this is not an instance-specific name for his target.

Examine the specified @a target, letting it perform any Initialisation that requires JTAG access. This routine is a wrapper for target->type->examine.

Add the @a breakpoint for @a target. This routine is a wrapper for target->type->add_breakpoint.

Add the @a ContextID breakpoint for @a target. This routine is a wrapper for target->type->add_context_breakpoint.

Add the @a ContextID & IVA breakpoint for @a target. This routine is a wrapper for target->type->add_hybrid_breakpoint.

Remove the @a breakpoint for @a target. This routine is a wrapper for target->type->remove_breakpoint.

Add the @a watchpoint for @a target. This routine is a wrapper for target->type->add_watchpoint.

Remove the @a watchpoint for @a target. This routine is a wrapper for target->type->remove_watchpoint.

Find out the just hit @a watchpoint for @a target. This routine is a wrapper for target->type->hit_watchpoint.

Obtain the architecture for GDB. This routine is a wrapper for target->type->get_gdb_arch.

Obtain the registers for GDB. This routine is a wrapper for target->type->get_gdb_reg_list.

Obtain the registers for GDB, but don't read register values from the target. This routine is a wrapper for target->type->get_gdb_reg_list_noread.

Check if @a target allows GDB connections. Some target do not implement the necessary code required by GDB.

Step the target. This routine is a wrapper for target->type->step.

Downloads a target-specific native code algorithm to the target, and executes it. * Note that some targets may need to set up, enable, and tear down a breakpoint (hard or * soft) to detect algorithm termination, while others may support lower overhead schemes where soft breakpoints embedded in the algorithm automatically terminate the algorithm.

Executes a target-specific native code algorithm and leaves it running.

Waits for an algorithm started with target_start_algorithm() to complete.

Streams data to a circular buffer on target intended for consumption by code running asynchronously on target. This is intended for applications where target-specific native code runs on the target, receives data from the circular buffer, does something with it (most likely writing it to a flash memory), and advances the circular buffer pointer. This assumes that the helper algorithm has already been loaded to the target, but has not been started yet. Given memory and register parameters are passed to the algorithm. The buffer is defined by (buffer_start, buffer_size) arguments and has the following format: [buffer_start + 0, buffer_start + 4): Write Pointer address (aka head). Written and updated by this routine when new data is written to the circular buffer. [buffer_start + 4, buffer_start + 8): Read Pointer address (aka tail). Updated by code running on the target after it consumes data. [buffer_start + 8, buffer_start + buffer_size): Circular buffer contents. See contrib/loaders/flash/stm32f1x.S for an example.

This routine is a wrapper for asynchronous algorithms.

Read @a count items of @a size bytes from the memory of @a target at the @a address given. This routine is a wrapper for target->type->read_memory.

Write @a count items of @a size bytes to the memory of @a target at the @a address given. @a address must be aligned to @a size in target memory. The endianness is the same in the host and target memory for this function. \todo TODO: Really @a buffer should have been defined as "const void *" and @a buffer should have been aligned to @a size in the host memory. This is not enforced via e.g. assert's today and e.g. the target_write_buffer fn breaks this assumption. This routine is wrapper for target->type->write_memory.

Obtain file-I/O information from target for GDB to do syscall. This routine is a wrapper for target->type->get_gdb_fileio_info.

Pass GDB file-I/O response to target after finishing host syscall. This routine is a wrapper for target->type->gdb_fileio_end.

Return the highest accessible address for this target.

Return the number of address bits this target supports. This routine is a wrapper for target->type->address_bits.

Return the number of data bits this target supports. This routine is a wrapper for target->type->data_bits.

Return the *name* of this targets current state

Free a working area. Restore target data if area backup is configured.

Builds cache of architecturally defined registers.

Runs ARM code in the target to calculate a CRC32 checksum.

Runs ARM code in the target to check whether a memory block holds all ones. NOR flash which has been erased, and thus may be written, holds all ones.

Configure hardware accordingly to the current ITM target settings

Builds cache of architecturally defined registers.

Logs summary of ARMv7-M state for a halted target.

Returns generic ARM userspace registers to GDB.

Sets up target as a generic ARMv7-M core

Runs a Thumb algorithm in the target.

Starts a Thumb algorithm in the target.

Waits for an algorithm in the target.

Restores target context using the cache of core registers set up by armv7m_build_reg_cache(), calling optional core-specific hooks.

Generates a CRC32 checksum of a memory region.

Checks an array of memory regions whether they are erased.

Erases @a length bytes in the @a target flash, starting at @a addr. The range @a addr to @a addr + @a length - 1 must be strictly sector aligned, unless @a pad is true. Setting @a pad true extends the range, at beginning and/or end, if needed for sector alignment.

Writes @a image into the @a target flash. The @a written parameter will contain the

Returns the flash bank located at a specified address.

Copies code to a working area. This will allocate room for the code plus the additional amount requested if the working area pointer is null.

Checks if the target is halted and prints an error message if it isn't.

Initialize the ECC controller on the AT91SAM9.

Read flash status from bootloader.

Modifies the user row register to the given value.

Erases a flash-row at the given address.

Returns the bitmask of reserved bits in register.

Modify the contents of the User Row in Flash. The User Row itself has a size of one page and contains a combination of "fuses" and calibration data. Bits which have a value of zero in the mask will not be changed. Up to now devices only use the first 64 bits.

Checks whether a memory region is erased.

Polls an ARM7/9 target for its current status. If DBGACK is set, the target is manipulated to the right halted state based on its current state. This is what happens: State Action TARGET_RUNNING | TARGET_RESET Enters debug mode. If TARGET_RESET, pc may be checked TARGET_UNKNOWN Warning is logged TARGET_DEBUG_RUNNING Enters debug mode TARGET_HALTED Nothing If the target does not end up in the halted state, a warning is produced. If DBGACK is cleared, then the target is expected to either be running or running in debug.

Get some data from the ARM7/9 target.

Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock while the core is held in reset (SRST). It isn't possible to program the halt condition once reset is asserted, hence a hook that allows the target to set up its reset-halt condition is setup prior to asserting reset.

Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST and the target is being reset into a halt, a warning will be triggered because it is not possible to reset into a halted mode in this case. The target is halted using the target's functions.

Issue a software reset and halt to an ARM7/9 target. The target is halted and then there is a wait until the processor shows the halt. This wait can timeout and results in an error being returned. The software reset involves clearing the halt, updating the debug control register, changing to ARM mode, reset of the program counter, and reset of all of the registers.

Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ line or by programming a watchpoint to trigger on any address. It is considered a bug to call this function while the target is in the TARGET_RESET state.

Add a breakpoint to an ARM7/9 target. This makes sure that there are no dangling breakpoints and that the desired breakpoint can be added.

Removes a breakpoint from an ARM7/9 target. This will make sure there are no dangling breakpoints and updates available watchpoints if it is a hardware breakpoint.

Add a watchpoint to an ARM7/9 target. If there are no watchpoint units available, an error response is returned.

Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and the used watchpoint unit will be reopened.

Restarts the target by sending a RESTART instruction and moving the JTAG state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be asserted by the processor.

Perform per-target setup that requires JTAG access.

Writes to flash memory. Does not check if flash is erased, it's up to the user to erase the flash before running this function. The flashing algorithm runs from RAM, reading from a register to which this function writes to. The algorithm is open loop, there is no control to verify that the FM read the register before writing the next data. A closed loop approach was much slower, and the current implementation does not fail, and if it did the crc check would detect it, allowing to flash again.

The FM has the functionality of checking if the flash array is erased. This function executes it. It does not support individual sector analysis.

Erases either a sector or the complete flash array. If either the range first-last covers the complete array or if first == 0 and last == 0 then a mass erase command is executed on the FM. If not, then individual sectors are erased.

Reads the memory mapped protection register. A 1 implies the sector is protected, a 0 implies the sector is not protected.

Writes the flash security words with a specific value. The chip's security will be enabled after the first reset following the execution of this function.

Executes a mass erase command. The must be done from the Master tap. It is up to the user to select the master tap (jtag tapenable dsp5680xx.chp) before running this function. The flash array will be unsecured (and erased) after the first reset following the execution of this function.

Probe EmbeddedICE module and set up local records of its registers. Different versions of the modules have different capabilities, such as hardware support for vector_catch, single stepping, and monitor mode.

Initialize EmbeddedICE module, if needed.

Invokes SROM API functions which are responsible for Flash operations

Retrieves SiliconID and Protection status of the target device

Simulates broken Vector Catch Function will try to determine entry point of user application. If it succeeds it will set HW breakpoint at that address, issue SW Reset and remove the breakpoint afterwards. In case of CM0, SYSRESETREQ is used. This allows to reset all peripherals. Boot code will reset CM4 anyway, so using SYSRESETREQ is safe here. In case of CM4, VECTRESET is used instead of SYSRESETREQ to not disturb CM0 core.

Starts pseudo flash algorithm and leaves it running. Function allocates working area for algorithm code and CPU stack, adjusts stack pointer, uploads and starts the algorithm. Algorithm (a basic infinite loop) runs asynchronously while driver performs Flash operations.

Stops running flash algorithm and releases associated resources. This function is also used for cleanup in case of errors so g_stack_area may be NULL. These cases have to be handled gracefully.

Waits for expected IPC lock status. PSoC6 uses IPC structures for inter-core communication. Same IPCs are used to invoke SROM API. IPC structure must be locked prior to invoking any SROM API. This ensures nothing else in the system will use same IPC thus corrupting our data. Locking is performed by ipc_acquire(), this function ensures that IPC is actually in expected state

Acquires IPC structure. PSoC6 uses IPC structures for inter-core communication. Same IPCs are used to invoke SROM API. IPC structure must be locked prior to invoking any SROM API. This ensures nothing else in the system will use same IPC thus corrupting our data. This function locks the IPC.

Erases a flash block or page at the given address.

Modify the contents of the User Row in Flash. The User Row itself has a size of one page and contains a combination of "fuses" and calibration data. Bits which have a value of zero in the mask will not be changed.

Modifies the user row register to the given value.

Initialize common semihosting support.

Portable implementation of ARM semihosting calls. Performs the currently pending semihosting operation encoded in target->semihosting.

Read all fields of a command from target to buffer.

Write all fields of a command from buffer to target.

Extract a field from the buffer, considering register size and endianness.

OpenOCD Interface **

RISC-V Interface **

Support functions for the RISC-V 'RTOS', which provides multihart support without requiring multiple targets.

This function is called when the debug user wants to change the value of a register. The new value may be cached, and may not be written until the hart is resumed.

Get register, from the cache if it's in there.

Count triggers, and initialize trigger_count for each hart. trigger_count is initialized even if this function fails to discover something. Disable any hardware triggers that have dmode set. We can't have set them ourselves. Maybe they're left over from some killed debug session.

Initialize RISC-V semihosting. Use common ARM code.

Check for and process a semihosting request using the ARM protocol). This is meant to be called when the target is stopped due to a debug mode entry.

Read one memory item using any memory access size that will work. Read larger section of memory and pick out the required portion, if needed.

Write one memory item using any memory access size that will work. Utilize read-modify-write, if needed.

Store a field in the buffer, considering register size and endianness.

Register an RTT source for a target.

Initialize ARM semihosting support.

Checks for and processes an ARM semihosting request. This is meant to be called when the target is stopped due to a debug mode entry. If the value 0 is returned then there was nothing to process. A non-zero return value signifies that a request was processed and the target resumed, or an error was encountered, in which case the caller must return immediately.

Setup the common pieces for an ARM7/9 target after reset or on startup.

Set either a hardware or software breakpoint on an ARM7/9 target. The breakpoint is set up even if it is already set. Some actions, e.g. reset, might have erased the values in Embedded ICE.

Clears the halt condition for an ARM7/9 target. If it isn't coming out of reset and if DBGRQ is used, it is programmed to be deasserted. If the reset vector catch was used, it is restored. Otherwise, the control value is restored and the watchpoint unit is restored if it was in use.

Restart the core of an ARM7/9 target. A RESTART command is sent to the instruction register and the JTAG state is set to TAP_IDLE causing a core restart.

Enable the watchpoints on an ARM7/9 target. The target's watchpoints are iterated through and are set on the target if they aren't already set.

Enable the breakpoints on an ARM7/9 target. The target's breakpoints are iterated through and are set on the target.

Unset an existing watchpoint and clear the used watchpoint unit.

Restarts the target by sending a RESTART instruction and moving the JTAG state to IDLE. This validates that DBGACK and SYSCOMP are set without waiting until they are.

Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the ARM. The JTAG queue is then executed and the reason for debug entry is examined. Once done, the target is verified to be halted and the processor is forced into ARM mode. The core registers are saved for the current core mode and the program counter (register 15) is updated as needed. The core registers and CPSR and SPSR are saved for restoration later.

Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware breakpoint, the watchpoint used will be freed and the Embedded ICE registers will be updated. Otherwise, the software breakpoint will be restored to its original instruction if it hasn't already been modified.

Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is considered a bug to call this function when there are no available watchpoint units.

Validate the full context for an ARM7/9 target in all processor modes. If there are any invalid registers for the target, they will all be read. This includes the PSR.

Restore the processor context on an ARM7/9 target. The full processor context is analyzed to see if any of the registers are dirty on this end, but have a valid new value. If this is the case, the processor is changed to the appropriate mode and the new register values are written out to the processor. If there happens to be a dirty register with an invalid value, an error will be logged.

Logs summary of ARM920 state for a halted target.

Reads a buffer, in the specified word size, with current MMU settings.

Writes a buffer, in the specified word size, with current MMU settings.

Writes a buffer, in the specified word size, with current MMU settings.

Logs summary of ARM926 state for a halted target.

Writes a buffer, in the specified word size, with current MMU settings.

@file Implements various ARM DPM operations using architectural debug registers. These routines layer over core-specific communication methods to cope with implementation differences between cores like ARM1136 and Cortex-A8. The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by Part C (Debug Architecture) of the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition (ARM DDI 0406B). In OpenOCD, DPM operations are abstracted through internal programming interfaces to share code and to minimize needless differences in debug behavior between cores.

Unset an existing watchpoint and clear the used watchpoint unit.

Add a watchpoint to an Cortex-A target. If there are no watchpoint units available, an error response is returned.

Remove a watchpoint from an Cortex-A target. The watchpoint will be unset and the used watchpoint unit will be reopened.

Sets a watchpoint for an Cortex-A target in one of the watchpoint units. It is considered a bug to call this function when there are no available watchpoint units.

Read DCB DHCSR register to cortex_m->dcb_dhcsr and cumulate sticky bits in cortex_m->dcb_dhcsr_cumulated_sticky

Test func

Executes EOnCE instruction.

Takes the core out of debug mode.

Puts the core into debug mode, enabling the EOnCE module. This will not always work, eonce_enter_debug_mode executes much more complicated routine, which is guaranteed to work, but requires a reset. This will complicate comm with the flash module, since after a reset clock divisors must be set again. This implementation works most of the time, and is not accessible to the user.

Puts the core into debug mode, enabling the EOnCE module.

Reads the current value of the program counter and stores it.

Writes @a buffer to memory. The parameter @a address determines whether @a buffer should be written to P: (program) memory or X: (dat) memory.

Executes the FM page erase command.

Executes the FM mass erase command. Erases the flash array completely.

This function is called by verify_image, it is used to read data from memory.

This function is not implemented. It returns an error in order to get OpenOCD to do read out the data and calculate the CRC, or try a binary comparison.

Resets the SIM. (System Integration Modul).

Halts the core and resets the SIM. (System Integration Modul).

Executes a command on the FM module. Some commands use the parameters @a address and @a data, others ignore them.

Prior to the execution of any Flash module command, the Flash module Clock Divider (CLKDIV) register must be initialized. The values of this register determine the speed of the internal Flash Clock (FCLK). FCLK must be in the range of 150kHz ≤ FCLK ≤ 200kHz for proper operation of the Flash module. (Running FCLK too slowly wears out the module, while running it too fast under programs Flash leading to bit errors.)

Executes the FM calculate signature command. The FM will calculate over the data from @a address to @a address + @a words -1. The result is written to a register, then read out by this function and returned in @a signature. The value @a signature may be compared to the one returned by perl_crc to verify the flash was written correctly.

Reset the @c examined flag for the given target. Pure paranoia -- targets are zeroed on allocation.

prepare single target for restart

find out which watchpoint hits get exception address and compare the address to watchpoints

Checks whether a memory region is erased.

Version-independent functions that we don't want in the main address space. **

Add ebreak and execute the program.

Write one memory item of given "size". Use memory access of given "access_size". Utilize read-modify-write, if needed.

Read one memory item of given "size". Use memory access of given "access_size". Read larger section of memory and pick out the required portion, if needed.

RISC-V Interface **

Get everything ready to resume.

Resume all the harts that have been prepped, as close to instantaneous as possible.

@par single_hart When true, only resume a single hart even if SMP is configured. This is used to run algorithms on just one hart.

Called via semihosting->setup() later, after the target is known, usually on the first semihosting command.

end of scans class **

Read the haltnot and interrupt bits.

Necessary prototypes. **

OpenOCD target functions. **