Outline ![]()
Files ![]()
loading...
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************
* Copyright (C) 2006, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* Copyright (C) 2007,2008 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2009 Michael Schwingen *
* michael@schwingen.org *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "breakpoints.h"
#include "xscale.h"
#include "target_type.h"
#include "arm_jtag.h"
#include "arm_simulator.h"
#include "arm_disassembler.h"
#include <helper/time_support.h>
#include "register.h"
#include "image.h"
#include "arm_opcodes.h"
#include "armv4_5.h"
/*
* Important XScale documents available as of October 2009 include:
*
* Intel XScale® Core Developer’s Manual, January 2004
* Order Number: 273473-002
* This has a chapter detailing debug facilities, and punts some
* details to chip-specific microarchitecture documents.
*
* Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
* Document Number: 273539-005
* Less detailed than the developer's manual, but summarizes those
* missing details (for most XScales) and gives LOTS of notes about
* debugger/handler interaction issues. Presents a simpler reset
* and load-handler sequence than the arch doc. (Note, OpenOCD
* doesn't currently support "Hot-Debug" as defined there.)
*
* Chip-specific microarchitecture documents may also be useful.
*/
/* forward declarations */
static int xscale_resume(struct target *, int current,
target_addr_t address, int handle_breakpoints, int debug_execution);
static int xscale_debug_entry(struct target *);
static int xscale_restore_banked(struct target *);
static int xscale_get_reg(struct reg *reg);
static int xscale_set_reg(struct reg *reg, uint8_t *buf);
static int xscale_set_breakpoint(struct target *, struct breakpoint *);
static int xscale_set_watchpoint(struct target *, struct watchpoint *);
static int xscale_unset_breakpoint(struct target *, struct breakpoint *);
static int xscale_read_trace(struct target *);
/* This XScale "debug handler" is loaded into the processor's
* mini-ICache, which is 2K of code writable only via JTAG.
*/
static const uint8_t xscale_debug_handler[] = {
#include "../../contrib/loaders/debug/xscale/debug_handler.inc"
};
static const char *const xscale_reg_list[] = {
"XSCALE_MAINID", /* 0 */
"XSCALE_CACHETYPE",
"XSCALE_CTRL",
"XSCALE_AUXCTRL",
"XSCALE_TTB",
"XSCALE_DAC",
"XSCALE_FSR",
"XSCALE_FAR",
"XSCALE_PID",
"XSCALE_CPACCESS",
"XSCALE_IBCR0", /* 10 */
"XSCALE_IBCR1",
"XSCALE_DBR0",
"XSCALE_DBR1",
"XSCALE_DBCON",
"XSCALE_TBREG",
"XSCALE_CHKPT0",
"XSCALE_CHKPT1",
"XSCALE_DCSR",
"XSCALE_TX",
"XSCALE_RX", /* 20 */
"XSCALE_TXRXCTRL",
};
static const struct xscale_reg xscale_reg_arch_info[] = {
{XSCALE_MAINID, NULL},
{XSCALE_CACHETYPE, NULL},
{XSCALE_CTRL, NULL},
{XSCALE_AUXCTRL, NULL},
{XSCALE_TTB, NULL},
{XSCALE_DAC, NULL},
{XSCALE_FSR, NULL},
{XSCALE_FAR, NULL},
{XSCALE_PID, NULL},
{XSCALE_CPACCESS, NULL},
{XSCALE_IBCR0, NULL},
{XSCALE_IBCR1, NULL},
{XSCALE_DBR0, NULL},
{XSCALE_DBR1, NULL},
{XSCALE_DBCON, NULL},
{XSCALE_TBREG, NULL},
{XSCALE_CHKPT0, NULL},
{XSCALE_CHKPT1, NULL},
{XSCALE_DCSR, NULL}, /* DCSR accessed via JTAG or SW */
{-1, NULL}, /* TX accessed via JTAG */
{-1, NULL}, /* RX accessed via JTAG */
{-1, NULL}, /* TXRXCTRL implicit access via JTAG */
};
/* convenience wrapper to access XScale specific registers */
static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
{
uint8_t buf[4] = { 0 };
buf_set_u32(buf, 0, 32, value);
return xscale_set_reg(reg, buf);
}
static const char xscale_not[] = "target is not an XScale";
static int xscale_verify_pointer(struct command_invocation *cmd,
struct xscale_common *xscale)
{
if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
command_print(cmd, xscale_not);
return ERROR_TARGET_INVALID;
}
return ERROR_OK;
}
static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
{
assert(tap);
if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
struct scan_field field;
uint8_t scratch[4] = { 0 };
memset(&field, 0, sizeof(field));
field.num_bits = tap->ir_length;
field.out_value = scratch;
buf_set_u32(scratch, 0, field.num_bits, new_instr);
jtag_add_ir_scan(tap, &field, end_state);
}
return ERROR_OK;
}
static int xscale_read_dcsr(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
int retval;
struct scan_field fields[3];
uint8_t field0 = 0x0;
uint8_t field0_check_value = 0x2;
uint8_t field0_check_mask = 0x7;
uint8_t field2 = 0x0;
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
xscale_jtag_set_instr(target->tap,
XSCALE_SELDCSR << xscale->xscale_variant,
TAP_DRPAUSE);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
memset(&fields, 0, sizeof(fields));
fields[0].num_bits = 3;
fields[0].out_value = &field0;
uint8_t tmp;
fields[0].in_value = &tmp;
fields[1].num_bits = 32;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp2;
fields[2].in_value = &tmp2;
jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("JTAG error while reading DCSR");
return retval;
}
xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = false;
xscale->reg_cache->reg_list[XSCALE_DCSR].valid = true;
/* write the register with the value we just read
* on this second pass, only the first bit of field0 is guaranteed to be 0)
*/
field0_check_mask = 0x1;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[1].in_value = NULL;
jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
/* DANGER!!! this must be here. It will make sure that the arguments
* to jtag_set_check_value() does not go out of scope! */
return jtag_execute_queue();
}
static void xscale_getbuf(jtag_callback_data_t arg)
{
uint8_t *in = (uint8_t *)arg;
*((uint32_t *)arg) = buf_get_u32(in, 0, 32);
}
static int xscale_receive(struct target *target, uint32_t *buffer, int num_words)
{
if (num_words == 0)
return ERROR_COMMAND_SYNTAX_ERROR;
struct xscale_common *xscale = target_to_xscale(target);
int retval = ERROR_OK;
tap_state_t path[3];
struct scan_field fields[3];
uint8_t *field0 = malloc(num_words * 1);
uint8_t field0_check_value = 0x2;
uint8_t field0_check_mask = 0x6;
uint32_t *field1 = malloc(num_words * 4);
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
int words_done = 0;
int words_scheduled = 0;
int i;
path[0] = TAP_DRSELECT;
path[1] = TAP_DRCAPTURE;
path[2] = TAP_DRSHIFT;
memset(&fields, 0, sizeof(fields));
fields[0].num_bits = 3;
uint8_t tmp;
fields[0].in_value = &tmp;
fields[0].check_value = &field0_check_value;
fields[0].check_mask = &field0_check_mask;
fields[1].num_bits = 32;
fields[2].num_bits = 1;
uint8_t tmp2;
fields[2].in_value = &tmp2;
fields[2].check_value = &field2_check_value;
fields[2].check_mask = &field2_check_mask;
xscale_jtag_set_instr(target->tap,
XSCALE_DBGTX << xscale->xscale_variant,
TAP_IDLE);
jtag_add_runtest(1, TAP_IDLE); /* ensures that we're in the TAP_IDLE state as the above
*could be a no-op */
/* repeat until all words have been collected */
int attempts = 0;
while (words_done < num_words) {
/* schedule reads */
words_scheduled = 0;
for (i = words_done; i < num_words; i++) {
fields[0].in_value = &field0[i];
jtag_add_pathmove(3, path);
fields[1].in_value = (uint8_t *)(field1 + i);
jtag_add_dr_scan_check(target->tap, 3, fields, TAP_IDLE);
jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
words_scheduled++;
}
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("JTAG error while receiving data from debug handler");
break;
}
/* examine results */
for (i = words_done; i < num_words; i++) {
if (!(field0[i] & 1)) {
/* move backwards if necessary */
int j;
for (j = i; j < num_words - 1; j++) {
field0[j] = field0[j + 1];
field1[j] = field1[j + 1];
}
words_scheduled--;
}
}
if (words_scheduled == 0) {
if (attempts++ == 1000) {
LOG_ERROR(
"Failed to receiving data from debug handler after 1000 attempts");
retval = ERROR_TARGET_TIMEOUT;
break;
}
}
words_done += words_scheduled;
}
for (i = 0; i < num_words; i++)
*(buffer++) = buf_get_u32((uint8_t *)&field1[i], 0, 32);
free(field1);
return retval;
}
static int xscale_read_tx(struct target *target, int consume)
{
struct xscale_common *xscale = target_to_xscale(target);
tap_state_t path[3];
tap_state_t noconsume_path[6];
int retval;
struct timeval timeout, now;
struct scan_field fields[3];
uint8_t field0_in = 0x0;
uint8_t field0_check_value = 0x2;
uint8_t field0_check_mask = 0x6;
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
xscale_jtag_set_instr(target->tap,
XSCALE_DBGTX << xscale->xscale_variant,
TAP_IDLE);
path[0] = TAP_DRSELECT;
path[1] = TAP_DRCAPTURE;
path[2] = TAP_DRSHIFT;
noconsume_path[0] = TAP_DRSELECT;
noconsume_path[1] = TAP_DRCAPTURE;
noconsume_path[2] = TAP_DREXIT1;
noconsume_path[3] = TAP_DRPAUSE;
noconsume_path[4] = TAP_DREXIT2;
noconsume_path[5] = TAP_DRSHIFT;
memset(&fields, 0, sizeof(fields));
fields[0].num_bits = 3;
fields[0].in_value = &field0_in;
fields[1].num_bits = 32;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
fields[2].num_bits = 1;
uint8_t tmp;
fields[2].in_value = &tmp;
gettimeofday(&timeout, NULL);
timeval_add_time(&timeout, 1, 0);
for (;; ) {
/* if we want to consume the register content (i.e. clear TX_READY),
* we have to go straight from Capture-DR to Shift-DR
* otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
*/
if (consume)
jtag_add_pathmove(3, path);
else
jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path);
jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("JTAG error while reading TX");
return ERROR_TARGET_TIMEOUT;
}
gettimeofday(&now, NULL);
if (timeval_compare(&now, &timeout) > 0) {
LOG_ERROR("time out reading TX register");
return ERROR_TARGET_TIMEOUT;
}
if (!((!(field0_in & 1)) && consume))
goto done;
if (debug_level >= 3) {
LOG_DEBUG("waiting 100ms");
alive_sleep(100); /* avoid flooding the logs */
} else
keep_alive();
}
done:
if (!(field0_in & 1))
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
return ERROR_OK;
}
static int xscale_write_rx(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
int retval;
struct timeval timeout, now;
struct scan_field fields[3];
uint8_t field0_out = 0x0;
uint8_t field0_in = 0x0;
uint8_t field0_check_value = 0x2;
uint8_t field0_check_mask = 0x6;
uint8_t field2 = 0x0;
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
xscale_jtag_set_instr(target->tap,
XSCALE_DBGRX << xscale->xscale_variant,
TAP_IDLE);
memset(&fields, 0, sizeof(fields));
fields[0].num_bits = 3;
fields[0].out_value = &field0_out;
fields[0].in_value = &field0_in;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp;
fields[2].in_value = &tmp;
gettimeofday(&timeout, NULL);
timeval_add_time(&timeout, 1, 0);
/* poll until rx_read is low */
LOG_DEBUG("polling RX");
for (;;) {
jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("JTAG error while writing RX");
return retval;
}
gettimeofday(&now, NULL);
if ((now.tv_sec > timeout.tv_sec) ||
((now.tv_sec == timeout.tv_sec) && (now.tv_usec > timeout.tv_usec))) {
LOG_ERROR("time out writing RX register");
return ERROR_TARGET_TIMEOUT;
}
if (!(field0_in & 1))
goto done;
if (debug_level >= 3) {
LOG_DEBUG("waiting 100ms");
alive_sleep(100); /* avoid flooding the logs */
} else
keep_alive();
}
done:
/* set rx_valid */
field2 = 0x1;
jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("JTAG error while writing RX");
return retval;
}
return ERROR_OK;
}
/* send count elements of size byte to the debug handler */
static int xscale_send(struct target *target, const uint8_t *buffer, int count, int size)
{
struct xscale_common *xscale = target_to_xscale(target);
int retval;
int done_count = 0;
xscale_jtag_set_instr(target->tap,
XSCALE_DBGRX << xscale->xscale_variant,
TAP_IDLE);
static const uint8_t t0;
uint8_t t1[4] = { 0 };
static const uint8_t t2 = 1;
struct scan_field fields[3] = {
{ .num_bits = 3, .out_value = &t0 },
{ .num_bits = 32, .out_value = t1 },
{ .num_bits = 1, .out_value = &t2 },
};
int endianness = target->endianness;
while (done_count++ < count) {
uint32_t t;
switch (size) {
case 4:
if (endianness == TARGET_LITTLE_ENDIAN)
t = le_to_h_u32(buffer);
else
t = be_to_h_u32(buffer);
break;
case 2:
if (endianness == TARGET_LITTLE_ENDIAN)
t = le_to_h_u16(buffer);
else
t = be_to_h_u16(buffer);
break;
case 1:
t = buffer[0];
break;
default:
LOG_ERROR("BUG: size neither 4, 2 nor 1");
return ERROR_COMMAND_SYNTAX_ERROR;
}
buf_set_u32(t1, 0, 32, t);
jtag_add_dr_scan(target->tap,
3,
fields,
TAP_IDLE);
buffer += size;
}
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("JTAG error while sending data to debug handler");
return retval;
}
return ERROR_OK;
}
static int xscale_send_u32(struct target *target, uint32_t value)
{
struct xscale_common *xscale = target_to_xscale(target);
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
return xscale_write_rx(target);
}
static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_brk)
{
struct xscale_common *xscale = target_to_xscale(target);
int retval;
struct scan_field fields[3];
uint8_t field0 = 0x0;
uint8_t field0_check_value = 0x2;
uint8_t field0_check_mask = 0x7;
uint8_t field2 = 0x0;
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
if (hold_rst != -1)
xscale->hold_rst = hold_rst;
if (ext_dbg_brk != -1)
xscale->external_debug_break = ext_dbg_brk;
xscale_jtag_set_instr(target->tap,
XSCALE_SELDCSR << xscale->xscale_variant,
TAP_IDLE);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
memset(&fields, 0, sizeof(fields));
fields[0].num_bits = 3;
fields[0].out_value = &field0;
uint8_t tmp;
fields[0].in_value = &tmp;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp2;
fields[2].in_value = &tmp2;
jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("JTAG error while writing DCSR");
return retval;
}
xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = false;
xscale->reg_cache->reg_list[XSCALE_DCSR].valid = true;
return ERROR_OK;
}
/* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
static unsigned int parity(unsigned int v)
{
/* unsigned int ov = v; */
v ^= v >> 16;
v ^= v >> 8;
v ^= v >> 4;
v &= 0xf;
/* LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); */
return (0x6996 >> v) & 1;
}
static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8])
{
struct xscale_common *xscale = target_to_xscale(target);
uint8_t packet[4] = { 0 };
uint8_t cmd = 0;
int word;
struct scan_field fields[2];
LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
/* LDIC into IR */
xscale_jtag_set_instr(target->tap,
XSCALE_LDIC << xscale->xscale_variant,
TAP_IDLE);
/* CMD is b011 to load a cacheline into the Mini ICache.
* Loading into the main ICache is deprecated, and unused.
* It's followed by three zero bits, and 27 address bits.
*/
buf_set_u32(&cmd, 0, 6, 0x3);
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
memset(&fields, 0, sizeof(fields));
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
fields[1].num_bits = 27;
fields[1].out_value = packet;
jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
/* rest of packet is a cacheline: 8 instructions, with parity */
fields[0].num_bits = 32;
fields[0].out_value = packet;
fields[1].num_bits = 1;
fields[1].out_value = &cmd;
for (word = 0; word < 8; word++) {
buf_set_u32(packet, 0, 32, buffer[word]);
uint32_t value;
memcpy(&value, packet, sizeof(uint32_t));
cmd = parity(value);
jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
}
return jtag_execute_queue();
}
static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
{
struct xscale_common *xscale = target_to_xscale(target);
uint8_t packet[4] = { 0 };
uint8_t cmd = 0;
struct scan_field fields[2];
xscale_jtag_set_instr(target->tap,
XSCALE_LDIC << xscale->xscale_variant,
TAP_IDLE);
/* CMD for invalidate IC line b000, bits [6:4] b000 */
buf_set_u32(&cmd, 0, 6, 0x0);
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
memset(&fields, 0, sizeof(fields));
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
fields[1].num_bits = 27;
fields[1].out_value = packet;
jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
return ERROR_OK;
}
static int xscale_update_vectors(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
int i;
int retval;
uint32_t low_reset_branch, high_reset_branch;
for (i = 1; i < 8; i++) {
/* if there's a static vector specified for this exception, override */
if (xscale->static_high_vectors_set & (1 << i))
xscale->high_vectors[i] = xscale->static_high_vectors[i];
else {
retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
if (retval == ERROR_TARGET_TIMEOUT)
return retval;
if (retval != ERROR_OK) {
/* Some of these reads will fail as part of normal execution */
xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
}
}
}
for (i = 1; i < 8; i++) {
if (xscale->static_low_vectors_set & (1 << i))
xscale->low_vectors[i] = xscale->static_low_vectors[i];
else {
retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
if (retval == ERROR_TARGET_TIMEOUT)
return retval;
if (retval != ERROR_OK) {
/* Some of these reads will fail as part of normal execution */
xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
}
}
}
/* calculate branches to debug handler */
low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
/* invalidate and load exception vectors in mini i-cache */
xscale_invalidate_ic_line(target, 0x0);
xscale_invalidate_ic_line(target, 0xffff0000);
xscale_load_ic(target, 0x0, xscale->low_vectors);
xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
return ERROR_OK;
}
static int xscale_arch_state(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
struct arm *arm = &xscale->arm;
static const char *state[] = {
"disabled", "enabled"
};
static const char *arch_dbg_reason[] = {
"", "\n(processor reset)", "\n(trace buffer full)"
};
if (arm->common_magic != ARM_COMMON_MAGIC) {
LOG_ERROR("BUG: called for a non-ARMv4/5 target");
return ERROR_COMMAND_SYNTAX_ERROR;
}
arm_arch_state(target);
LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
state[xscale->armv4_5_mmu.mmu_enabled],
state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
arch_dbg_reason[xscale->arch_debug_reason]);
return ERROR_OK;
}
static int xscale_poll(struct target *target)
{
int retval = ERROR_OK;
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING)) {
enum target_state previous_state = target->state;
retval = xscale_read_tx(target, 0);
if (retval == ERROR_OK) {
/* there's data to read from the tx register, we entered debug state */
target->state = TARGET_HALTED;
/* process debug entry, fetching current mode regs */
retval = xscale_debug_entry(target);
} else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
LOG_USER("error while polling TX register, reset CPU");
/* here we "lie" so GDB won't get stuck and a reset can be performed */
target->state = TARGET_HALTED;
}
/* debug_entry could have overwritten target state (i.e. immediate resume)
* don't signal event handlers in that case
*/
if (target->state != TARGET_HALTED)
return ERROR_OK;
/* if target was running, signal that we halted
* otherwise we reentered from debug execution */
if (previous_state == TARGET_RUNNING)
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
else
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
}
return retval;
}
static int xscale_debug_entry(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
struct arm *arm = &xscale->arm;
uint32_t pc;
uint32_t buffer[10];
unsigned i;
int retval;
uint32_t moe;
/* clear external dbg break (will be written on next DCSR read) */
xscale->external_debug_break = 0;
retval = xscale_read_dcsr(target);
if (retval != ERROR_OK)
return retval;
/* get r0, pc, r1 to r7 and cpsr */
retval = xscale_receive(target, buffer, 10);
if (retval != ERROR_OK)
return retval;
/* move r0 from buffer to register cache */
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, buffer[0]);
arm->core_cache->reg_list[0].dirty = true;
arm->core_cache->reg_list[0].valid = true;
LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
/* move pc from buffer to register cache */
buf_set_u32(arm->pc->value, 0, 32, buffer[1]);
arm->pc->dirty = true;
arm->pc->valid = true;
LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
/* move data from buffer to register cache */
for (i = 1; i <= 7; i++) {
buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
arm->core_cache->reg_list[i].dirty = true;
arm->core_cache->reg_list[i].valid = true;
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
}
arm_set_cpsr(arm, buffer[9]);
LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
if (!is_arm_mode(arm->core_mode)) {
target->state = TARGET_UNKNOWN;
LOG_ERROR("cpsr contains invalid mode value - communication failure");
return ERROR_TARGET_FAILURE;
}
LOG_DEBUG("target entered debug state in %s mode",
arm_mode_name(arm->core_mode));
/* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
if (arm->spsr) {
xscale_receive(target, buffer, 8);
buf_set_u32(arm->spsr->value, 0, 32, buffer[7]);
arm->spsr->dirty = false;
arm->spsr->valid = true;
} else {
/* r8 to r14, but no spsr */
xscale_receive(target, buffer, 7);
}
/* move data from buffer to right banked register in cache */
for (i = 8; i <= 14; i++) {
struct reg *r = arm_reg_current(arm, i);
buf_set_u32(r->value, 0, 32, buffer[i - 8]);
r->dirty = false;
r->valid = true;
}
/* mark xscale regs invalid to ensure they are retrieved from the
* debug handler if requested */
for (i = 0; i < xscale->reg_cache->num_regs; i++)
xscale->reg_cache->reg_list[i].valid = false;
/* examine debug reason */
xscale_read_dcsr(target);
moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
/* stored PC (for calculating fixup) */
pc = buf_get_u32(arm->pc->value, 0, 32);
switch (moe) {
case 0x0: /* Processor reset */
target->debug_reason = DBG_REASON_DBGRQ;
xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
pc -= 4;
break;
case 0x1: /* Instruction breakpoint hit */
target->debug_reason = DBG_REASON_BREAKPOINT;
xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
pc -= 4;
break;
case 0x2: /* Data breakpoint hit */
target->debug_reason = DBG_REASON_WATCHPOINT;
xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
pc -= 4;
break;
case 0x3: /* BKPT instruction executed */
target->debug_reason = DBG_REASON_BREAKPOINT;
xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
pc -= 4;
break;
case 0x4: /* Ext. debug event */
target->debug_reason = DBG_REASON_DBGRQ;
xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
pc -= 4;
break;
case 0x5: /* Vector trap occurred */
target->debug_reason = DBG_REASON_BREAKPOINT;
xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
pc -= 4;
break;
case 0x6: /* Trace buffer full break */
target->debug_reason = DBG_REASON_DBGRQ;
xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
pc -= 4;
break;
case 0x7: /* Reserved (may flag Hot-Debug support) */
default:
LOG_ERROR("Method of Entry is 'Reserved'");
exit(-1);
break;
}
/* apply PC fixup */
buf_set_u32(arm->pc->value, 0, 32, pc);
/* on the first debug entry, identify cache type */
if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1) {
uint32_t cache_type_reg;
/* read cp15 cache type register */
xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value,
0,
32);
armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache);
}
/* examine MMU and Cache settings
* read cp15 control register */
xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
xscale->cp15_control_reg =
buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
(xscale->cp15_control_reg & 0x4U) ? 1 : 0;
xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
(xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
/* tracing enabled, read collected trace data */
if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
xscale_read_trace(target);
/* Resume if entered debug due to buffer fill and we're still collecting
* trace data. Note that a debug exception due to trace buffer full
* can only happen in fill mode. */
if (xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL) {
if (--xscale->trace.fill_counter > 0)
xscale_resume(target, 1, 0x0, 1, 0);
} else /* entered debug for other reason; reset counter */
xscale->trace.fill_counter = 0;
}
return ERROR_OK;
}
static int xscale_halt(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
LOG_DEBUG("target->state: %s",
target_state_name(target));
if (target->state == TARGET_HALTED) {
LOG_DEBUG("target was already halted");
return ERROR_OK;
} else if (target->state == TARGET_UNKNOWN) {
/* this must not happen for a xscale target */
LOG_ERROR("target was in unknown state when halt was requested");
return ERROR_TARGET_INVALID;
} else if (target->state == TARGET_RESET)
LOG_DEBUG("target->state == TARGET_RESET");
else {
/* assert external dbg break */
xscale->external_debug_break = 1;
xscale_read_dcsr(target);
target->debug_reason = DBG_REASON_DBGRQ;
}
return ERROR_OK;
}
static int xscale_enable_single_step(struct target *target, uint32_t next_pc)
{
struct xscale_common *xscale = target_to_xscale(target);
struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
int retval;
if (xscale->ibcr0_used) {
struct breakpoint *ibcr0_bp =
breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe);
if (ibcr0_bp)
xscale_unset_breakpoint(target, ibcr0_bp);
else {
LOG_ERROR(
"BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
exit(-1);
}
}
retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
static int xscale_disable_single_step(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
int retval;
retval = xscale_set_reg_u32(ibcr0, 0x0);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
static void xscale_enable_watchpoints(struct target *target)
{
struct watchpoint *watchpoint = target->watchpoints;
while (watchpoint) {
if (!watchpoint->is_set)
xscale_set_watchpoint(target, watchpoint);
watchpoint = watchpoint->next;
}
}
static void xscale_enable_breakpoints(struct target *target)
{
struct breakpoint *breakpoint = target->breakpoints;
/* set any pending breakpoints */
while (breakpoint) {
if (!breakpoint->is_set)
xscale_set_breakpoint(target, breakpoint);
breakpoint = breakpoint->next;
}
}
static void xscale_free_trace_data(struct xscale_common *xscale)
{
struct xscale_trace_data *td = xscale->trace.data;
while (td) {
struct xscale_trace_data *next_td = td->next;
free(td->entries);
free(td);
td = next_td;
}
xscale->trace.data = NULL;
}
static int xscale_resume(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution)
{
struct xscale_common *xscale = target_to_xscale(target);
struct arm *arm = &xscale->arm;
uint32_t current_pc;
int retval;
int i;
LOG_DEBUG("-");
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (!debug_execution)
target_free_all_working_areas(target);
/* update vector tables */
retval = xscale_update_vectors(target);
if (retval != ERROR_OK)
return retval;
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
buf_set_u32(arm->pc->value, 0, 32, address);
current_pc = buf_get_u32(arm->pc->value, 0, 32);
/* if we're at the reset vector, we have to simulate the branch */
if (current_pc == 0x0) {
arm_simulate_step(target, NULL);
current_pc = buf_get_u32(arm->pc->value, 0, 32);
}
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints) {
struct breakpoint *breakpoint;
breakpoint = breakpoint_find(target,
buf_get_u32(arm->pc->value, 0, 32));
if (breakpoint) {
uint32_t next_pc;
enum trace_mode saved_trace_mode;
/* there's a breakpoint at the current PC, we have to step over it */
LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",
breakpoint->address);
xscale_unset_breakpoint(target, breakpoint);
/* calculate PC of next instruction */
retval = arm_simulate_step(target, &next_pc);
if (retval != ERROR_OK) {
uint32_t current_opcode;
target_read_u32(target, current_pc, ¤t_opcode);
LOG_ERROR(
"BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
current_opcode);
}
LOG_DEBUG("enable single-step");
xscale_enable_single_step(target, next_pc);
/* restore banked registers */
retval = xscale_restore_banked(target);
if (retval != ERROR_OK)
return retval;
/* send resume request */
xscale_send_u32(target, 0x30);
/* send CPSR */
xscale_send_u32(target,
buf_get_u32(arm->cpsr->value, 0, 32));
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
buf_get_u32(arm->cpsr->value, 0, 32));
for (i = 7; i >= 0; i--) {
/* send register */
xscale_send_u32(target,
buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
}
/* send PC */
xscale_send_u32(target,
buf_get_u32(arm->pc->value, 0, 32));
LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
buf_get_u32(arm->pc->value, 0, 32));
/* disable trace data collection in xscale_debug_entry() */
saved_trace_mode = xscale->trace.mode;
xscale->trace.mode = XSCALE_TRACE_DISABLED;
/* wait for and process debug entry */
xscale_debug_entry(target);
/* re-enable trace buffer, if enabled previously */
xscale->trace.mode = saved_trace_mode;
LOG_DEBUG("disable single-step");
xscale_disable_single_step(target);
LOG_DEBUG("set breakpoint at " TARGET_ADDR_FMT "",
breakpoint->address);
xscale_set_breakpoint(target, breakpoint);
}
}
/* enable any pending breakpoints and watchpoints */
xscale_enable_breakpoints(target);
xscale_enable_watchpoints(target);
/* restore banked registers */
retval = xscale_restore_banked(target);
if (retval != ERROR_OK)
return retval;
/* send resume request (command 0x30 or 0x31)
* clean the trace buffer if it is to be enabled (0x62) */
if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
if (xscale->trace.mode == XSCALE_TRACE_FILL) {
/* If trace enabled in fill mode and starting collection of new set
* of buffers, initialize buffer counter and free previous buffers */
if (xscale->trace.fill_counter == 0) {
xscale->trace.fill_counter = xscale->trace.buffer_fill;
xscale_free_trace_data(xscale);
}
} else /* wrap mode; free previous buffer */
xscale_free_trace_data(xscale);
xscale_send_u32(target, 0x62);
xscale_send_u32(target, 0x31);
} else
xscale_send_u32(target, 0x30);
/* send CPSR */
xscale_send_u32(target, buf_get_u32(arm->cpsr->value, 0, 32));
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
buf_get_u32(arm->cpsr->value, 0, 32));
for (i = 7; i >= 0; i--) {
/* send register */
xscale_send_u32(target, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
}
/* send PC */
xscale_send_u32(target, buf_get_u32(arm->pc->value, 0, 32));
LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
buf_get_u32(arm->pc->value, 0, 32));
target->debug_reason = DBG_REASON_NOTHALTED;
if (!debug_execution) {
/* registers are now invalid */
register_cache_invalidate(arm->core_cache);
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
} else {
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
}
LOG_DEBUG("target resumed");
return ERROR_OK;
}
static int xscale_step_inner(struct target *target, int current,
uint32_t address, int handle_breakpoints)
{
struct xscale_common *xscale = target_to_xscale(target);
struct arm *arm = &xscale->arm;
uint32_t next_pc;
int retval;
int i;
target->debug_reason = DBG_REASON_SINGLESTEP;
/* calculate PC of next instruction */
retval = arm_simulate_step(target, &next_pc);
if (retval != ERROR_OK) {
uint32_t current_opcode, current_pc;
current_pc = buf_get_u32(arm->pc->value, 0, 32);
target_read_u32(target, current_pc, ¤t_opcode);
LOG_ERROR(
"BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
current_opcode);
return retval;
}
LOG_DEBUG("enable single-step");
retval = xscale_enable_single_step(target, next_pc);
if (retval != ERROR_OK)
return retval;
/* restore banked registers */
retval = xscale_restore_banked(target);
if (retval != ERROR_OK)
return retval;
/* send resume request (command 0x30 or 0x31)
* clean the trace buffer if it is to be enabled (0x62) */
if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
retval = xscale_send_u32(target, 0x62);
if (retval != ERROR_OK)
return retval;
retval = xscale_send_u32(target, 0x31);
if (retval != ERROR_OK)
return retval;
} else {
retval = xscale_send_u32(target, 0x30);
if (retval != ERROR_OK)
return retval;
}
/* send CPSR */
retval = xscale_send_u32(target,
buf_get_u32(arm->cpsr->value, 0, 32));
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
buf_get_u32(arm->cpsr->value, 0, 32));
for (i = 7; i >= 0; i--) {
/* send register */
retval = xscale_send_u32(target,
buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i,
buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
}
/* send PC */
retval = xscale_send_u32(target,
buf_get_u32(arm->pc->value, 0, 32));
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
buf_get_u32(arm->pc->value, 0, 32));
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
/* registers are now invalid */
register_cache_invalidate(arm->core_cache);
/* wait for and process debug entry */
retval = xscale_debug_entry(target);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("disable single-step");
retval = xscale_disable_single_step(target);
if (retval != ERROR_OK)
return retval;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
return ERROR_OK;
}
static int xscale_step(struct target *target, int current,
target_addr_t address, int handle_breakpoints)
{
struct arm *arm = target_to_arm(target);
struct breakpoint *breakpoint = NULL;
uint32_t current_pc;
int retval;
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
buf_set_u32(arm->pc->value, 0, 32, address);
current_pc = buf_get_u32(arm->pc->value, 0, 32);
/* if we're at the reset vector, we have to simulate the step */
if (current_pc == 0x0) {
retval = arm_simulate_step(target, NULL);
if (retval != ERROR_OK)
return retval;
current_pc = buf_get_u32(arm->pc->value, 0, 32);
LOG_DEBUG("current pc %" PRIx32, current_pc);
target->debug_reason = DBG_REASON_SINGLESTEP;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
return ERROR_OK;
}
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
breakpoint = breakpoint_find(target,
buf_get_u32(arm->pc->value, 0, 32));
if (breakpoint) {
retval = xscale_unset_breakpoint(target, breakpoint);
if (retval != ERROR_OK)
return retval;
}
retval = xscale_step_inner(target, current, address, handle_breakpoints);
if (retval != ERROR_OK)
return retval;
if (breakpoint)
xscale_set_breakpoint(target, breakpoint);
LOG_DEBUG("target stepped");
return ERROR_OK;
}
static int xscale_assert_reset(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
/* TODO: apply hw reset signal in not examined state */
if (!(target_was_examined(target))) {
LOG_WARNING("Reset is not asserted because the target is not examined.");
LOG_WARNING("Use a reset button or power cycle the target.");
return ERROR_TARGET_NOT_EXAMINED;
}
LOG_DEBUG("target->state: %s",
target_state_name(target));
/* assert reset */
jtag_add_reset(0, 1);
/* sleep 1ms, to be sure we fulfill any requirements */
jtag_add_sleep(1000);
jtag_execute_queue();
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG
*/
xscale_jtag_set_instr(target->tap,
XSCALE_SELDCSR << xscale->xscale_variant,
TAP_IDLE);
/* set Hold reset, Halt mode and Trap Reset */
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
xscale_write_dcsr(target, 1, 0);
/* select BYPASS, because having DCSR selected caused problems on the PXA27x */
xscale_jtag_set_instr(target->tap, ~0, TAP_IDLE);
jtag_execute_queue();
target->state = TARGET_RESET;
if (target->reset_halt) {
int retval = target_halt(target);
if (retval != ERROR_OK)
return retval;
}
return ERROR_OK;
}
static int xscale_deassert_reset(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
struct breakpoint *breakpoint = target->breakpoints;
LOG_DEBUG("-");
xscale->ibcr_available = 2;
xscale->ibcr0_used = 0;
xscale->ibcr1_used = 0;
xscale->dbr_available = 2;
xscale->dbr0_used = 0;
xscale->dbr1_used = 0;
/* mark all hardware breakpoints as unset */
while (breakpoint) {
if (breakpoint->type == BKPT_HARD)
breakpoint->is_set = false;
breakpoint = breakpoint->next;
}
xscale->trace.mode = XSCALE_TRACE_DISABLED;
xscale_free_trace_data(xscale);
register_cache_invalidate(xscale->arm.core_cache);
/* FIXME mark hardware watchpoints got unset too. Also,
* at least some of the XScale registers are invalid...
*/
/*
* REVISIT: *assumes* we had a SRST+TRST reset so the mini-icache
* contents got invalidated. Safer to force that, so writing new
* contents can't ever fail..
*/
{
uint32_t address;
unsigned buf_cnt;
const uint8_t *buffer = xscale_debug_handler;
int retval;
/* release SRST */
jtag_add_reset(0, 0);
/* wait 300ms; 150 and 100ms were not enough */
jtag_add_sleep(300*1000);
jtag_add_runtest(2030, TAP_IDLE);
jtag_execute_queue();
/* set Hold reset, Halt mode and Trap Reset */
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
xscale_write_dcsr(target, 1, 0);
/* Load the debug handler into the mini-icache. Since
* it's using halt mode (not monitor mode), it runs in
* "Special Debug State" for access to registers, memory,
* coprocessors, trace data, etc.
*/
address = xscale->handler_address;
for (unsigned binary_size = sizeof(xscale_debug_handler);
binary_size > 0;
binary_size -= buf_cnt, buffer += buf_cnt) {
uint32_t cache_line[8];
unsigned i;
buf_cnt = binary_size;
if (buf_cnt > 32)
buf_cnt = 32;
for (i = 0; i < buf_cnt; i += 4) {
/* convert LE buffer to host-endian uint32_t */
cache_line[i / 4] = le_to_h_u32(&buffer[i]);
}
for (; i < 32; i += 4)
cache_line[i / 4] = 0xe1a08008;
/* only load addresses other than the reset vectors */
if ((address % 0x400) != 0x0) {
retval = xscale_load_ic(target, address,
cache_line);
if (retval != ERROR_OK)
return retval;
}
address += buf_cnt;
}
retval = xscale_load_ic(target, 0x0,
xscale->low_vectors);
if (retval != ERROR_OK)
return retval;
retval = xscale_load_ic(target, 0xffff0000,
xscale->high_vectors);
if (retval != ERROR_OK)
return retval;
jtag_add_runtest(30, TAP_IDLE);
jtag_add_sleep(100000);
/* set Hold reset, Halt mode and Trap Reset */
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
xscale_write_dcsr(target, 1, 0);
/* clear Hold reset to let the target run (should enter debug handler) */
xscale_write_dcsr(target, 0, 1);
target->state = TARGET_RUNNING;
if (!target->reset_halt) {
jtag_add_sleep(10000);
/* we should have entered debug now */
xscale_debug_entry(target);
target->state = TARGET_HALTED;
/* resume the target */
xscale_resume(target, 1, 0x0, 1, 0);
}
}
return ERROR_OK;
}
static int xscale_read_core_reg(struct target *target, struct reg *r,
int num, enum arm_mode mode)
{
/** \todo add debug handler support for core register reads */
LOG_ERROR("not implemented");
return ERROR_OK;
}
static int xscale_write_core_reg(struct target *target, struct reg *r,
int num, enum arm_mode mode, uint8_t *value)
{
/** \todo add debug handler support for core register writes */
LOG_ERROR("not implemented");
return ERROR_OK;
}
static int xscale_full_context(struct target *target)
{
struct arm *arm = target_to_arm(target);
uint32_t *buffer;
int i, j;
LOG_DEBUG("-");
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
buffer = malloc(4 * 8);
/* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
* we can't enter User mode on an XScale (unpredictable),
* but User shares registers with SYS
*/
for (i = 1; i < 7; i++) {
enum arm_mode mode = armv4_5_number_to_mode(i);
bool valid = true;
struct reg *r;
if (mode == ARM_MODE_USR)
continue;
/* check if there are invalid registers in the current mode
*/
for (j = 0; valid && j <= 16; j++) {
if (!ARMV4_5_CORE_REG_MODE(arm->core_cache,
mode, j).valid)
valid = false;
}
if (valid)
continue;
/* request banked registers */
xscale_send_u32(target, 0x0);
/* send CPSR for desired bank mode */
xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
/* get banked registers: r8 to r14; and SPSR
* except in USR/SYS mode
*/
if (mode != ARM_MODE_SYS) {
/* SPSR */
r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
mode, 16);
xscale_receive(target, buffer, 8);
buf_set_u32(r->value, 0, 32, buffer[7]);
r->dirty = false;
r->valid = true;
} else
xscale_receive(target, buffer, 7);
/* move data from buffer to register cache */
for (j = 8; j <= 14; j++) {
r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
mode, j);
buf_set_u32(r->value, 0, 32, buffer[j - 8]);
r->dirty = false;
r->valid = true;
}
}
free(buffer);
return ERROR_OK;
}
static int xscale_restore_banked(struct target *target)
{
struct arm *arm = target_to_arm(target);
int i, j;
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
/* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
* and check if any banked registers need to be written. Ignore
* USR mode (number 0) in favor of SYS; we can't enter User mode on
* an XScale (unpredictable), but they share all registers.
*/
for (i = 1; i < 7; i++) {
enum arm_mode mode = armv4_5_number_to_mode(i);
struct reg *r;
if (mode == ARM_MODE_USR)
continue;
/* check if there are dirty registers in this mode */
for (j = 8; j <= 14; j++) {
if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
mode, j).dirty)
goto dirty;
}
/* if not USR/SYS, check if the SPSR needs to be written */
if (mode != ARM_MODE_SYS) {
if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
mode, 16).dirty)
goto dirty;
}
/* there's nothing to flush for this mode */
continue;
dirty:
/* command 0x1: "send banked registers" */
xscale_send_u32(target, 0x1);
/* send CPSR for desired mode */
xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
/* send r8 to r14/lr ... only FIQ needs more than r13..r14,
* but this protocol doesn't understand that nuance.
*/
for (j = 8; j <= 14; j++) {
r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
mode, j);
xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
r->dirty = false;
}
/* send spsr if not in USR/SYS mode */
if (mode != ARM_MODE_SYS) {
r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
mode, 16);
xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
r->dirty = false;
}
}
return ERROR_OK;
}
static int xscale_read_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct xscale_common *xscale = target_to_xscale(target);
uint32_t *buf32;
uint32_t i;
int retval;
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address,
size,
count);
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
/* sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
return ERROR_COMMAND_SYNTAX_ERROR;
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory read request (command 0x1n, n: access size) */
retval = xscale_send_u32(target, 0x10 | size);
if (retval != ERROR_OK)
return retval;
/* send base address for read request */
retval = xscale_send_u32(target, address);
if (retval != ERROR_OK)
return retval;
/* send number of requested data words */
retval = xscale_send_u32(target, count);
if (retval != ERROR_OK)
return retval;
/* receive data from target (count times 32-bit words in host endianness) */
buf32 = malloc(4 * count);
retval = xscale_receive(target, buf32, count);
if (retval != ERROR_OK) {
free(buf32);
return retval;
}
/* extract data from host-endian buffer into byte stream */
for (i = 0; i < count; i++) {
switch (size) {
case 4:
target_buffer_set_u32(target, buffer, buf32[i]);
buffer += 4;
break;
case 2:
target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
buffer += 2;
break;
case 1:
*buffer++ = buf32[i] & 0xff;
break;
default:
LOG_ERROR("invalid read size");
return ERROR_COMMAND_SYNTAX_ERROR;
}
}
free(buf32);
/* examine DCSR, to see if Sticky Abort (SA) got set */
retval = xscale_read_dcsr(target);
if (retval != ERROR_OK)
return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) {
/* clear SA bit */
retval = xscale_send_u32(target, 0x60);
if (retval != ERROR_OK)
return retval;
return ERROR_TARGET_DATA_ABORT;
}
return ERROR_OK;
}
static int xscale_read_phys_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct xscale_common *xscale = target_to_xscale(target);
/* with MMU inactive, there are only physical addresses */
if (!xscale->armv4_5_mmu.mmu_enabled)
return xscale_read_memory(target, address, size, count, buffer);
/** \todo: provide a non-stub implementation of this routine. */
LOG_ERROR("%s: %s is not implemented. Disable MMU?",
target_name(target), __func__);
return ERROR_FAIL;
}
static int xscale_write_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct xscale_common *xscale = target_to_xscale(target);
int retval;
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address,
size,
count);
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
/* sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
return ERROR_COMMAND_SYNTAX_ERROR;
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory write request (command 0x2n, n: access size) */
retval = xscale_send_u32(target, 0x20 | size);
if (retval != ERROR_OK)
return retval;
/* send base address for read request */
retval = xscale_send_u32(target, address);
if (retval != ERROR_OK)
return retval;
/* send number of requested data words to be written*/
retval = xscale_send_u32(target, count);
if (retval != ERROR_OK)
return retval;
/* extract data from host-endian buffer into byte stream */
#if 0
for (i = 0; i < count; i++) {
switch (size) {
case 4:
value = target_buffer_get_u32(target, buffer);
xscale_send_u32(target, value);
buffer += 4;
break;
case 2:
value = target_buffer_get_u16(target, buffer);
xscale_send_u32(target, value);
buffer += 2;
break;
case 1:
value = *buffer;
xscale_send_u32(target, value);
buffer += 1;
break;
default:
LOG_ERROR("should never get here");
exit(-1);
}
}
#endif
retval = xscale_send(target, buffer, count, size);
if (retval != ERROR_OK)
return retval;
/* examine DCSR, to see if Sticky Abort (SA) got set */
retval = xscale_read_dcsr(target);
if (retval != ERROR_OK)
return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) {
/* clear SA bit */
retval = xscale_send_u32(target, 0x60);
if (retval != ERROR_OK)
return retval;
LOG_ERROR("data abort writing memory");
return ERROR_TARGET_DATA_ABORT;
}
return ERROR_OK;
}
static int xscale_write_phys_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct xscale_common *xscale = target_to_xscale(target);
/* with MMU inactive, there are only physical addresses */
if (!xscale->armv4_5_mmu.mmu_enabled)
return xscale_write_memory(target, address, size, count, buffer);
/** \todo: provide a non-stub implementation of this routine. */
LOG_ERROR("%s: %s is not implemented. Disable MMU?",
target_name(target), __func__);
return ERROR_FAIL;
}
static int xscale_get_ttb(struct target *target, uint32_t *result)
{
struct xscale_common *xscale = target_to_xscale(target);
uint32_t ttb;
int retval;
retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
if (retval != ERROR_OK)
return retval;
ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
*result = ttb;
return ERROR_OK;
}
static int xscale_disable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache)
{
struct xscale_common *xscale = target_to_xscale(target);
uint32_t cp15_control;
int retval;
/* read cp15 control register */
retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
if (retval != ERROR_OK)
return retval;
cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
if (mmu)
cp15_control &= ~0x1U;
if (d_u_cache) {
/* clean DCache */
retval = xscale_send_u32(target, 0x50);
if (retval != ERROR_OK)
return retval;
retval = xscale_send_u32(target, xscale->cache_clean_address);
if (retval != ERROR_OK)
return retval;
/* invalidate DCache */
retval = xscale_send_u32(target, 0x51);
if (retval != ERROR_OK)
return retval;
cp15_control &= ~0x4U;
}
if (i_cache) {
/* invalidate ICache */
retval = xscale_send_u32(target, 0x52);
if (retval != ERROR_OK)
return retval;
cp15_control &= ~0x1000U;
}
/* write new cp15 control register */
retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
if (retval != ERROR_OK)
return retval;
/* execute cpwait to ensure outstanding operations complete */
retval = xscale_send_u32(target, 0x53);
return retval;
}
static int xscale_enable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache)
{
struct xscale_common *xscale = target_to_xscale(target);
uint32_t cp15_control;
int retval;
/* read cp15 control register */
retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
if (retval != ERROR_OK)
return retval;
cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
if (mmu)
cp15_control |= 0x1U;
if (d_u_cache)
cp15_control |= 0x4U;
if (i_cache)
cp15_control |= 0x1000U;
/* write new cp15 control register */
retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
if (retval != ERROR_OK)
return retval;
/* execute cpwait to ensure outstanding operations complete */
retval = xscale_send_u32(target, 0x53);
return retval;
}
static int xscale_set_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
int retval;
struct xscale_common *xscale = target_to_xscale(target);
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (breakpoint->is_set) {
LOG_WARNING("breakpoint already set");
return ERROR_OK;
}
if (breakpoint->type == BKPT_HARD) {
uint32_t value = breakpoint->address | 1;
if (!xscale->ibcr0_used) {
xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
xscale->ibcr0_used = 1;
/* breakpoint set on first breakpoint register */
breakpoint_hw_set(breakpoint, 0);
} else if (!xscale->ibcr1_used) {
xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
xscale->ibcr1_used = 1;
/* breakpoint set on second breakpoint register */
breakpoint_hw_set(breakpoint, 1);
} else {/* bug: availability previously verified in xscale_add_breakpoint() */
LOG_ERROR("BUG: no hardware comparator available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
} else if (breakpoint->type == BKPT_SOFT) {
if (breakpoint->length == 4) {
/* keep the original instruction in target endianness */
retval = target_read_memory(target, breakpoint->address, 4, 1,
breakpoint->orig_instr);
if (retval != ERROR_OK)
return retval;
/* write the bkpt instruction in target endianness
*(arm7_9->arm_bkpt is host endian) */
retval = target_write_u32(target, breakpoint->address,
xscale->arm_bkpt);
if (retval != ERROR_OK)
return retval;
} else {
/* keep the original instruction in target endianness */
retval = target_read_memory(target, breakpoint->address, 2, 1,
breakpoint->orig_instr);
if (retval != ERROR_OK)
return retval;
/* write the bkpt instruction in target endianness
*(arm7_9->arm_bkpt is host endian) */
retval = target_write_u16(target, breakpoint->address,
xscale->thumb_bkpt);
if (retval != ERROR_OK)
return retval;
}
breakpoint->is_set = true;
xscale_send_u32(target, 0x50); /* clean dcache */
xscale_send_u32(target, xscale->cache_clean_address);
xscale_send_u32(target, 0x51); /* invalidate dcache */
xscale_send_u32(target, 0x52); /* invalidate icache and flush fetch buffers */
}
return ERROR_OK;
}
static int xscale_add_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
struct xscale_common *xscale = target_to_xscale(target);
if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1)) {
LOG_ERROR("no breakpoint unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if ((breakpoint->length != 2) && (breakpoint->length != 4)) {
LOG_ERROR("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (breakpoint->type == BKPT_HARD)
xscale->ibcr_available--;
return xscale_set_breakpoint(target, breakpoint);
}
static int xscale_unset_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
int retval;
struct xscale_common *xscale = target_to_xscale(target);
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (!breakpoint->is_set) {
LOG_WARNING("breakpoint not set");
return ERROR_OK;
}
if (breakpoint->type == BKPT_HARD) {
if (breakpoint->number == 0) {
xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
xscale->ibcr0_used = 0;
} else if (breakpoint->number == 1) {
xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
xscale->ibcr1_used = 0;
}
breakpoint->is_set = false;
} else {
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4) {
retval = target_write_memory(target, breakpoint->address, 4, 1,
breakpoint->orig_instr);
if (retval != ERROR_OK)
return retval;
} else {
retval = target_write_memory(target, breakpoint->address, 2, 1,
breakpoint->orig_instr);
if (retval != ERROR_OK)
return retval;
}
breakpoint->is_set = false;
xscale_send_u32(target, 0x50); /* clean dcache */
xscale_send_u32(target, xscale->cache_clean_address);
xscale_send_u32(target, 0x51); /* invalidate dcache */
xscale_send_u32(target, 0x52); /* invalidate icache and flush fetch buffers */
}
return ERROR_OK;
}
static int xscale_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct xscale_common *xscale = target_to_xscale(target);
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (breakpoint->is_set)
xscale_unset_breakpoint(target, breakpoint);
if (breakpoint->type == BKPT_HARD)
xscale->ibcr_available++;
return ERROR_OK;
}
static int xscale_set_watchpoint(struct target *target,
struct watchpoint *watchpoint)
{
struct xscale_common *xscale = target_to_xscale(target);
uint32_t enable = 0;
struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
switch (watchpoint->rw) {
case WPT_READ:
enable = 0x3;
break;
case WPT_ACCESS:
enable = 0x2;
break;
case WPT_WRITE:
enable = 0x1;
break;
default:
LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
}
/* For watchpoint across more than one word, both DBR registers must
be enlisted, with the second used as a mask. */
if (watchpoint->length > 4) {
if (xscale->dbr0_used || xscale->dbr1_used) {
LOG_ERROR("BUG: sufficient hardware comparators unavailable");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
/* Write mask value to DBR1, based on the length argument.
* Address bits ignored by the comparator are those set in mask. */
xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1],
watchpoint->length - 1);
xscale->dbr1_used = 1;
enable |= 0x100; /* DBCON[M] */
}
if (!xscale->dbr0_used) {
xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
dbcon_value |= enable;
xscale_set_reg_u32(dbcon, dbcon_value);
watchpoint_set(watchpoint, 0);
xscale->dbr0_used = 1;
} else if (!xscale->dbr1_used) {
xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
dbcon_value |= enable << 2;
xscale_set_reg_u32(dbcon, dbcon_value);
watchpoint_set(watchpoint, 1);
xscale->dbr1_used = 1;
} else {
LOG_ERROR("BUG: no hardware comparator available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
return ERROR_OK;
}
static int xscale_add_watchpoint(struct target *target,
struct watchpoint *watchpoint)
{
struct xscale_common *xscale = target_to_xscale(target);
if (xscale->dbr_available < 1) {
LOG_ERROR("no more watchpoint registers available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (watchpoint->mask != WATCHPOINT_IGNORE_DATA_VALUE_MASK)
LOG_WARNING("xscale does not support value, mask arguments; ignoring");
/* check that length is a power of two */
for (uint32_t len = watchpoint->length; len != 1; len /= 2) {
if (len % 2) {
LOG_ERROR("xscale requires that watchpoint length is a power of two");
return ERROR_COMMAND_ARGUMENT_INVALID;
}
}
if (watchpoint->length == 4) { /* single word watchpoint */
xscale->dbr_available--;/* one DBR reg used */
return ERROR_OK;
}
/* watchpoints across multiple words require both DBR registers */
if (xscale->dbr_available < 2) {
LOG_ERROR("insufficient watchpoint registers available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (watchpoint->length > watchpoint->address) {
LOG_ERROR("xscale does not support watchpoints with length "
"greater than address");
return ERROR_COMMAND_ARGUMENT_INVALID;
}
xscale->dbr_available = 0;
return ERROR_OK;
}
static int xscale_unset_watchpoint(struct target *target,
struct watchpoint *watchpoint)
{
struct xscale_common *xscale = target_to_xscale(target);
struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (!watchpoint->is_set) {
LOG_WARNING("breakpoint not set");
return ERROR_OK;
}
if (watchpoint->number == 0) {
if (watchpoint->length > 4) {
dbcon_value &= ~0x103; /* clear DBCON[M] as well */
xscale->dbr1_used = 0; /* DBR1 was used for mask */
} else
dbcon_value &= ~0x3;
xscale_set_reg_u32(dbcon, dbcon_value);
xscale->dbr0_used = 0;
} else if (watchpoint->number == 1) {
dbcon_value &= ~0xc;
xscale_set_reg_u32(dbcon, dbcon_value);
xscale->dbr1_used = 0;
}
watchpoint->is_set = false;
return ERROR_OK;
}
static int xscale_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
struct xscale_common *xscale = target_to_xscale(target);
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (watchpoint->is_set)
xscale_unset_watchpoint(target, watchpoint);
if (watchpoint->length > 4)
xscale->dbr_available++;/* both DBR regs now available */
xscale->dbr_available++;
return ERROR_OK;
}
static int xscale_get_reg(struct reg *reg)
{
struct xscale_reg *arch_info = reg->arch_info;
struct target *target = arch_info->target;
struct xscale_common *xscale = target_to_xscale(target);
/* DCSR, TX and RX are accessible via JTAG */
if (strcmp(reg->name, "XSCALE_DCSR") == 0)
return xscale_read_dcsr(arch_info->target);
else if (strcmp(reg->name, "XSCALE_TX") == 0) {
/* 1 = consume register content */
return xscale_read_tx(arch_info->target, 1);
} else if (strcmp(reg->name, "XSCALE_RX") == 0) {
/* can't read from RX register (host -> debug handler) */
return ERROR_OK;
} else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) {
/* can't (explicitly) read from TXRXCTRL register */
return ERROR_OK;
} else {/* Other DBG registers have to be transferred by the debug handler
* send CP read request (command 0x40) */
xscale_send_u32(target, 0x40);
/* send CP register number */
xscale_send_u32(target, arch_info->dbg_handler_number);
/* read register value */
xscale_read_tx(target, 1);
buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
reg->dirty = false;
reg->valid = true;
}
return ERROR_OK;
}
static int xscale_set_reg(struct reg *reg, uint8_t *buf)
{
struct xscale_reg *arch_info = reg->arch_info;
struct target *target = arch_info->target;
struct xscale_common *xscale = target_to_xscale(target);
uint32_t value = buf_get_u32(buf, 0, 32);
/* DCSR, TX and RX are accessible via JTAG */
if (strcmp(reg->name, "XSCALE_DCSR") == 0) {
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
return xscale_write_dcsr(arch_info->target, -1, -1);
} else if (strcmp(reg->name, "XSCALE_RX") == 0) {
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
return xscale_write_rx(arch_info->target);
} else if (strcmp(reg->name, "XSCALE_TX") == 0) {
/* can't write to TX register (debug-handler -> host) */
return ERROR_OK;
} else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) {
/* can't (explicitly) write to TXRXCTRL register */
return ERROR_OK;
} else {/* Other DBG registers have to be transferred by the debug handler
* send CP write request (command 0x41) */
xscale_send_u32(target, 0x41);
/* send CP register number */
xscale_send_u32(target, arch_info->dbg_handler_number);
/* send CP register value */
xscale_send_u32(target, value);
buf_set_u32(reg->value, 0, 32, value);
}
return ERROR_OK;
}
static int xscale_write_dcsr_sw(struct target *target, uint32_t value)
{
struct xscale_common *xscale = target_to_xscale(target);
struct reg *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
struct xscale_reg *dcsr_arch_info = dcsr->arch_info;
/* send CP write request (command 0x41) */
xscale_send_u32(target, 0x41);
/* send CP register number */
xscale_send_u32(target, dcsr_arch_info->dbg_handler_number);
/* send CP register value */
xscale_send_u32(target, value);
buf_set_u32(dcsr->value, 0, 32, value);
return ERROR_OK;
}
static int xscale_read_trace(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
struct arm *arm = &xscale->arm;
struct xscale_trace_data **trace_data_p;
/* 258 words from debug handler
* 256 trace buffer entries
* 2 checkpoint addresses
*/
uint32_t trace_buffer[258];
int is_address[256];
int i, j;
unsigned int num_checkpoints = 0;
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "must be stopped to read trace data");
return ERROR_TARGET_NOT_HALTED;
}
/* send read trace buffer command (command 0x61) */
xscale_send_u32(target, 0x61);
/* receive trace buffer content */
xscale_receive(target, trace_buffer, 258);
/* parse buffer backwards to identify address entries */
for (i = 255; i >= 0; i--) {
/* also count number of checkpointed entries */
if ((trace_buffer[i] & 0xe0) == 0xc0)
num_checkpoints++;
is_address[i] = 0;
if (((trace_buffer[i] & 0xf0) == 0x90) ||
((trace_buffer[i] & 0xf0) == 0xd0)) {
if (i > 0)
is_address[--i] = 1;
if (i > 0)
is_address[--i] = 1;
if (i > 0)
is_address[--i] = 1;
if (i > 0)
is_address[--i] = 1;
}
}
/* search first non-zero entry that is not part of an address */
for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++)
;
if (j == 256) {
LOG_DEBUG("no trace data collected");
return ERROR_XSCALE_NO_TRACE_DATA;
}
/* account for possible partial address at buffer start (wrap mode only) */
if (is_address[0]) { /* first entry is address; complete set of 4? */
i = 1;
while (i < 4)
if (!is_address[i++])
break;
if (i < 4)
j += i; /* partial address; can't use it */
}
/* if first valid entry is indirect branch, can't use that either (no address) */
if (((trace_buffer[j] & 0xf0) == 0x90) || ((trace_buffer[j] & 0xf0) == 0xd0))
j++;
/* walk linked list to terminating entry */
for (trace_data_p = &xscale->trace.data; *trace_data_p;
trace_data_p = &(*trace_data_p)->next)
;
*trace_data_p = malloc(sizeof(struct xscale_trace_data));
(*trace_data_p)->next = NULL;
(*trace_data_p)->chkpt0 = trace_buffer[256];
(*trace_data_p)->chkpt1 = trace_buffer[257];
(*trace_data_p)->last_instruction = buf_get_u32(arm->pc->value, 0, 32);
(*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j));
(*trace_data_p)->depth = 256 - j;
(*trace_data_p)->num_checkpoints = num_checkpoints;
for (i = j; i < 256; i++) {
(*trace_data_p)->entries[i - j].data = trace_buffer[i];
if (is_address[i])
(*trace_data_p)->entries[i - j].type = XSCALE_TRACE_ADDRESS;
else
(*trace_data_p)->entries[i - j].type = XSCALE_TRACE_MESSAGE;
}
return ERROR_OK;
}
static int xscale_read_instruction(struct target *target, uint32_t pc,
struct arm_instruction *instruction)
{
struct xscale_common *const xscale = target_to_xscale(target);
int section = -1;
size_t size_read;
uint32_t opcode;
int retval;
if (!xscale->trace.image)
return ERROR_TRACE_IMAGE_UNAVAILABLE;
/* search for the section the current instruction belongs to */
for (unsigned int i = 0; i < xscale->trace.image->num_sections; i++) {
if ((xscale->trace.image->sections[i].base_address <= pc) &&
(xscale->trace.image->sections[i].base_address +
xscale->trace.image->sections[i].size > pc)) {
section = i;
break;
}
}
if (section == -1) {
/* current instruction couldn't be found in the image */
return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
}
if (xscale->trace.core_state == ARM_STATE_ARM) {
uint8_t buf[4];
retval = image_read_section(xscale->trace.image, section,
pc - xscale->trace.image->sections[section].base_address,
4, buf, &size_read);
if (retval != ERROR_OK) {
LOG_ERROR("error while reading instruction");
return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
}
opcode = target_buffer_get_u32(target, buf);
arm_evaluate_opcode(opcode, pc, instruction);
} else if (xscale->trace.core_state == ARM_STATE_THUMB) {
uint8_t buf[2];
retval = image_read_section(xscale->trace.image, section,
pc - xscale->trace.image->sections[section].base_address,
2, buf, &size_read);
if (retval != ERROR_OK) {
LOG_ERROR("error while reading instruction");
return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
}
opcode = target_buffer_get_u16(target, buf);
thumb_evaluate_opcode(opcode, pc, instruction);
} else {
LOG_ERROR("BUG: unknown core state encountered");
exit(-1);
}
return ERROR_OK;
}
/* Extract address encoded into trace data.
* Write result to address referenced by argument 'target', or 0 if incomplete. */
static inline void xscale_branch_address(struct xscale_trace_data *trace_data,
int i, uint32_t *target)
{
/* if there are less than four entries prior to the indirect branch message
* we can't extract the address */
if (i < 4)
*target = 0;
else {
*target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) |
(trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24);
}
}
static inline void xscale_display_instruction(struct target *target, uint32_t pc,
struct arm_instruction *instruction,
struct command_invocation *cmd)
{
int retval = xscale_read_instruction(target, pc, instruction);
if (retval == ERROR_OK)
command_print(cmd, "%s", instruction->text);
else
command_print(cmd, "0x%8.8" PRIx32 "\t<not found in image>", pc);
}
static int xscale_analyze_trace(struct target *target, struct command_invocation *cmd)
{
struct xscale_common *xscale = target_to_xscale(target);
struct xscale_trace_data *trace_data = xscale->trace.data;
int i, retval;
uint32_t breakpoint_pc = 0;
struct arm_instruction instruction;
uint32_t current_pc = 0;/* initialized when address determined */
if (!xscale->trace.image)
LOG_WARNING("No trace image loaded; use 'xscale trace_image'");
/* loop for each trace buffer that was loaded from target */
while (trace_data) {
int chkpt = 0; /* incremented as checkpointed entries found */
int j;
/* FIXME: set this to correct mode when trace buffer is first enabled */
xscale->trace.core_state = ARM_STATE_ARM;
/* loop for each entry in this trace buffer */
for (i = 0; i < trace_data->depth; i++) {
int exception = 0;
uint32_t chkpt_reg = 0x0;
uint32_t branch_target = 0;
int count;
/* trace entry type is upper nybble of 'message byte' */
int trace_msg_type = (trace_data->entries[i].data & 0xf0) >> 4;
/* Target addresses of indirect branches are written into buffer
* before the message byte representing the branch. Skip past it */
if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS)
continue;
switch (trace_msg_type) {
case 0: /* Exceptions */
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
exception = (trace_data->entries[i].data & 0x70) >> 4;
/* FIXME: vector table may be at ffff0000 */
branch_target = (trace_data->entries[i].data & 0xf0) >> 2;
break;
case 8: /* Direct Branch */
break;
case 9: /* Indirect Branch */
xscale_branch_address(trace_data, i, &branch_target);
break;
case 13: /* Checkpointed Indirect Branch */
xscale_branch_address(trace_data, i, &branch_target);
if ((trace_data->num_checkpoints == 2) && (chkpt == 0))
chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is
*oldest */
else
chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and
*newest */
chkpt++;
break;
case 12: /* Checkpointed Direct Branch */
if ((trace_data->num_checkpoints == 2) && (chkpt == 0))
chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is
*oldest */
else
chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and
*newest */
/* if no current_pc, checkpoint will be starting point */
if (current_pc == 0)
branch_target = chkpt_reg;
chkpt++;
break;
case 15:/* Roll-over */
break;
default:/* Reserved */
LOG_WARNING("trace is suspect: invalid trace message byte");
continue;
}
/* If we don't have the current_pc yet, but we did get the branch target
* (either from the trace buffer on indirect branch, or from a checkpoint reg),
* then we can start displaying instructions at the next iteration, with
* branch_target as the starting point.
*/
if (current_pc == 0) {
current_pc = branch_target; /* remains 0 unless branch_target *obtained */
continue;
}
/* We have current_pc. Read and display the instructions from the image.
* First, display count instructions (lower nybble of message byte). */
count = trace_data->entries[i].data & 0x0f;
for (j = 0; j < count; j++) {
xscale_display_instruction(target, current_pc, &instruction,
cmd);
current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
}
/* An additional instruction is implicitly added to count for
* rollover and some exceptions: undef, swi, prefetch abort. */
if ((trace_msg_type == 15) || (exception > 0 && exception < 4)) {
xscale_display_instruction(target, current_pc, &instruction,
cmd);
current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
}
if (trace_msg_type == 15) /* rollover */
continue;
if (exception) {
command_print(cmd, "--- exception %i ---", exception);
continue;
}
/* not exception or rollover; next instruction is a branch and is
* not included in the count */
xscale_display_instruction(target, current_pc, &instruction, cmd);
/* for direct branches, extract branch destination from instruction */
if ((trace_msg_type == 8) || (trace_msg_type == 12)) {
retval = xscale_read_instruction(target, current_pc, &instruction);
if (retval == ERROR_OK)
current_pc = instruction.info.b_bl_bx_blx.target_address;
else
current_pc = 0; /* branch destination unknown */
/* direct branch w/ checkpoint; can also get from checkpoint reg */
if (trace_msg_type == 12) {
if (current_pc == 0)
current_pc = chkpt_reg;
else if (current_pc != chkpt_reg) /* sanity check */
LOG_WARNING("trace is suspect: checkpoint register "
"inconsistent with address from image");
}
if (current_pc == 0)
command_print(cmd, "address unknown");
continue;
}
/* indirect branch; the branch destination was read from trace buffer */
if ((trace_msg_type == 9) || (trace_msg_type == 13)) {
current_pc = branch_target;
/* sanity check (checkpoint reg is redundant) */
if ((trace_msg_type == 13) && (chkpt_reg != branch_target))
LOG_WARNING("trace is suspect: checkpoint register "
"inconsistent with address from trace buffer");
}
} /* END: for (i = 0; i < trace_data->depth; i++) */
breakpoint_pc = trace_data->last_instruction; /* used below */
trace_data = trace_data->next;
} /* END: while (trace_data) */
/* Finally... display all instructions up to the value of the pc when the
* debug break occurred (saved when trace data was collected from target).
* This is necessary because the trace only records execution branches and 16
* consecutive instructions (rollovers), so last few typically missed.
*/
if (current_pc == 0)
return ERROR_OK;/* current_pc was never found */
/* how many instructions remaining? */
int gap_count = (breakpoint_pc - current_pc) /
(xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2);
/* should never be negative or over 16, but verify */
if (gap_count < 0 || gap_count > 16) {
LOG_WARNING("trace is suspect: excessive gap at end of trace");
return ERROR_OK;/* bail; large number or negative value no good */
}
/* display remaining instructions */
for (i = 0; i < gap_count; i++) {
xscale_display_instruction(target, current_pc, &instruction, cmd);
current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
}
return ERROR_OK;
}
static const struct reg_arch_type xscale_reg_type = {
.get = xscale_get_reg,
.set = xscale_set_reg,
};
static void xscale_build_reg_cache(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
struct arm *arm = &xscale->arm;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
int i;
int num_regs = ARRAY_SIZE(xscale_reg_arch_info);
(*cache_p) = arm_build_reg_cache(target, arm);
(*cache_p)->next = malloc(sizeof(struct reg_cache));
cache_p = &(*cache_p)->next;
/* fill in values for the xscale reg cache */
(*cache_p)->name = "XScale registers";
(*cache_p)->next = NULL;
(*cache_p)->reg_list = calloc(num_regs, sizeof(struct reg));
(*cache_p)->num_regs = num_regs;
for (i = 0; i < num_regs; i++) {
(*cache_p)->reg_list[i].name = xscale_reg_list[i];
(*cache_p)->reg_list[i].value = calloc(4, 1);
(*cache_p)->reg_list[i].dirty = false;
(*cache_p)->reg_list[i].valid = false;
(*cache_p)->reg_list[i].size = 32;
(*cache_p)->reg_list[i].arch_info = &arch_info[i];
(*cache_p)->reg_list[i].type = &xscale_reg_type;
(*cache_p)->reg_list[i].exist = true;
arch_info[i] = xscale_reg_arch_info[i];
arch_info[i].target = target;
}
xscale->reg_cache = (*cache_p);
}
static void xscale_free_reg_cache(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
struct reg_cache *cache = xscale->reg_cache;
for (unsigned int i = 0; i < ARRAY_SIZE(xscale_reg_arch_info); i++)
free(cache->reg_list[i].value);
free(cache->reg_list[0].arch_info);
free(cache->reg_list);
free(cache);
arm_free_reg_cache(&xscale->arm);
}
static int xscale_init_target(struct command_context *cmd_ctx,
struct target *target)
{
xscale_build_reg_cache(target);
return ERROR_OK;
}
static void xscale_deinit_target(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
xscale_free_reg_cache(target);
free(xscale);
}
static int xscale_init_arch_info(struct target *target,
struct xscale_common *xscale, struct jtag_tap *tap)
{
struct arm *arm;
uint32_t high_reset_branch, low_reset_branch;
int i;
arm = &xscale->arm;
/* store architecture specific data */
xscale->common_magic = XSCALE_COMMON_MAGIC;
/* PXA3xx with 11 bit IR shifts the JTAG instructions */
if (tap->ir_length == 11)
xscale->xscale_variant = XSCALE_PXA3XX;
else
xscale->xscale_variant = XSCALE_IXP4XX_PXA2XX;
/* the debug handler isn't installed (and thus not running) at this time */
xscale->handler_address = 0xfe000800;
/* clear the vectors we keep locally for reference */
memset(xscale->low_vectors, 0, sizeof(xscale->low_vectors));
memset(xscale->high_vectors, 0, sizeof(xscale->high_vectors));
/* no user-specified vectors have been configured yet */
xscale->static_low_vectors_set = 0x0;
xscale->static_high_vectors_set = 0x0;
/* calculate branches to debug handler */
low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
for (i = 1; i <= 7; i++) {
xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
}
/* 64kB aligned region used for DCache cleaning */
xscale->cache_clean_address = 0xfffe0000;
xscale->hold_rst = 0;
xscale->external_debug_break = 0;
xscale->ibcr_available = 2;
xscale->ibcr0_used = 0;
xscale->ibcr1_used = 0;
xscale->dbr_available = 2;
xscale->dbr0_used = 0;
xscale->dbr1_used = 0;
LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints",
target_name(target));
xscale->arm_bkpt = ARMV5_BKPT(0x0);
xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
xscale->vector_catch = 0x1;
xscale->trace.data = NULL;
xscale->trace.image = NULL;
xscale->trace.mode = XSCALE_TRACE_DISABLED;
xscale->trace.buffer_fill = 0;
xscale->trace.fill_counter = 0;
/* prepare ARMv4/5 specific information */
arm->arch_info = xscale;
arm->core_type = ARM_CORE_TYPE_STD;
arm->read_core_reg = xscale_read_core_reg;
arm->write_core_reg = xscale_write_core_reg;
arm->full_context = xscale_full_context;
arm_init_arch_info(target, arm);
xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
xscale->armv4_5_mmu.read_memory = xscale_read_memory;
xscale->armv4_5_mmu.write_memory = xscale_write_memory;
xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
xscale->armv4_5_mmu.has_tiny_pages = 1;
xscale->armv4_5_mmu.mmu_enabled = 0;
return ERROR_OK;
}
static int xscale_target_create(struct target *target, Jim_Interp *interp)
{
struct xscale_common *xscale;
if (sizeof(xscale_debug_handler) > 0x800) {
LOG_ERROR("debug_handler.bin: larger than 2kb");
return ERROR_FAIL;
}
xscale = calloc(1, sizeof(*xscale));
if (!xscale)
return ERROR_FAIL;
return xscale_init_arch_info(target, xscale, target->tap);
}
COMMAND_HANDLER(xscale_handle_debug_handler_command)
{
struct target *target = NULL;
struct xscale_common *xscale;
int retval;
uint32_t handler_address;
if (CMD_ARGC < 2)
return ERROR_COMMAND_SYNTAX_ERROR;
target = get_target(CMD_ARGV[0]);
if (!target) {
LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
return ERROR_FAIL;
}
xscale = target_to_xscale(target);
retval = xscale_verify_pointer(CMD, xscale);
if (retval != ERROR_OK)
return retval;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], handler_address);
if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
xscale->handler_address = handler_address;
else {
LOG_ERROR(
"xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
return ERROR_FAIL;
}
return ERROR_OK;
}
COMMAND_HANDLER(xscale_handle_cache_clean_address_command)
{
struct target *target = NULL;
struct xscale_common *xscale;
int retval;
uint32_t cache_clean_address;
if (CMD_ARGC < 2)
return ERROR_COMMAND_SYNTAX_ERROR;
target = get_target(CMD_ARGV[0]);
if (!target) {
LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
return ERROR_FAIL;
}
xscale = target_to_xscale(target);
retval = xscale_verify_pointer(CMD, xscale);
if (retval != ERROR_OK)
return retval;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cache_clean_address);
if (cache_clean_address & 0xffff)
LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
else
xscale->cache_clean_address = cache_clean_address;
return ERROR_OK;
}
COMMAND_HANDLER(xscale_handle_cache_info_command)
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
int retval;
retval = xscale_verify_pointer(CMD, xscale);
if (retval != ERROR_OK)
return retval;
return armv4_5_handle_cache_info_command(CMD, &xscale->armv4_5_mmu.armv4_5_cache);
}
static int xscale_virt2phys(struct target *target,
target_addr_t virtual, target_addr_t *physical)
{
struct xscale_common *xscale = target_to_xscale(target);
uint32_t cb;
if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
LOG_ERROR(xscale_not);
return ERROR_TARGET_INVALID;
}
uint32_t ret;
int retval = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu,
virtual, &cb, &ret);
if (retval != ERROR_OK)
return retval;
*physical = ret;
return ERROR_OK;
}
static int xscale_mmu(struct target *target, int *enabled)
{
struct xscale_common *xscale = target_to_xscale(target);
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}
*enabled = xscale->armv4_5_mmu.mmu_enabled;
return ERROR_OK;
}
COMMAND_HANDLER(xscale_handle_mmu_command)
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
int retval;
retval = xscale_verify_pointer(CMD, xscale);
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED) {
command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_TARGET_NOT_HALTED;
}
if (CMD_ARGC >= 1) {
bool enable;
COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
if (enable)
xscale_enable_mmu_caches(target, 1, 0, 0);
else
xscale_disable_mmu_caches(target, 1, 0, 0);
xscale->armv4_5_mmu.mmu_enabled = enable;
}
command_print(CMD, "mmu %s",
(xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
return ERROR_OK;
}
COMMAND_HANDLER(xscale_handle_idcache_command)
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
int retval = xscale_verify_pointer(CMD, xscale);
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED) {
command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_TARGET_NOT_HALTED;
}
bool icache = false;
if (strcmp(CMD_NAME, "icache") == 0)
icache = true;
if (CMD_ARGC >= 1) {
bool enable;
COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
if (icache) {
xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
if (enable)
xscale_enable_mmu_caches(target, 0, 0, 1);
else
xscale_disable_mmu_caches(target, 0, 0, 1);
} else {
xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
if (enable)
xscale_enable_mmu_caches(target, 0, 1, 0);
else
xscale_disable_mmu_caches(target, 0, 1, 0);
}
}
bool enabled = icache ?
xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled :
xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled;
const char *msg = enabled ? "enabled" : "disabled";
command_print(CMD, "%s %s", CMD_NAME, msg);
return ERROR_OK;
}
static const struct {
char name[15];
unsigned mask;
} vec_ids[] = {
{ "fiq", DCSR_TF, },
{ "irq", DCSR_TI, },
{ "dabt", DCSR_TD, },
{ "pabt", DCSR_TA, },
{ "swi", DCSR_TS, },
{ "undef", DCSR_TU, },
{ "reset", DCSR_TR, },
};
COMMAND_HANDLER(xscale_handle_vector_catch_command)
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
int retval;
uint32_t dcsr_value;
uint32_t catch = 0;
struct reg *dcsr_reg = &xscale->reg_cache->reg_list[XSCALE_DCSR];
retval = xscale_verify_pointer(CMD, xscale);
if (retval != ERROR_OK)
return retval;
if (CMD_ARGC > 0) {
if (CMD_ARGC == 1) {
if (strcmp(CMD_ARGV[0], "all") == 0) {
catch = DCSR_TRAP_MASK;
CMD_ARGC--;
} else if (strcmp(CMD_ARGV[0], "none") == 0) {
catch = 0;
CMD_ARGC--;
}
}
while (CMD_ARGC-- > 0) {
unsigned i;
for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name))
continue;
catch |= vec_ids[i].mask;
break;
}
if (i == ARRAY_SIZE(vec_ids)) {
LOG_ERROR("No vector '%s'", CMD_ARGV[CMD_ARGC]);
return ERROR_COMMAND_SYNTAX_ERROR;
}
}
buf_set_u32(dcsr_reg->value, 0, 32,
(buf_get_u32(dcsr_reg->value, 0, 32) & ~DCSR_TRAP_MASK) | catch);
xscale_write_dcsr(target, -1, -1);
}
dcsr_value = buf_get_u32(dcsr_reg->value, 0, 32);
for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
command_print(CMD, "%15s: %s", vec_ids[i].name,
(dcsr_value & vec_ids[i].mask) ? "catch" : "ignore");
}
return ERROR_OK;
}
COMMAND_HANDLER(xscale_handle_vector_table_command)
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
int err = 0;
int retval;
retval = xscale_verify_pointer(CMD, xscale);
if (retval != ERROR_OK)
return retval;
if (CMD_ARGC == 0) { /* print current settings */
int idx;
command_print(CMD, "active user-set static vectors:");
for (idx = 1; idx < 8; idx++)
if (xscale->static_low_vectors_set & (1 << idx))
command_print(CMD,
"low %d: 0x%" PRIx32,
idx,
xscale->static_low_vectors[idx]);
for (idx = 1; idx < 8; idx++)
if (xscale->static_high_vectors_set & (1 << idx))
command_print(CMD,
"high %d: 0x%" PRIx32,
idx,
xscale->static_high_vectors[idx]);
return ERROR_OK;
}
if (CMD_ARGC != 3)
err = 1;
else {
int idx;
COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], idx);
uint32_t vec;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], vec);
if (idx < 1 || idx >= 8)
err = 1;
if (!err && strcmp(CMD_ARGV[0], "low") == 0) {
xscale->static_low_vectors_set |= (1<<idx);
xscale->static_low_vectors[idx] = vec;
} else if (!err && (strcmp(CMD_ARGV[0], "high") == 0)) {
xscale->static_high_vectors_set |= (1<<idx);
xscale->static_high_vectors[idx] = vec;
} else
err = 1;
}
if (err)
return ERROR_COMMAND_SYNTAX_ERROR;
return ERROR_OK;
}
COMMAND_HANDLER(xscale_handle_trace_buffer_command)
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
uint32_t dcsr_value;
int retval;
retval = xscale_verify_pointer(CMD, xscale);
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED) {
command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_TARGET_NOT_HALTED;
}
if (CMD_ARGC >= 1) {
if (strcmp("enable", CMD_ARGV[0]) == 0)
xscale->trace.mode = XSCALE_TRACE_WRAP; /* default */
else if (strcmp("disable", CMD_ARGV[0]) == 0)
xscale->trace.mode = XSCALE_TRACE_DISABLED;
else
return ERROR_COMMAND_SYNTAX_ERROR;
}
if (CMD_ARGC >= 2 && xscale->trace.mode != XSCALE_TRACE_DISABLED) {
if (strcmp("fill", CMD_ARGV[1]) == 0) {
int buffcount = 1; /* default */
if (CMD_ARGC >= 3)
COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], buffcount);
if (buffcount < 1) { /* invalid */
command_print(CMD, "fill buffer count must be > 0");
xscale->trace.mode = XSCALE_TRACE_DISABLED;
return ERROR_COMMAND_SYNTAX_ERROR;
}
xscale->trace.buffer_fill = buffcount;
xscale->trace.mode = XSCALE_TRACE_FILL;
} else if (strcmp("wrap", CMD_ARGV[1]) == 0)
xscale->trace.mode = XSCALE_TRACE_WRAP;
else {
xscale->trace.mode = XSCALE_TRACE_DISABLED;
return ERROR_COMMAND_SYNTAX_ERROR;
}
}
if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
char fill_string[12];
sprintf(fill_string, "fill %d", xscale->trace.buffer_fill);
command_print(CMD, "trace buffer enabled (%s)",
(xscale->trace.mode == XSCALE_TRACE_FILL)
? fill_string : "wrap");
} else
command_print(CMD, "trace buffer disabled");
dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
if (xscale->trace.mode == XSCALE_TRACE_FILL)
xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2);
else
xscale_write_dcsr_sw(target, dcsr_value & 0xfffffffc);
return ERROR_OK;
}
COMMAND_HANDLER(xscale_handle_trace_image_command)
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
int retval;
if (CMD_ARGC < 1)
return ERROR_COMMAND_SYNTAX_ERROR;
retval = xscale_verify_pointer(CMD, xscale);
if (retval != ERROR_OK)
return retval;
if (xscale->trace.image) {
image_close(xscale->trace.image);
free(xscale->trace.image);
command_print(CMD, "previously loaded image found and closed");
}
xscale->trace.image = malloc(sizeof(struct image));
xscale->trace.image->base_address_set = false;
xscale->trace.image->start_address_set = false;
/* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
if (CMD_ARGC >= 2) {
xscale->trace.image->base_address_set = true;
COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], xscale->trace.image->base_address);
} else
xscale->trace.image->base_address_set = false;
if (image_open(xscale->trace.image, CMD_ARGV[0],
(CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) {
free(xscale->trace.image);
xscale->trace.image = NULL;
return ERROR_OK;
}
return ERROR_OK;
}
COMMAND_HANDLER(xscale_handle_dump_trace_command)
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
struct xscale_trace_data *trace_data;
struct fileio *file;
int retval;
retval = xscale_verify_pointer(CMD, xscale);
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED) {
command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_TARGET_NOT_HALTED;
}
if (CMD_ARGC < 1)
return ERROR_COMMAND_SYNTAX_ERROR;
trace_data = xscale->trace.data;
if (!trace_data) {
command_print(CMD, "no trace data collected");
return ERROR_OK;
}
if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
return ERROR_OK;
while (trace_data) {
int i;
fileio_write_u32(file, trace_data->chkpt0);
fileio_write_u32(file, trace_data->chkpt1);
fileio_write_u32(file, trace_data->last_instruction);
fileio_write_u32(file, trace_data->depth);
for (i = 0; i < trace_data->depth; i++)
fileio_write_u32(file, trace_data->entries[i].data |
((trace_data->entries[i].type & 0xffff) << 16));
trace_data = trace_data->next;
}
fileio_close(file);
return ERROR_OK;
}
COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command)
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
int retval;
retval = xscale_verify_pointer(CMD, xscale);
if (retval != ERROR_OK)
return retval;
xscale_analyze_trace(target, CMD);
return ERROR_OK;
}
COMMAND_HANDLER(xscale_handle_cp15)
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
int retval;
retval = xscale_verify_pointer(CMD, xscale);
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED) {
command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_TARGET_NOT_HALTED;
}
uint32_t reg_no = 0;
struct reg *reg = NULL;
if (CMD_ARGC > 0) {
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no);
/*translate from xscale cp15 register no to openocd register*/
switch (reg_no) {
case 0:
reg_no = XSCALE_MAINID;
break;
case 1:
reg_no = XSCALE_CTRL;
break;
case 2:
reg_no = XSCALE_TTB;
break;
case 3:
reg_no = XSCALE_DAC;
break;
case 5:
reg_no = XSCALE_FSR;
break;
case 6:
reg_no = XSCALE_FAR;
break;
case 13:
reg_no = XSCALE_PID;
break;
case 15:
reg_no = XSCALE_CPACCESS;
break;
default:
command_print(CMD, "invalid register number");
return ERROR_COMMAND_SYNTAX_ERROR;
}
reg = &xscale->reg_cache->reg_list[reg_no];
}
if (CMD_ARGC == 1) {
uint32_t value;
/* read cp15 control register */
xscale_get_reg(reg);
value = buf_get_u32(reg->value, 0, 32);
command_print(CMD, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size),
value);
} else if (CMD_ARGC == 2) {
uint32_t value;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
/* send CP write request (command 0x41) */
xscale_send_u32(target, 0x41);
/* send CP register number */
xscale_send_u32(target, reg_no);
/* send CP register value */
xscale_send_u32(target, value);
/* execute cpwait to ensure outstanding operations complete */
xscale_send_u32(target, 0x53);
} else
return ERROR_COMMAND_SYNTAX_ERROR;
return ERROR_OK;
}
static const struct command_registration xscale_exec_command_handlers[] = {
{
.name = "cache_info",
.handler = xscale_handle_cache_info_command,
.mode = COMMAND_EXEC,
.help = "display information about CPU caches",
.usage = "",
},
{
.name = "mmu",
.handler = xscale_handle_mmu_command,
.mode = COMMAND_EXEC,
.help = "enable or disable the MMU",
.usage = "['enable'|'disable']",
},
{
.name = "icache",
.handler = xscale_handle_idcache_command,
.mode = COMMAND_EXEC,
.help = "display ICache state, optionally enabling or "
"disabling it",
.usage = "['enable'|'disable']",
},
{
.name = "dcache",
.handler = xscale_handle_idcache_command,
.mode = COMMAND_EXEC,
.help = "display DCache state, optionally enabling or "
"disabling it",
.usage = "['enable'|'disable']",
},
{
.name = "vector_catch",
.handler = xscale_handle_vector_catch_command,
.mode = COMMAND_EXEC,
.help = "set or display mask of vectors "
"that should trigger debug entry",
.usage = "['all'|'none'|'fiq'|'irq'|'dabt'|'pabt'|'swi'|'undef'|'reset']",
},
{
.name = "vector_table",
.handler = xscale_handle_vector_table_command,
.mode = COMMAND_EXEC,
.help = "set vector table entry in mini-ICache, "
"or display current tables",
.usage = "[('high'|'low') index code]",
},
{
.name = "trace_buffer",
.handler = xscale_handle_trace_buffer_command,
.mode = COMMAND_EXEC,
.help = "display trace buffer status, enable or disable "
"tracing, and optionally reconfigure trace mode",
.usage = "['enable'|'disable' ['fill' [number]|'wrap']]",
},
{
.name = "dump_trace",
.handler = xscale_handle_dump_trace_command,
.mode = COMMAND_EXEC,
.help = "dump content of trace buffer to file",
.usage = "filename",
},
{
.name = "analyze_trace",
.handler = xscale_handle_analyze_trace_buffer_command,
.mode = COMMAND_EXEC,
.help = "analyze content of trace buffer",
.usage = "",
},
{
.name = "trace_image",
.handler = xscale_handle_trace_image_command,
.mode = COMMAND_EXEC,
.help = "load image from file to address (default 0)",
.usage = "filename [offset [filetype]]",
},
{
.name = "cp15",
.handler = xscale_handle_cp15,
.mode = COMMAND_EXEC,
.help = "Read or write coprocessor 15 register.",
.usage = "register [value]",
},
COMMAND_REGISTRATION_DONE
};
static const struct command_registration xscale_any_command_handlers[] = {
{
.name = "debug_handler",
.handler = xscale_handle_debug_handler_command,
.mode = COMMAND_ANY,
.help = "Change address used for debug handler.",
.usage = "<target> <address>",
},
{
.name = "cache_clean_address",
.handler = xscale_handle_cache_clean_address_command,
.mode = COMMAND_ANY,
.help = "Change address used for cleaning data cache.",
.usage = "address",
},
{
.chain = xscale_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
static const struct command_registration xscale_command_handlers[] = {
{
.chain = arm_command_handlers,
},
{
.name = "xscale",
.mode = COMMAND_ANY,
.help = "xscale command group",
.usage = "",
.chain = xscale_any_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
struct target_type xscale_target = {
.name = "xscale",
.poll = xscale_poll,
.arch_state = xscale_arch_state,
.halt = xscale_halt,
.resume = xscale_resume,
.step = xscale_step,
.assert_reset = xscale_assert_reset,
.deassert_reset = xscale_deassert_reset,
/* REVISIT on some cores, allow exporting iwmmxt registers ... */
.get_gdb_arch = arm_get_gdb_arch,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = xscale_read_memory,
.read_phys_memory = xscale_read_phys_memory,
.write_memory = xscale_write_memory,
.write_phys_memory = xscale_write_phys_memory,
.checksum_memory = arm_checksum_memory,
.blank_check_memory = arm_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = xscale_add_breakpoint,
.remove_breakpoint = xscale_remove_breakpoint,
.add_watchpoint = xscale_add_watchpoint,
.remove_watchpoint = xscale_remove_watchpoint,
.commands = xscale_command_handlers,
.target_create = xscale_target_create,
.init_target = xscale_init_target,
.deinit_target = xscale_deinit_target,
.virt2phys = xscale_virt2phys,
.mmu = xscale_mmu
};
Details ![]()
Show: from Types: Columns: ![]( "Show Project Names")
![]( "Show Locations")
![]( "Show Referring Symbols")
![]( "Show Scope")
Click anywhere in the source to view detailed information here...