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// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************
* Copyright (C) 2006, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* Copyright (C) 2007,2008 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2009 Michael Schwingen *
* michael@schwingen.org *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "breakpoints.h"
#include "xscale.h"
#include "target_type.h"
#include "arm_jtag.h"
#include "arm_simulator.h"
#include "arm_disassembler.h"
#include <helper/time_support.h>
#include "register.h"
#include "image.h"
#include "arm_opcodes.h"
#include "armv4_5.h"
/*
* Important XScale documents available as of October 2009 include:
*
* Intel XScale® Core Developer’s Manual, January 2004
* Order Number: 273473-002
* This has a chapter detailing debug facilities, and punts some
* details to chip-specific microarchitecture documents.
*
* Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
* Document Number: 273539-005
* Less detailed than the developer's manual, but summarizes those
* missing details (for most XScales) and gives LOTS of notes about
* debugger/handler interaction issues. Presents a simpler reset
* and load-handler sequence than the arch doc. (Note, OpenOCD
* doesn't currently support "Hot-Debug" as defined there.)
*
* Chip-specific microarchitecture documents may also be useful.
*/
/* forward declarations */
static int xscale_resume(struct target *, int current,
target_addr_t address, int handle_breakpoints, int debug_execution);
static int xscale_debug_entry(struct target *);
static int xscale_restore_banked(struct target *);
static int xscale_get_reg(struct reg *reg);
static int xscale_set_reg(struct reg *reg, uint8_t *buf);
static int xscale_set_breakpoint(struct target *, struct breakpoint *);
static int xscale_set_watchpoint(struct target *, struct watchpoint *);
static int xscale_unset_breakpoint(struct target *, struct breakpoint *);
static int xscale_read_trace(struct target *);
/* This XScale "debug handler" is loaded into the processor's
* mini-ICache, which is 2K of code writable only via JTAG.
*/
static const uint8_t xscale_debug_handler[] = {
#include "../../contrib/loaders/debug/xscale/debug_handler.inc"
};
static const char *const xscale_reg_list[] = {
"XSCALE_MAINID", /* 0 */
"XSCALE_CACHETYPE",
"XSCALE_CTRL",
"XSCALE_AUXCTRL",
"XSCALE_TTB",
"XSCALE_DAC",
"XSCALE_FSR",
"XSCALE_FAR",
"XSCALE_PID",
"XSCALE_CPACCESS",
"XSCALE_IBCR0", /* 10 */
"XSCALE_IBCR1",
"XSCALE_DBR0",
"XSCALE_DBR1",
"XSCALE_DBCON",
"XSCALE_TBREG",
"XSCALE_CHKPT0",
"XSCALE_CHKPT1",
"XSCALE_DCSR",
"XSCALE_TX",
"XSCALE_RX", /* 20 */
"XSCALE_TXRXCTRL",
};
static const struct xscale_reg xscale_reg_arch_info[] = {
{XSCALE_MAINID, NULL},
{XSCALE_CACHETYPE, NULL},
{XSCALE_CTRL, NULL},
{XSCALE_AUXCTRL, NULL},
{XSCALE_TTB, NULL},
{XSCALE_DAC, NULL},
{XSCALE_FSR, NULL},
{XSCALE_FAR, NULL},
{XSCALE_PID, NULL},
{XSCALE_CPACCESS, NULL},
{XSCALE_IBCR0, NULL},
{XSCALE_IBCR1, NULL},
{XSCALE_DBR0, NULL},
{XSCALE_DBR1, NULL},
{XSCALE_DBCON, NULL},
{XSCALE_TBREG, NULL},
{XSCALE_CHKPT0, NULL},
{XSCALE_CHKPT1, NULL},
{XSCALE_DCSR, NULL}, /* DCSR accessed via JTAG or SW */
{-1, NULL}, /* TX accessed via JTAG */
{-1, NULL}, /* RX accessed via JTAG */
{-1, NULL}, /* TXRXCTRL implicit access via JTAG */
};
/* convenience wrapper to access XScale specific registers */
static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
{
uint8_t buf[4] = { 0 };
buf_set_u32(buf, 0, 32, value);
return xscale_set_reg(reg, buf);
}
static const char xscale_not[] = "target is not an XScale";
static int xscale_verify_pointer(struct command_invocation *cmd,
struct xscale_common *xscale)
{
if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
command_print(cmd, xscale_not);
return ERROR_TARGET_INVALID;
}
return ERROR_OK;
}
static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
{
assert(tap);
if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
struct scan_field field;
uint8_t scratch[4] = { 0 };
memset(&field, 0, sizeof(field));
field.num_bits = tap->ir_length;
field.out_value = scratch;
buf_set_u32(scratch, 0, field.num_bits, new_instr);
jtag_add_ir_scan(tap, &field, end_state);
}
return ERROR_OK;
}
static int xscale_read_dcsr(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
int retval;
struct scan_field fields[3];
uint8_t field0 = 0x0;
uint8_t field0_check_value = 0x2;
uint8_t field0_check_mask = 0x7;
uint8_t field2 = 0x0;
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
xscale_jtag_set_instr(target->tap,
XSCALE_SELDCSR << xscale->xscale_variant,
TAP_DRPAUSE);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
memset(&fields, 0, sizeof(fields));
fields[0].num_bits = 3;
fields[0].out_value = &field0;
uint8_t tmp;
fields[0].in_value = &tmp;
fields[1].num_bits = 32;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp2;
fields[2].in_value = &tmp2;
jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("JTAG error while reading DCSR");
return retval;
}
xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = false;
xscale->reg_cache->reg_list[XSCALE_DCSR].valid = true;
/* write the register with the value we just read
* on this second pass, only the first bit of field0 is guaranteed to be 0)
*/
field0_check_mask = 0x1;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[1].in_value = NULL;
jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
/* DANGER!!! this must be here. It will make sure that the arguments
* to jtag_set_check_value() does not go out of scope! */
return jtag_execute_queue();
}
static void xscale_getbuf(jtag_callback_data_t arg)
{
uint8_t *in = (uint8_t *)arg;
*((uint32_t *)arg) = buf_get_u32(in, 0, 32);
}
static int xscale_receive(struct target *target, uint32_t *buffer, int num_words)
{
if (num_words == 0)
return ERROR_COMMAND_SYNTAX_ERROR;
struct xscale_common *xscale = target_to_xscale(target);
int retval = ERROR_OK;
tap_state_t path[3];
struct scan_field fields[3];
uint8_t *field0 = malloc(num_words * 1);
uint8_t field0_check_value = 0x2;
uint8_t field0_check_mask = 0x6;
uint32_t *field1 = malloc(num_words * 4);
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
int words_done = 0;
int words_scheduled = 0;
int i;
path[0] = TAP_DRSELECT;
path[1] = TAP_DRCAPTURE;
path[2] = TAP_DRSHIFT;
memset(&fields, 0, sizeof(fields));
fields[0].num_bits = 3;
uint8_t tmp;
fields[0].in_value = &tmp;
fields[0].check_value = &field0_check_value;
fields[0].check_mask = &field0_check_mask;
fields[1].num_bits = 32;
fields[2].num_bits = 1;
uint8_t tmp2;
fields[2].in_value = &tmp2;
fields[2].check_value = &field2_check_value;
fields[2].check_mask = &field2_check_mask;
xscale_jtag_set_instr(target->tap,
XSCALE_DBGTX << xscale->xscale_variant,
TAP_IDLE);
jtag_add_runtest(1, TAP_IDLE); /* ensures that we're in the TAP_IDLE state as the above
*could be a no-op */
/* repeat until all words have been collected */
int attempts = 0;
while (words_done < num_words) {
/* schedule reads */
words_scheduled = 0;
for (i = words_done; i < num_words; i++) {
fields[0].in_value = &field0[i];
jtag_add_pathmove(3, path);
fields[1].in_value = (uint8_t *)(field1 + i);
jtag_add_dr_scan_check(target->tap, 3, fields, TAP_IDLE);
jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
words_scheduled++;
}
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("JTAG error while receiving data from debug handler");
break;
}
/* examine results */
for (i = words_done; i < num_words; i++) {
if (!(field0[i] & 1)) {
/* move backwards if necessary */
int j;
for (j = i; j < num_words - 1; j++) {
field0[j] = field0[j + 1];
field1[j] = field1[j + 1];
}
words_scheduled--;
}
}
if (words_scheduled == 0) {
if (attempts++ == 1000) {
LOG_ERROR(
"Failed to receiving data from debug handler after 1000 attempts");
retval = ERROR_TARGET_TIMEOUT;
break;
}
}
words_done += words_scheduled;
}
for (i = 0; i < num_words; i++)
*(buffer++) = buf_get_u32((uint8_t *)&field1[i], 0, 32);
free(field1);
return retval;
}
static int xscale_read_tx(struct target *target, int consume)
{
struct xscale_common *xscale = target_to_xscale(target);
tap_state_t path[3];
tap_state_t noconsume_path[6];
int retval;
struct timeval timeout, now;
struct scan_field fields[3];
uint8_t field0_in = 0x0;
uint8_t field0_check_value = 0x2;
uint8_t field0_check_mask = 0x6;
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
xscale_jtag_set_instr(target->tap,
XSCALE_DBGTX << xscale->xscale_variant,
TAP_IDLE);
path[0] = TAP_DRSELECT;
path[1] = TAP_DRCAPTURE;
path[2] = TAP_DRSHIFT;
noconsume_path[0] = TAP_DRSELECT;
noconsume_path[1] = TAP_DRCAPTURE;
noconsume_path[2] = TAP_DREXIT1;
noconsume_path[3] = TAP_DRPAUSE;
noconsume_path[4] = TAP_DREXIT2;
noconsume_path[5] = TAP_DRSHIFT;
memset(&fields, 0, sizeof(fields));
fields[0].num_bits = 3;
fields[0].in_value = &field0_in;
fields[1].num_bits = 32;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
fields[2].num_bits = 1;
uint8_t tmp;
fields[2].in_value = &tmp;
gettimeofday(&timeout, NULL);
timeval_add_time(&timeout, 1, 0);
for (;; ) {
/* if we want to consume the register content (i.e. clear TX_READY),
* we have to go straight from Capture-DR to Shift-DR
* otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
*/
if (consume)
jtag_add_pathmove(3, path);
else
jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path);
jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("JTAG error while reading TX");
return ERROR_TARGET_TIMEOUT;
}
gettimeofday(&now, NULL);
if (timeval_compare(&now, &timeout) > 0) {
LOG_ERROR("time out reading TX register");
return ERROR_TARGET_TIMEOUT;
}
if (!((!(field0_in & 1)) && consume))
goto done;
if (debug_level >= 3) {
LOG_DEBUG("waiting 100ms");
alive_sleep(100); /* avoid flooding the logs */
} else
keep_alive();
}
done:
if (!(field0_in & 1))
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
return ERROR_OK;
}
static int xscale_write_rx(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
int retval;
struct timeval timeout, now;
struct scan_field fields[3];
uint8_t field0_out = 0x0;
uint8_t field0_in = 0x0;
uint8_t field0_check_value = 0x2;
uint8_t field0_check_mask = 0x6;
uint8_t field2 = 0x0;
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
xscale_jtag_set_instr(target->tap,
XSCALE_DBGRX << xscale->xscale_variant,
TAP_IDLE);
memset(&fields, 0, sizeof(fields));
fields[0].num_bits = 3;
fields[0].out_value = &field0_out;
fields[0].in_value = &field0_in;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp;
fields[2].in_value = &tmp;
gettimeofday(&timeout, NULL);
timeval_add_time(&timeout, 1, 0);
/* poll until rx_read is low */
LOG_DEBUG("polling RX");
for (;;) {
jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("JTAG error while writing RX");
return retval;
}
gettimeofday(&now, NULL);
if ((now.tv_sec > timeout.tv_sec) ||
((now.tv_sec == timeout.tv_sec) && (now.tv_usec > timeout.tv_usec))) {
LOG_ERROR("time out writing RX register");
return ERROR_TARGET_TIMEOUT;
}
if (!(field0_in & 1))
goto done;
if (debug_level >= 3) {
LOG_DEBUG("waiting 100ms");
alive_sleep(100); /* avoid flooding the logs */
} else
keep_alive();
}
done:
/* set rx_valid */
field2 = 0x1;
jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("JTAG error while writing RX");
return retval;
}
return ERROR_OK;
}
/* send count elements of size byte to the debug handler */
static int xscale_send(struct target *target, const uint8_t *buffer, int count, int size)
{
struct xscale_common *xscale = target_to_xscale(target);
int retval;
int done_count = 0;
xscale_jtag_set_instr(target->tap,
XSCALE_DBGRX << xscale->xscale_variant,
TAP_IDLE);
static const uint8_t t0;
uint8_t t1[4] = { 0 };
static const uint8_t t2 = 1;
struct scan_field fields[3] = {
{ .num_bits = 3, .out_value = &t0 },
{ .num_bits = 32, .out_value = t1 },
{ .num_bits = 1, .out_value = &t2 },
};
int endianness = target->endianness;
while (done_count++ < count) {
uint32_t t;
switch (size) {
case 4:
if (endianness == TARGET_LITTLE_ENDIAN)
t = le_to_h_u32(buffer);
else
t = be_to_h_u32(buffer);
break;
case 2:
if (endianness == TARGET_LITTLE_ENDIAN)
t = le_to_h_u16(buffer);
else
t = be_to_h_u16(buffer);
break;
case 1:
t = buffer[0];
break;
default:
LOG_ERROR("BUG: size neither 4, 2 nor 1");
return ERROR_COMMAND_SYNTAX_ERROR;
}
buf_set_u32(t1, 0, 32, t);
jtag_add_dr_scan(target->tap,
3,
fields,
TAP_IDLE);
buffer += size;
}
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("JTAG error while sending data to debug handler");
return retval;
}
return ERROR_OK;
}
static int xscale_send_u32(struct target *target, uint32_t value)
{
struct xscale_common *xscale = target_to_xscale(target);
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
return xscale_write_rx(target);
}
static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_brk)
{
struct xscale_common *xscale = target_to_xscale(target);
int retval;
struct scan_field fields[3];
uint8_t field0 = 0x0;
uint8_t field0_check_value = 0x2;
uint8_t field0_check_mask = 0x7;
uint8_t field2 = 0x0;
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
if (hold_rst != -1)
xscale->hold_rst = hold_rst;
if (ext_dbg_brk != -1)
xscale->external_debug_break = ext_dbg_brk;
xscale_jtag_set_instr(target->tap,
XSCALE_SELDCSR << xscale->xscale_variant,
TAP_IDLE);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
memset(&fields, 0, sizeof(fields));
fields[0].num_bits = 3;
fields[0].out_value = &field0;
uint8_t tmp;
fields[0].in_value = &tmp;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp2;
fields[2].in_value = &tmp2;
jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("JTAG error while writing DCSR");
return retval;
}
xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = false;
xscale->reg_cache->reg_list[XSCALE_DCSR].valid = true;
return ERROR_OK;
}
/* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
static unsigned int parity(unsigned int v)
{
/* unsigned int ov = v; */
v ^= v >> 16;
v ^= v >> 8;
v ^= v >> 4;
v &= 0xf;
/* LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); */
return (0x6996 >> v) & 1;
}
static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8])
{
struct xscale_common *xscale = target_to_xscale(target);
uint8_t packet[4] = { 0 };
uint8_t cmd = 0;
int word;
struct scan_field fields[2];
LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
/* LDIC into IR */
xscale_jtag_set_instr(target->tap,
XSCALE_LDIC << xscale->xscale_variant,
TAP_IDLE);
/* CMD is b011 to load a cacheline into the Mini ICache.
* Loading into the main ICache is deprecated, and unused.
* It's followed by three zero bits, and 27 address bits.
*/
buf_set_u32(&cmd, 0, 6, 0x3);
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
memset(&fields, 0, sizeof(fields));
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
fields[1].num_bits = 27;
fields[1].out_value = packet;
jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
/* rest of packet is a cacheline: 8 instructions, with parity */
fields[0].num_bits = 32;
fields[0].out_value = packet;
fields[1].num_bits = 1;
fields[1].out_value = &cmd;
for (word = 0; word < 8; word++) {
buf_set_u32(packet, 0, 32, buffer[word]);
uint32_t value;
memcpy(&value, packet, sizeof(uint32_t));
cmd = parity(value);
jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
}
return jtag_execute_queue();
}
static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
{
struct xscale_common *xscale = target_to_xscale(target);
uint8_t packet[4] = { 0 };
uint8_t cmd = 0;
struct scan_field fields[2];
xscale_jtag_set_instr(target->tap,
XSCALE_LDIC << xscale->xscale_variant,
TAP_IDLE);
/* CMD for invalidate IC line b000, bits [6:4] b000 */
buf_set_u32(&cmd, 0, 6, 0x0);
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
memset(&fields, 0, sizeof(fields));
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
fields[1].num_bits = 27;
fields[1].out_value = packet;
jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
return ERROR_OK;
}
static int xscale_update_vectors(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
int i;
int retval;
uint32_t low_reset_branch, high_reset_branch;
for (i = 1; i < 8; i++) {
/* if there's a static vector specified for this exception, override */
if (xscale->static_high_vectors_set & (1 << i))
xscale->high_vectors[i] = xscale->static_high_vectors[i];
else {
retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
if (retval == ERROR_TARGET_TIMEOUT)
return retval;
if (retval != ERROR_OK) {
/* Some of these reads will fail as part of normal execution */
xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
}
}
}
for (i = 1; i < 8; i++) {
if (xscale->static_low_vectors_set & (1 << i))
xscale->low_vectors[i] = xscale->static_low_vectors[i];
else {
retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
if (retval == ERROR_TARGET_TIMEOUT)
return retval;
if (retval != ERROR_OK) {
/* Some of these reads will fail as part of normal execution */
xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
}
}
}
/* calculate branches to debug handler */
low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
/* invalidate and load exception vectors in mini i-cache */
xscale_invalidate_ic_line(target, 0x0);
xscale_invalidate_ic_line(target, 0xffff0000);
xscale_load_ic(target, 0x0, xscale->low_vectors);
xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
return ERROR_OK;
}
static int xscale_arch_state(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
struct arm *arm = &xscale->arm;
static const char *state[] = {
"disabled", "enabled"
};
static const char *arch_dbg_reason[] = {
"", "\n(processor reset)", "\n(trace buffer full)"
};
if (arm->common_magic != ARM_COMMON_MAGIC) {
LOG_ERROR("BUG: called for a non-ARMv4/5 target");
return ERROR_COMMAND_SYNTAX_ERROR;
}
arm_arch_state(target);
LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
state[xscale->armv4_5_mmu.mmu_enabled],
state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
arch_dbg_reason[xscale->arch_debug_reason]);
return ERROR_OK;
}
static int xscale_poll(struct target *target)
{
int retval = ERROR_OK;
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING)) {
enum target_state previous_state = target->state;
retval = xscale_read_tx(target, 0);
if (retval == ERROR_OK) {
/* there's data to read from the tx register, we entered debug state */
target->state = TARGET_HALTED;
/* process debug entry, fetching current mode regs */
retval = xscale_debug_entry(target);
} else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
LOG_USER("error while polling TX register, reset CPU");
/* here we "lie" so GDB won't get stuck and a reset can be performed */
target->state = TARGET_HALTED;
}
/* debug_entry could have overwritten target state (i.e. immediate resume)
* don't signal event handlers in that case
*/
if (target->state != TARGET_HALTED)
return ERROR_OK;
/* if target was running, signal that we halted
* otherwise we reentered from debug execution */
if (previous_state == TARGET_RUNNING)
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
else
target_call_event_callbacks(target,