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#include <assert.h>
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#include <stdlib.h>
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#include <time.h>
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#include "config.h"
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#include <helper/log.h>
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#include <helper/time_support.h>
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#include "target/target.h"
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#include "target/algorithm.h"
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#include "target/target_type.h"
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#include <target/smp.h>
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#include "jtag/jtag.h"
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#include "target/register.h"
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#include "target/breakpoints.h"
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#include "riscv.h"
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#include "gdb_regs.h"
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#include "rtos/rtos.h"
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#include "debug_defines.h"
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#include <helper/bits.h>
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#define get_field
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#define set_field
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#define CSR_BPCONTROL_X
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#define CSR_BPCONTROL_W
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#define CSR_BPCONTROL_R
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#define CSR_BPCONTROL_U
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#define CSR_BPCONTROL_S
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#define CSR_BPCONTROL_H
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#define CSR_BPCONTROL_M
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#define CSR_BPCONTROL_BPMATCH
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#define CSR_BPCONTROL_BPACTION
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#define DEBUG_ROM_START
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#define DEBUG_ROM_RESUME
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#define DEBUG_ROM_EXCEPTION
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#define DEBUG_RAM_START
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#define SETHALTNOT
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#define DTMCONTROL
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#define DTMCONTROL_DBUS_RESET
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#define DTMCONTROL_IDLE
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#define DTMCONTROL_ADDRBITS
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#define DTMCONTROL_VERSION
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#define DBUS
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#define DBUS_OP_START
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#define DBUS_OP_SIZE
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dbus_op_t
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DBUS_OP_NOP
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DBUS_OP_READ
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DBUS_OP_WRITE
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dbus_status_t
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DBUS_STATUS_SUCCESS
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DBUS_STATUS_FAILED
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DBUS_STATUS_BUSY
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#define DBUS_DATA_START
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#define DBUS_DATA_SIZE
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#define DBUS_ADDRESS_START
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slot
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SLOT0
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SLOT1
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SLOT_LAST
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#define DMCONTROL
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#define DMCONTROL_INTERRUPT
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#define DMCONTROL_HALTNOT
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#define DMCONTROL_BUSERROR
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#define DMCONTROL_SERIAL
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#define DMCONTROL_AUTOINCREMENT
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#define DMCONTROL_ACCESS
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#define DMCONTROL_HARTID
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#define DMCONTROL_NDRESET
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#define DMCONTROL_FULLRESET
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#define DMINFO
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#define DMINFO_ABUSSIZE
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#define DMINFO_SERIALCOUNT
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#define DMINFO_ACCESS128
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#define DMINFO_ACCESS64
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#define DMINFO_ACCESS32
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#define DMINFO_ACCESS16
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#define DMINFO_ACCESS8
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#define DMINFO_DRAMSIZE
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#define DMINFO_AUTHENTICATED
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#define DMINFO_AUTHBUSY
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#define DMINFO_AUTHTYPE
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#define DMINFO_VERSION
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#define DBUS_ADDRESS_UNKNOWN
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#define MAX_HWBPS
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#define DRAM_CACHE_SIZE
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ir_dtmcontrol
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select_dtmcontrol
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ir_dbus
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select_dbus
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ir_idcode
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select_idcode
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bscan_tunnel_type
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bscan_tunnel_ir_width
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bscan_zero
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bscan_one
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ir_user4
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select_user4
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bscan_tunneled_ir_width
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_bscan_tunnel_data_register_select_dmi
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_bscan_tunnel_nested_tap_select_dmi
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bscan_tunnel_nested_tap_select_dmi
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bscan_tunnel_nested_tap_select_dmi_num_fields
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bscan_tunnel_data_register_select_dmi
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bscan_tunnel_data_register_select_dmi_num_fields
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trigger
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address
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length
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mask
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value
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read
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write
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execute
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unique_id
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riscv_command_timeout_sec
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riscv_reset_timeout_sec
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riscv_enable_virt2phys
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riscv_ebreakm
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riscv_ebreaks
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riscv_ebreaku
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riscv_enable_virtual
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resume_order
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<anonymous enum>
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RO_NORMAL
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RO_REVERSED
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sv32
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sv39
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sv48
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riscv_sample_buf_maybe_add_timestamp(struct target *, bool)
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if
(r->sample_buf.used + 5 < r->sample_buf.size)
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select_dmi_via_bscan(struct target *)
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dtmcontrol_scan_via_bscan(struct target *, uint32_t)
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if
(bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
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else
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if
(retval != ERROR_OK)
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dtmcontrol_scan(struct target *, uint32_t)
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if
(retval != ERROR_OK)
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get_target_type(struct target *)
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if
(!target->arch_info)
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switch
(info->dtm_version)
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case
0:
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case
1:
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default
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riscv_create_target(struct target *, Jim_Interp *)
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if
(!target->arch_info)
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riscv_init_target(struct command_context *, struct target *)
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if
(bscan_tunnel_ir_width != 0)
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riscv_free_registers(struct target *)
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if
(target->reg_cache)
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if
(target->reg_cache->reg_list)
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riscv_deinit_target(struct target *)
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list_for_each_entry_safe
(entry, tmp, &info->expose_csr, list)
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list_for_each_entry_safe
(entry, tmp, &info->expose_custom, list)
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trigger_from_breakpoint(struct trigger *, const struct breakpoint *)
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maybe_add_trigger_t1(struct target *, struct trigger *, uint64_t)
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if
(tdata1 & (bpcontrol_r | bpcontrol_w | bpcontrol_x))
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if
(tdata1 != tdata1_rb)
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maybe_add_trigger_t2(struct target *, struct trigger *, uint64_t)
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if
(tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD))
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if
(tdata1 != tdata1_rb)
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maybe_add_trigger_t6(struct target *, struct trigger *, uint64_t)
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if
(tdata1 & (CSR_MCONTROL6_EXECUTE | CSR_MCONTROL6_STORE | CSR_MCONTROL6_LOAD))
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if
(tdata1 != tdata1_rb)
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add_trigger(struct target *, struct trigger *)
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for
(i = 0; i < r->trigger_count; i++)
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switch
(type)
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case
1:
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case
2:
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case
6:
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default
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if
(i >= r->trigger_count)
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write_by_given_size(struct target *, target_addr_t, uint32_t, uint8_t *, uint32_t)
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read_by_given_size(struct target *, target_addr_t, uint32_t, uint8_t *, uint32_t)
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riscv_write_by_any_size(struct target *, target_addr_t, uint32_t, uint8_t *)
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for
(unsigned int access_size = 8; access_size > 0; access_size /= 2)
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riscv_read_by_any_size(struct target *, target_addr_t, uint32_t, uint8_t *)
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for
(unsigned int access_size = 8; access_size > 0; access_size /= 2)
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riscv_add_breakpoint(struct target *, struct breakpoint *)
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if
(breakpoint->type == BKPT_SOFT)
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if
(!(breakpoint->length == 4 || breakpoint->length == 2))
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if
(0 != (breakpoint->address % 2))
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if
(riscv_read_by_any_size( target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK)
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if
(riscv_write_by_any_size(target, breakpoint->address, breakpoint->length, buff) != ERROR_OK)
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else if
(breakpoint->type == BKPT_HARD)
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else
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remove_trigger(struct target *, struct trigger *)
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for
(i = 0; i < r->trigger_count; i++)
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if
(i >= r->trigger_count)
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riscv_remove_breakpoint(struct target *, struct breakpoint *)
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if
(breakpoint->type == BKPT_SOFT)
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if
(riscv_write_by_any_size( target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK)
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else if
(breakpoint->type == BKPT_HARD)
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else
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trigger_from_watchpoint(struct trigger *, const struct watchpoint *)
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riscv_add_watchpoint(struct target *, struct watchpoint *)
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riscv_remove_watchpoint(struct target *, struct watchpoint *)
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riscv_hit_watchpoint(struct target *, struct watchpoint **)
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if
(target_read_buffer(target, dpc, length, buffer) != ERROR_OK)
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for
(int i = 0; i < length; i++)
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if
(opcode == MATCH_LB || opcode == MATCH_SB)
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if
(opcode == MATCH_SB)
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else
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else
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while
(wp)
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if
(wp->address == mem_addr)
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oldriscv_step(struct target *, int, uint32_t, int)
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old_or_new_riscv_step(struct target *, int, target_addr_t, int)
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riscv_examine(struct target *)
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if
(target_was_examined(target))
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oldriscv_poll(struct target *)
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old_or_new_riscv_poll(struct target *)
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riscv_select_current_hart(struct target *)
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halt_prep(struct target *)
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if
(riscv_is_halted(target))
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else
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riscv_halt_go_all_harts(struct target *)
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if
(riscv_is_halted(target))
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else
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halt_go(struct target *)
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if
(!r->is_halted)
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else
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halt_finish(struct target *)
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riscv_halt(struct target *)
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if
(!r->is_halted)
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if
(target->smp)
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foreach_smp_target
(tlist, target->smp_targets)
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foreach_smp_target
(tlist, target->smp_targets)
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if
(i->prepped)
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foreach_smp_target
(tlist, target->smp_targets)
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else
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riscv_assert_reset(struct target *)
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riscv_deassert_reset(struct target *)
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riscv_resume_prep_all_harts(struct target *)
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if
(riscv_is_halted(target))
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else
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disable_triggers(struct target *, riscv_reg_t *)
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if
(r->manual_hwbp_set)
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for
(unsigned int t = 0; t < r->trigger_count; t++)
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if
(tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
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else
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while
(watchpoint)
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if
(watchpoint->is_set)
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enable_triggers(struct target *, riscv_reg_t *)
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if
(r->manual_hwbp_set)
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for
(unsigned int t = 0; t < r->trigger_count; t++)
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if
(state[t] != 0)
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else
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while
(watchpoint)
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if
(state[i])
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resume_prep(struct target *, int, target_addr_t, int, int)
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if
(target->debug_reason == DBG_REASON_WATCHPOINT)
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if
(r->is_halted)
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resume_go(struct target *, int, target_addr_t, int, int)
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if
(!r->is_halted)
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else
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resume_finish(struct target *)
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riscv_resume(struct target *, int, target_addr_t, int, int, bool)
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if
(target->smp && !single_hart)
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foreach_smp_target_direction
(resume_order == RO_NORMAL, tlist, target->smp_targets)
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foreach_smp_target_direction
(resume_order == RO_NORMAL, tlist, target->smp_targets)
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if
(i->prepped)
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foreach_smp_target_direction
(resume_order == RO_NORMAL, tlist, target->smp_targets)
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else
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riscv_target_resume(struct target *, int, target_addr_t, int, int)
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riscv_mmu(struct target *, int *)
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if
(!riscv_enable_virt2phys)
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if
(riscv_get_register(target, &priv, GDB_REGNO_PRIV) != ERROR_OK)
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if
(riscv_get_register(target, &mstatus, GDB_REGNO_MSTATUS) != ERROR_OK)
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if
((get_field(mstatus, MSTATUS_MPRV) ? get_field(mstatus, MSTATUS_MPP) : priv) == PRV_M)
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if
(riscv_get_register(target, &satp, GDB_REGNO_SATP) != ERROR_OK)
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if
(get_field(satp, RISCV_SATP_MODE(riscv_xlen(target))) == SATP_MODE_OFF)
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else
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riscv_address_translate(struct target *, target_addr_t, target_addr_t *)
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switch
(mode)
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case
SATP_MODE_SV32:
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case
SATP_MODE_SV39:
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case
SATP_MODE_SV48:
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case
SATP_MODE_OFF:
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default
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if
(masked_msbs != 0 && masked_msbs != mask)
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while
(i >= 0)
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if
(i < 0)
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while
(i < info->level)
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riscv_virt2phys(struct target *, target_addr_t, target_addr_t *)
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if
(riscv_mmu(target, &enabled) == ERROR_OK)
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riscv_read_phys_memory(struct target *, target_addr_t, uint32_t, uint32_t, uint8_t *)
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riscv_read_memory(struct target *, target_addr_t, uint32_t, uint32_t, uint8_t *)
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if
(count == 0)
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riscv_write_phys_memory(struct target *, target_addr_t, uint32_t, uint32_t, const uint8_t *)
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riscv_write_memory(struct target *, target_addr_t, uint32_t, uint32_t, const uint8_t *)
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if
(count == 0)
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riscv_get_gdb_arch(const struct target *)
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switch
(riscv_xlen(target))
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case
32:
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case
64:
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riscv_get_gdb_reg_list_internal(struct target *, struct reg ***, int *, enum target_register_class, bool)
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if
(!target->reg_cache)
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switch
(reg_class)
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case
REG_CLASS_GENERAL:
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case
REG_CLASS_ALL:
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default
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for
(int i = 0; i < *reg_list_size; i++)
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if
(read && target->reg_cache->reg_list[i].exist && !target->reg_cache->reg_list[i].valid)
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riscv_get_gdb_reg_list_noread(struct target *, struct reg ***, int *, enum target_register_class)
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riscv_get_gdb_reg_list(struct target *, struct reg ***, int *, enum target_register_class)
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riscv_arch_state(struct target *)
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riscv_run_algorithm(struct target *, int, struct mem_param *, int, struct reg_param *, target_addr_t, target_addr_t, unsigned int, void *)
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if
(num_mem_params > 0)
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if
(target->state != TARGET_HALTED)
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for
(int i = 0; i < num_reg_params; i++)
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if
(!r)
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if
(r->size != reg_params[i].size)
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if
(r->number > GDB_REGNO_XPR31)
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if
(reg_params[i].direction == PARAM_OUT || reg_params[i].direction == PARAM_IN_OUT)
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if
(!reg_mstatus)
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while
(target->state != TARGET_HALTED)
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if
(now - start > timeout_ms)
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for
(unsigned i = 0; i < ARRAY_SIZE(regnums); i++)
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if
(exit_point && final_pc != exit_point)
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for
(int i = 0; i < num_reg_params; i++)
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if
(reg_params[i].direction == PARAM_IN || reg_params[i].direction == PARAM_IN_OUT)
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if
(r->type->get(r) != ERROR_OK)
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if
(r->type->set(r, buf) != ERROR_OK)
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riscv_checksum_memory(struct target *, target_addr_t, uint32_t, uint32_t *)
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if
(xlen == 32)
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else
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if
(count < crc_code_size * 4)
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if
(crc_algorithm->address + crc_algorithm->size > address && crc_algorithm->address < address + count)
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if
(retval != ERROR_OK)
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riscv_poll_hart
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RPH_NO_CHANGE
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RPH_DISCOVERED_HALTED
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RPH_DISCOVERED_RUNNING
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RPH_ERROR
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riscv_poll_hart(struct target *, int)
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if
(target->state != TARGET_HALTED && halted)
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else if
(target->state != TARGET_RUNNING && !halted)
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set_debug_reason(struct target *, enum riscv_halt_reason)
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switch
(halt_reason)
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case
RISCV_HALT_BREAKPOINT:
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case
RISCV_HALT_TRIGGER:
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case
RISCV_HALT_INTERRUPT:
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case
RISCV_HALT_GROUP:
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case
RISCV_HALT_SINGLESTEP:
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case
RISCV_HALT_UNKNOWN:
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case
RISCV_HALT_ERROR:
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sample_memory(struct target *)
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if
(r->sample_memory)
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while
(timeval_ms() - start < TARGET_DEFAULT_POLLING_INTERVAL)
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for
(unsigned int i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++)
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if
(r->sample_config.bucket[i].enabled && r->sample_buf.used + 1 + r->sample_config.bucket[i].size_bytes < r->sample_buf.size)
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if
(result != ERROR_OK)
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riscv_openocd_poll(struct target *)
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if
(target->smp)
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foreach_smp_target
(list, target->smp_targets)
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switch
(out)
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case
RPH_NO_CHANGE:
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case
RPH_DISCOVERED_RUNNING:
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case
RPH_DISCOVERED_HALTED:
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if
(halt_reason == RISCV_HALT_BREAKPOINT)
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switch
(riscv_semihosting(t, &retval))
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case
SEMIHOSTING_NONE:
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case
SEMIHOSTING_WAITING:
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case
SEMIHOSTING_HANDLED:
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case
SEMIHOSTING_ERROR:
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![]()
else if
(halt_reason != RISCV_HALT_GROUP)
![]()
![]()
case
RPH_ERROR:
![]()
![]()
if
(should_remain_halted && should_resume)
![]()
![]()
if
(should_remain_halted)
![]()
![]()
else if
(should_resume)
![]()
![]()
foreach_smp_target
(list, target->smp_targets)
![]()
![]()
if
(t->state == TARGET_RUNNING)
![]()
![]()
else
![]()
![]()
if
(out == RPH_NO_CHANGE || out == RPH_DISCOVERED_RUNNING)
![]()
![]()
else if
(out == RPH_ERROR)
![]()
![]()
if
(target->debug_reason == DBG_REASON_BREAKPOINT)
![]()
![]()
switch
(riscv_semihosting(target, &retval))
![]()
![]()
case
SEMIHOSTING_NONE:
![]()
![]()
case
SEMIHOSTING_WAITING:
![]()
![]()
case
SEMIHOSTING_HANDLED:
![]()
![]()
case
SEMIHOSTING_ERROR:
![]()
![]()
else
![]()
![]()
riscv_openocd_step(struct target *, int, target_addr_t, int)
![]()
![]()
if
(out != ERROR_OK)
![]()
![]()
riscv_set_command_timeout_sec(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC != 1)
![]()
![]()
if
(timeout <= 0)
![]()
![]()
riscv_set_reset_timeout_sec(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC != 1)
![]()
![]()
if
(timeout <= 0)
![]()
![]()
riscv_set_mem_access(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC < 1 || CMD_ARGC > RISCV_NUM_MEM_ACCESS_METHODS)
![]()
![]()
for
(unsigned int i = 0; i < CMD_ARGC; i++)
![]()
![]()
if
(strcmp("progbuf", CMD_ARGV[i]) == 0)
![]()
![]()
else if
(strcmp("sysbus", CMD_ARGV[i]) == 0)
![]()
![]()
else if
(strcmp("abstract", CMD_ARGV[i]) == 0)
![]()
![]()
else
![]()
![]()
if
(progbuf_cnt > 1 || sysbus_cnt > 1 || abstract_cnt > 1)
![]()
![]()
for
(unsigned int i = 0; i < CMD_ARGC; i++)
![]()
![]()
riscv_set_enable_virtual(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC != 1)
![]()
![]()
parse_ranges(struct list_head *, const char *, const char *, unsigned int)
![]()
![]()
while
(arg)
![]()
![]()
if
(!dash && !equals)
![]()
![]()
if
(sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg))
![]()
![]()
else if
(dash && !equals)
![]()
![]()
if
(sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg))
![]()
![]()
if
(sscanf(dash, "%u%n", &high, &pos) != 1 || pos != strlen(dash))
![]()
![]()
if
(high < low)
![]()
![]()
else if
(!dash && equals)
![]()
![]()
if
(sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg))
![]()
![]()
if
(!name)
![]()
![]()
if
(sscanf(equals, "%[_a-zA-Z0-9]%n", name + strlen(reg_type) + 1, &pos) != 1 || pos != strlen(equals))
![]()
![]()
else
![]()
![]()
if
(high > max_val)
![]()
![]()
list_for_each_entry
(entry, ranges, list)
![]()
![]()
if
((entry->low <= high) && (low <= entry->high))
![]()
![]()
if
(entry->name && name && (strcasecmp(entry->name, name) == 0))
![]()
![]()
if
(!range)
![]()
![]()
riscv_set_expose_csrs(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC == 0)
![]()
![]()
for
(unsigned int i = 0; i < CMD_ARGC; i++)
![]()
![]()
riscv_set_expose_custom(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC == 0)
![]()
![]()
for
(unsigned int i = 0; i < CMD_ARGC; i++)
![]()
![]()
riscv_authdata_read(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC == 0)
![]()
![]()
else if
(CMD_ARGC == 1)
![]()
![]()
else
![]()
![]()
if
(!target)
![]()
![]()
if
(!r)
![]()
![]()
if
(r->authdata_read)
![]()
![]()
else
![]()
![]()
riscv_authdata_write(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC == 1)
![]()
![]()
else
![]()
![]()
if
(!r->authdata_write)
![]()
![]()
riscv_dmi_read(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC != 1)
![]()
![]()
if
(!target)
![]()
![]()
if
(!r)
![]()
![]()
if
(r->dmi_read)
![]()
![]()
else
![]()
![]()
riscv_dmi_write(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC != 2)
![]()
![]()
if
(r->dmi_write)
![]()
![]()
else
![]()
![]()
riscv_reset_delays(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC > 1)
![]()
![]()
riscv_set_ir(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC != 2)
![]()
![]()
riscv_resume_order(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC > 1)
![]()
![]()
if
(!strcmp(CMD_ARGV[0], "normal"))
![]()
![]()
else if
(!strcmp(CMD_ARGV[0], "reversed"))
![]()
![]()
else
![]()
![]()
riscv_use_bscan_tunnel(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC > 2)
![]()
![]()
else if
(CMD_ARGC == 1)
![]()
![]()
else if
(CMD_ARGC == 2)
![]()
![]()
riscv_set_enable_virt2phys(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC != 1)
![]()
![]()
riscv_set_ebreakm(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC != 1)
![]()
![]()
riscv_set_ebreaks(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC != 1)
![]()
![]()
riscv_set_ebreaku(struct command_invocation *)
![]()
![]()
if
(CMD_ARGC != 1)
![]()
![]()
riscv_print_info_line(struct command_invocation *, const char *, const char *, unsigned int)
![]()
![]()
handle_info(struct command_invocation *)
![]()
![]()
riscv_exec_command_handlers
![]()
![]()
riscv_command_handlers
![]()
![]()
riscv_xlen_nonconst(struct target *)
![]()
![]()
riscv_data_bits(struct target *)
![]()
![]()
riscv_target
![]()
![]()
riscv_info_init(struct target *, struct riscv_info *)
![]()
![]()
riscv_resume_go_all_harts(struct target *)
![]()
![]()
if
(riscv_is_halted(target))
![]()
![]()
else
![]()
![]()
riscv_step_rtos_hart(struct target *)
![]()
![]()
if
(!riscv_is_halted(target))
![]()
![]()
if
(!riscv_is_halted(target))
![]()
![]()
riscv_supports_extension(struct target *, char)
![]()
![]()
riscv_xlen(const struct target *)
![]()
![]()
riscv_set_current_hartid(struct target *, int)
![]()
![]()
riscv_invalidate_register_cache(struct target *)
![]()
![]()
for
(size_t i = 0; i < target->reg_cache->num_regs; ++i)
![]()
![]()
riscv_current_hartid(const struct target *)
![]()
![]()
riscv_count_harts(struct target *)
![]()
![]()
gdb_regno_cacheable(enum gdb_regno, bool)
![]()
![]()
switch
(regno)
![]()
![]()
case
GDB_REGNO_DPC:
![]()
![]()
case
GDB_REGNO_VSTART:
![]()
![]()
case
GDB_REGNO_VXSAT:
![]()
![]()
case
GDB_REGNO_VXRM:
![]()
![]()
case
GDB_REGNO_VLENB:
![]()
![]()
case
GDB_REGNO_VL:
![]()
![]()
case
GDB_REGNO_VTYPE:
![]()
![]()
case
GDB_REGNO_MISA:
![]()
![]()
case
GDB_REGNO_DCSR:
![]()
![]()
case
GDB_REGNO_DSCRATCH0:
![]()
![]()
case
GDB_REGNO_MSTATUS:
![]()
![]()
case
GDB_REGNO_MEPC:
![]()
![]()
case
GDB_REGNO_MCAUSE:
![]()
![]()
case
GDB_REGNO_SATP:
![]()
![]()
case
GDB_REGNO_TSELECT:
![]()
![]()
case
GDB_REGNO_TDATA1:
![]()
![]()
case
GDB_REGNO_TDATA2:
![]()
![]()
default
![]()
![]()
riscv_set_register(struct target *, enum gdb_regno, riscv_reg_t)
![]()
![]()
riscv_get_register(struct target *, riscv_reg_t *, enum gdb_regno)
![]()
![]()
if
(!reg->exist)
![]()
![]()
if
(reg && reg->valid)
![]()
![]()
if
(regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 && riscv_supports_extension(target, 'E'))
![]()
![]()
riscv_is_halted(struct target *)
![]()
![]()
riscv_halt_reason(struct target *, int)
![]()
![]()
if
(!riscv_is_halted(target))
![]()
![]()
riscv_debug_buffer_size(struct target *)
![]()
![]()
riscv_write_debug_buffer(struct target *, int, riscv_insn_t)
![]()
![]()
riscv_read_debug_buffer(struct target *, int)
![]()
![]()
riscv_execute_debug_buffer(struct target *)
![]()
![]()
riscv_fill_dmi_write_u64(struct target *, char *, int, uint64_t)
![]()
![]()
riscv_fill_dmi_read_u64(struct target *, char *, int)
![]()
![]()
riscv_fill_dmi_nop_u64(struct target *, char *)
![]()
![]()
riscv_dmi_write_u64_bits(struct target *)
![]()
![]()
riscv_enumerate_triggers(struct target *)
![]()
![]()
if
(result != ERROR_OK)
![]()
![]()
for
(unsigned int t = 0; t < RISCV_MAX_TRIGGERS; ++t)
![]()
![]()
switch
(type)
![]()
![]()
case
1:
![]()
![]()
case
2:
![]()
![]()
case
6:
![]()
![]()
gdb_regno_name(enum gdb_regno)
![]()
![]()
switch
(regno)
![]()
![]()
case
GDB_REGNO_ZERO:
![]()
![]()
case
GDB_REGNO_RA:
![]()
![]()
case
GDB_REGNO_SP:
![]()
![]()
case
GDB_REGNO_GP:
![]()
![]()
case
GDB_REGNO_TP:
![]()
![]()
case
GDB_REGNO_T0:
![]()
![]()
case
GDB_REGNO_T1:
![]()
![]()
case
GDB_REGNO_T2:
![]()
![]()
case
GDB_REGNO_S0:
![]()
![]()
case
GDB_REGNO_S1:
![]()
![]()
case
GDB_REGNO_A0:
![]()
![]()
case
GDB_REGNO_A1:
![]()
![]()
case
GDB_REGNO_A2:
![]()
![]()
case
GDB_REGNO_A3:
![]()
![]()
case
GDB_REGNO_A4:
![]()
![]()
case
GDB_REGNO_A5:
![]()
![]()
case
GDB_REGNO_A6:
![]()
![]()
case
GDB_REGNO_A7:
![]()
![]()
case
GDB_REGNO_S2:
![]()
![]()
case
GDB_REGNO_S3:
![]()
![]()
case
GDB_REGNO_S4:
![]()
![]()
case
GDB_REGNO_S5:
![]()
![]()
case
GDB_REGNO_S6:
![]()
![]()
case
GDB_REGNO_S7:
![]()
![]()
case
GDB_REGNO_S8:
![]()
![]()
case
GDB_REGNO_S9:
![]()
![]()
case
GDB_REGNO_S10:
![]()
![]()
case
GDB_REGNO_S11:
![]()
![]()
case
GDB_REGNO_T3:
![]()
![]()
case
GDB_REGNO_T4:
![]()
![]()
case
GDB_REGNO_T5:
![]()
![]()
case
GDB_REGNO_T6:
![]()
![]()
case
GDB_REGNO_PC:
![]()
![]()
case
GDB_REGNO_FPR0:
![]()
![]()
case
GDB_REGNO_FPR31:
![]()
![]()
case
GDB_REGNO_CSR0:
![]()
![]()
case
GDB_REGNO_TSELECT:
![]()
![]()
case
GDB_REGNO_TDATA1:
![]()
![]()
case
GDB_REGNO_TDATA2:
![]()
![]()
case
GDB_REGNO_MISA:
![]()
![]()
case
GDB_REGNO_DPC:
![]()
![]()
case
GDB_REGNO_DCSR:
![]()
![]()
case
GDB_REGNO_DSCRATCH0:
![]()
![]()
case
GDB_REGNO_MSTATUS:
![]()
![]()
case
GDB_REGNO_MEPC:
![]()
![]()
case
GDB_REGNO_MCAUSE:
![]()
![]()
case
GDB_REGNO_PRIV:
![]()
![]()
case
GDB_REGNO_SATP:
![]()
![]()
case
GDB_REGNO_VTYPE:
![]()
![]()
case
GDB_REGNO_VL:
![]()
![]()
case
GDB_REGNO_V0:
![]()
![]()
case
GDB_REGNO_V1:
![]()
![]()
case
GDB_REGNO_V2:
![]()
![]()
case
GDB_REGNO_V3:
![]()
![]()
case
GDB_REGNO_V4:
![]()
![]()
case
GDB_REGNO_V5:
![]()
![]()
case
GDB_REGNO_V6:
![]()
![]()
case
GDB_REGNO_V7:
![]()
![]()
case
GDB_REGNO_V8:
![]()
![]()
case
GDB_REGNO_V9:
![]()
![]()
case
GDB_REGNO_V10:
![]()
![]()
case
GDB_REGNO_V11:
![]()
![]()
case
GDB_REGNO_V12:
![]()
![]()
case
GDB_REGNO_V13:
![]()
![]()
case
GDB_REGNO_V14:
![]()
![]()
case
GDB_REGNO_V15:
![]()
![]()
case
GDB_REGNO_V16:
![]()
![]()
case
GDB_REGNO_V17:
![]()
![]()
case
GDB_REGNO_V18:
![]()
![]()
case
GDB_REGNO_V19:
![]()
![]()
case
GDB_REGNO_V20:
![]()
![]()
case
GDB_REGNO_V21:
![]()
![]()
case
GDB_REGNO_V22:
![]()
![]()
case
GDB_REGNO_V23:
![]()
![]()
case
GDB_REGNO_V24:
![]()
![]()
case
GDB_REGNO_V25:
![]()
![]()
case
GDB_REGNO_V26:
![]()
![]()
case
GDB_REGNO_V27:
![]()
![]()
case
GDB_REGNO_V28:
![]()
![]()
case
GDB_REGNO_V29:
![]()
![]()
case
GDB_REGNO_V30:
![]()
![]()
case
GDB_REGNO_V31:
![]()
![]()
default
![]()
![]()
register_get(struct reg *)
![]()
![]()
if
(reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31)
![]()
![]()
if
(!r->get_register_buf)
![]()
![]()
else
![]()
![]()
register_set(struct reg *, uint8_t *)
![]()
![]()
if
(reg->number == GDB_REGNO_TDATA1 || reg->number == GDB_REGNO_TDATA2)
![]()
![]()
if
(reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31)
![]()
![]()
if
(!r->set_register_buf)
![]()
![]()
else
![]()
![]()
riscv_reg_arch_type
![]()
![]()
csr_info
![]()
![]()
number
![]()
![]()
name
![]()
![]()
cmp_csr_info(const void *, const void *)
![]()
![]()
riscv_init_registers(struct target *)
![]()
![]()
if
(!list_empty(&info->expose_custom))
![]()
![]()
if
(info->vlenb >= 2)
![]()
![]()
else
![]()
![]()
if
(info->vlenb >= 4)
![]()
![]()
else
![]()
![]()
if
(info->vlenb >= 8)
![]()
![]()
else
![]()
![]()
if
(info->vlenb >= 16)
![]()
![]()
else
![]()
![]()
for
(uint32_t number = 0; number < target->reg_cache->num_regs; number++)
![]()
![]()
if
(number <= GDB_REGNO_XPR31)
![]()
![]()
switch
(number)
![]()
![]()
case
GDB_REGNO_ZERO:
![]()
![]()
case
GDB_REGNO_RA:
![]()
![]()
case
GDB_REGNO_SP:
![]()
![]()
case
GDB_REGNO_GP:
![]()
![]()
case
GDB_REGNO_TP:
![]()
![]()
case
GDB_REGNO_T0:
![]()
![]()
case
GDB_REGNO_T1:
![]()
![]()
case
GDB_REGNO_T2:
![]()
![]()
case
GDB_REGNO_FP:
![]()
![]()
case
GDB_REGNO_S1:
![]()
![]()
case
GDB_REGNO_A0:
![]()
![]()
case
GDB_REGNO_A1:
![]()
![]()
case
GDB_REGNO_A2:
![]()
![]()
case
GDB_REGNO_A3:
![]()
![]()
case
GDB_REGNO_A4:
![]()
![]()
case
GDB_REGNO_A5:
![]()
![]()
case
GDB_REGNO_A6:
![]()
![]()
case
GDB_REGNO_A7:
![]()
![]()
case
GDB_REGNO_S2:
![]()
![]()
case
GDB_REGNO_S3:
![]()
![]()
case
GDB_REGNO_S4:
![]()
![]()
case
GDB_REGNO_S5:
![]()
![]()
case
GDB_REGNO_S6:
![]()
![]()
case
GDB_REGNO_S7:
![]()
![]()
case
GDB_REGNO_S8:
![]()
![]()
case
GDB_REGNO_S9:
![]()
![]()
case
GDB_REGNO_S10:
![]()
![]()
case
GDB_REGNO_S11:
![]()
![]()
case
GDB_REGNO_T3:
![]()
![]()
case
GDB_REGNO_T4:
![]()
![]()
case
GDB_REGNO_T5:
![]()
![]()
case
GDB_REGNO_T6:
![]()
![]()
else if
(number == GDB_REGNO_PC)
![]()
![]()
else if
(number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31)
![]()
![]()
if
(riscv_supports_extension(target, 'D'))
![]()
![]()
else if
(riscv_supports_extension(target, 'F'))
![]()
![]()
else
![]()
![]()
switch
(number)
![]()
![]()
case
GDB_REGNO_FT0:
![]()
![]()
case
GDB_REGNO_FT1:
![]()
![]()
case
GDB_REGNO_FT2:
![]()
![]()
case
GDB_REGNO_FT3:
![]()
![]()
case
GDB_REGNO_FT4:
![]()
![]()
case
GDB_REGNO_FT5:
![]()
![]()
case
GDB_REGNO_FT6:
![]()
![]()
case
GDB_REGNO_FT7:
![]()
![]()
case
GDB_REGNO_FS0:
![]()
![]()
case
GDB_REGNO_FS1:
![]()
![]()
case
GDB_REGNO_FA0:
![]()
![]()
case
GDB_REGNO_FA1:
![]()
![]()
case
GDB_REGNO_FA2:
![]()
![]()
case
GDB_REGNO_FA3:
![]()
![]()
case
GDB_REGNO_FA4:
![]()
![]()
case
GDB_REGNO_FA5:
![]()
![]()
case
GDB_REGNO_FA6:
![]()
![]()
case
GDB_REGNO_FA7:
![]()
![]()
case
GDB_REGNO_FS2:
![]()
![]()
case
GDB_REGNO_FS3:
![]()
![]()
case
GDB_REGNO_FS4:
![]()
![]()
case
GDB_REGNO_FS5:
![]()
![]()
case
GDB_REGNO_FS6:
![]()
![]()
case
GDB_REGNO_FS7:
![]()
![]()
case
GDB_REGNO_FS8:
![]()
![]()
case
GDB_REGNO_FS9:
![]()
![]()
case
GDB_REGNO_FS10:
![]()
![]()
case
GDB_REGNO_FS11:
![]()
![]()
case
GDB_REGNO_FT8:
![]()
![]()
case
GDB_REGNO_FT9:
![]()
![]()
case
GDB_REGNO_FT10:
![]()
![]()
case
GDB_REGNO_FT11:
![]()
![]()
else if
(number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095)
![]()
![]()
while
(csr_info[csr_info_index].number < csr_number && csr_info_index < ARRAY_SIZE(csr_info) - 1)
![]()
![]()
if
(csr_info[csr_info_index].number == csr_number)
![]()
![]()
else
![]()
![]()
switch
(csr_number)
![]()
![]()
case
CSR_FFLAGS:
![]()
![]()
case
CSR_FRM:
![]()
![]()
case
CSR_FCSR:
![]()
![]()
case
CSR_SSTATUS:
![]()
![]()
case
CSR_STVEC:
![]()
![]()
case
CSR_SIP:
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case
CSR_SIE:
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case
CSR_SCOUNTEREN:
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case
CSR_SSCRATCH:
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case
CSR_SEPC:
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case
CSR_SCAUSE:
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case
CSR_STVAL:
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case
CSR_SATP:
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case
CSR_MEDELEG:
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case
CSR_MIDELEG:
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case
CSR_PMPCFG1:
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case
CSR_PMPCFG3:
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case
CSR_CYCLEH:
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case
CSR_TIMEH:
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case
CSR_INSTRETH:
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case
CSR_HPMCOUNTER3H:
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case
CSR_HPMCOUNTER4H:
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case
CSR_HPMCOUNTER5H:
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![]()
case
CSR_HPMCOUNTER6H:
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case
CSR_HPMCOUNTER7H:
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![]()
case
CSR_HPMCOUNTER8H:
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case
CSR_HPMCOUNTER9H:
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case
CSR_HPMCOUNTER10H:
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case
CSR_HPMCOUNTER11H:
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case
CSR_HPMCOUNTER12H:
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![]()
case
CSR_HPMCOUNTER13H:
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case
CSR_HPMCOUNTER14H:
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case
CSR_HPMCOUNTER15H:
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![]()
case
CSR_HPMCOUNTER16H:
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![]()
case
CSR_HPMCOUNTER17H:
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![]()
case
CSR_HPMCOUNTER18H:
![]()
![]()
case
CSR_HPMCOUNTER19H:
![]()
![]()
case
CSR_HPMCOUNTER20H:
![]()
![]()
case
CSR_HPMCOUNTER21H:
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![]()
case
CSR_HPMCOUNTER22H:
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![]()
case
CSR_HPMCOUNTER23H:
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![]()
case
CSR_HPMCOUNTER24H:
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![]()
case
CSR_HPMCOUNTER25H:
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![]()
case
CSR_HPMCOUNTER26H:
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![]()
case
CSR_HPMCOUNTER27H:
![]()
![]()
case
CSR_HPMCOUNTER28H:
![]()
![]()
case
CSR_HPMCOUNTER29H:
![]()
![]()
case
CSR_HPMCOUNTER30H:
![]()
![]()
case
CSR_HPMCOUNTER31H:
![]()
![]()
case
CSR_MCYCLEH:
![]()
![]()
case
CSR_MINSTRETH:
![]()
![]()
case
CSR_MHPMCOUNTER3H:
![]()
![]()
case
CSR_MHPMCOUNTER4H:
![]()
![]()
case
CSR_MHPMCOUNTER5H:
![]()
![]()
case
CSR_MHPMCOUNTER6H:
![]()
![]()
case
CSR_MHPMCOUNTER7H:
![]()
![]()
case
CSR_MHPMCOUNTER8H:
![]()
![]()
case
CSR_MHPMCOUNTER9H:
![]()
![]()
case
CSR_MHPMCOUNTER10H:
![]()
![]()
case
CSR_MHPMCOUNTER11H:
![]()
![]()
case
CSR_MHPMCOUNTER12H:
![]()
![]()
case
CSR_MHPMCOUNTER13H:
![]()
![]()
case
CSR_MHPMCOUNTER14H:
![]()
![]()
case
CSR_MHPMCOUNTER15H:
![]()
![]()
case
CSR_MHPMCOUNTER16H:
![]()
![]()
case
CSR_MHPMCOUNTER17H:
![]()
![]()
case
CSR_MHPMCOUNTER18H:
![]()
![]()
case
CSR_MHPMCOUNTER19H:
![]()
![]()
case
CSR_MHPMCOUNTER20H:
![]()
![]()
case
CSR_MHPMCOUNTER21H:
![]()
![]()
case
CSR_MHPMCOUNTER22H:
![]()
![]()
case
CSR_MHPMCOUNTER23H:
![]()
![]()
case
CSR_MHPMCOUNTER24H:
![]()
![]()
case
CSR_MHPMCOUNTER25H:
![]()
![]()
case
CSR_MHPMCOUNTER26H:
![]()
![]()
case
CSR_MHPMCOUNTER27H:
![]()
![]()
case
CSR_MHPMCOUNTER28H:
![]()
![]()
case
CSR_MHPMCOUNTER29H:
![]()
![]()
case
CSR_MHPMCOUNTER30H:
![]()
![]()
case
CSR_MHPMCOUNTER31H:
![]()
![]()
case
CSR_VSTART:
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![]()
case
CSR_VXSAT:
![]()
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case
CSR_VXRM:
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![]()
case
CSR_VL:
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![]()
case
CSR_VTYPE:
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![]()
case
CSR_VLENB:
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if
(!r->exist && !list_empty(&info->expose_csr))
![]()
![]()
if
((entry->low <= csr_number) && (csr_number <= entry->high))
![]()
![]()
if
(entry->name)
![]()
![]()
else if
(number == GDB_REGNO_PRIV)
![]()
![]()
else if
(number >= GDB_REGNO_V0 && number <= GDB_REGNO_V31)
![]()
![]()
else if
(number >= GDB_REGNO_COUNT)
![]()
![]()
if
(range->name)
![]()
![]()
if
(custom_within_range > range->high - range->low)
![]()
![]()
if
(reg_name[0])
![]()
![]()
riscv_add_bscan_tunneled_scan(struct target *, struct scan_field *, riscv_bscan_tunneled_scan_context_t *)
![]()
![]()
if
(bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
![]()
![]()
else