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/* ... */
/* ... */
/* ... */
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "jtag/interface.h"
#include "arm.h"
#include "arm_adi_v5.h"
#include "arm_coresight.h"
#include "jtag/swd.h"
#include "transport/transport.h"
#include <helper/align.h>
#include <helper/jep106.h>
#include <helper/time_support.h>
#include <helper/list.h>
#include <helper/jim-nvp.h>
11 includes
/* ... */
static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, target_addr_t address)
{
return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
}{ ... }
/* ... */
static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
{
csw |= ap->csw_default;
if (csw != ap->csw_value) {
int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW(ap->dap), csw);
if (retval != ERROR_OK) {
ap->csw_value = 0;
return retval;
}if (retval != ERROR_OK) { ... }
ap->csw_value = csw;
}if (csw != ap->csw_value) { ... }
return ERROR_OK;
}{ ... }
static int mem_ap_setup_tar(struct adiv5_ap *ap, target_addr_t tar)
{
if (!ap->tar_valid || tar != ap->tar_value) {
int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR(ap->dap), (uint32_t)(tar & 0xffffffffUL));
if (retval == ERROR_OK && is_64bit_ap(ap)) {
if (!ap->tar_valid || (ap->tar_value >> 32) != (tar >> 32))
retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR64(ap->dap), (uint32_t)(tar >> 32));
}if (retval == ERROR_OK && is_64bit_ap(ap)) { ... }
if (retval != ERROR_OK) {
ap->tar_valid = false;
return retval;
}if (retval != ERROR_OK) { ... }
ap->tar_value = tar;
ap->tar_valid = true;
}if (!ap->tar_valid || tar != ap->tar_value) { ... }
return ERROR_OK;
}{ ... }
static int mem_ap_read_tar(struct adiv5_ap *ap, target_addr_t *tar)
{
uint32_t lower;
uint32_t upper = 0;
int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR(ap->dap), &lower);
if (retval == ERROR_OK && is_64bit_ap(ap))
retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR64(ap->dap), &upper);
if (retval != ERROR_OK) {
ap->tar_valid = false;
return retval;
}if (retval != ERROR_OK) { ... }
retval = dap_run(ap->dap);
if (retval != ERROR_OK) {
ap->tar_valid = false;
return retval;
}if (retval != ERROR_OK) { ... }
*tar = (((target_addr_t)upper) << 32) | (target_addr_t)lower;
ap->tar_value = *tar;
ap->tar_valid = true;
return ERROR_OK;
}{ ... }
static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
{
switch (ap->csw_value & CSW_ADDRINC_MASK) {
case CSW_ADDRINC_SINGLE:
switch (ap->csw_value & CSW_SIZE_MASK) {
case CSW_8BIT:
return 1;case CSW_8BIT:
case CSW_16BIT:
return 2;case CSW_16BIT:
case CSW_32BIT:
return 4;case CSW_32BIT:
case CSW_64BIT:
return 8;case CSW_64BIT:
case CSW_128BIT:
return 16;case CSW_128BIT:
case CSW_256BIT:
return 32;case CSW_256BIT:
default:
return 0;default
}switch (ap->csw_value & CSW_SIZE_MASK) { ... }
case CSW_ADDRINC_SINGLE: case CSW_ADDRINC_PACKED:
return 4;case CSW_ADDRINC_PACKED:
}switch (ap->csw_value & CSW_ADDRINC_MASK) { ... }
return 0;
}{ ... }
/* ... */
static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
{
if (!ap->tar_valid)
return;
uint32_t inc = mem_ap_get_tar_increment(ap);
if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
ap->tar_valid = false;
else
ap->tar_value += inc;
}{ ... }
/* ... */
static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, target_addr_t tar)
{
int retval;
retval = mem_ap_setup_csw(ap, csw);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_setup_tar(ap, tar);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}{ ... }
/* ... */
int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address,
uint32_t *value)
{
int retval;
/* ... */
retval = mem_ap_setup_transfer(ap,
CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
address & 0xFFFFFFFFFFFFFFF0ull);
if (retval != ERROR_OK)
return retval;
return dap_queue_ap_read(ap, MEM_AP_REG_BD0(ap->dap) | (address & 0xC), value);
}{ ... }
/* ... */
int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address,
uint32_t *value)
{
int retval;
retval = mem_ap_read_u32(ap, address, value);
if (retval != ERROR_OK)
return retval;
return dap_run(ap->dap);
}{ ... }
/* ... */
int mem_ap_write_u32(struct adiv5_ap *ap, target_addr_t address,
uint32_t value)
{
int retval;
/* ... */
retval = mem_ap_setup_transfer(ap,
CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
address & 0xFFFFFFFFFFFFFFF0ull);
if (retval != ERROR_OK)
return retval;
return dap_queue_ap_write(ap, MEM_AP_REG_BD0(ap->dap) | (address & 0xC),
value);
}{ ... }
/* ... */
int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address,
uint32_t value)
{
int retval = mem_ap_write_u32(ap, address, value);
if (retval != ERROR_OK)
return retval;
return dap_run(ap->dap);
}{ ... }
/* ... */
static int mem_ap_setup_transfer_verify_size_packing(struct adiv5_ap *ap,
unsigned int size, target_addr_t address,
bool addrinc, bool pack, unsigned int *this_size)
{
int retval;
uint32_t csw_size;
switch (size) {
case 1:
csw_size = CSW_8BIT;
break;case 1:
case 2:
csw_size = CSW_16BIT;
break;case 2:
case 4:
csw_size = CSW_32BIT;
break;case 4:
case 8:
csw_size = CSW_64BIT;
break;case 8:
case 16:
csw_size = CSW_128BIT;
break;case 16:
case 32:
csw_size = CSW_256BIT;
break;case 32:
default:
LOG_ERROR("Size %u not supported", size);
return ERROR_TARGET_SIZE_NOT_SUPPORTED;default
}switch (size) { ... }
if (!addrinc || size >= 4
|| (ap->packed_transfers_probed && !ap->packed_transfers_supported)
|| max_tar_block_size(ap->tar_autoincr_block, address) < 4)
pack = false;
uint32_t csw_addrinc = pack ? CSW_ADDRINC_PACKED :
addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
retval = mem_ap_setup_csw(ap, csw_size | csw_addrinc);
if (retval != ERROR_OK)
return retval;
bool do_probe = !(ap->csw_size_probed_mask & size)
|| (pack && !ap->packed_transfers_probed);
if (do_probe) {
uint32_t csw_readback;
retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW(ap->dap), &csw_readback);
if (retval != ERROR_OK)
return retval;
retval = dap_run(ap->dap);
if (retval != ERROR_OK)
return retval;
bool size_supported = ((csw_readback & CSW_SIZE_MASK) == csw_size);
LOG_DEBUG("AP#0x%" PRIx64 " probed size %u: %s", ap->ap_num, size,
size_supported ? "supported" : "not supported");
ap->csw_size_probed_mask |= size;
if (size_supported) {
ap->csw_size_supported_mask |= size;
if (pack && !ap->packed_transfers_probed) {
ap->packed_transfers_probed = true;
ap->packed_transfers_supported =
((csw_readback & CSW_ADDRINC_MASK) == csw_addrinc);
LOG_DEBUG("probed packing: %s",
ap->packed_transfers_supported ? "supported" : "not supported");
}if (pack && !ap->packed_transfers_probed) { ... }
}if (size_supported) { ... }
}if (do_probe) { ... }
if (!(ap->csw_size_supported_mask & size)) {
LOG_ERROR("Size %u not supported", size);
return ERROR_TARGET_SIZE_NOT_SUPPORTED;
}if (!(ap->csw_size_supported_mask & size)) { ... }
if (pack && !ap->packed_transfers_supported)
return ERROR_TARGET_PACKING_NOT_SUPPORTED;
*this_size = pack ? 4 : size;
return mem_ap_setup_tar(ap, address);
}{ ... }
/* ... */
static int mem_ap_setup_transfer_verify_size_packing_fallback(struct adiv5_ap *ap,
unsigned int size, target_addr_t address,
bool addrinc, bool pack, unsigned int *this_size)
{
int retval = mem_ap_setup_transfer_verify_size_packing(ap,
size, address,
addrinc, pack, this_size);
if (retval == ERROR_TARGET_PACKING_NOT_SUPPORTED) {
retval = mem_ap_setup_transfer_verify_size_packing(ap,
size, address,
addrinc, false, this_size);
}if (retval == ERROR_TARGET_PACKING_NOT_SUPPORTED) { ... }
return retval;
}{ ... }
/* ... */
static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
target_addr_t address, bool addrinc)
{
struct adiv5_dap *dap = ap->dap;
size_t nbytes = size * count;
int retval = ERROR_OK;
/* ... */
target_addr_t ti_be_addr_xor = 0;
target_addr_t ti_be_lane_xor = 0;
if (dap->ti_be_32_quirks) {
ti_be_lane_xor = 3;
switch (size) {
case 1:
ti_be_addr_xor = 3;
break;case 1:
case 2:
ti_be_addr_xor = 2;
break;case 2:
case 4:
break;case 4:
default:
LOG_ERROR("Write more than 32 bits not supported with ti_be_32_quirks");
return ERROR_TARGET_SIZE_NOT_SUPPORTED;default
}switch (size) { ... }
}if (dap->ti_be_32_quirks) { ... }
if (ap->unaligned_access_bad && (address % size != 0))
return ERROR_TARGET_UNALIGNED_ACCESS;
bool pack = !dap->nu_npcx_quirks;
while (nbytes > 0) {
unsigned int this_size;
retval = mem_ap_setup_transfer_verify_size_packing_fallback(ap,
size, address ^ ti_be_addr_xor,
addrinc, pack && nbytes >= 4, &this_size);
if (retval != ERROR_OK)
return retval;
/* ... */
uint32_t drw_byte_idx = address;
unsigned int drw_ops = DIV_ROUND_UP(this_size, 4);
while (drw_ops--) {
uint32_t outvalue = 0;
if (dap->nu_npcx_quirks && this_size <= 2) {
switch (this_size) {
case 2:
{
uint32_t low = *buffer++;
uint32_t high = *buffer++;
outvalue |= low << 8 * (drw_byte_idx++ & 3);
outvalue |= high << 8 * (drw_byte_idx++ & 3);
outvalue |= low << 8 * (drw_byte_idx++ & 3);
outvalue |= high << 8 * (drw_byte_idx & 3);
...}
break;case 2:
case 1:
{
uint32_t data = *buffer++;
outvalue |= data;
outvalue |= data << 8;
outvalue |= data << 16;
outvalue |= data << 24;
...}case 1:
}switch (this_size) { ... }
}if (dap->nu_npcx_quirks && this_size <= 2) { ... } else {
unsigned int drw_bytes = MIN(this_size, 4);
while (drw_bytes--)
outvalue |= (uint32_t)*buffer++ <<
8 * ((drw_byte_idx++ & 3) ^ ti_be_lane_xor);
}else { ... }
retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW(dap), outvalue);
if (retval != ERROR_OK)
break;
}while (drw_ops--) { ... }
if (retval != ERROR_OK)
break;
mem_ap_update_tar_cache(ap);
nbytes -= this_size;
if (addrinc)
address += this_size;
}while (nbytes > 0) { ... }
if (retval == ERROR_OK)
retval = dap_run(dap);
if (retval != ERROR_OK) {
target_addr_t tar;
if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
LOG_ERROR("Failed to write memory at " TARGET_ADDR_FMT, tar);
else
LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
}if (retval != ERROR_OK) { ... }
return retval;
}{ ... }
/* ... */
static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
target_addr_t adr, bool addrinc)
{
struct adiv5_dap *dap = ap->dap;
size_t nbytes = size * count;
target_addr_t address = adr;
int retval = ERROR_OK;
/* ... */
if (dap->ti_be_32_quirks && size > 4) {
LOG_ERROR("Read more than 32 bits not supported with ti_be_32_quirks");
return ERROR_TARGET_SIZE_NOT_SUPPORTED;
}if (dap->ti_be_32_quirks && size > 4) { ... }
if (ap->unaligned_access_bad && (adr % size != 0))
return ERROR_TARGET_UNALIGNED_ACCESS;
/* ... */
uint32_t *read_buf = calloc(count, MAX(sizeof(uint32_t), size));
uint32_t *read_ptr = read_buf;
if (!read_buf) {
LOG_ERROR("Failed to allocate read buffer");
return ERROR_FAIL;
}if (!read_buf) { ... }
/* ... */
while (nbytes > 0) {
unsigned int this_size;
retval = mem_ap_setup_transfer_verify_size_packing_fallback(ap,
size, address,
addrinc, nbytes >= 4, &this_size);
if (retval != ERROR_OK)
break;
unsigned int drw_ops = DIV_ROUND_UP(this_size, 4);
while (drw_ops--) {
retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW(dap), read_ptr++);
if (retval != ERROR_OK)
break;
}while (drw_ops--) { ... }
nbytes -= this_size;
if (addrinc)
address += this_size;
mem_ap_update_tar_cache(ap);
}while (nbytes > 0) { ... }
if (retval == ERROR_OK)
retval = dap_run(dap);
address = adr;
nbytes = size * count;
read_ptr = read_buf;
/* ... */
if (retval == ERROR_TARGET_SIZE_NOT_SUPPORTED) {
nbytes = 0;
}if (retval == ERROR_TARGET_SIZE_NOT_SUPPORTED) { ... } else if (retval != ERROR_OK) {
target_addr_t tar;
if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
LOG_ERROR("Failed to read memory at " TARGET_ADDR_FMT, tar);
if (nbytes > tar - address)
nbytes = tar - address;
}if (mem_ap_read_tar(ap, &tar) == ERROR_OK) { ... } else {
LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
nbytes = 0;
}else { ... }
}else if (retval != ERROR_OK) { ... }
target_addr_t ti_be_lane_xor = dap->ti_be_32_quirks ? 3 : 0;
while (nbytes > 0) {
unsigned int this_size = MIN(size, 4);
if (size < 4 && addrinc && ap->packed_transfers_supported && nbytes >= 4
&& max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
this_size = 4;
}if (size < 4 && addrinc && ap->packed_transfers_supported && nbytes >= 4 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) { ... }
switch (this_size) {
case 4:
*buffer++ = *read_ptr >> 8 * ((address++ & 3) ^ ti_be_lane_xor);
*buffer++ = *read_ptr >> 8 * ((address++ & 3) ^ ti_be_lane_xor);
case 4:
case 2:
*buffer++ = *read_ptr >> 8 * ((address++ & 3) ^ ti_be_lane_xor);
case 2:
case 1:
*buffer++ = *read_ptr >> 8 * ((address++ & 3) ^ ti_be_lane_xor);case 1:
}switch (this_size) { ... }
read_ptr++;
nbytes -= this_size;
}while (nbytes > 0) { ... }
free(read_buf);
return retval;
}{ ... }
int mem_ap_read_buf(struct adiv5_ap *ap,
uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
{
return mem_ap_read(ap, buffer, size, count, address, true);
}{ ... }
int mem_ap_write_buf(struct adiv5_ap *ap,
const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
{
return mem_ap_write(ap, buffer, size, count, address, true);
}{ ... }
int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
{
return mem_ap_read(ap, buffer, size, count, address, false);
}{ ... }
int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
{
return mem_ap_write(ap, buffer, size, count, address, false);
}{ ... }
#define DAP_POWER_DOMAIN_TIMEOUT (10)
/* ... */
void dap_invalidate_cache(struct adiv5_dap *dap)
{
dap->select = 0;
dap->select_valid = false;
dap->select1_valid = false;
dap->select_dpbanksel_valid = false;
dap->last_read = NULL;
int i;
for (i = 0; i <= DP_APSEL_MAX; i++) {
dap->ap[i].tar_valid = false;
dap->ap[i].csw_value = 0;
}for (i = 0; i <= DP_APSEL_MAX; i++) { ... }
}{ ... }
/* ... */
int dap_dp_init(struct adiv5_dap *dap)
{
int retval;
LOG_DEBUG("%s", adiv5_dap_name(dap));
dap->do_reconnect = false;
dap_invalidate_cache(dap);
/* ... */
dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
/* ... */
retval = dap_queue_dp_write(dap, DP_CTRL_STAT,
dap->dp_ctrl_stat | SSTICKYERR | SSTICKYORUN);
if (retval != ERROR_OK)
return retval;
retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
if (retval != ERROR_OK)
return retval;
retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("DAP: wait CDBGPWRUPACK");
retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
CDBGPWRUPACK, CDBGPWRUPACK,
DAP_POWER_DOMAIN_TIMEOUT);
if (retval != ERROR_OK)
return retval;
if (!dap->ignore_syspwrupack) {
LOG_DEBUG("DAP: wait CSYSPWRUPACK");
retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
CSYSPWRUPACK, CSYSPWRUPACK,
DAP_POWER_DOMAIN_TIMEOUT);
if (retval != ERROR_OK)
return retval;
}if (!dap->ignore_syspwrupack) { ... }
retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
if (retval != ERROR_OK)
return retval;
dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
if (retval != ERROR_OK)
return retval;
retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
if (retval != ERROR_OK)
return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
return retval;
}{ ... }
/* ... */
int dap_dp_init_or_reconnect(struct adiv5_dap *dap)
{
LOG_DEBUG("%s", adiv5_dap_name(dap));
/* ... */
dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
dap->do_reconnect = false;
dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
if (dap->do_reconnect) {
return dap->ops->connect(dap);
}if (dap->do_reconnect) { ... } else {
return dap_dp_init(dap);
}else { ... }
}{ ... }
/* ... */
int mem_ap_init(struct adiv5_ap *ap)
{
uint32_t cfg;
int retval;
struct adiv5_dap *dap = ap->dap;
retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG(dap), &cfg);
if (retval != ERROR_OK)
return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
ap->cfg_reg = cfg;
ap->tar_valid = false;
ap->csw_value = 0;
ap->csw_size_supported_mask = BIT(CSW_32BIT);
ap->csw_size_probed_mask = BIT(CSW_32BIT);
if (!(cfg & MEM_AP_REG_CFG_LD))
ap->csw_size_probed_mask |= BIT(CSW_64BIT) | BIT(CSW_128BIT) | BIT(CSW_256BIT);
/* ... */
ap->packed_transfers_supported = false;
ap->packed_transfers_probed = dap->ti_be_32_quirks ? true : false;
/* ... */
ap->unaligned_access_bad = dap->ti_be_32_quirks;
LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
!!(cfg & MEM_AP_REG_CFG_LD), !!(cfg & MEM_AP_REG_CFG_LA), !!(cfg & MEM_AP_REG_CFG_BE));
return ERROR_OK;
}{ ... }
/* ... */
int dap_to_swd(struct adiv5_dap *dap)
{
LOG_DEBUG("Enter SWD mode");
return dap_send_sequence(dap, JTAG_TO_SWD);
}{ ... }
/* ... */
int dap_to_jtag(struct adiv5_dap *dap)
{
LOG_DEBUG("Enter JTAG mode");
return dap_send_sequence(dap, SWD_TO_JTAG);
}{ ... }
/* ... */
static const char *class_description[16] = {
[0x0] = "Generic verification component",
[0x1] = "ROM table",
[0x2] = "Reserved",
[0x3] = "Reserved",
[0x4] = "Reserved",
[0x5] = "Reserved",
[0x6] = "Reserved",
[0x7] = "Reserved",
[0x8] = "Reserved",
[0x9] = "CoreSight component",
[0xA] = "Reserved",
[0xB] = "Peripheral Test Block",
[0xC] = "Reserved",
[0xD] = "OptimoDE DESS",
[0xE] = "Generic IP component",
[0xF] = "CoreLink, PrimeCell or System component",
...};
#define ARCH_ID(architect, archid) ( \
(((architect) << ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT) & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) | \
(((archid) << ARM_CS_C9_DEVARCH_ARCHID_SHIFT) & ARM_CS_C9_DEVARCH_ARCHID_MASK) \
)...
static const struct {
uint32_t arch_id;
const char *description;
...} class0x9_devarch[] = {
{ ARCH_ID(ARM_ID, 0x0A00), "RAS architecture" },
{ ARCH_ID(ARM_ID, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" },
{ ARCH_ID(ARM_ID, 0x1A02), "DWT architecture" },
{ ARCH_ID(ARM_ID, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" },
{ ARCH_ID(ARM_ID, 0x2A04), "Processor debug architecture (ARMv8-M)" },
{ ARCH_ID(ARM_ID, 0x6A05), "Processor debug architecture (ARMv8-R)" },
{ ARCH_ID(ARM_ID, 0x0A10), "PC sample-based profiling" },
{ ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" },
{ ARCH_ID(ARM_ID, 0x1A14), "Cross Trigger Interface (CTI) architecture" },
{ ARCH_ID(ARM_ID, 0x6A15), "Processor debug architecture (v8.0-A)" },
{ ARCH_ID(ARM_ID, 0x7A15), "Processor debug architecture (v8.1-A)" },
{ ARCH_ID(ARM_ID, 0x8A15), "Processor debug architecture (v8.2-A)" },
{ ARCH_ID(ARM_ID, 0x2A16), "Processor Performance Monitor (PMU) architecture" },
{ ARCH_ID(ARM_ID, 0x0A17), "Memory Access Port v2 architecture" },
{ ARCH_ID(ARM_ID, 0x0A27), "JTAG Access Port v2 architecture" },
{ ARCH_ID(ARM_ID, 0x0A31), "Basic trace router" },
{ ARCH_ID(ARM_ID, 0x0A37), "Power requestor" },
{ ARCH_ID(ARM_ID, 0x0A47), "Unknown Access Port v2 architecture" },
{ ARCH_ID(ARM_ID, 0x0A50), "HSSTP architecture" },
{ ARCH_ID(ARM_ID, 0x0A63), "System Trace Macrocell (STM) architecture" },
{ ARCH_ID(ARM_ID, 0x0A75), "CoreSight ELA architecture" },
{ ARCH_ID(ARM_ID, 0x0AF7), "CoreSight ROM architecture" },
...};
#define DEVARCH_ID_MASK (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
#define DEVARCH_MEM_AP ARCH_ID(ARM_ID, 0x0A17)
#define DEVARCH_ROM_C_0X9 ARCH_ID(ARM_ID, 0x0AF7)
#define DEVARCH_UNKNOWN_V2 ARCH_ID(ARM_ID, 0x0A47)
static const char *class0x9_devarch_description(uint32_t devarch)
{
if (!(devarch & ARM_CS_C9_DEVARCH_PRESENT))
return "not present";
for (unsigned int i = 0; i < ARRAY_SIZE(class0x9_devarch); i++)
if ((devarch & DEVARCH_ID_MASK) == class0x9_devarch[i].arch_id)
return class0x9_devarch[i].description;
return "unknown";
}{ ... }
static const struct {
enum ap_type type;
const char *description;
...} ap_types[] = {
{ AP_TYPE_JTAG_AP, "JTAG-AP" },
{ AP_TYPE_COM_AP, "COM-AP" },
{ AP_TYPE_AHB3_AP, "MEM-AP AHB3" },
{ AP_TYPE_APB_AP, "MEM-AP APB2 or APB3" },
{ AP_TYPE_AXI_AP, "MEM-AP AXI3 or AXI4" },
{ AP_TYPE_AHB5_AP, "MEM-AP AHB5" },
{ AP_TYPE_APB4_AP, "MEM-AP APB4" },
{ AP_TYPE_AXI5_AP, "MEM-AP AXI5" },
{ AP_TYPE_AHB5H_AP, "MEM-AP AHB5 with enhanced HPROT" },
...};
static const char *ap_type_to_description(enum ap_type type)
{
for (unsigned int i = 0; i < ARRAY_SIZE(ap_types); i++)
if (type == ap_types[i].type)
return ap_types[i].description;
return "Unknown";
}{ ... }
bool is_ap_num_valid(struct adiv5_dap *dap, uint64_t ap_num)
{
if (!dap)
return false;
/* ... */
if (!is_adiv6(dap)) {
if (ap_num > DP_APSEL_MAX)
return false;
return true;
}if (!is_adiv6(dap)) { ... }
if (is_adiv6(dap)) {
if (ap_num & 0x0fffULL)
return false;
if (dap->asize != 0)
if (ap_num & ((~0ULL) << dap->asize))
return false;
return true;
}if (is_adiv6(dap)) { ... }
return false;
}{ ... }
/* ... */
int dap_find_get_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
{
if (is_adiv6(dap)) {
LOG_DEBUG("On ADIv6 we cannot scan all the possible AP");
return ERROR_FAIL;
}if (is_adiv6(dap)) { ... }
for (unsigned int ap_num = 0; ap_num <= DP_APSEL_MAX; ap_num++) {
struct adiv5_ap *ap = dap_get_ap(dap, ap_num);
if (!ap)
continue;
uint32_t id_val = 0;
int retval = dap_queue_ap_read(ap, AP_REG_IDR(dap), &id_val);
if (retval != ERROR_OK) {
dap_put_ap(ap);
return retval;
}if (retval != ERROR_OK) { ... }
retval = dap_run(dap);
/* ... */
if (retval == ERROR_OK && (id_val & AP_TYPE_MASK) == type_to_find) {
LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
ap_type_to_description(type_to_find),
ap_num, id_val);
*ap_out = ap;
return ERROR_OK;
}if (retval == ERROR_OK && (id_val & AP_TYPE_MASK) == type_to_find) { ... }
dap_put_ap(ap);
}for (unsigned int ap_num = 0; ap_num <= DP_APSEL_MAX; ap_num++) { ... }
LOG_DEBUG("No %s found", ap_type_to_description(type_to_find));
return ERROR_FAIL;
}{ ... }
static inline bool is_ap_in_use(struct adiv5_ap *ap)
{
return ap->refcount > 0 || ap->config_ap_never_release;
}{ ... }
static struct adiv5_ap *_dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
{
if (!is_ap_num_valid(dap, ap_num)) {
LOG_ERROR("Invalid AP#0x%" PRIx64, ap_num);
return NULL;
}if (!is_ap_num_valid(dap, ap_num)) { ... }
if (is_adiv6(dap)) {
for (unsigned int i = 0; i <= DP_APSEL_MAX; i++) {
struct adiv5_ap *ap = &dap->ap[i];
if (is_ap_in_use(ap) && ap->ap_num == ap_num) {
++ap->refcount;
return ap;
}if (is_ap_in_use(ap) && ap->ap_num == ap_num) { ... }
}for (unsigned int i = 0; i <= DP_APSEL_MAX; i++) { ... }
for (unsigned int i = 0; i <= DP_APSEL_MAX; i++) {
struct adiv5_ap *ap = &dap->ap[i];
if (!is_ap_in_use(ap)) {
ap->ap_num = ap_num;
++ap->refcount;
return ap;
}if (!is_ap_in_use(ap)) { ... }
}for (unsigned int i = 0; i <= DP_APSEL_MAX; i++) { ... }
LOG_ERROR("No more AP available!");
return NULL;
}if (is_adiv6(dap)) { ... }
struct adiv5_ap *ap = &dap->ap[ap_num];
ap->ap_num = ap_num;
++ap->refcount;
return ap;
}{ ... }
struct adiv5_ap *dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
{
struct adiv5_ap *ap = _dap_get_ap(dap, ap_num);
if (ap)
LOG_DEBUG("refcount AP#0x%" PRIx64 " get %u", ap_num, ap->refcount);
return ap;
}{ ... }
struct adiv5_ap *dap_get_config_ap(struct adiv5_dap *dap, uint64_t ap_num)
{
struct adiv5_ap *ap = _dap_get_ap(dap, ap_num);
if (ap) {
ap->config_ap_never_release = true;
LOG_DEBUG("refcount AP#0x%" PRIx64 " get_config %u", ap_num, ap->refcount);
}if (ap) { ... }
return ap;
}{ ... }
int dap_put_ap(struct adiv5_ap *ap)
{
if (ap->refcount == 0) {
LOG_ERROR("BUG: refcount AP#0x%" PRIx64 " put underflow", ap->ap_num);
return ERROR_FAIL;
}if (ap->refcount == 0) { ... }
--ap->refcount;
LOG_DEBUG("refcount AP#0x%" PRIx64 " put %u", ap->ap_num, ap->refcount);
if (!is_ap_in_use(ap)) {
ap->ap_num = DP_APSEL_INVALID;
ap->memaccess_tck = 255;
ap->tar_autoincr_block = (1 << 10)