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// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2009 Michael Schwingen *
* michael@schwingen.org *
* Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com> *
* Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "imp.h"
#include "cfi.h"
#include "non_cfi.h"
#include <target/arm.h>
#include <target/arm7_9_common.h>
#include <target/armv7m.h>
#include <target/mips32.h>
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
/* defines internal maximum size for code fragment in cfi_intel_write_block() */
#define CFI_MAX_INTEL_CODESIZE 256
/* some id-types with specific handling */
#define AT49BV6416 0x00d6
#define AT49BV6416T 0x00d2
static const struct cfi_unlock_addresses cfi_unlock_addresses[] = {
[CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
[CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
};
static const int cfi_status_poll_mask_dq6_dq7 = CFI_STATUS_POLL_MASK_DQ6_DQ7;
/* CFI fixups forward declarations */
static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, const void *param);
static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, const void *param);
static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, const void *param);
static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, const void *param);
static void cfi_fixup_0002_polling_bits(struct flash_bank *bank, const void *param);
/* fixup after reading cmdset 0002 primary query table */
static const struct cfi_fixup cfi_0002_fixups[] = {
{CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses,
&cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses,
&cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses,
&cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses,
&cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses,
&cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_SST, 0x274b, cfi_fixup_0002_unlock_addresses,
&cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_SST, 0x235f, cfi_fixup_0002_polling_bits, /* 39VF3201C */
&cfi_status_poll_mask_dq6_dq7},
{CFI_MFR_SST, 0x236d, cfi_fixup_0002_unlock_addresses,
&cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
{CFI_MFR_ATMEL, 0x00C8, cfi_fixup_reversed_erase_regions, NULL},
{CFI_MFR_ST, 0x22C4, cfi_fixup_reversed_erase_regions, NULL}, /* M29W160ET */
{CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses,
&cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
{CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses,
&cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses,
&cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
{CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses,
&cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
{CFI_MFR_EON, 0x225b, cfi_fixup_0002_unlock_addresses,
&cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
{CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses,
&cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
{CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
{CFI_MFR_ST, 0x227E, cfi_fixup_0002_write_buffer, NULL},/* M29W128G */
{0, 0, NULL, NULL}
};
/* fixup after reading cmdset 0001 primary query table */
static const struct cfi_fixup cfi_0001_fixups[] = {
{0, 0, NULL, NULL}
};
static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
for (const struct cfi_fixup *f = fixups; f->fixup; f++) {
if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
f->fixup(bank, f->param);
}
}
uint32_t cfi_flash_address(struct flash_bank *bank, int sector, uint32_t offset)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
if (cfi_info->x16_as_x8)
offset *= 2;
/* while the sector list isn't built, only accesses to sector 0 work */
if (sector == 0)
return bank->base + offset * bank->bus_width;
else {
if (!bank->sectors) {
LOG_ERROR("BUG: sector list not yet built");
exit(-1);
}
return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
}
}
static int cfi_target_write_memory(struct flash_bank *bank, target_addr_t addr,
uint32_t count, const uint8_t *buffer)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
if (cfi_info->write_mem) {
return cfi_info->write_mem(bank, addr, count, buffer);
} else {
return target_write_memory(bank->target, addr, bank->bus_width,
count, buffer);
}
}
int cfi_target_read_memory(struct flash_bank *bank, target_addr_t addr,
uint32_t count, uint8_t *buffer)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
if (cfi_info->read_mem) {
return cfi_info->read_mem(bank, addr, count, buffer);
} else {
return target_read_memory(bank->target, addr, bank->bus_width,
count, buffer);
}
}
static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
/* clear whole buffer, to ensure bits that exceed the bus_width
* are set to zero
*/
for (size_t i = 0; i < CFI_MAX_BUS_WIDTH; i++)
cmd_buf[i] = 0;
if (cfi_info->endianness == TARGET_LITTLE_ENDIAN) {
for (unsigned int i = bank->bus_width; i > 0; i--)
*cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
} else {
for (unsigned int i = 1; i <= bank->bus_width; i++)
*cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
}
}
int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
{
uint8_t command[CFI_MAX_BUS_WIDTH];
cfi_command(bank, cmd, command);
return cfi_target_write_memory(bank, address, 1, command);
}
/* read unsigned 8-bit value from the bank
* flash banks are expected to be made of similar chips
* the query result should be the same for all
*/
static int cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
uint8_t data[CFI_MAX_BUS_WIDTH];
int retval;
retval = cfi_target_read_memory(bank, cfi_flash_address(bank, sector, offset),
1, data);
if (retval != ERROR_OK)
return retval;
if (cfi_info->endianness == TARGET_LITTLE_ENDIAN)
*val = data[0];
else
*val = data[bank->bus_width - 1];
return ERROR_OK;
}
/* read unsigned 8-bit value from the bank
* in case of a bank made of multiple chips,
* the individual values are ORed
*/
static int cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
uint8_t data[CFI_MAX_BUS_WIDTH];
int retval;
retval = cfi_target_read_memory(bank, cfi_flash_address(bank, sector, offset),
1, data);
if (retval != ERROR_OK)
return retval;
if (cfi_info->endianness == TARGET_LITTLE_ENDIAN) {
for (unsigned int i = 0; i < bank->bus_width / bank->chip_width; i++)
data[0] |= data[i];
*val = data[0];
} else {
uint8_t value = 0;
for (unsigned int i = 0; i < bank->bus_width / bank->chip_width; i++)
value |= data[bank->bus_width - 1 - i];
*val = value;
}
return ERROR_OK;
}
static int cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset, uint16_t *val)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
uint8_t data[CFI_MAX_BUS_WIDTH * 2];
int retval;
if (cfi_info->x16_as_x8) {
for (uint8_t i = 0; i < 2; i++) {
retval = cfi_target_read_memory(bank, cfi_flash_address(bank, sector, offset + i),
1, &data[i * bank->bus_width]);
if (retval != ERROR_OK)
return retval;
}
} else {
retval = cfi_target_read_memory(bank, cfi_flash_address(bank, sector, offset),
2, data);
if (retval != ERROR_OK)
return retval;
}
if (cfi_info->endianness == TARGET_LITTLE_ENDIAN)
*val = data[0] | data[bank->bus_width] << 8;
else
*val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
return ERROR_OK;
}
static int cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset, uint32_t *val)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
uint8_t data[CFI_MAX_BUS_WIDTH * 4];
int retval;
if (cfi_info->x16_as_x8) {
for (uint8_t i = 0; i < 4; i++) {
retval = cfi_target_read_memory(bank, cfi_flash_address(bank, sector, offset + i),
1, &data[i * bank->bus_width]);
if (retval != ERROR_OK)
return retval;
}
} else {
retval = cfi_target_read_memory(bank, cfi_flash_address(bank, sector, offset),
4, data);
if (retval != ERROR_OK)
return retval;
}
if (cfi_info->endianness == TARGET_LITTLE_ENDIAN)
*val = data[0] | data[bank->bus_width] << 8 |
data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
else
*val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8 |
data[(3 * bank->bus_width) - 1] << 16 |
data[(4 * bank->bus_width) - 1] << 24;
return ERROR_OK;
}
int cfi_reset(struct flash_bank *bank)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
int retval = ERROR_OK;
retval = cfi_send_command(bank, 0xf0, cfi_flash_address(bank, 0, 0x0));
if (retval != ERROR_OK)
return retval;
retval = cfi_send_command(bank, 0xff, cfi_flash_address(bank, 0, 0x0));
if (retval != ERROR_OK)
return retval;
if (cfi_info->manufacturer == 0x20 &&
(cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E)) {
/* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
* so we send an extra 0xF0 reset to fix the bug */
retval = cfi_send_command(bank, 0xf0, cfi_flash_address(bank, 0, 0x00));
if (retval != ERROR_OK)
return retval;
}
return retval;
}
static void cfi_intel_clear_status_register(struct flash_bank *bank)
{
cfi_send_command(bank, 0x50, cfi_flash_address(bank, 0, 0x0));
}
static int cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout, uint8_t *val)
{
uint8_t status;
int retval = ERROR_OK;
for (;; ) {
if (timeout-- < 0) {
LOG_ERROR("timeout while waiting for WSM to become ready");
return ERROR_FAIL;
}
retval = cfi_get_u8(bank, 0, 0x0, &status);
if (retval != ERROR_OK)
return retval;
if (status & 0x80)
break;
alive_sleep(1);
}
/* mask out bit 0 (reserved) */
status = status & 0xfe;
LOG_DEBUG("status: 0x%x", status);
if (status != 0x80) {
LOG_ERROR("status register: 0x%x", status);
if (status & 0x2)
LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
if (status & 0x4)
LOG_ERROR("Program suspended");
if (status & 0x8)
LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
if (status & 0x10)
LOG_ERROR("Program Error / Error in Setting Lock-Bit");
if (status & 0x20)
LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
if (status & 0x40)
LOG_ERROR("Block Erase Suspended");
cfi_intel_clear_status_register(bank);
retval = ERROR_FAIL;
}
*val = status;
return retval;
}
int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
{
uint8_t status, oldstatus;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
int retval;
retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
if (retval != ERROR_OK)
return retval;
do {
retval = cfi_get_u8(bank, 0, 0x0, &status);
if (retval != ERROR_OK)
return retval;
if ((status ^ oldstatus) & 0x40) {
if (status & cfi_info->status_poll_mask & 0x20) {
retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
if (retval != ERROR_OK)
return retval;
retval = cfi_get_u8(bank, 0, 0x0, &status);
if (retval != ERROR_OK)
return retval;
if ((status ^ oldstatus) & 0x40) {
LOG_ERROR("dq5 timeout, status: 0x%x", status);
return ERROR_FLASH_OPERATION_FAILED;
} else {
LOG_DEBUG("status: 0x%x", status);
return ERROR_OK;
}
}
} else {/* no toggle: finished, OK */
LOG_DEBUG("status: 0x%x", status);
return ERROR_OK;
}
oldstatus = status;
alive_sleep(1);
} while (timeout-- > 0);
LOG_ERROR("timeout, status: 0x%x", status);
return ERROR_FLASH_BUSY;
}
static int cfi_read_intel_pri_ext(struct flash_bank *bank)
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_intel_pri_ext *pri_ext;
free(cfi_info->pri_ext);
pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
if (!pri_ext) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
cfi_info->pri_ext = pri_ext;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
if (retval != ERROR_OK)
return retval;
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I')) {
retval = cfi_reset(bank);
if (retval != ERROR_OK)
return retval;
LOG_ERROR("Could not read bank flash bank information");
return ERROR_FLASH_BANK_INVALID;
}
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
retval = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5, &pri_ext->feature_support);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->suspend_cmd_support);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa, &pri_ext->blk_status_reg_mask);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: "
"0x%x, blk_status_reg_mask: 0x%x",
pri_ext->feature_support,
pri_ext->suspend_cmd_support,
pri_ext->blk_status_reg_mask);
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc, &pri_ext->vcc_optimal);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd, &pri_ext->vpp_optimal);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
(pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
(pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe, &pri_ext->num_protection_fields);
if (retval != ERROR_OK)
return retval;
if (pri_ext->num_protection_fields != 1) {
LOG_WARNING("expected one protection register field, but found %i",
pri_ext->num_protection_fields);
}
retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf, &pri_ext->prot_reg_addr);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11, &pri_ext->fact_prot_reg_size);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12, &pri_ext->user_prot_reg_size);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, "
"factory pre-programmed: %i, user programmable: %i",
pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
return ERROR_OK;
}
static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext;
free(cfi_info->pri_ext);
pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
if (!pri_ext) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
cfi_info->pri_ext = pri_ext;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
if (retval != ERROR_OK)
return retval;
/* default values for implementation specific workarounds */
pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
pri_ext->_reversed_geometry = 0;
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I')) {
retval = cfi_send_command(bank, 0xf0, cfi_flash_address(bank, 0, 0x0));
if (retval != ERROR_OK)
return retval;
LOG_ERROR("Could not read spansion bank information");
return ERROR_FLASH_BANK_INVALID;
}
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->silicon_revision);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->erase_suspend);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->blk_prot);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->tmp_blk_unprotected);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->blk_prot_unprot);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->simultaneous_ops);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->burst_mode);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->page_mode);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->vpp_min);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->vpp_max);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->top_bottom);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x",
pri_ext->silicon_revision, pri_ext->erase_suspend, pri_ext->blk_prot);
LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, "
"Simultaneous Ops: 0x%x", pri_ext->tmp_blk_unprotected,
pri_ext->blk_prot_unprot, pri_ext->simultaneous_ops);
LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->burst_mode, pri_ext->page_mode);
LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
(pri_ext->vpp_min & 0xf0) >> 4, pri_ext->vpp_min & 0x0f,
(pri_ext->vpp_max & 0xf0) >> 4, pri_ext->vpp_max & 0x0f);
LOG_DEBUG("WP# protection 0x%x", pri_ext->top_bottom);
return ERROR_OK;
}
static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
{
int retval;
struct cfi_atmel_pri_ext atmel_pri_ext;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext;
free(cfi_info->pri_ext);
pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
if (!pri_ext) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
/* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
* but a different primary extended query table.
* We read the atmel table, and prepare a valid AMD/Spansion query table.
*/
memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
cfi_info->pri_ext = pri_ext;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &atmel_pri_ext.pri[0]);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &atmel_pri_ext.pri[1]);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &atmel_pri_ext.pri[2]);
if (retval != ERROR_OK)
return retval;
if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R')
|| (atmel_pri_ext.pri[2] != 'I')) {
retval = cfi_send_command(bank, 0xf0, cfi_flash_address(bank, 0, 0x0));
if (retval != ERROR_OK)
return retval;
LOG_ERROR("Could not read atmel bank information");
return ERROR_FLASH_BANK_INVALID;
}
pri_ext->pri[0] = atmel_pri_ext.pri[0];
pri_ext->pri[1] = atmel_pri_ext.pri[1];
pri_ext->pri[2] = atmel_pri_ext.pri[2];
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &atmel_pri_ext.major_version);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &atmel_pri_ext.minor_version);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0],
atmel_pri_ext.pri[1], atmel_pri_ext.pri[2],
atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
pri_ext->major_version = atmel_pri_ext.major_version;
pri_ext->minor_version = atmel_pri_ext.minor_version;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &atmel_pri_ext.features);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &atmel_pri_ext.bottom_boot);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &atmel_pri_ext.burst_mode);
if (retval != ERROR_OK)
return retval;
retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &atmel_pri_ext.page_mode);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG(
"features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
atmel_pri_ext.features,
atmel_pri_ext.bottom_boot,
atmel_pri_ext.burst_mode,
atmel_pri_ext.page_mode);
if (atmel_pri_ext.features & 0x02)
pri_ext->erase_suspend = 2;
/* some chips got it backwards... */
if (cfi_info->device_id == AT49BV6416 ||
cfi_info->device_id == AT49BV6416T) {
if (atmel_pri_ext.bottom_boot)
pri_ext->top_bottom = 3;
else
pri_ext->top_bottom = 2;
} else {
if (atmel_pri_ext.bottom_boot)
pri_ext->top_bottom = 2;
else
pri_ext->top_bottom = 3;
}
pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
return ERROR_OK;
}
static int cfi_read_0002_pri_ext(struct flash_bank *bank)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
if (cfi_info->manufacturer == CFI_MFR_ATMEL)
return cfi_read_atmel_pri_ext(bank);
else
return cfi_read_spansion_pri_ext(bank);
}
static int cfi_spansion_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
command_print_sameline(cmd, "\nSpansion primary algorithm extend information:\n");
command_print_sameline(cmd, "pri: '%c%c%c', version: %c.%c\n",
pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2],
pri_ext->major_version, pri_ext->minor_version);
command_print_sameline(cmd, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
(pri_ext->silicon_revision) >> 2,
(pri_ext->silicon_revision) & 0x03);
command_print_sameline(cmd, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
pri_ext->erase_suspend,
pri_ext->blk_prot);
command_print_sameline(cmd, "VppMin: %u.%x, VppMax: %u.%x\n",
(pri_ext->vpp_min & 0xf0) >> 4, pri_ext->vpp_min & 0x0f,
(pri_ext->vpp_max & 0xf0) >> 4, pri_ext->vpp_max & 0x0f);
return ERROR_OK;
}
static int cfi_intel_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
command_print_sameline(cmd, "\nintel primary algorithm extend information:\n");
command_print_sameline(cmd, "pri: '%c%c%c', version: %c.%c\n",
pri_ext->pri[0],
pri_ext->pri[1],
pri_ext->pri[2],
pri_ext->major_version,
pri_ext->minor_version);
command_print_sameline(cmd, "feature_support: 0x%" PRIx32 ", "
"suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n",
pri_ext->feature_support,
pri_ext->suspend_cmd_support,
pri_ext->blk_status_reg_mask);
command_print_sameline(cmd, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
(pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
(pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
command_print_sameline(cmd, "protection_fields: %i, prot_reg_addr: 0x%x, "
"factory pre-programmed: %i, user programmable: %i\n",
pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
return ERROR_OK;
}
int cfi_flash_bank_cmd(struct flash_bank *bank, unsigned int argc, const char **argv)
{
struct cfi_flash_bank *cfi_info;
bool bus_swap = false;
if (argc < 6)
return ERROR_COMMAND_SYNTAX_ERROR;
/* both widths must:
* - not exceed max value;
* - not be null;
* - be equal to a power of 2.
* bus must be wide enough to hold one chip */
if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
|| (bank->bus_width > CFI_MAX_BUS_WIDTH)
|| (bank->chip_width == 0)
|| (bank->bus_width == 0)
|| (bank->chip_width & (bank->chip_width - 1))
|| (bank->bus_width & (bank->bus_width - 1))
|| (bank->chip_width > bank->bus_width)) {
LOG_ERROR("chip and bus width have to specified in bytes");
return ERROR_FLASH_BANK_INVALID;
}
cfi_info = calloc(1, sizeof(struct cfi_flash_bank));
if (!cfi_info) {
LOG_ERROR("No memory for flash bank info");
return ERROR_FAIL;
}
bank->driver_priv = cfi_info;
for (unsigned i = 6; i < argc; i++) {
if (strcmp(argv[i], "x16_as_x8") == 0)
cfi_info->x16_as_x8 = true;
else if (strcmp(argv[i], "data_swap") == 0)
cfi_info->data_swap = true;
else if (strcmp(argv[i], "bus_swap") == 0)
bus_swap = true;
else if (strcmp(argv[i], "jedec_probe") == 0)
cfi_info->jedec_probe = true;
}
if (bus_swap)
cfi_info->endianness =
bank->target->endianness == TARGET_LITTLE_ENDIAN ?
TARGET_BIG_ENDIAN : TARGET_LITTLE_ENDIAN;
else
cfi_info->endianness = bank->target->endianness;
/* bank wasn't probed yet */
cfi_info->qry[0] = 0xff;
return ERROR_OK;
}
/* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
*/
FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
{
return cfi_flash_bank_cmd(bank, CMD_ARGC, CMD_ARGV);
}
static int cfi_intel_erase(struct flash_bank *bank, unsigned int first,
unsigned int last)
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
cfi_intel_clear_status_register(bank);
for (unsigned int i = first; i <= last; i++) {
retval = cfi_send_command(bank, 0x20, cfi_flash_address(bank, i, 0x0));
if (retval != ERROR_OK)
return retval;
retval = cfi_send_command(bank, 0xd0, cfi_flash_address(bank, i, 0x0));
if (retval != ERROR_OK)
return retval;
uint8_t status;
retval = cfi_intel_wait_status_busy(bank, cfi_info->block_erase_timeout, &status);
if (retval != ERROR_OK)
return retval;
if (status != 0x80) {
retval = cfi_send_command(bank, 0xff, cfi_flash_address(bank, 0, 0x0));
if (retval != ERROR_OK)
return retval;
LOG_ERROR("couldn't erase block %u of flash bank at base "
TARGET_ADDR_FMT, i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
}
return cfi_send_command(bank, 0xff, cfi_flash_address(bank, 0, 0x0));
}
int cfi_spansion_unlock_seq(struct flash_bank *bank)
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
retval = cfi_send_command(bank, 0xaa, cfi_flash_address(bank, 0, pri_ext->_unlock1));
if (retval != ERROR_OK)
return retval;
retval = cfi_send_command(bank, 0x55, cfi_flash_address(bank, 0, pri_ext->_unlock2));
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
static int cfi_spansion_erase(struct flash_bank *bank, unsigned int first,
unsigned int last)
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
for (unsigned int i = first; i <= last; i++) {
retval = cfi_spansion_unlock_seq(bank);
if (retval != ERROR_OK)
return retval;
retval = cfi_send_command(bank, 0x80, cfi_flash_address(bank, 0, pri_ext->_unlock1));
if (retval != ERROR_OK)
return retval;
retval = cfi_spansion_unlock_seq(bank);
if (retval != ERROR_OK)
return retval;
retval = cfi_send_command(bank, 0x30, cfi_flash_address(bank, i, 0x0));
if (retval != ERROR_OK)
return retval;
if (cfi_spansion_wait_status_busy(bank, cfi_info->block_erase_timeout) != ERROR_OK) {
retval = cfi_send_command(bank, 0xf0, cfi_flash_address(bank, 0, 0x0));
if (retval != ERROR_OK)
return retval;
LOG_ERROR("couldn't erase block %i of flash bank at base "
TARGET_ADDR_FMT, i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
}
return cfi_send_command(bank, 0xf0, cfi_flash_address(bank, 0, 0x0));
}
int cfi_erase(struct flash_bank *bank, unsigned int first,
unsigned int last)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if ((last < first) || (last >= bank->num_sectors))
return ERROR_FLASH_SECTOR_INVALID;
if (cfi_info->qry[0] != 'Q')
return ERROR_FLASH_BANK_NOT_PROBED;
switch (cfi_info->pri_id) {
case 1:
case 3:
return cfi_intel_erase(bank, first, last);
case 2:
return cfi_spansion_erase(bank, first, last);
default:
LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}
return ERROR_OK;
}
static int cfi_intel_protect(struct flash_bank *bank, int set,
unsigned int first, unsigned int last)
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
int retry = 0;
/* if the device supports neither legacy lock/unlock (bit 3) nor
* instant individual block locking (bit 5).
*/
if (!(pri_ext->feature_support & 0x28)) {
LOG_ERROR("lock/unlock not supported on flash");
return ERROR_FLASH_OPERATION_FAILED;
}
cfi_intel_clear_status_register(bank);
for (unsigned int i = first; i <= last; i++) {
retval = cfi_send_command(bank, 0x60, cfi_flash_address(bank, i, 0x0));
if (retval != ERROR_OK)
return retval;
if (set) {
retval = cfi_send_command(bank, 0x01, cfi_flash_address(bank, i, 0x0));
if (retval != ERROR_OK)
return retval;
bank->sectors[i].is_protected = 1;
} else {
retval = cfi_send_command(bank, 0xd0, cfi_flash_address(bank, i, 0x0));
if (retval != ERROR_OK)
return retval;
bank->sectors[i].is_protected = 0;
}
/* instant individual block locking doesn't require reading of the status register
**/
if (!(pri_ext->feature_support & 0x20)) {
/* Clear lock bits operation may take up to 1.4s */
uint8_t status;
retval = cfi_intel_wait_status_busy(bank, 1400, &status);
if (retval != ERROR_OK)
return retval;
} else {
uint8_t block_status;
/* read block lock bit, to verify status */
retval = cfi_send_command(bank, 0x90, cfi_flash_address(bank, 0, 0x55));
if (retval != ERROR_OK)
return retval;
retval = cfi_get_u8(bank, i, 0x2, &block_status);
if (retval != ERROR_OK)
return retval;
if ((block_status & 0x1) != set) {
LOG_ERROR(
"couldn't change block lock status (set = %i, block_status = 0x%2.2x)",
set, block_status);
retval = cfi_send_command(bank, 0x70, cfi_flash_address(bank, 0, 0x55));
if (retval != ERROR_OK)
return retval;
uint8_t status;
retval = cfi_intel_wait_status_busy(bank, 10, &status);
if (retval != ERROR_OK)
return retval;
if (retry > 10)
return ERROR_FLASH_OPERATION_FAILED;
else {
i--;
retry++;
}
}
}
}
/* if the device doesn't support individual block lock bits set/clear,
* all blocks have been unlocked in parallel, so we set those that should be protected
*/
if ((!set) && (!(pri_ext->feature_support & 0x20))) {
/* FIX!!! this code path is broken!!!
*
* The correct approach is:
*
* 1. read out current protection status
*
* 2. override read out protection status w/unprotected.
*
* 3. re-protect what should be protected.
*
*/
for (unsigned int i = 0; i < bank->num_sectors; i++) {
if (bank->sectors[i].is_protected == 1) {
cfi_intel_clear_status_register(bank);
retval = cfi_send_command(bank,