1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
46
47
50
51
54
55
58
59
62
63
66
67
70
71
74
75
84
87
93
99
105
111
117
123
129
133
139
145
146
148
152
156
160
161
162
168
169
170
171
180
181
182
190
191
192
193
194
195
197
199
201
203
205
207
209
211
212
214
216
219
220
221
222
223
224
225
226
228
230
232
234
236
238
240
242
244
247
248
249
250
253
254
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
283
284
285
286
287
288
289
290
291
292
296
297
298
299
300
301
302
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
403
404
407
410
413
416
419
422
425
428
431
432
433
438
439
440
441
442
443
447
452
453
454
455
456
457
461
462
463
464
465
466
467
468
469
470
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
513
514
515
518
522
523
524
525
526
527
528
531
532
538
539
540
541
542
543
544
545
546
547
548
549
550
551
555
556
557
558
559
560
561
562
563
564
565
566
567
568
573
574
575
576
577
578
579
580
584
585
586
587
591
592
593
594
595
596
597
598
599
600
601
602
606
607
610
611
612
613
618
619
620
621
622
623
624
625
626
627
628
636
637
638
639
640
641
645
646
647
648
649
650
651
652
653
654
655
656
657
658
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
712
713
714
715
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
774
775
776
777
778
779
780
781
782
783
784
785
786
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
818
819
823
824
829
830
834
835
840
841
842
843
844
845
846
847
848
849
850
851
852
853
855
859
863
864
869
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
918
919
931
932
933
934
935
936
937
938
939
940
941
942
946
947
948
949
950
951
952
956
957
961
962
984
985
986
987
989
990
991
992
993
994
995
996
997
1001
1002
1003
1004
1005
1006
1010
1014
1015
1016
1020
1021
1025
1026
1027
1028
1029
1030
1031
1032
1033
1038
1039
1043
1044
1045
1049
1050
1051
1055
1056
1057
1061
1062
1063
1067
1068
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1105
1106
1107
1108
1109
1110
1114
1118
1119
1120
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1138
1139
1143
1144
1145
1149
1150
1151
1155
1156
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1271
1272
1273
1274
1275
1276
1277
1278
1279
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1339
1340
1341
1342
1347
1348
1349
1350
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1412
1413
1417
1418
1422
1423
1424
1428
1429
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1462
1463
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1687
1688
1689
1690
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1762
1763
1764
1765
1766
1767
1768
1773
1774
1775
1776
1781
1782
1783
1784
1785
1790
1791
1792
1793
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
/* ... */
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "arm.h"
#include "armv4_5.h"
#include "arm_jtag.h"
#include "breakpoints.h"
#include "arm_disassembler.h"
#include <helper/binarybuffer.h>
#include "algorithm.h"
#include "register.h"
#include "semihosting_common.h"
9 includes
enum {
ARMV4_5_SPSR_FIQ = 32,
ARMV4_5_SPSR_IRQ = 33,
ARMV4_5_SPSR_SVC = 34,
ARMV4_5_SPSR_ABT = 35,
ARMV4_5_SPSR_UND = 36,
ARM_SPSR_MON = 41,
ARM_SPSR_HYP = 43,
...};
static const uint8_t arm_usr_indices[17] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
...};
static const uint8_t arm_fiq_indices[8] = {
16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
...};
static const uint8_t arm_irq_indices[3] = {
23, 24, ARMV4_5_SPSR_IRQ,
...};
static const uint8_t arm_svc_indices[3] = {
25, 26, ARMV4_5_SPSR_SVC,
...};
static const uint8_t arm_abt_indices[3] = {
27, 28, ARMV4_5_SPSR_ABT,
...};
static const uint8_t arm_und_indices[3] = {
29, 30, ARMV4_5_SPSR_UND,
...};
static const uint8_t arm_mon_indices[3] = {
39, 40, ARM_SPSR_MON,
...};
static const uint8_t arm_hyp_indices[2] = {
42, ARM_SPSR_HYP,
...};
static const struct {
const char *name;
unsigned short psr;
/* ... */
unsigned short n_indices;
const uint8_t *indices;
...} arm_mode_data[] = {
/* ... */
{
.name = "User",
.psr = ARM_MODE_USR,
.n_indices = ARRAY_SIZE(arm_usr_indices),
.indices = arm_usr_indices,
...},
{
.name = "FIQ",
.psr = ARM_MODE_FIQ,
.n_indices = ARRAY_SIZE(arm_fiq_indices),
.indices = arm_fiq_indices,
...},
{
.name = "Supervisor",
.psr = ARM_MODE_SVC,
.n_indices = ARRAY_SIZE(arm_svc_indices),
.indices = arm_svc_indices,
...},
{
.name = "Abort",
.psr = ARM_MODE_ABT,
.n_indices = ARRAY_SIZE(arm_abt_indices),
.indices = arm_abt_indices,
...},
{
.name = "IRQ",
.psr = ARM_MODE_IRQ,
.n_indices = ARRAY_SIZE(arm_irq_indices),
.indices = arm_irq_indices,
...},
{
.name = "Undefined instruction",
.psr = ARM_MODE_UND,
.n_indices = ARRAY_SIZE(arm_und_indices),
.indices = arm_und_indices,
...},
{
.name = "System",
.psr = ARM_MODE_SYS,
.n_indices = ARRAY_SIZE(arm_usr_indices),
.indices = arm_usr_indices,
...},
/* ... */
{
.name = "Secure Monitor",
.psr = ARM_MODE_MON,
.n_indices = ARRAY_SIZE(arm_mon_indices),
.indices = arm_mon_indices,
...},
{
.name = "Secure Monitor ARM1176JZF-S",
.psr = ARM_MODE_1176_MON,
.n_indices = ARRAY_SIZE(arm_mon_indices),
.indices = arm_mon_indices,
...},
/* ... */
{
.name = "Thread",
.psr = ARM_MODE_THREAD,
...},
{
.name = "Thread (User)",
.psr = ARM_MODE_USER_THREAD,
...},
{
.name = "Handler",
.psr = ARM_MODE_HANDLER,
...},
{
.name = "Hypervisor",
.psr = ARM_MODE_HYP,
.n_indices = ARRAY_SIZE(arm_hyp_indices),
.indices = arm_hyp_indices,
...},
...};
const char *arm_mode_name(unsigned psr_mode)
{
for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
if (arm_mode_data[i].psr == psr_mode)
return arm_mode_data[i].name;
}for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) { ... }
LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
return "UNRECOGNIZED";
}{ ... }
bool is_arm_mode(unsigned psr_mode)
{
for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
if (arm_mode_data[i].psr == psr_mode)
return true;
}for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) { ... }
return false;
}{ ... }
int arm_mode_to_number(enum arm_mode mode)
{
switch (mode) {
case ARM_MODE_ANY:
case ARM_MODE_ANY:
case ARM_MODE_USR:
return 0;case ARM_MODE_USR:
case ARM_MODE_FIQ:
return 1;case ARM_MODE_FIQ:
case ARM_MODE_IRQ:
return 2;case ARM_MODE_IRQ:
case ARM_MODE_SVC:
return 3;case ARM_MODE_SVC:
case ARM_MODE_ABT:
return 4;case ARM_MODE_ABT:
case ARM_MODE_UND:
return 5;case ARM_MODE_UND:
case ARM_MODE_SYS:
return 6;case ARM_MODE_SYS:
case ARM_MODE_MON:
case ARM_MODE_1176_MON:
return 7;case ARM_MODE_1176_MON:
case ARM_MODE_HYP:
return 8;case ARM_MODE_HYP:
default:
LOG_ERROR("invalid mode value encountered %d", mode);
return -1;default
}switch (mode) { ... }
}{ ... }
enum arm_mode armv4_5_number_to_mode(int number)
{
switch (number) {
case 0:
return ARM_MODE_USR;case 0:
case 1:
return ARM_MODE_FIQ;case 1:
case 2:
return ARM_MODE_IRQ;case 2:
case 3:
return ARM_MODE_SVC;case 3:
case 4:
return ARM_MODE_ABT;case 4:
case 5:
return ARM_MODE_UND;case 5:
case 6:
return ARM_MODE_SYS;case 6:
case 7:
return ARM_MODE_MON;case 7:
case 8:
return ARM_MODE_HYP;case 8:
default:
LOG_ERROR("mode index out of bounds %d", number);
return ARM_MODE_ANY;default
}switch (number) { ... }
}{ ... }
static const char *arm_state_strings[] = {
"ARM", "Thumb", "Jazelle", "ThumbEE",
...};
/* ... */
static const struct {
const char *name;
/* ... */
unsigned cookie;
unsigned gdb_index;
enum arm_mode mode;
...} arm_core_regs[] = {
/* ... */
[0] = { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
[1] = { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
[2] = { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
[3] = { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
[4] = { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
[5] = { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
[6] = { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
[7] = { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
/* ... */
[8] = { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
[9] = { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
[10] = { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
[11] = { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
[12] = { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
/* ... */
[13] = { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
[14] = { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
[15] = { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
[16] = { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
[17] = { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
[18] = { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
[19] = { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
[20] = { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
[21] = { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
[22] = { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
[23] = { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
[24] = { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
[25] = { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
[26] = { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
[27] = { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
[28] = { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
[29] = { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
[30] = { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
[31] = { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
[32] = { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
[33] = { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
[34] = { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
[35] = { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
[36] = { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
[37] = { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
[38] = { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
[39] = { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
[40] = { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
[41] = { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
[42] = { .name = "sp_hyp", .cookie = 13, .mode = ARM_MODE_HYP, .gdb_index = 51, },
[43] = { .name = "spsr_hyp", .cookie = 16, .mode = ARM_MODE_HYP, .gdb_index = 52, },
...};
static const struct {
unsigned int id;
const char *name;
uint32_t bits;
enum arm_mode mode;
enum reg_type type;
const char *group;
const char *feature;
...} arm_vfp_v3_regs[] = {
{ ARM_VFP_V3_D0, "d0", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D1, "d1", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D2, "d2", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D3, "d3", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D4, "d4", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D5, "d5", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D6, "d6", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D7, "d7", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D8, "d8", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D9, "d9", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D10, "d10", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D11, "d11", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D12, "d12", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D13, "d13", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D14, "d14", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D15, "d15", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D16, "d16", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D17, "d17", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D18, "d18", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D19, "d19", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D20, "d20", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D21, "d21", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D22, "d22", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D23, "d23", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D24, "d24", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D25, "d25", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D26, "d26", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D27, "d27", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D28, "d28", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D29, "d29", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D30, "d30", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_D31, "d31", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARM_VFP_V3_FPSCR, "fpscr", 32, ARM_MODE_ANY, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp"},
...};
/* ... */
const int armv4_5_core_reg_map[9][17] = {
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
...},
{
0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
...},
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
...},
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
...},
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
...},
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
...},
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
...},
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 39, 40, 15, 41,
...},
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 42, 14, 15, 43,
...}
...};
/* ... */
void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
{
enum arm_mode mode = cpsr & 0x1f;
int num;
/* ... */
if (arm->cpsr) {
buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
arm->cpsr->valid = true;
arm->cpsr->dirty = false;
}if (arm->cpsr) { ... }
arm->core_mode = mode;
num = arm_mode_to_number(mode);
if (num < 0) {
mode = ARM_MODE_USR;
num = 0;
}if (num < 0) { ... }
arm->map = &armv4_5_core_reg_map[num][0];
arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
? NULL
: arm->core_cache->reg_list + arm->map[16];
enum arm_state state;
if (cpsr & (1 << 5)) {
if (cpsr & (1 << 24)) {
LOG_WARNING("ThumbEE -- incomplete support");
state = ARM_STATE_THUMB_EE;
}if (cpsr & (1 << 24)) { ... } else
state = ARM_STATE_THUMB;
}if (cpsr & (1 << 5)) { ... } else {
if (cpsr & (1 << 24)) {
LOG_ERROR("Jazelle state handling is BROKEN!");
state = ARM_STATE_JAZELLE;
}if (cpsr & (1 << 24)) { ... } else
state = ARM_STATE_ARM;
}else { ... }
arm->core_state = state;
LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
arm_mode_name(mode),
arm_state_strings[arm->core_state]);
}{ ... }
/* ... */
struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
{
struct reg *r;
if (regnum > 16)
return NULL;
if (!arm->map) {
LOG_ERROR("Register map is not available yet, the target is not fully initialised");
r = arm->core_cache->reg_list + regnum;
}if (!arm->map) { ... } else
r = arm->core_cache->reg_list + arm->map[regnum];
/* ... */
if (!r) {
LOG_ERROR("Invalid CPSR mode");
r = arm->core_cache->reg_list + regnum;
}if (!r) { ... }
return r;
}{ ... }
static const uint8_t arm_gdb_dummy_fp_value[12];
static struct reg_feature arm_gdb_dummy_fp_features = {
.name = "net.sourceforge.openocd.fake_fpa"
...};
/* ... */
static struct reg arm_gdb_dummy_fp_reg = {
.name = "GDB dummy FPA register",
.value = (uint8_t *) arm_gdb_dummy_fp_value,
.valid = true,
.size = 96,
.exist = false,
.number = 16,
.feature = &arm_gdb_dummy_fp_features,
.group = "fake_fpa",
...};
static const uint8_t arm_gdb_dummy_fps_value[4];
/* ... */
static struct reg arm_gdb_dummy_fps_reg = {
.name = "GDB dummy FPA status register",
.value = (uint8_t *) arm_gdb_dummy_fps_value,
.valid = true,
.size = 32,
.exist = false,
.number = 24,
.feature = &arm_gdb_dummy_fp_features,
.group = "fake_fpa",
...};
static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
static void arm_gdb_dummy_init(void)
{
register_init_dummy(&arm_gdb_dummy_fp_reg);
register_init_dummy(&arm_gdb_dummy_fps_reg);
}{ ... }
static int armv4_5_get_core_reg(struct reg *reg)
{
int retval;
struct arm_reg *reg_arch_info = reg->arch_info;
struct target *target = reg_arch_info->target;
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}if (target->state != TARGET_HALTED) { ... }
retval = reg_arch_info->arm->read_core_reg(target, reg,
reg_arch_info->num, reg_arch_info->mode);
if (retval == ERROR_OK) {
reg->valid = true;
reg->dirty = false;
}if (retval == ERROR_OK) { ... }
return retval;
}{ ... }
static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
{
struct arm_reg *reg_arch_info = reg->arch_info;
struct target *target = reg_arch_info->target;
struct arm *armv4_5_target = target_to_arm(target);
uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
return ERROR_TARGET_NOT_HALTED;
}if (target->state != TARGET_HALTED) { ... }
/* ... */
if (reg == armv4_5_target->cpsr) {
arm_set_cpsr(armv4_5_target, value);
/* ... */
if (armv4_5_target->core_mode !=
(enum arm_mode)(value & 0x1f)) {
LOG_DEBUG("changing ARM core mode to '%s'",
arm_mode_name(value & 0x1f));
value &= ~((1 << 24) | (1 << 5));
uint8_t t[4];
buf_set_u32(t, 0, 32, value);
armv4_5_target->write_core_reg(target, reg,
16, ARM_MODE_ANY, t);
}if (armv4_5_target->core_mode != (enum arm_mode)(value & 0x1f)) { ... }
}if (reg == armv4_5_target->cpsr) { ... } else {
buf_set_u32(reg->value, 0, 32, value);
if (reg->size == 64) {
value = buf_get_u32(buf + 4, 0, 32);
buf_set_u32(reg->value + 4, 0, 32, value);
}if (reg->size == 64) { ... }
reg->valid = true;
}else { ... }
reg->dirty = true;
return ERROR_OK;
}{ ... }
static const struct reg_arch_type arm_reg_type = {
.get = armv4_5_get_core_reg,
.set = armv4_5_set_core_reg,
...};
struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
{
int num_regs = ARRAY_SIZE(arm_core_regs);
int num_core_regs = num_regs;
if (arm->arm_vfp_version == ARM_VFP_V3)
num_regs += ARRAY_SIZE(arm_vfp_v3_regs);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
int i;
if (!cache || !reg_list || !reg_arch_info) {
free(cache);
free(reg_list);
free(reg_arch_info);
return NULL;
}if (!cache || !reg_list || !reg_arch_info) { ... }
cache->name = "ARM registers";
cache->next = NULL;
cache->reg_list = reg_list;
cache->num_regs = 0;
for (i = 0; i < num_core_regs; i++) {
if (arm_core_regs[i].mode == ARM_MODE_MON
&& arm->core_type != ARM_CORE_TYPE_SEC_EXT
&& arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
if (arm_core_regs[i].mode == ARM_MODE_HYP
&& arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
reg_arch_info[i].num = arm_core_regs[i].cookie;
reg_arch_info[i].mode = arm_core_regs[i].mode;
reg_arch_info[i].target = target;
reg_arch_info[i].arm = arm;
reg_list[i].name = arm_core_regs[i].name;
reg_list[i].number = arm_core_regs[i].gdb_index;
reg_list[i].size = 32;
reg_list[i].value = reg_arch_info[i].value;
reg_list[i].type = &arm_reg_type;
reg_list[i].arch_info = ®_arch_info[i];
reg_list[i].exist = true;
reg_list[i].caller_save = false;
reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
switch (arm_core_regs[i].cookie) {
case 13:
reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR;
break;case 13:
case 14:
case 15:
reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR;
break;case 15:
default:
reg_list[i].reg_data_type->type = REG_TYPE_UINT32;
break;default
}switch (arm_core_regs[i].cookie) { ... }
reg_list[i].feature = malloc(sizeof(struct reg_feature));
if (reg_list[i].number <= 15 || reg_list[i].number == 25) {
reg_list[i].feature->name = "org.gnu.gdb.arm.core";
reg_list[i].group = "general";
}if (reg_list[i].number <= 15 || reg_list[i].number == 25) { ... } else {
reg_list[i].feature->name = "net.sourceforge.openocd.banked";
reg_list[i].group = "banked";
}else { ... }
cache->num_regs++;
}for (i = 0; i < num_core_regs; i++) { ... }
int j;
for (i = num_core_regs, j = 0; i < num_regs; i++, j++) {
reg_arch_info[i].num = arm_vfp_v3_regs[j].id;
reg_arch_info[i].mode = arm_vfp_v3_regs[j].mode;
reg_arch_info[i].target = target;
reg_arch_info[i].arm = arm;
reg_list[i].name = arm_vfp_v3_regs[j].name;
reg_list[i].number = arm_vfp_v3_regs[j].id;
reg_list[i].size = arm_vfp_v3_regs[j].bits;
reg_list[i].value = reg_arch_info[i].value;
reg_list[i].type = &arm_reg_type;
reg_list[i].arch_info = ®_arch_info[i];
reg_list[i].exist = true;
reg_list[i].caller_save = false;
reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
reg_list[i].reg_data_type->type = arm_vfp_v3_regs[j].type;
reg_list[i].feature = malloc(sizeof(struct reg_feature));
reg_list[i].feature->name = arm_vfp_v3_regs[j].feature;
reg_list[i].group = arm_vfp_v3_regs[j].group;
cache->num_regs++;
}for (i = num_core_regs, j = 0; i < num_regs; i++, j++) { ... }
arm->pc = reg_list + 15;
arm->cpsr = reg_list + ARMV4_5_CPSR;
arm->core_cache = cache;
return cache;
}{ ... }
void arm_free_reg_cache(struct arm *arm)
{
if (!arm || !arm->core_cache)
return;
struct reg_cache *cache = arm->core_cache;
for (unsigned int i = 0; i < cache->num_regs; i++) {
struct reg *reg = &cache->reg_list[i];
free(reg->feature);
free(reg->reg_data_type);
}for (unsigned int i = 0; i < cache->num_regs; i++) { ... }
free(cache->reg_list[0].arch_info);
free(cache->reg_list);
free(cache);
arm->core_cache = NULL;
}{ ... }
int arm_arch_state(struct target *target)
{
struct arm *arm = target_to_arm(target);
if (arm->common_magic != ARM_COMMON_MAGIC) {
LOG_ERROR("BUG: called for a non-ARM target");
return ERROR_FAIL;
}if (arm->common_magic != ARM_COMMON_MAGIC) { ... }
if (target->semihosting && target->semihosting->hit_fileio)
return ERROR_OK;
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s%s",
arm_state_strings[arm->core_state],
debug_reason_name(target),
arm_mode_name(arm->core_mode),
buf_get_u32(arm->cpsr->value, 0, 32),
buf_get_u32(arm->pc->value, 0, 32),
(target->semihosting && target->semihosting->is_active) ? ", semihosting" : "",
(target->semihosting && target->semihosting->is_fileio) ? " fileio" : "");
return ERROR_OK;
}{ ... }
COMMAND_HANDLER(handle_armv4_5_reg_command)
{
struct target *target = get_current_target(CMD_CTX);
struct arm *arm = target_to_arm(target);
struct reg *regs;
if (!is_arm(arm)) {
command_print(CMD, "current target isn't an ARM");
return ERROR_FAIL;
}if (!is_arm(arm)) { ... }
if (target->state != TARGET_HALTED) {
command_print(CMD, "Error: target must be halted for register accesses");
return ERROR_TARGET_NOT_HALTED;
}if (target->state != TARGET_HALTED) { ... }
if (arm->core_type != ARM_CORE_TYPE_STD) {
command_print(CMD,
"Microcontroller Profile not supported - use standard reg cmd");
return ERROR_OK;
}if (arm->core_type != ARM_CORE_TYPE_STD) { ... }
if (!is_arm_mode(arm->core_mode)) {
LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
}if (!is_arm_mode(arm->core_mode)) { ... }
if (!arm->full_context) {
command_print(CMD, "Error: target doesn't support %s",
CMD_NAME);
return ERROR_FAIL;
}if (!arm->full_context) { ... }
regs = arm->core_cache->reg_list;
for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
const char *name;
char *sep = "\n";
char *shadow = "";
if (!arm_mode_data[mode].n_indices)
continue;
switch (arm_mode_data[mode].psr) {
case ARM_MODE_SYS:
continue;case ARM_MODE_SYS:
case ARM_MODE_USR:
name = "System and User";
sep = "";
break;case ARM_MODE_USR:
case ARM_MODE_HYP:
if (arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
case ARM_MODE_HYP:
case ARM_MODE_MON:
case ARM_MODE_1176_MON:
if (arm->core_type != ARM_CORE_TYPE_SEC_EXT
&& arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
case ARM_MODE_1176_MON:
default:
name = arm_mode_data[mode].name;
shadow = "shadow ";
break;default
}switch (arm_mode_data[mode].psr) { ... }
command_print(CMD, "%s%s mode %sregisters",
sep, name, shadow);
for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
char output[80];
int output_len = 0;
for (unsigned j = 0; j < 4; j++, i++) {
uint32_t value;
struct reg *reg = regs;
if (i >= arm_mode_data[mode].n_indices)
break;
reg += arm_mode_data[mode].indices[i];
if (!reg->valid)
arm->full_context(target);
value = buf_get_u32(reg->value, 0, 32);
output_len += snprintf(output + output_len,
sizeof(output) - output_len,
"%8s: %8.8" PRIx32 " ",
reg->name, value);
}for (unsigned j = 0; j < 4; j++, i++) { ... }
command_print(CMD, "%s", output);
}for (unsigned i = 0; i < arm_mode_data[mode].n_indices;) { ... }
}for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) { ... }
return ERROR_OK;
}{ ... }
COMMAND_HANDLER(handle_arm_core_state_command)
{
struct target *target = get_current_target(CMD_CTX);
struct arm *arm = target_to_arm(target);
int ret = ERROR_OK;
if (!is_arm(arm)) {
command_print(CMD, "current target isn't an ARM");
return ERROR_FAIL;
}if (!is_arm(arm)) { ... }
if (CMD_ARGC > 0) {
if (strcmp(CMD_ARGV[0], "arm") == 0) {
if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
command_print(CMD, "arm mode not supported on Cortex-M");
ret = ERROR_FAIL;
}if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) { ... } else {
arm->core_state = ARM_STATE_ARM;
}else { ... }
}if (strcmp(CMD_ARGV[0], "arm") == 0) { ... }
if (strcmp(CMD_ARGV[0], "thumb") == 0)
arm->core_state = ARM_STATE_THUMB;
}if (CMD_ARGC > 0) { ... }
command_print(CMD, "core state: %s", arm_state_strings[arm->core_state]);
return ret;
}{ ... }
COMMAND_HANDLER(handle_arm_disassemble_command)
{
#if HAVE_CAPSTONE
struct target *target = get_current_target(CMD_CTX);
if (!target) {
LOG_ERROR("No target selected");
return ERROR_FAIL;
}if (!target) { ... }
struct arm *arm = target_to_arm(target);
target_addr_t address;
unsigned int count = 1;
bool thumb = false;
if (!is_arm(arm)) {
command_print(CMD, "current target isn't an ARM");
return ERROR_FAIL;
}if (!is_arm(arm)) { ... }
if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
thumb = true;
}if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) { ... }
switch (CMD_ARGC) {
case 3:
if (strcmp(CMD_ARGV[2], "thumb") != 0)
return ERROR_COMMAND_SYNTAX_ERROR;
thumb = true;
case 3:
case 2:
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], count);
case 2:
case 1:
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
if (address & 0x01) {
if (!thumb) {
command_print(CMD, "Disassemble as Thumb");
thumb = true;
}if (!thumb) { ... }
address &= ~1;
}if (address & 0x01) { ... }
break;case 1:
default:
return ERROR_COMMAND_SYNTAX_ERROR;default
}switch (CMD_ARGC) { ... }
return arm_disassemble(CMD, target, address, count, thumb);/* ... */
#else
command_print(CMD, "capstone disassembly framework required");
return ERROR_FAIL;/* ... */
#endif
}{ ... }
COMMAND_HANDLER(handle_armv4_5_mcrmrc)
{
bool is_mcr = false;
unsigned int arg_cnt = 5;
if (!strcmp(CMD_NAME, "mcr")) {
is_mcr = true;
arg_cnt = 6;
}if (!strcmp(CMD_NAME, "mcr")) { ... }
if (arg_cnt != CMD_ARGC)
return ERROR_COMMAND_SYNTAX_ERROR;
struct target *target = get_current_target(CMD_CTX);
if (!target) {
command_print(CMD, "no current target");
return ERROR_FAIL;
}if (!target) { ... }
if (!target_was_examined(target)) {
command_print(CMD, "%s: not yet examined", target_name(target));
return ERROR_TARGET_NOT_EXAMINED;
}if (!target_was_examined(target)) { ... }
struct arm *arm = target_to_arm(target);
if (!is_arm(arm)) {
command_print(CMD, "%s: not an ARM", target_name(target));
return ERROR_FAIL;
}if (!is_arm(arm)) { ... }
if (target->state != TARGET_HALTED) {
command_print(CMD, "Error: [%s] not halted", target_name(target));
return ERROR_TARGET_NOT_HALTED;
}if (target->state != TARGET_HALTED) { ... }
int cpnum;
uint32_t op1;
uint32_t op2;
uint32_t crn;
uint32_t crm;
uint32_t value;
/* ... */
COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], cpnum);
if (cpnum & ~0xf) {
command_print(CMD, "coprocessor %d out of range", cpnum);
return ERROR_COMMAND_ARGUMENT_INVALID;
}if (cpnum & ~0xf) { ... }
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], op1);
if (op1 & ~0x7) {
command_print(CMD, "op1 %d out of range", op1);
return ERROR_COMMAND_ARGUMENT_INVALID;
}if (op1 & ~0x7) { ... }
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], crn);
if (crn & ~0xf) {
command_print(CMD, "CRn %d out of range", crn);
return ERROR_COMMAND_ARGUMENT_INVALID;
}if (crn & ~0xf) { ... }
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], crm);
if (crm & ~0xf) {
command_print(CMD, "CRm %d out of range", crm);
return ERROR_COMMAND_ARGUMENT_INVALID;
}if (crm & ~0xf) { ... }
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], op2);
if (op2 & ~0x7) {
command_print(CMD, "op2 %d out of range", op2);
return ERROR_COMMAND_ARGUMENT_INVALID;
}if (op2 & ~0x7) { ... }
/* ... */
if (is_mcr) {
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[5], value);
int retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value);
if (retval != ERROR_OK)
return retval;
}if (is_mcr) { ... } else {
value = 0;
int retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value);
if (retval != ERROR_OK)
return retval;
command_print(CMD, "0x%" PRIx32, value);
}else { ... }
return ERROR_OK;
}{ ... }
COMMAND_HANDLER(handle_armv4_5_mcrrmrrc)
{
bool is_mcrr = false;
unsigned int arg_cnt = 3;
if (!strcmp(CMD_NAME, "mcrr")) {
is_mcrr = true;
arg_cnt = 4;
}if (!strcmp(CMD_NAME, "mcrr")) { ... }
if (arg_cnt != CMD_ARGC)
return ERROR_COMMAND_SYNTAX_ERROR;
struct target *target = get_current_target(CMD_CTX);
if (!target) {
command_print(CMD, "no current target");
return ERROR_FAIL;
}if (!target) { ... }
if (!target_was_examined(target)) {
command_print(CMD, "%s: not yet examined", target_name(target));
return ERROR_TARGET_NOT_EXAMINED;
}if (!target_was_examined(target)) { ... }
struct arm *arm = target_to_arm(target);
if (!is_arm(arm)) {
command_print(CMD, "%s: not an ARM", target_name(target));
return ERROR_FAIL;
}if (!is_arm(arm)) { ... }
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
int cpnum;
uint32_t op1;
uint32_t crm;
uint64_t value;
/* ... */
COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], cpnum);
if (cpnum & ~0xf) {
command_print(CMD, "coprocessor %d out of range", cpnum);
return ERROR_COMMAND_ARGUMENT_INVALID;
}if (cpnum & ~0xf) { ... }
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], op1);
if (op1 & ~0xf) {
command_print(CMD, "op1 %d out of range", op1);
return ERROR_COMMAND_ARGUMENT_INVALID;
}if (op1 & ~0xf) { ... }
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], crm);
if (crm & ~0xf) {
command_print(CMD, "CRm %d out of range", crm);
return ERROR_COMMAND_ARGUMENT_INVALID;
}if (crm & ~0xf) { ... }
/* ... */
if (is_mcrr) {
COMMAND_PARSE_NUMBER(u64, CMD_ARGV[3], value);
int retval = arm->mcrr(target, cpnum, op1, crm, value);
if (retval != ERROR_OK)
return retval;
}if (is_mcrr) { ... } else {
value = 0;
int retval = arm->mrrc(target, cpnum, op1, crm, &value);
if (retval != ERROR_OK)
return retval;
command_print(CMD, "0x%" PRIx64, value);
}else { ... }
return ERROR_OK;
}{ ... }
static const struct command_registration arm_exec_command_handlers[] = {
{
.name = "reg",
.handler = handle_armv4_5_reg_command,
.mode = COMMAND_EXEC,
.help = "display ARM core registers",
.usage = "",
...},
{
.name = "mcr",
.mode = COMMAND_EXEC,
.handler = handle_armv4_5_mcrmrc,
.help = "write coprocessor register",
.usage = "cpnum op1 CRn CRm op2 value",
...},
{
.name = "mrc",
.mode = COMMAND_EXEC,
.handler = handle_armv4_5_mcrmrc,
.help = "read coprocessor register",
.usage = "cpnum op1 CRn CRm op2",
...},
{
.name = "mcrr",
.mode = COMMAND_EXEC,
.handler = handle_armv4_5_mcrrmrrc,
.help = "write coprocessor 64-bit register",
.usage = "cpnum op1 CRm value",
...},
{
.name = "mrrc",
.mode = COMMAND_EXEC,
.handler = handle_armv4_5_mcrrmrrc,
.help = "read coprocessor 64-bit register",
.usage = "cpnum op1 CRm",
...},
{
.chain = arm_all_profiles_command_handlers,
...},
COMMAND_REGISTRATION_DONE
...};
const struct command_registration arm_all_profiles_command_handlers[] = {
{
.name = "core_state",
.handler = handle_arm_core_state_command,
.mode = COMMAND_EXEC,
.usage = "['arm'|'thumb']",
.help = "display/change ARM core state",
...},
{
.name = "disassemble",
.handler = handle_arm_disassemble_command,
.mode = COMMAND_EXEC,
.usage = "address [count ['thumb']]",
.help = "disassemble instructions",
...},
{
.chain = semihosting_common_handlers,
...},
COMMAND_REGISTRATION_DONE
...};
const struct command_registration arm_command_handlers[] = {
{
.name = "arm",
.mode = COMMAND_ANY,
.help = "ARM command group",
.usage = "",
.chain = arm_exec_command_handlers,
...},
COMMAND_REGISTRATION_DONE
...};
/* ... */
const char *arm_get_gdb_arch(const struct target *target)
{
return "arm";
}{ ... }
int arm_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size,
enum target_register_class reg_class)
{
struct arm *arm = target_to_arm(target);
unsigned int i;
if (!is_arm_mode(arm->core_mode)) {
LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
}if (!is_arm_mode(arm->core_mode)) { ... }
switch (reg_class) {
case REG_CLASS_GENERAL:
*reg_list_size = 26;
*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
for (i = 0; i < 16; i++)
(*reg_list)[i] = arm_reg_current(arm, i);
for (i = 16; i < 24; i++)
(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
(*reg_list)[25] = arm->cpsr;
return ERROR_OK;
case REG_CLASS_GENERAL:
case REG_CLASS_ALL:
switch (arm->core_type) {
case ARM_CORE_TYPE_SEC_EXT:
*reg_list_size = 51;
break;case ARM_CORE_TYPE_SEC_EXT:
case ARM_CORE_TYPE_VIRT_EXT:
*reg_list_size = 53;
break;case ARM_CORE_TYPE_VIRT_EXT:
default:
*reg_list_size = 48;default
}switch (arm->core_type) { ... }
unsigned int list_size_core = *reg_list_size;
if (arm->arm_vfp_version == ARM_VFP_V3)
*reg_list_size += 33;
*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
for (i = 0; i < 16; i++)
(*reg_list)[i] = arm_reg_current(arm, i);
for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
int reg_index = arm->core_cache->reg_list[i].number;
if (arm_core_regs[i].mode == ARM_MODE_MON
&& arm->core_type != ARM_CORE_TYPE_SEC_EXT
&& arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
if (arm_core_regs[i].mode == ARM_MODE_HYP
&& arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
(*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
}for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) { ... }
for (i = 16; i < 24; i++) {
(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
(*reg_list)[i]->size = 0;
}for (i = 16; i < 24; i++) { ... }
(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
(*reg_list)[24]->size = 0;
if (arm->arm_vfp_version == ARM_VFP_V3) {
unsigned int num_core_regs = ARRAY_SIZE(arm_core_regs);
for (i = 0; i < 33; i++)
(*reg_list)[list_size_core + i] = &(arm->core_cache->reg_list[num_core_regs + i]);
}if (arm->arm_vfp_version == ARM_VFP_V3) { ... }
return ERROR_OK;
case REG_CLASS_ALL:
default:
LOG_ERROR("not a valid register class type in query.");
return ERROR_FAIL;default
}switch (reg_class) { ... }
}{ ... }
static int armv4_5_run_algorithm_completion(struct target *target,
uint32_t exit_point,
unsigned int timeout_ms,
void *arch_info)
{
int retval;
struct arm *arm = target_to_arm(target);
retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED) {
retval = target_halt(target);
if (retval != ERROR_OK)
return retval;
retval = target_wait_state(target, TARGET_HALTED, 500);
if (retval != ERROR_OK)
return retval;
return ERROR_TARGET_TIMEOUT;
}if (target->state != TARGET_HALTED) { ... }
if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
LOG_WARNING(
"target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
buf_get_u32(arm->pc->value, 0, 32));
return ERROR_TARGET_TIMEOUT;
}if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) { ... }
return ERROR_OK;
}{ ... }
int armv4_5_run_algorithm_inner(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
uint32_t entry_point, uint32_t exit_point,
unsigned int timeout_ms, void *arch_info,
int (*run_it)(struct target *target, uint32_t exit_point,
unsigned int timeout_ms, void *arch_info))
{
struct arm *arm = target_to_arm(target);
struct arm_algorithm *arm_algorithm_info = arch_info;
enum arm_state core_state = arm->core_state;
uint32_t context[17];
uint32_t cpsr;
int exit_breakpoint_size = 0;
int i;
int retval = ERROR_OK;
LOG_DEBUG("Running algorithm");
if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
LOG_ERROR("current target isn't an ARMV4/5 target");
return ERROR_TARGET_INVALID;
}if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) { ... }
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted (run target algo)");
return ERROR_TARGET_NOT_HALTED;
}if (target->state != TARGET_HALTED) { ... }
if (!is_arm_mode(arm->core_mode)) {
LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
}if (!is_arm_mode(arm->core_mode)) { ... }
if (!exit_point && arm->arch == ARM_ARCH_V4) {
LOG_ERROR("ARMv4 target needs HW breakpoint location");
return ERROR_FAIL;
}if (!exit_point && arm->arch == ARM_ARCH_V4) { ... }
/* ... */
for (i = 0; i <= 16; i++) {
struct reg *r;
r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm_algorithm_info->core_mode, i);
if (!r->valid)
arm->read_core_reg(target, r, i,
arm_algorithm_info->core_mode);
context[i] = buf_get_u32(r->value, 0, 32);
}for (i = 0; i <= 16; i++) { ... }
cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
for (i = 0; i < num_mem_params; i++) {
if (mem_params[i].direction == PARAM_IN)
continue;
retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
mem_params[i].value);
if (retval != ERROR_OK)
return retval;
}for (i = 0; i < num_mem_params; i++) { ... }
for (i = 0; i < num_reg_params; i++) {
if (reg_params[i].direction == PARAM_IN)
continue;
struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
return ERROR_COMMAND_SYNTAX_ERROR;
}if (!reg) { ... }
if (reg->size != reg_params[i].size) {
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
reg_params[i].reg_name);
return ERROR_COMMAND_SYNTAX_ERROR;
}if (reg->size != reg_params[i].size) { ... }
retval = armv4_5_set_core_reg(reg, reg_params[i].value);
if (retval != ERROR_OK)
return retval;
}for (i = 0; i < num_reg_params; i++) { ... }
arm->core_state = arm_algorithm_info->core_state;
if (arm->core_state == ARM_STATE_ARM)
exit_breakpoint_size = 4;
else if (arm->core_state == ARM_STATE_THUMB)
exit_breakpoint_size = 2;
else {
LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
return ERROR_COMMAND_SYNTAX_ERROR;
}else { ... }
if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
LOG_DEBUG("setting core_mode: 0x%2.2x",
arm_algorithm_info->core_mode);
buf_set_u32(arm->cpsr->value, 0, 5,
arm_algorithm_info->core_mode);
arm->cpsr->dirty = true;
arm->cpsr->valid = true;
}if (arm_algorithm_info->core_mode != ARM_MODE_ANY) { ... }
if (exit_point) {
retval = breakpoint_add(target, exit_point,
exit_breakpoint_size, BKPT_HARD);
if (retval != ERROR_OK) {
LOG_ERROR("can't add HW breakpoint to terminate algorithm");
return ERROR_TARGET_FAILURE;
}if (retval != ERROR_OK) { ... }
}if (exit_point) { ... }
retval = target_resume(target, 0, entry_point, 1, 1);
if (retval != ERROR_OK)
return retval;
retval = run_it(target, exit_point, timeout_ms, arch_info);
if (exit_point)
breakpoint_remove(target, exit_point);
if (retval != ERROR_OK)
return retval;
for (i = 0; i < num_mem_params; i++) {
if (mem_params[i].direction != PARAM_OUT) {
int retvaltemp = target_read_buffer(target, mem_params[i].address,
mem_params[i].size,
mem_params[i].value);
if (retvaltemp != ERROR_OK)
retval = retvaltemp;
}if (mem_params[i].direction != PARAM_OUT) { ... }
}for (i = 0; i < num_mem_params; i++) { ... }
for (i = 0; i < num_reg_params; i++) {
if (reg_params[i].direction != PARAM_OUT) {
struct reg *reg = register_get_by_name(arm->core_cache,
reg_params[i].reg_name,
false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
retval = ERROR_COMMAND_SYNTAX_ERROR;
continue;
}if (!reg) { ... }
if (reg->size != reg_params[i].size) {
LOG_ERROR(
"BUG: register '%s' size doesn't match reg_params[i].size",
reg_params[i].reg_name);
retval = ERROR_COMMAND_SYNTAX_ERROR;
continue;
}if (reg->size != reg_params[i].size) { ... }
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
}if (reg_params[i].direction != PARAM_OUT) { ... }
}for (i = 0; i < num_reg_params; i++) { ... }
for (i = 0; i <= 16; i++) {
uint32_t regvalue;
regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm_algorithm_info->core_mode, i).value, 0, 32);
if (regvalue != context[i]) {
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm_algorithm_info->core_mode, i).name, context[i]);
buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache