OpenOCD
Select one of the symbols to view example projects that use it.
 
Outline
#include "config.h"
#include <helper/log.h>
#include "target.h"
#include "armv4_5_mmu.h"
armv4_5_mmu_translate_va(struct target *, struct armv4_5_mmu_common *, uint32_t, uint32_t *, uint32_t *)
armv4_5_mmu_read_physical(struct target *, struct armv4_5_mmu_common *, uint32_t, uint32_t, uint32_t, uint8_t *)
armv4_5_mmu_write_physical(struct target *, struct armv4_5_mmu_common *, uint32_t, uint32_t, uint32_t, const uint8_t *)
Files
loading...
SourceVuDevelopment ToolsOpenOCDsrc/target/armv4_5_mmu.c
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * ***************************************************************************//* ... */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include <helper/log.h> #include "target.h" #include "armv4_5_mmu.h" int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val) { uint32_t first_lvl_descriptor = 0x0; uint32_t second_lvl_descriptor = 0x0; uint32_t ttb; int retval; retval = armv4_5_mmu->get_ttb(target, &ttb); if (retval != ERROR_OK) return retval; retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18), 4, 1, (uint8_t *)&first_lvl_descriptor); if (retval != ERROR_OK) return retval; first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&first_lvl_descriptor); LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor); if ((first_lvl_descriptor & 0x3) == 0) { LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; }if ((first_lvl_descriptor & 0x3) == 0) { ... } if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3)) { LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; }if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3)) { ... } if ((first_lvl_descriptor & 0x3) == 2) { /* section descriptor */ *cb = (first_lvl_descriptor & 0xc) >> 2; *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff); return ERROR_OK; }if ((first_lvl_descriptor & 0x3) == 2) { ... } if ((first_lvl_descriptor & 0x3) == 1) { /* coarse page table */ retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10), 4, 1, (uint8_t *)&second_lvl_descriptor); if (retval != ERROR_OK) return retval; }if ((first_lvl_descriptor & 0x3) == 1) { ... } else if ((first_lvl_descriptor & 0x3) == 3) { /* fine page table */ retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8), 4, 1, (uint8_t *)&second_lvl_descriptor); if (retval != ERROR_OK) return retval; }else if ((first_lvl_descriptor & 0x3) == 3) { ... } second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&second_lvl_descriptor); LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor); if ((second_lvl_descriptor & 0x3) == 0) { LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; }if ((second_lvl_descriptor & 0x3) == 0) { ... } /* cacheable/bufferable is always specified in bits 3-2 */ *cb = (second_lvl_descriptor & 0xc) >> 2; if ((second_lvl_descriptor & 0x3) == 1) { /* large page descriptor */ *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff); return ERROR_OK; }if ((second_lvl_descriptor & 0x3) == 1) { ... } if ((second_lvl_descriptor & 0x3) == 2) { /* small page descriptor */ *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff); return ERROR_OK; }if ((second_lvl_descriptor & 0x3) == 2) { ... } if ((second_lvl_descriptor & 0x3) == 3) { /* tiny page descriptor */ *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff); return ERROR_OK; }if ((second_lvl_descriptor & 0x3) == 3) { ... } /* should not happen */ LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; }{ ... } int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; if (target->state != TARGET_HALTED) { LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; }if (target->state != TARGET_HALTED) { ... } /* disable MMU and data (or unified) cache */ retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0); if (retval != ERROR_OK) return retval; retval = armv4_5_mmu->read_memory(target, address, size, count, buffer); if (retval != ERROR_OK) return retval; /* reenable MMU / cache */ retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled, armv4_5_mmu->armv4_5_cache.d_u_cache_enabled, armv4_5_mmu->armv4_5_cache.i_cache_enabled); if (retval != ERROR_OK) return retval; return retval; }{ ... } int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { int retval; if (target->state != TARGET_HALTED) { LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; }if (target->state != TARGET_HALTED) { ... } /* disable MMU and data (or unified) cache */ retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0); if (retval != ERROR_OK) return retval; retval = armv4_5_mmu->write_memory(target, address, size, count, buffer); if (retval != ERROR_OK) return retval; /* reenable MMU / cache */ retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled, armv4_5_mmu->armv4_5_cache.d_u_cache_enabled, armv4_5_mmu->armv4_5_cache.i_cache_enabled); if (retval != ERROR_OK) return retval; return retval; }{ ... }
Details
Show:
from
Types: Columns:
Click anywhere in the source to view detailed information here...