arm11_write_dscr() function

Target state variable.

DSCR content

Restore processor state. This is called in preparation for the RESTART function.

Check and if necessary take control of the system

Save processor state. This is called after a HALT instruction succeeds, and on other occasions the processor enters debug mode (breakpoint, watchpoint, etc). Caller has updated arm11->dscr.

Code de-clutter: Construct struct scan_field to write out a value

Write JTAG instruction register \remarks This adds to the JTAG command queue but does \em not execute it.

Select and write to Scan Chain Register (SCREG) This function sets the instruction register to SCAN_N and writes the data register with the selected chain number. http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html Changes the current scan chain if needed, transitions to the specified TAP state, and leaves the IR undefined. The chain takes effect when Update-DR is passed (usually when subsequently the INTEXT/EXTEST instructions are written). \warning (Obsolete) Using this twice in a row will \em fail. The first call will end in Pause-DR. The second call, due to the IR caching, will not go through Capture-DR when shifting in the new scan chain number. As a result the verification in arm11_in_handler_scan_n() must fail. \remarks This adds to the JTAG command queue but does \em not execute it.

Read and save the Debug Status and Control Register (DSCR). \remarks This is a stand-alone function that executes the JTAG command queue. It does not require the ARM11 debug TAP to be in any particular state.

Prepare the stage for ITR/DTR operations from the arm11_run_instr... group of functions. Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish() around a block of arm11_run_instr_... calls. Select scan chain 5 to allow quick access to DTR. When scan chain 4 is needed to put in a register the ITRSel instruction shortcut is used instead of actually changing the Scan_N register.

Cleanup after ITR/DTR operations from the arm11_run_instr... group of functions Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish() around a block of arm11_run_instr_... calls. Any IDLE can lead to an instruction execution when scan chains 4 or 5 are selected and the IR holds INTEST or EXTEST. So we must disable that before any following activities lead to an IDLE.

Execute one instruction via ITR \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Execute one instruction via ITR repeatedly while passing data to the core via DTR on each execution. Caller guarantees that processor is in debug state, that DSCR_ITR_EN is set, the ITR Ready flag is set (as seen on the previous entry to TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. The executed instruction \em must read data from DTR. \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Execute one instruction via ITR repeatedly while passing data to the core via DTR on each execution. Caller guarantees that processor is in debug state, that DSCR_ITR_EN is set, the ITR Ready flag is set (as seen on the previous entry to TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. No Ready check during transmission. The executed instruction \em must read data from DTR. \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Execute an instruction via ITR while handing data into the core via DTR. The executed instruction \em must read data from DTR. \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Execute one instruction via ITR repeatedly while reading data from the core via DTR on each execution. Caller guarantees that processor is in debug state, that DSCR_ITR_EN is set, the ITR Ready flag is set (as seen on the previous entry to TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. The executed instruction \em must write data to DTR. \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Execute one instruction via ITR then load r0 into DTR and read DTR from core. The first executed instruction (\p opcode) should write data to r0. \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Load data into core via DTR then move it to r0 then execute one instruction via ITR The final executed instruction (\p opcode) should read data from r0. \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Apply reads and writes to scan chain 7 \see struct arm11_sc7_action

Clear VCR and all breakpoints and watchpoints via scan chain 7

Write VCR register

Read word from address

Set up high-level debug module utilities

Flush any pending breakpoint and watchpoint updates.

Execute one or more instructions via ITR. Caller guarantees that processor is in debug state, that DSCR_ITR_EN is set, the ITR Ready flag is set (as seen on the previous entry to TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Queue a DR scan of the ITR register. Caller must have selected scan chain 4 (ITR), possibly using ITRSEL. Going through the TAP_DRUPDATE state writes ITR only if Ready was previously set. Only the Ready flag is readable by the scan. An instruction loaded into ITR is executed when going through the TAP_IDLE state only if Ready was previously set and the debug state is properly set up. Depending on the instruction, you may also need to ensure that the rDTR is ready before that Run-Test/Idle state.