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/* ... */
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "arm.h"
#include "arm_dpm.h"
#include "armv8_dpm.h"
#include <jtag/jtag.h>
#include "register.h"
#include "breakpoints.h"
#include "target_type.h"
#include "arm_opcodes.h"
8 includes
/* ... */
/* ... */
static int dpm_mrc(struct target *target, int cpnum,
uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
uint32_t *value)
{
struct arm *arm = target_to_arm(target);
struct arm_dpm *dpm = arm->dpm;
int retval;
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
(int) op1, (int) crn,
(int) crm, (int) op2);
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
value);
dpm->finish(dpm);
return retval;
}{ ... }
static int dpm_mrrc(struct target *target, int cpnum,
uint32_t op, uint32_t crm, uint64_t *value)
{
struct arm *arm = target_to_arm(target);
struct arm_dpm *dpm = arm->dpm;
int retval;
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("MRRC p%d, %d, r0, r1, c%d", cpnum,
(int)op, (int)crm);
retval = dpm->instr_read_data_r0_r1(dpm,
ARMV5_T_MRRC(cpnum, op, 0, 1, crm),
value);
dpm->finish(dpm);
return retval;
}{ ... }
static int dpm_mcr(struct target *target, int cpnum,
uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
uint32_t value)
{
struct arm *arm = target_to_arm(target);
struct arm_dpm *dpm = arm->dpm;
int retval;
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
(int) op1, (int) crn,
(int) crm, (int) op2);
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
value);
dpm->finish(dpm);
return retval;
}{ ... }
static int dpm_mcrr(struct target *target, int cpnum,
uint32_t op, uint32_t crm, uint64_t value)
{
struct arm *arm = target_to_arm(target);
struct arm_dpm *dpm = arm->dpm;
int retval;
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("MCRR p%d, %d, r0, r1, c%d", cpnum,
(int)op, (int)crm);
retval = dpm->instr_write_data_r0_r1(dpm,
ARMV5_T_MCRR(cpnum, op, 0, 1, crm), value);
dpm->finish(dpm);
return retval;
}{ ... }
/* ... */
/* ... */
int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
{
int retval;
uint32_t cpsr;
if (mode == ARM_MODE_ANY)
cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
else
cpsr = mode;
retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
if (retval != ERROR_OK)
return retval;
if (dpm->instr_cpsr_sync)
retval = dpm->instr_cpsr_sync(dpm);
return retval;
}{ ... }
static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
{
int retval = ERROR_FAIL;
uint32_t value_r0, value_r1;
switch (regnum) {
case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
/* ... */
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_VMOV(1, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4),
((regnum - ARM_VFP_V3_D0) & 0xf)), &value_r0);
if (retval != ERROR_OK)
break;
retval = dpm->instr_read_data_dcc(dpm,
ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
&value_r1);
break;case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
default:
break;default
}switch (regnum) { ... }
if (retval == ERROR_OK) {
buf_set_u32(r->value, 0, 32, value_r0);
buf_set_u32(r->value + 4, 0, 32, value_r1);
r->valid = true;
r->dirty = false;
LOG_DEBUG("READ: %s, %8.8x, %8.8x", r->name,
(unsigned) value_r0, (unsigned) value_r1);
}if (retval == ERROR_OK) { ... }
return retval;
}{ ... }
int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
{
uint32_t value;
int retval;
switch (regnum) {
case 0 ... 14:
retval = dpm->instr_read_data_dcc(dpm,
ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
&value);
break;case 0 ... 14:
case 15:
/* ... */
retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
/* ... */
switch (dpm->arm->core_state) {
case ARM_STATE_ARM:
value -= 8;
break;case ARM_STATE_ARM:
case ARM_STATE_THUMB:
case ARM_STATE_THUMB_EE:
value -= 4;
break;case ARM_STATE_THUMB_EE:
case ARM_STATE_JAZELLE:
LOG_WARNING("Jazelle PC adjustment unknown");
break;case ARM_STATE_JAZELLE:
default:
LOG_WARNING("unknown core state");
break;default
}switch (dpm->arm->core_state) { ... }
break;case 15:
case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
return dpm_read_reg_u64(dpm, r, regnum);case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
case ARM_VFP_V3_FPSCR:
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_VMRS(0), &value);
break;case ARM_VFP_V3_FPSCR:
default:
/* ... */
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_MRS(0, regnum & 1),
&value);
break;default
}switch (regnum) { ... }
if (retval == ERROR_OK) {
buf_set_u32(r->value, 0, 32, value);
r->valid = true;
r->dirty = false;
LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
}if (retval == ERROR_OK) { ... }
return retval;
}{ ... }
static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
{
int retval = ERROR_FAIL;
uint32_t value_r0 = buf_get_u32(r->value, 0, 32);
uint32_t value_r1 = buf_get_u32(r->value + 4, 0, 32);
switch (regnum) {
case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
retval = dpm->instr_write_data_dcc(dpm,
ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
value_r1);
if (retval != ERROR_OK)
break;
/* ... */
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_VMOV(0, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4),
((regnum - ARM_VFP_V3_D0) & 0xf)), value_r0);
break;case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
default:
break;default
}switch (regnum) { ... }
if (retval == ERROR_OK) {
r->dirty = false;
LOG_DEBUG("WRITE: %s, %8.8x, %8.8x", r->name,
(unsigned) value_r0, (unsigned) value_r1);
}if (retval == ERROR_OK) { ... }
return retval;
}{ ... }
static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
{
int retval;
uint32_t value = buf_get_u32(r->value, 0, 32);
switch (regnum) {
case 0 ... 14:
retval = dpm->instr_write_data_dcc(dpm,
ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
value);
break;case 0 ... 14:
case 15:
/* ... */
retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
break;case 15:
case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
return dpm_write_reg_u64(dpm, r, regnum);case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
case ARM_VFP_V3_FPSCR:
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_VMSR(0), value);
break;case ARM_VFP_V3_FPSCR:
default:
/* ... */
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
value);
if (retval != ERROR_OK)
return retval;
if (regnum == 16 && dpm->instr_cpsr_sync)
retval = dpm->instr_cpsr_sync(dpm);
break;default
}switch (regnum) { ... }
if (retval == ERROR_OK) {
r->dirty = false;
LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
}if (retval == ERROR_OK) { ... }
return retval;
}{ ... }
/* ... */
static int dpm_write_pc_core_state(struct arm_dpm *dpm, struct reg *r)
{
uint32_t value = buf_get_u32(r->value, 0, 32);
return dpm->instr_write_data_r0(dpm, ARMV4_5_BX(0), value);
}{ ... }
/* ... */
int arm_dpm_read_current_registers(struct arm_dpm *dpm)
{
struct arm *arm = dpm->arm;
uint32_t cpsr;
int retval;
struct reg *r;
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
return retval;
for (unsigned i = 0; i < 2; i++) {
r = arm->core_cache->reg_list + i;
if (!r->valid) {
retval = arm_dpm_read_reg(dpm, r, i);
if (retval != ERROR_OK)
goto fail;
}if (!r->valid) { ... }
r->dirty = true;
}for (unsigned i = 0; i < 2; i++) { ... }
retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRS(0, 0), &cpsr);
if (retval != ERROR_OK)
goto fail;
arm_set_cpsr(arm, cpsr);
for (unsigned i = 2; i < 16; i++) {
r = arm_reg_current(arm, i);
if (r->valid)
continue;
retval = arm_dpm_read_reg(dpm, r, i);
if (retval != ERROR_OK)
goto fail;
}for (unsigned i = 2; i < 16; i++) { ... }
/* ... */
fail:
dpm->finish(dpm);
return retval;
}{ ... }
/* ... */
static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
struct dpm_bpwp *xp, bool *set_p)
{
int retval = ERROR_OK;
bool disable;
if (!set_p) {
if (!xp->dirty)
goto done;
xp->dirty = false;
disable = true;
}if (!set_p) { ... } else if (bpwp) {
if (!xp->dirty)
goto done;
xp->dirty = disable = false;
*set_p = true;
}else if (bpwp) { ... } else {
if (!*set_p)
goto done;
xp->dirty = disable = true;
*set_p = false;
}else { ... }
if (disable)
retval = dpm->bpwp_disable(dpm, xp->number);
else
retval = dpm->bpwp_enable(dpm, xp->number,
xp->address, xp->control);
if (retval != ERROR_OK)
LOG_ERROR("%s: can't %s HW %spoint %d",
disable ? "disable" : "enable",
target_name(dpm->arm->target),
(xp->number < 16) ? "break" : "watch",
xp->number & 0xf);
done:
return retval;
}{ ... }
static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp);
/* ... */
int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
{
struct arm *arm = dpm->arm;
struct reg_cache *cache = arm->core_cache;
int retval;
bool did_write;
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
goto done;
/* ... */
if (arm->target->type->add_breakpoint == dpm_add_breakpoint) {
for (unsigned i = 0; i < dpm->nbp; i++) {
struct dpm_bp *dbp = dpm->dbp + i;
struct breakpoint *bp = dbp->bp;
retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
bp ? &bp->is_set : NULL);
if (retval != ERROR_OK)
goto done;
}for (unsigned i = 0; i < dpm->nbp; i++) { ... }
}if (arm->target->type->add_breakpoint == dpm_add_breakpoint) { ... }
for (unsigned i = 0; i < dpm->nwp; i++) {
struct dpm_wp *dwp = dpm->dwp + i;
struct watchpoint *wp = dwp->wp;
retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
wp ? &wp->is_set : NULL);
if (retval != ERROR_OK)
goto done;
}for (unsigned i = 0; i < dpm->nwp; i++) { ... }
/* ... */
/* ... */
do {
enum arm_mode mode = ARM_MODE_ANY;
did_write = false;
for (unsigned i = 2; i < cache->num_regs; i++) {
struct arm_reg *r;
unsigned regnum;
if (i == 15)
continue;
if (arm->cpsr == cache->reg_list + i)
continue;
if (!cache->reg_list[i].exist || !cache->reg_list[i].dirty)
continue;
r = cache->reg_list[i].arch_info;
regnum = r->num;
if (!did_write) {
enum arm_mode tmode;
did_write = true;
mode = tmode = r->mode;
switch (regnum) {
case 8 ... 12:
/* ... */
if (arm->core_mode == ARM_MODE_FIQ
&& ARM_MODE_ANY
!= mode)
tmode = ARM_MODE_USR;
break;case 8 ... 12:
case 16:
regnum++;
break;case 16:
}switch (regnum) { ... }
if (tmode != ARM_MODE_ANY) {
retval = arm_dpm_modeswitch(dpm, tmode);
if (retval != ERROR_OK)
goto done;
}if (tmode != ARM_MODE_ANY) { ... }
}if (!did_write) { ... }
if (r->mode != mode)
continue;
retval = dpm_write_reg(dpm,
&cache->reg_list[i],
regnum);
if (retval != ERROR_OK)
goto done;
}for (unsigned i = 2; i < cache->num_regs; i++) { ... }
...} while (did_write);
/* ... */
retval = arm_dpm_modeswitch(dpm, ARM_MODE_ANY);
if (retval != ERROR_OK)
goto done;
arm->cpsr->dirty = false;
/* ... */
retval = dpm_write_pc_core_state(dpm, arm->pc);
if (retval != ERROR_OK)
goto done;
/* ... */
retval = dpm_write_reg(dpm, arm->pc, 15);
if (retval != ERROR_OK)
goto done;
arm->pc->dirty = false;
for (unsigned i = 0; i < 2; i++) {
retval = dpm_write_reg(dpm, &cache->reg_list[i], i);
if (retval != ERROR_OK)
goto done;
cache->reg_list[i].dirty = false;
}for (unsigned i = 0; i < 2; i++) { ... }
dpm->finish(dpm);
done:
return retval;
}{ ... }
/* ... */
static enum arm_mode dpm_mapmode(struct arm *arm,
unsigned num, enum arm_mode mode)
{
enum arm_mode amode = arm->core_mode;
if (amode == ARM_MODE_SYS)
amode = ARM_MODE_USR;
if (mode == amode)
return ARM_MODE_ANY;
switch (num) {
case 0 ... 7:
case 15:
case 16:
break;
case 16:
case 8 ... 12:
if (mode == ARM_MODE_FIQ)
return mode;
break;
case 8 ... 12:
case 13:
case 14:
case ARM_VFP_V3_D0 ... ARM_VFP_V3_FPSCR:
return mode;case ARM_VFP_V3_D0 ... ARM_VFP_V3_FPSCR:
default:
LOG_WARNING("invalid register #%u", num);
break;default
}switch (num) { ... }
return ARM_MODE_ANY;
}{ ... }
/* ... */
static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
int regnum, enum arm_mode mode)
{
struct arm_dpm *dpm = target_to_arm(target)->dpm;
int retval;
if (regnum < 0 || (regnum > 16 && regnum < ARM_VFP_V3_D0) ||
(regnum > ARM_VFP_V3_FPSCR))
return ERROR_COMMAND_SYNTAX_ERROR;
if (regnum == 16) {
if (mode != ARM_MODE_ANY)
regnum = 17;
}if (regnum == 16) { ... } else
mode = dpm_mapmode(dpm->arm, regnum, mode);
/* ... */
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
return retval;
if (mode != ARM_MODE_ANY) {
retval = arm_dpm_modeswitch(dpm, mode);
if (retval != ERROR_OK)
goto fail;
}if (mode != ARM_MODE_ANY) { ... }
retval = arm_dpm_read_reg(dpm, r, regnum);
if (retval != ERROR_OK)
goto fail;
if (mode != ARM_MODE_ANY)
arm_dpm_modeswitch(dpm, ARM_MODE_ANY);
fail:
dpm->finish(dpm);
return retval;
}{ ... }
static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
int regnum, enum arm_mode mode, uint8_t *value)
{
struct arm_dpm *dpm = target_to_arm(target)->dpm;
int retval;
if (regnum < 0 || (regnum > 16 && regnum < ARM_VFP_V3_D0) ||
(regnum > ARM_VFP_V3_FPSCR))
return ERROR_COMMAND_SYNTAX_ERROR;
if (regnum == 16) {
if (mode != ARM_MODE_ANY)
regnum = 17;
}if (regnum == 16) { ... } else
mode = dpm_mapmode(dpm->arm, regnum, mode);
/* ... */
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
return retval;
if (mode != ARM_MODE_ANY) {
retval = arm_dpm_modeswitch(dpm, mode);
if (retval != ERROR_OK)
goto fail;
}if (mode != ARM_MODE_ANY) { ... }
retval = dpm_write_reg(dpm, r, regnum);
if (mode != ARM_MODE_ANY)
arm_dpm_modeswitch(dpm, ARM_MODE_ANY);
fail:
dpm->finish(dpm);
return retval;
}{ ... }
static int arm_dpm_full_context(struct target *target)
{
struct arm *arm = target_to_arm(target);
struct arm_dpm *dpm = arm->dpm;
struct reg_cache *cache = arm->core_cache;
int retval;
bool did_read;
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
goto done;
do {
enum arm_mode mode = ARM_MODE_ANY;
did_read = false;
/* ... */
for (unsigned i = 0; i < cache->num_regs; i++) {
struct arm_reg *r;
if (!cache->reg_list[i].exist || cache->reg_list[i].valid)
continue;
r = cache->reg_list[i].arch_info;
if (!did_read) {
did_read = true;
mode = r->mode;
/* ... */
if (mode != ARM_MODE_ANY)
retval = arm_dpm_modeswitch(dpm, mode);
else
retval = arm_dpm_modeswitch(dpm, ARM_MODE_USR);
if (retval != ERROR_OK)
goto done;
}if (!did_read) { ... }
if (r->mode != mode)
continue;
retval = arm_dpm_read_reg(dpm,
&cache->reg_list[i],
(r->num == 16) ? 17 : r->num);
if (retval != ERROR_OK)
goto done;
}for (unsigned i = 0; i < cache->num_regs; i++) { ... }
...} while (did_read);
retval = arm_dpm_modeswitch(dpm, ARM_MODE_ANY);
dpm->finish(dpm);
done:
return retval;
}{ ... }
/* ... */
static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
uint32_t addr, uint32_t length)
{
uint32_t control;
control = (1 << 0)
| (3 << 1);
/* ... */
switch (length) {
case 1:
control |= (1 << (addr & 3)) << 5;
break;case 1:
case 2:
if (!(addr & 1)) {
control |= (3 << (addr & 2)) << 5;
break;
}if (!(addr & 1)) { ... }
case 2:
case 4:
if (!(addr & 3)) {
control |= 0xf << 5;
break;
}if (!(addr & 3)) { ... }
case 4:
default:
LOG_ERROR("unsupported {break,watch}point length/alignment");
return ERROR_COMMAND_SYNTAX_ERROR;default
}switch (length) { ... }
/* ... */
xp->address = addr & ~3;
xp->control = control;
xp->dirty = true;
LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
xp->address, control, xp->number);
return ERROR_OK;
}{ ... }
static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp)
{
struct arm *arm = target_to_arm(target);
struct arm_dpm *dpm = arm->dpm;
int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
if (bp->length < 2)
return ERROR_COMMAND_SYNTAX_ERROR;
if (!dpm->bpwp_enable)
return retval;
if (bp->type == BKPT_SOFT)
LOG_DEBUG("using HW bkpt, not SW...");
for (unsigned i = 0; i < dpm->nbp; i++) {
if (!dpm->dbp[i].bp) {
retval = dpm_bpwp_setup(dpm, &dpm->dbp[i].bpwp,
bp->address, bp->length);
if (retval == ERROR_OK)
dpm->dbp[i].bp = bp;
break;
}if (!dpm->dbp[i].bp) { ... }
}for (unsigned i = 0; i < dpm->nbp; i++) { ... }
return retval;
}{ ... }
static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp)
{
struct arm *arm = target_to_arm(target);
struct arm_dpm *dpm = arm->dpm;
int retval = ERROR_COMMAND_SYNTAX_ERROR;
for (unsigned i = 0; i < dpm->nbp; i++) {
if (dpm->dbp[i].bp == bp) {
dpm->dbp[i].bp = NULL;
dpm->dbp[i].bpwp.dirty = true;
retval = ERROR_OK;
break;
}if (dpm->dbp[i].bp == bp) { ... }
}for (unsigned i = 0; i < dpm->nbp; i++) { ... }
return retval;
}{ ... }
static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
struct watchpoint *wp)
{
int retval;
struct dpm_wp *dwp = dpm->dwp + index_t;
uint32_t control;
if (wp->mask != WATCHPOINT_IGNORE_DATA_VALUE_MASK) {
LOG_DEBUG("watchpoint values and masking not supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}if (wp->mask != WATCHPOINT_IGNORE_DATA_VALUE_MASK) { ... }
retval = dpm_bpwp_setup(dpm, &dwp->bpwp, wp->address, wp->length);
if (retval != ERROR_OK)
return retval;
control = dwp->bpwp.control;
switch (wp->rw) {
case WPT_READ:
control |= 1 << 3;
break;case WPT_READ:
case WPT_WRITE:
control |= 2 << 3;
break;case WPT_WRITE:
case WPT_ACCESS:
control |= 3 << 3;
break;case WPT_ACCESS:
}switch (wp->rw) { ... }
dwp->bpwp.control = control;
dpm->dwp[index_t].wp = wp;
return retval;
}{ ... }
static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp)
{
struct arm *arm = target_to_arm(target);
struct arm_dpm *dpm = arm->dpm;
int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
if (dpm->bpwp_enable) {
for (unsigned i = 0; i < dpm->nwp; i++) {
if (!dpm->dwp[i].wp) {
retval = dpm_watchpoint_setup(dpm, i, wp);
break;
}if (!dpm->dwp[i].wp) { ... }
}for (unsigned i = 0; i < dpm->nwp; i++) { ... }
}if (dpm->bpwp_enable) { ... }
return retval;
}{ ... }
static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
{
struct arm *arm = target_to_arm(target);
struct arm_dpm *dpm = arm->dpm;
int retval = ERROR_COMMAND_SYNTAX_ERROR;
for (unsigned i = 0; i < dpm->nwp; i++) {
if (dpm->dwp[i].wp == wp) {
dpm->dwp[i].wp = NULL;
dpm->dwp[i].bpwp.dirty = true;
retval = ERROR_OK;
break;
}if (dpm->dwp[i].wp == wp) { ... }
}for (unsigned i = 0; i < dpm->nwp; i++) { ... }
return retval;
}{ ... }
void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
{
switch (dpm->arm->core_state) {
case ARM_STATE_ARM:
addr -= 8;
break;case ARM_STATE_ARM:
case ARM_STATE_THUMB:
case ARM_STATE_THUMB_EE:
addr -= 4;
break;case ARM_STATE_THUMB_EE:
case ARM_STATE_JAZELLE:
case ARM_STATE_AARCH64:
break;case ARM_STATE_AARCH64:
}switch (dpm->arm->core_state) { ... }
dpm->wp_addr = addr;
}{ ... }
/* ... */
void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
{
struct target *target = dpm->arm->target;
dpm->dscr = dscr;
switch (DSCR_ENTRY(dscr)) {
case DSCR_ENTRY_HALT_REQ:
case DSCR_ENTRY_EXT_DBG_REQ:
target->debug_reason = DBG_REASON_DBGRQ;
break;case DSCR_ENTRY_EXT_DBG_REQ:
case DSCR_ENTRY_BREAKPOINT:
case DSCR_ENTRY_BKPT_INSTR:
target->debug_reason = DBG_REASON_BREAKPOINT;
break;case DSCR_ENTRY_BKPT_INSTR:
case DSCR_ENTRY_IMPRECISE_WATCHPT:
case DSCR_ENTRY_PRECISE_WATCHPT:
target->debug_reason = DBG_REASON_WATCHPOINT;
break;case DSCR_ENTRY_PRECISE_WATCHPT:
default:
target->debug_reason = DBG_REASON_UNDEFINED;
break;default
}switch (DSCR_ENTRY(dscr)) { ... }
}{ ... }
/* ... */
/* ... */
int arm_dpm_setup(struct arm_dpm *dpm)
{
struct arm *arm = dpm->arm;
struct target *target = arm->target;
struct reg_cache *cache = NULL;
arm->dpm = dpm;
arm->full_context = arm_dpm_full_context;
arm->read_core_reg = arm_dpm_read_core_reg;
arm->write_core_reg = arm_dpm_write_core_reg;
if (!arm->core_cache) {
cache = arm_build_reg_cache(target, arm);
if (!cache)
return ERROR_FAIL;
*register_get_last_cache_p(&target->reg_cache) = cache;
}if (!arm->core_cache) { ... }
arm->mrc = dpm_mrc;
arm->mcr = dpm_mcr;
arm->mrrc = dpm_mrrc;
arm->mcrr = dpm_mcrr;
if (!target->type->add_breakpoint) {
target->type->add_breakpoint = dpm_add_breakpoint;
target->type->remove_breakpoint = dpm_remove_breakpoint;
}if (!target->type->add_breakpoint) { ... }
if (!target->type->add_watchpoint) {
target->type->add_watchpoint = dpm_add_watchpoint;
target->type->remove_watchpoint = dpm_remove_watchpoint;
}if (!target->type->add_watchpoint) { ... }
dpm->nbp = 1 + ((dpm->didr >> 24) & 0xf);
dpm->nwp = 1 + ((dpm->didr >> 28) & 0xf);
dpm->dbp = calloc(dpm->nbp, sizeof(*dpm->dbp));
dpm->dwp = calloc(dpm->nwp, sizeof(*dpm->dwp));
if (!dpm->dbp || !dpm->dwp) {
arm_free_reg_cache(arm);
free(dpm->dbp);
free(dpm->dwp);
return ERROR_FAIL;
}if (!dpm->dbp || !dpm->dwp) { ... }
LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
target_name(target), dpm->nbp, dpm->nwp);
/* ... */
return ERROR_OK;
}{ ... }
/* ... */
int arm_dpm_initialize(struct arm_dpm *dpm)
{
if (dpm->bpwp_disable) {
unsigned i;
for (i = 0; i < dpm->nbp; i++) {
dpm->dbp[i].bpwp.number = i;
(void) dpm->bpwp_disable(dpm, i);
}for (i = 0; i < dpm->nbp; i++) { ... }
for (i = 0; i < dpm->nwp; i++) {
dpm->dwp[i].bpwp.number = 16 + i;
(void) dpm->bpwp_disable(dpm, 16 + i);
}for (i = 0; i < dpm->nwp; i++) { ... }
}if (dpm->bpwp_disable) { ... } else
LOG_WARNING("%s: can't disable breakpoints and watchpoints",
target_name(dpm->arm->target));
return ERROR_OK;
}{ ... }