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#include <assert.h>
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#include <stdlib.h>
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#include <time.h>
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#include "config.h"
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#include "target/target.h"
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#include "target/algorithm.h"
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#include "target/target_type.h"
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#include <helper/log.h>
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#include "jtag/jtag.h"
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#include "target/register.h"
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#include "target/breakpoints.h"
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#include "helper/time_support.h"
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#include "helper/list.h"
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#include "riscv.h"
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#include "debug_defines.h"
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#include "rtos/rtos.h"
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#include "program.h"
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#include "asm.h"
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#include "batch.h"
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#define get_field
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#define set_field
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#define CSR_DCSR_CAUSE_SWBP
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#define CSR_DCSR_CAUSE_TRIGGER
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#define CSR_DCSR_CAUSE_DEBUGINT
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#define CSR_DCSR_CAUSE_STEP
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#define CSR_DCSR_CAUSE_HALT
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#define CSR_DCSR_CAUSE_GROUP
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#define RISCV013_INFO
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dmi_op_t
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DMI_OP_NOP
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DMI_OP_READ
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DMI_OP_WRITE
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dmi_status_t
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DMI_STATUS_SUCCESS
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DMI_STATUS_FAILED
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DMI_STATUS_BUSY
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slot
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SLOT0
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SLOT1
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SLOT_LAST
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#define CMDERR_NONE
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#define CMDERR_BUSY
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#define CMDERR_NOT_SUPPORTED
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#define CMDERR_EXCEPTION
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#define CMDERR_HALT_RESUME
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#define CMDERR_OTHER
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trigger
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address
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length
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mask
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value
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read
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write
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execute
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unique_id
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yes_no_maybe_t
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YNM_MAYBE
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YNM_YES
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YNM_NO
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dm013_info_t
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list
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abs_chain_position
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hart_count
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was_reset
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target_list
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current_hartid
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hasel_supported
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progbuf_cache
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target_list_t
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list
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target
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riscv013_info_t
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index
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abits
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datacount
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progbufsize
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sbcs
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progbuf_writable
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progbuf_address
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dtmcs_idle
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dmi_busy_delay
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bus_master_write_delay
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bus_master_read_delay
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ac_busy_delay
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abstract_read_csr_supported
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abstract_write_csr_supported
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abstract_read_fpr_supported
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abstract_write_fpr_supported
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has_aampostincrement
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cmderr
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datasize
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dataaccess
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dataaddr
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hartsellen
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dm
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dm_list
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get_info(const struct target *)
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get_dm(struct target *)
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list_for_each_entry
(entry, &dm_list, list)
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if
(entry->abs_chain_position == abs_chain_position)
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if
(!dm)
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list_for_each_entry
(target_entry, &dm->target_list, list)
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if
(!target_entry)
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set_hartsel(uint32_t, uint32_t)
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decode_dmi(char *, unsigned int, unsigned int)
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for
(unsigned i = 0; i < ARRAY_SIZE(description); i++)
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if
(description[i].address == address)
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if
(value)
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if
(mask & (mask >> 1))
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else
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dump_field(int, const struct scan_field *)
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if
(in_text[0] || out_text[0])
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select_dmi(struct target *)
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if
(bscan_tunnel_ir_width != 0)
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dtmcontrol_scan(struct target *, uint32_t)
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if
(retval != ERROR_OK)
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increase_dmi_busy_delay(struct target *)
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dmi_scan(struct target *, uint32_t *, uint32_t *, dmi_op_t, uint32_t, uint32_t, bool)
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if
(r->reset_delays_wait >= 0)
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if
(r->reset_delays_wait < 0)
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if
(bscan_tunnel_ir_width != 0)
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else
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if
(retval != ERROR_OK)
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if
(bscan_tunnel_ir_width != 0)
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dmi_op_timeout(struct target *, uint32_t *, bool *, int, uint32_t, uint32_t, int, bool, bool)
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switch
(dmi_op)
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case
DMI_OP_NOP:
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case
DMI_OP_READ:
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case
DMI_OP_WRITE:
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default
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while
(1)
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if
(status == DMI_STATUS_BUSY)
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else if
(status == DMI_STATUS_SUCCESS)
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else
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if
(status != DMI_STATUS_SUCCESS)
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if
(ensure_success)
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while
(1)
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if
(status == DMI_STATUS_BUSY)
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else if
(status == DMI_STATUS_SUCCESS)
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else
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if
(data_in)
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else
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dmi_op(struct target *, uint32_t *, bool *, int, uint32_t, uint32_t, bool, bool)
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if
(result == ERROR_TIMEOUT_REACHED)
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dmi_read(struct target *, uint32_t *, uint32_t)
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dmi_read_exec(struct target *, uint32_t *, uint32_t)
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dmi_write(struct target *, uint32_t, uint32_t)
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dmi_write_exec(struct target *, uint32_t, uint32_t, bool)
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dmstatus_read_timeout(struct target *, uint32_t *, bool, unsigned int)
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if
(dmstatus_version != 2 && dmstatus_version != 3)
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else if
(authenticated && !get_field(*dmstatus, DM_DMSTATUS_AUTHENTICATED))
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dmstatus_read(struct target *, uint32_t *, bool)
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increase_ac_busy_delay(struct target *)
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abstract_register_size(unsigned int)
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switch
(width)
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case
32:
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case
64:
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case
128:
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default
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wait_for_idle(struct target *, uint32_t *)
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while
(1)
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if
(time(NULL) - start > riscv_command_timeout_sec)
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if
(info->cmderr != CMDERR_NONE)
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execute_abstract_command(struct target *, uint32_t)
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if
(debug_level >= LOG_LVL_DEBUG)
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switch
(get_field(command, DM_COMMAND_CMDTYPE))
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case
0:
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default
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if
(info->cmderr != 0 || result != ERROR_OK)
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read_abstract_arg(struct target *, unsigned int, unsigned int)
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switch
(size_bits)
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default
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case
64:
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case
32:
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write_abstract_arg(struct target *, unsigned int, riscv_reg_t, unsigned int)
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switch
(size_bits)
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default
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case
64:
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case
32:
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access_register_command(struct target *, uint32_t, unsigned int, uint32_t)
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switch
(size)
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case
32:
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case
64:
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default
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if
(number <= GDB_REGNO_XPR31)
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else if
(number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31)
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else if
(number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095)
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else if
(number >= GDB_REGNO_COUNT)
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else
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register_read_abstract(struct target *, uint64_t *, uint32_t, unsigned int)
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if
(result != ERROR_OK)
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if
(info->cmderr == CMDERR_NOT_SUPPORTED)
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if
(number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31)
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else if
(number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095)
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register_write_abstract(struct target *, uint32_t, uint64_t, unsigned int)
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if
(result != ERROR_OK)
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if
(info->cmderr == CMDERR_NOT_SUPPORTED)
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if
(number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31)
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else if
(number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095)
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abstract_memory_size(unsigned int)
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switch
(width)
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case
8:
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case
16:
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case
32:
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case
64:
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case
128:
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default
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access_memory_command(struct target *, bool, unsigned int, bool, bool)
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examine_progbuf(struct target *)
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if
(info->progbufsize < 1)
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if
(result != ERROR_OK)
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if
(written == (uint32_t) info->progbuf_address)
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else
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is_fpu_reg(uint32_t)
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is_vector_reg(uint32_t)
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prep_for_register_access(struct target *, uint64_t *, int)
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if
(is_fpu_reg(regno) || is_vector_reg(regno))
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if
(is_fpu_reg(regno) && (*mstatus & MSTATUS_FS) == 0)
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else if
(is_vector_reg(regno) && (*mstatus & MSTATUS_VS) == 0)
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else
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cleanup_after_register_access(struct target *, uint64_t, int)
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memory_space_t
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SPACE_DM_DATA
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SPACE_DMI_PROGBUF
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SPACE_DMI_RAM
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scratch_mem_t
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memory_space
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hart_address
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debug_address
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area
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scratch_reserve(struct target *, scratch_mem_t *, struct riscv_program *, unsigned int)
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if
(info->dataaccess == 1)
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if
((size_bytes + scratch->hart_address - info->dataaddr + 3) / 4 >= info->datasize)
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if
((info->progbuf_writable == YNM_YES) && ((size_bytes + scratch->hart_address - info->progbuf_address + 3) / 4 >= info->progbufsize))
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if
(target_alloc_working_area(target, size_bytes + alignment - 1, &scratch->area) == ERROR_OK)
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scratch_release(struct target *, scratch_mem_t *)
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scratch_read64(struct target *, scratch_mem_t *, uint64_t *)
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switch
(scratch->memory_space)
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case
SPACE_DM_DATA:
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case
SPACE_DMI_PROGBUF:
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case
SPACE_DMI_RAM:
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scratch_write64(struct target *, scratch_mem_t *, uint64_t)
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switch
(scratch->memory_space)
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case
SPACE_DM_DATA:
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case
SPACE_DMI_PROGBUF:
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case
SPACE_DMI_RAM:
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register_size(struct target *, unsigned int)
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has_sufficient_progbuf(struct target *, unsigned int)
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register_write_direct(struct target *, unsigned int, uint64_t)
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if
(number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31 && riscv_supports_extension(target, 'D') && riscv_xlen(target) < 64)
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if
(register_write_direct(target, GDB_REGNO_S0, scratch.hart_address) != ERROR_OK)
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if
(scratch_write64(target, &scratch, value) != ERROR_OK)
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else if
(number == GDB_REGNO_VTYPE)
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else
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if
(number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31)
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else if
(number == GDB_REGNO_VL)
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else if
(number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095)
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else
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if
(exec_out == ERROR_OK && target->reg_cache)
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register_read(struct target *, uint64_t *, uint32_t)
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if
(number == GDB_REGNO_ZERO)
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if
(target->reg_cache)
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register_read_direct(struct target *, uint64_t *, uint32_t)
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if
(result != ERROR_OK && has_sufficient_progbuf(target, 2) && number > GDB_REGNO_XPR31)
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if
(number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31)
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if
(riscv_supports_extension(target, 'D') && riscv_xlen(target) < 64)
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if
(register_write_direct(target, GDB_REGNO_S0, scratch.hart_address) != ERROR_OK)
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else if
(riscv_supports_extension(target, 'D'))
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else
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else if
(number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095)
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else
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if
(use_scratch)
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else
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if
(result == ERROR_OK)
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wait_for_authbusy(struct target *, uint32_t *)
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while
(1)
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if
(time(NULL) - start > riscv_command_timeout_sec)
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deinit_target(struct target *)
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set_haltgroup(struct target *, bool *)
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discover_vlenb(struct target *)
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if
(register_read(target, &vlenb, GDB_REGNO_VLENB) != ERROR_OK)
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examine(struct target *)
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if
(dtmcontrol == 0)
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if
(get_field(dtmcontrol, DTM_DTMCS_VERSION) != 1)
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if
(!dm->was_reset)
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if
(!get_field(dmcontrol, DM_DMCONTROL_DMACTIVE))
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if
(dmstatus_version != 2 && dmstatus_version != 3)
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while
(hartsel & 1)
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if
(!get_field(dmstatus, DM_DMSTATUS_AUTHENTICATED))
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if
(!has_sufficient_progbuf(target, 2))
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if
(info->progbufsize < 4 && riscv_enable_virtual)
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if
(dm->hart_count < 0)
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for
(int i = 0; i < MIN(RISCV_MAX_HARTS, 1 << info->hartsellen); ++i)
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if
(dm->hart_count == 0)
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if
(!halted)
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if
(riscv013_halt_go(target) != ERROR_OK)
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if
(register_read(target, &r->misa, GDB_REGNO_MISA))
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if
(riscv_supports_extension(target, 'V'))
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if
(target->smp)
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riscv013_authdata_read(struct target *, uint32_t *, unsigned int)
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if
(index > 0)
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riscv013_authdata_write(struct target *, uint32_t, unsigned int)
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if
(index > 0)
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if
(!get_field(before, DM_DMSTATUS_AUTHENTICATED) && get_field(after, DM_DMSTATUS_AUTHENTICATED))
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list_for_each_entry
(entry, &dm->target_list, list)
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riscv013_hart_count(struct target *)
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riscv013_data_bits(struct target *)
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for
(unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++)
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if
(method == RISCV_MEM_ACCESS_PROGBUF)
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else if
(method == RISCV_MEM_ACCESS_SYSBUS)
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else if
(method == RISCV_MEM_ACCESS_ABSTRACT)
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riscv013_print_info(struct command_invocation *, struct target *)
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prep_for_vector_access(struct target *, uint64_t *, uint64_t *, unsigned int *)
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switch
(riscv_xlen(target))
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case
32:
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case
64:
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default
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cleanup_after_vector_access(struct target *, uint64_t, uint64_t)
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riscv013_get_register_buf(struct target *, uint8_t *, int)
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for
(unsigned i = 0; i < debug_vl; i++)
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if
(result == ERROR_OK)
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else
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riscv013_set_register_buf(struct target *, int, const uint8_t *)
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for
(unsigned i = 0; i < debug_vl; i++)
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sb_sbaccess(unsigned int)
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switch
(size_bytes)
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case
1:
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case
2:
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case
4:
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case
8:
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case
16:
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sb_write_address(struct target *, target_addr_t, bool)
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batch_run(const struct target *, struct riscv_batch *)
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if
(r->reset_delays_wait >= 0)
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if
(r->reset_delays_wait <= 0)
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sba_supports_access(struct target *, unsigned int)
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switch
(size_bytes)
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case
1:
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case
2:
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case
4:
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case
8:
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case
16:
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default
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sample_memory_bus_v1(struct target *, struct riscv_sample_buf *, const riscv_sample_config_t *, int64_t)
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if
(sbasize > 64)
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if
(get_field(info->sbcs, DM_SBCS_SBVERSION) != 1)
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for
(unsigned int i = 0; i < ARRAY_SIZE(config->bucket); i++)
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while
(timeval_ms() < until_ms)
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for
(unsigned int n = 0; n < repeat; n++)
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for
(unsigned int i = 0; i < ARRAY_SIZE(config->bucket); i++)
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if
(config->bucket[i].enabled)
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if
(!sba_supports_access(target, config->bucket[i].size_bytes))
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if
(!sbcs_valid || sbcs_write != sbcs)
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if
(sbasize > 32 && (!sbaddress1_valid || sbaddress1 != config->bucket[i].address >> 32))
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if
(!sbaddress0_valid || sbaddress0 != (config->bucket[i].address & 0xffffffff))
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if
(buf->used + result_bytes >= buf->size)
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if
(get_field(sbcs_read, DM_SBCS_SBBUSYERROR))
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if
(get_field(sbcs_read, DM_SBCS_SBERROR))
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for
(unsigned int n = 0; n < repeat; n++)
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for
(unsigned int i = 0; i < ARRAY_SIZE(config->bucket); i++)
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if
(config->bucket[i].enabled)
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sample_memory(struct target *, struct riscv_sample_buf *, riscv_sample_config_t *, int64_t)
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init_target(struct command_context *, struct target *)
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if
(!generic_info->version_specific)
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assert_reset(struct target *)
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if
(target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
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else if
(target->rtos)
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else
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deassert_reset(struct target *)
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for
(int i = 0; i < riscv_count_harts(target); ++i)
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if
(target->rtos)
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else
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while
(1)
![]()
![]()
if
(time(NULL) - start > riscv_reset_timeout_sec)
![]()
![]()
if
(get_field(dmstatus, DM_DMSTATUS_ALLHAVERESET))
![]()
![]()
execute_fence(struct target *)
![]()
![]()
execute_fence
(struct target *target)
![]()
![]()
log_memory_access(target_addr_t, uint64_t, unsigned int, bool)
![]()
![]()
switch
(size_bytes)
![]()
![]()
case
1:
![]()
![]()
case
2:
![]()
![]()
case
4:
![]()
![]()
case
8:
![]()
![]()
default
![]()
![]()
read_memory_bus_word(struct target *, target_addr_t, uint32_t, uint8_t *)
![]()
![]()
for
(int i = (size - 1) / 4; i >= 0; i--)
![]()
![]()
sb_read_address(struct target *)
![]()
![]()
if
(sbasize > 32)
![]()
![]()
read_sbcs_nonbusy(struct target *, uint32_t *)
![]()
![]()
while
(1)
![]()
![]()
if
(time(NULL) - start > riscv_command_timeout_sec)
![]()
![]()
modify_privilege(struct target *, uint64_t *, uint64_t *)
![]()
![]()
if
(riscv_enable_virtual && has_sufficient_progbuf(target, 5))
![]()
![]()
if
(get_field(dcsr, DCSR_PRV) < 3)
![]()
![]()
read_memory_bus_v0(struct target *, target_addr_t, uint32_t, uint32_t, uint8_t *, uint32_t)
![]()
![]()
if
(size != increment)
![]()
![]()
if
(count == 1)
![]()
![]()
for
(uint32_t i = 0; i < count; i++)
![]()
![]()
while
(cur_addr < fin_addr)
![]()
![]()
if
(cur_addr == fin_addr && count != 1)
![]()
![]()
read_memory_bus_v1(struct target *, target_addr_t, uint32_t, uint32_t, uint8_t *, uint32_t)
![]()
![]()
if
(increment != size && increment != 0)
![]()
![]()
while
(next_address < end_address)
![]()
![]()
if
(info->bus_master_read_delay)
![]()
![]()
if
(jtag_execute_queue() != ERROR_OK)
![]()
![]()
for
(uint32_t i = (next_address - address) / size; i < count - 1; i++)
![]()
![]()
for
(int j = (size - 1) / 4; j >= 0; j--)
![]()
![]()
while
(1)
![]()
![]()
if
(attempt++ > 100)
![]()
![]()
if
(next_read != address - 1)
![]()
![]()
if
(count > 1)
![]()
![]()
while
(1)
![]()
![]()
if
(attempt++ > 100)
![]()
![]()
if
(!get_field(sbcs_read, DM_SBCS_SBERROR) && !get_field(sbcs_read, DM_SBCS_SBBUSYERROR))
![]()
![]()
if
(get_field(sbcs_read, DM_SBCS_SBBUSYERROR))
![]()
![]()
if
(error == 0)
![]()
![]()
else
![]()
![]()
log_mem_access_result(struct target *, bool, int, bool)
![]()
![]()
if
(!success)
![]()
![]()
if
(method == RISCV_MEM_ACCESS_PROGBUF)
![]()
![]()
if
(method == RISCV_MEM_ACCESS_SYSBUS)
![]()
![]()
if
(method == RISCV_MEM_ACCESS_ABSTRACT)
![]()
![]()
mem_should_skip_progbuf(struct target *, target_addr_t, uint32_t, bool, char **)
![]()
![]()
if
(!has_sufficient_progbuf(target, 3))
![]()
![]()
if
(target->state != TARGET_HALTED)
![]()
![]()
if
(riscv_xlen(target) < size * 8)
![]()
![]()
if
(size > 8)
![]()
![]()
if
((sizeof(address) * 8 > riscv_xlen(target)) && (address >> riscv_xlen(target)))
![]()
![]()
mem_should_skip_sysbus(struct target *, target_addr_t, uint32_t, uint32_t, bool, char **)
![]()
![]()
if
(!sba_supports_access(target, size))
![]()
![]()
if
((sizeof(address) * 8 > sbasize) && (address >> sbasize))
![]()
![]()
if
(read && increment != size && (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0 || increment != 0))
![]()
![]()
mem_should_skip_abstract(struct target *, target_addr_t, uint32_t, uint32_t, bool, char **)
![]()
![]()
if
(size > 8)
![]()
![]()
if
((sizeof(address) * 8 > riscv_xlen(target)) && (address >> riscv_xlen(target)))
![]()
![]()
if
(read && size != increment)
![]()
![]()
read_memory_abstract(struct target *, target_addr_t, uint32_t, uint32_t, uint8_t *, uint32_t)
![]()
![]()
for
(uint32_t c = 0; c < count; c++)
![]()
![]()
if
(updateaddr)
![]()
![]()
if
(result != ERROR_OK)
![]()
![]()
if
(info->has_aampostincrement == YNM_MAYBE)
![]()
![]()
if
(result == ERROR_OK)
![]()
![]()
if
(new_address == address + size)
![]()
![]()
else
![]()
![]()
else
![]()
![]()
if
(result == ERROR_OK)
![]()
![]()
write_memory_abstract(struct target *, target_addr_t, uint32_t, uint32_t, const uint8_t *)
![]()
![]()
for
(uint32_t c = 0; c < count; c++)
![]()
![]()
if
(result != ERROR_OK)
![]()
![]()
if
(updateaddr)
![]()
![]()
if
(result != ERROR_OK)
![]()
![]()
if
(info->has_aampostincrement == YNM_MAYBE)
![]()
![]()
if
(result == ERROR_OK)
![]()
![]()
if
(new_address == address + size)
![]()
![]()
else
![]()
![]()
else
![]()
![]()
if
(result == ERROR_OK)
![]()
![]()
read_memory_progbuf_inner(struct target *, target_addr_t, uint32_t, uint32_t, uint8_t *, uint32_t)
![]()
![]()
if
(count == 1)
![]()
![]()
while
(index < count)
![]()
![]()
for
(unsigned j = index; j < count; j++)
![]()
![]()
switch
(info->cmderr)
![]()
![]()
case
CMDERR_NONE:
![]()
![]()
case
CMDERR_BUSY:
![]()
![]()
if
(dmi_read(target, &dmi_data0, DM_DATA0) != ERROR_OK)
![]()
![]()
if
(size > 4 && dmi_read(target, &dmi_data1, DM_DATA1) != ERROR_OK)
![]()
![]()
if
(increment == 0)
![]()
![]()
else
![]()
![]()
if
(result != ERROR_OK)
![]()
![]()
default
![]()
![]()
for
(unsigned j = index - 2; j < index + reads; j++)
![]()
![]()
if
(status != DMI_STATUS_SUCCESS)
![]()
![]()
if
(size > 4)
![]()
![]()
if
(status != DMI_STATUS_SUCCESS)
![]()
![]()
if
(count > 1)
![]()
![]()
read_memory_progbuf_one(struct target *, target_addr_t, uint32_t, uint8_t *)
![]()
![]()
switch
(size)
![]()
![]()
case
1:
![]()
![]()
case
2:
![]()
![]()
case
4:
![]()
![]()
case
8:
![]()
![]()
default
![]()
![]()
read_memory_progbuf(struct target *, target_addr_t, uint32_t, uint32_t, uint8_t *, uint32_t)
![]()
![]()
if
(riscv_xlen(target) < size * 8)
![]()
![]()
switch
(size)
![]()
![]()
case
1:
![]()
![]()
case
2:
![]()
![]()
case
4:
![]()
![]()
case
8:
![]()
![]()
default
![]()
![]()
if
(result != ERROR_OK)
![]()
![]()
for
(uint32_t i = 0; i < count; i++, address_i += increment, buffer_i += size)
![]()
![]()
if
(result != ERROR_OK)
![]()
![]()
read_memory(struct target *, target_addr_t, uint32_t, uint32_t, uint8_t *, uint32_t)
![]()
![]()
if
(size != 1 && size != 2 && size != 4 && size != 8 && size != 16)
![]()
![]()
for
(unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++)
![]()
![]()
if
(method == RISCV_MEM_ACCESS_PROGBUF)
![]()
![]()
else if
(method == RISCV_MEM_ACCESS_SYSBUS)
![]()
![]()
else if
(method == RISCV_MEM_ACCESS_ABSTRACT)
![]()
![]()
write_memory_bus_v0(struct target *, target_addr_t, uint32_t, uint32_t, const uint8_t *)
![]()
![]()
if
(count == 1)
![]()
![]()
for
(riscv_addr_t i = 0; i < count; ++i)
![]()
![]()
write_memory_bus_v1(struct target *, target_addr_t, uint32_t, uint32_t, const uint8_t *)
![]()
![]()
while
(next_address < end_address)
![]()
![]()
for
(uint32_t i = (next_address - address) / size; i < count; i++)
![]()
![]()
if
(size > 2)
![]()
![]()
while
(get_field(sbcs, DM_SBCS_SBBUSY))
![]()
![]()
if
(time(NULL) - start > riscv_command_timeout_sec)
![]()
![]()
if
(get_field(sbcs, DM_SBCS_SBBUSYERROR))
![]()
![]()
if
(get_field(sbcs, DM_SBCS_SBBUSYERROR) || dmi_busy_encountered)
![]()
![]()
if
(next_address < address)
![]()
![]()
if
(sberror != 0)
![]()
![]()
if
(sbaddress < address)
![]()
![]()
write_memory_progbuf(struct target *, target_addr_t, uint32_t, uint32_t, const uint8_t *)
![]()
![]()
if
(riscv_xlen(target) < size * 8)
![]()
![]()
switch
(size)
![]()
![]()
case
1:
![]()
![]()
case
2:
![]()
![]()
case
4:
![]()
![]()
case
8:
![]()
![]()
default
![]()
![]()
while
(cur_addr < fin_addr)
![]()
![]()
for
(unsigned i = start; i < count; ++i)
![]()
![]()
if
(setup_needed)
![]()
![]()
if
(result != ERROR_OK)
![]()
![]()
if
(result != ERROR_OK)
![]()
![]()
else
![]()
![]()
if
(info->cmderr == CMDERR_NONE && !dmi_busy_encountered)
![]()
![]()
else if
(info->cmderr == CMDERR_BUSY || dmi_busy_encountered)
![]()
![]()
else
![]()
![]()
write_memory(struct target *, target_addr_t, uint32_t, uint32_t, const uint8_t *)
![]()
![]()
if
(size != 1 && size != 2 && size != 4 && size != 8 && size != 16)
![]()
![]()
for
(unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++)
![]()
![]()
if
(method == RISCV_MEM_ACCESS_PROGBUF)
![]()
![]()
else if
(method == RISCV_MEM_ACCESS_SYSBUS)
![]()
![]()
else if
(method == RISCV_MEM_ACCESS_ABSTRACT)
![]()
![]()
arch_state(struct target *)
![]()
![]()
riscv013_target
![]()
![]()
riscv013_get_register(struct target *, riscv_reg_t *, int)
![]()
![]()
if
(rid == GDB_REGNO_PC)
![]()
![]()
else if
(rid == GDB_REGNO_PRIV)
![]()
![]()
else
![]()
![]()
riscv013_set_register(struct target *, int, uint64_t)
![]()
![]()
if
(rid <= GDB_REGNO_XPR31)
![]()
![]()
else if
(rid == GDB_REGNO_PC)
![]()
![]()
if
(value != actual_value)
![]()
![]()
else if
(rid == GDB_REGNO_PRIV)
![]()
![]()
else
![]()
![]()
riscv013_select_current_hart(struct target *)
![]()
![]()
select_prepped_harts(struct target *, bool *)
![]()
![]()
if
(!dm->hasel_supported)
![]()
![]()
list_for_each_entry
(entry, &dm->target_list, list)
![]()
![]()
if
(r->prepped)
![]()
![]()
if
(total_selected <= 1)
![]()
![]()
for
(unsigned i = 0; i < hawindow_count; i++)
![]()
![]()
riscv013_halt_prep(struct target *)
![]()
![]()
riscv013_halt_go(struct target *)
![]()
![]()
if
(!riscv_is_halted(target))
![]()
![]()
if
(use_hasel)
![]()
![]()
list_for_each_entry
(entry, &dm->target_list, list)
![]()
![]()
riscv013_resume_go(struct target *)
![]()
![]()
riscv013_step_current_hart(struct target *)
![]()
![]()
riscv013_resume_prep(struct target *)
![]()
![]()
riscv013_on_step(struct target *)
![]()
![]()
riscv013_on_halt(struct target *)
![]()
![]()
riscv013_is_halted(struct target *)
![]()
![]()
if
(get_field(dmstatus, DM_DMSTATUS_ANYHAVERESET))
![]()
![]()
riscv013_halt_reason(struct target *)
![]()
![]()
switch
(get_field(dcsr, CSR_DCSR_CAUSE))
![]()
![]()
case
CSR_DCSR_CAUSE_SWBP:
![]()
![]()
case
CSR_DCSR_CAUSE_TRIGGER:
![]()
![]()
case
CSR_DCSR_CAUSE_STEP:
![]()
![]()
case
CSR_DCSR_CAUSE_DEBUGINT:
![]()
![]()
case
CSR_DCSR_CAUSE_HALT:
![]()
![]()
case
CSR_DCSR_CAUSE_GROUP:
![]()
![]()
riscv013_write_debug_buffer(struct target *, unsigned int, riscv_insn_t)
![]()
![]()
if
(dm->progbuf_cache[index] != data)
![]()
![]()
else
![]()
![]()
riscv013_read_debug_buffer(struct target *, unsigned int)
![]()
![]()
riscv013_execute_debug_buffer(struct target *)
![]()
![]()
riscv013_fill_dmi_write_u64(struct target *, char *, int, uint64_t)
![]()
![]()
riscv013_fill_dmi_read_u64(struct target *, char *, int)
![]()
![]()
riscv013_fill_dmi_nop_u64(struct target *, char *)
![]()
![]()
riscv013_dmi_write_u64_bits(struct target *)
![]()
![]()
maybe_execute_fence_i(struct target *)
![]()
![]()
riscv013_on_step_or_resume(struct target *, bool)
![]()
![]()
riscv013_step_or_resume_current_hart(struct target *, bool, bool)
![]()
![]()
if
(!riscv_is_halted(target))
![]()
![]()
for
(size_t i = 0; i < 256; ++i)
![]()
![]()
if
(step)
![]()
![]()
riscv013_clear_abstract_error(struct target *)
![]()
![]()
while
(get_field(abstractcs, DM_ABSTRACTCS_BUSY))
![]()
![]()
if
(time(NULL) - start > riscv_command_timeout_sec)