OpenOCD
Select one of the symbols to view example projects that use it.
 
Outline
#include "config.h"
#include "assert.h"
#include <target/target.h>
#include <target/target_type.h>
#include <target/smp.h>
#include <target/semihosting_common.h>
#include "esp_xtensa_smp.h"
#include "esp_xtensa_semihosting.h"
#include "esp_algorithm.h"
#define ESP_XTENSA_SMP_EXAMINE_OTHER_CORES
target_to_esp_xtensa_smp(struct target *)
esp_xtensa_smp_assert_reset(struct target *)
esp_xtensa_smp_deassert_reset(struct target *)
esp_xtensa_smp_soft_reset_halt(struct target *)
esp_xtensa_smp_on_halt(struct target *)
get_halted_esp_xtensa_smp(struct target *, int32_t)
esp_xtensa_smp_poll(struct target *)
esp_xtensa_smp_update_halt_gdb(struct target *, bool *)
esp_xtensa_smp_smpbreak_disable(struct target *, uint32_t *)
esp_xtensa_smp_smpbreak_restore(struct target *, uint32_t)
esp_xtensa_smp_resume_cores(struct target *, int, int)
esp_xtensa_smp_resume(struct target *, int, target_addr_t, int, int)
esp_xtensa_smp_step(struct target *, int, target_addr_t, int)
esp_xtensa_smp_watchpoint_add(struct target *, struct watchpoint *)
esp_xtensa_smp_watchpoint_remove(struct target *, struct watchpoint *)
esp_xtensa_smp_run_func_image(struct target *, struct esp_algorithm_run_data *, uint32_t, ...)
esp_xtensa_smp_run_onboard_func(struct target *, struct esp_algorithm_run_data *, uint32_t, uint32_t, ...)
esp_xtensa_smp_init_arch_info(struct target *, struct esp_xtensa_smp_common *, struct xtensa_debug_module_config *, const struct esp_xtensa_smp_chip_ops *, const struct esp_semihost_ops *)
esp_xtensa_smp_target_init(struct command_context *, struct target *)
esp_xtensa_smp_cmd_xtdef(struct command_invocation *)
esp_xtensa_smp_cmd_xtopt(struct command_invocation *)
esp_xtensa_smp_cmd_xtmem(struct command_invocation *)
esp_xtensa_smp_cmd_xtmpu(struct command_invocation *)
esp_xtensa_smp_cmd_xtmmu(struct command_invocation *)
esp_xtensa_smp_cmd_xtreg(struct command_invocation *)
esp_xtensa_smp_cmd_xtregfmt(struct command_invocation *)
esp_xtensa_smp_cmd_permissive_mode(struct command_invocation *)
esp_xtensa_smp_cmd_smpbreak(struct command_invocation *)
esp_xtensa_smp_cmd_mask_interrupts(struct command_invocation *)
esp_xtensa_smp_cmd_perfmon_enable(struct command_invocation *)
esp_xtensa_smp_cmd_perfmon_dump(struct command_invocation *)
esp_xtensa_smp_cmd_tracestart(struct command_invocation *)
esp_xtensa_smp_cmd_tracestop(struct command_invocation *)
esp_xtensa_smp_cmd_tracedump(struct command_invocation *)
esp_xtensa_smp_xtensa_command_handlers
esp_xtensa_smp_command_handlers
Files
loading...
SourceVuDevelopment ToolsOpenOCDsrc/target/espressif/esp_xtensa_smp.c
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// SPDX-License-Identifier: GPL-2.0-or-later /*************************************************************************** * ESP Xtensa SMP target API for OpenOCD * * Copyright (C) 2020 Espressif Systems Ltd. Co * ***************************************************************************//* ... */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "assert.h" #include <target/target.h> #include <target/target_type.h> #include <target/smp.h> #include <target/semihosting_common.h> #include "esp_xtensa_smp.h" #include "esp_xtensa_semihosting.h" #include "esp_algorithm.h" 8 includes /* Multiprocessor stuff common: The ESP Xtensa chip can have several cores in it, which can run in SMP-mode if an SMP-capable OS is running. The hardware has a few features which makes SMP debugging much easier. First of all, there's something called a 'break network', consisting of a BreakIn input and a BreakOut output on each CPU. The idea is that as soon as a CPU goes into debug mode for whatever reason, it'll signal that using its DebugOut pin. This signal is connected to the other CPU's DebugIn input, causing this CPU also to go into debugging mode. To resume execution when using only this break network, we will need to manually resume both CPUs. An alternative to this is the XOCDMode output and the RunStall (or DebugStall) input. When these are cross-connected, a CPU that goes into debug mode will halt execution entirely on the other CPU. Execution on the other CPU can be resumed by either the first CPU going out of debug mode, or the second CPU going into debug mode: the stall is temporarily lifted as long as the stalled CPU is in debug mode. A third, separate, signal is CrossTrigger. This is connected in the same way as the breakIn/breakOut network, but is for the TRAX (trace memory) feature; it does not affect OCD in any way. *//* ... */ /* Multiprocessor stuff: The ESP Xtensa chip has several Xtensa cores inside, but represent themself to the OCD as one chip that works in multithreading mode under FreeRTOS OS. The core that initiate the stop condition will be defined as an active cpu. When one core stops, then other core will be stopped automatically by smpbreak. The core that initiates stop condition will be defined as an active core, and registers of this core will be transferred. *//* ... */ #define ESP_XTENSA_SMP_EXAMINE_OTHER_CORES 5 static int esp_xtensa_smp_update_halt_gdb(struct target *target, bool *need_resume); static inline struct esp_xtensa_smp_common *target_to_esp_xtensa_smp(struct target *target) { return container_of(target->arch_info, struct esp_xtensa_smp_common, esp_xtensa); }{ ... } int esp_xtensa_smp_assert_reset(struct target *target) { return ERROR_OK; }{ ... } int esp_xtensa_smp_deassert_reset(struct target *target) { LOG_TARGET_DEBUG(target, "begin"); int ret = xtensa_deassert_reset(target); if (ret != ERROR_OK) return ret; /* in SMP mode when chip was running single-core app the other core can be left un-examined, because examination is done before SOC reset. But after SOC reset it is functional and should be handled. So try to examine un-examined core just after SOC reset *//* ... */ if (target->smp && !target_was_examined(target)) ret = xtensa_examine(target); return ret; }{ ... } int esp_xtensa_smp_soft_reset_halt(struct target *target) { int res; struct target_list *head; struct esp_xtensa_smp_common *esp_xtensa_smp = target_to_esp_xtensa_smp(target); LOG_TARGET_DEBUG(target, "begin"); /* in SMP mode we need to ensure that at first we reset SOC on PRO-CPU and then call xtensa_assert_reset() for all cores *//* ... */ if (target->smp) { head = list_first_entry(target->smp_targets, struct target_list, lh); if (head->target != target) return ERROR_OK; }if (target->smp) { ... } /* Reset the SoC first */ if (esp_xtensa_smp->chip_ops->reset) { res = esp_xtensa_smp->chip_ops->reset(target); if (res != ERROR_OK) return res; }if (esp_xtensa_smp->chip_ops->reset) { ... } if (!target->smp) return xtensa_assert_reset(target); foreach_smp_target(head, target->smp_targets) { res = xtensa_assert_reset(head->target); if (res != ERROR_OK) return res; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }{ ... } int esp_xtensa_smp_on_halt(struct target *target) { struct target_list *head; if (!target->smp) return esp_xtensa_on_halt(target); foreach_smp_target(head, target->smp_targets) { int res = esp_xtensa_on_halt(head->target); if (res != ERROR_OK) return res; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }{ ... } static struct target *get_halted_esp_xtensa_smp(struct target *target, int32_t coreid) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED)) return curr; }foreach_smp_target (head, target->smp_targets) { ... } return target; }{ ... } int esp_xtensa_smp_poll(struct target *target) { enum target_state old_state = target->state; struct esp_xtensa_smp_common *esp_xtensa_smp = target_to_esp_xtensa_smp(target); struct esp_xtensa_common *esp_xtensa = target_to_esp_xtensa(target); uint32_t old_dbg_stubs_base = esp_xtensa->esp.dbg_stubs.base; struct target_list *head; struct target *curr; bool other_core_resume_req = false; if (target->state == TARGET_HALTED && target->smp && target->gdb_service && !target->gdb_service->target) { target->gdb_service->target = get_halted_esp_xtensa_smp(target, target->gdb_service->core[1]); LOG_INFO("Switch GDB target to '%s'", target_name(target->gdb_service->target)); if (esp_xtensa_smp->chip_ops->on_halt) esp_xtensa_smp->chip_ops->on_halt(target); target_call_event_callbacks(target, TARGET_EVENT_HALTED); return ERROR_OK; }if (target->state == TARGET_HALTED && target->smp && target->gdb_service && !target->gdb_service->target) { ... } int ret = esp_xtensa_poll(target); if (ret != ERROR_OK) return ret; if (esp_xtensa->esp.dbg_stubs.base && old_dbg_stubs_base != esp_xtensa->esp.dbg_stubs.base) { /* debug stubs base is set only in PRO-CPU TRAX register, so sync this info */ foreach_smp_target(head, target->smp_targets) { curr = head->target; if (curr == target) continue; target_to_esp_xtensa(curr)->esp.dbg_stubs.base = esp_xtensa->esp.dbg_stubs.base; }foreach_smp_target (head, target->smp_targets) { ... } }if (esp_xtensa->esp.dbg_stubs.base && old_dbg_stubs_base != esp_xtensa->esp.dbg_stubs.base) { ... } if (target->smp) { if (target->state == TARGET_RESET) { esp_xtensa_smp->examine_other_cores = ESP_XTENSA_SMP_EXAMINE_OTHER_CORES; }if (target->state == TARGET_RESET) { ... } else if (esp_xtensa_smp->examine_other_cores > 0 && (target->state == TARGET_RUNNING || target->state == TARGET_HALTED)) { LOG_TARGET_DEBUG(target, "Check for unexamined cores after reset"); bool all_examined = true; foreach_smp_target(head, target->smp_targets) { curr = head->target; if (curr == target) continue; if (!target_was_examined(curr)) { if (target_examine_one(curr) != ERROR_OK) { LOG_DEBUG("Failed to examine!"); all_examined = false; }if (target_examine_one(curr) != ERROR_OK) { ... } }if (!target_was_examined(curr)) { ... } }foreach_smp_target (head, target->smp_targets) { ... } if (all_examined) esp_xtensa_smp->examine_other_cores = 0; else esp_xtensa_smp->examine_other_cores--; }else if (esp_xtensa_smp->examine_other_cores > 0 && (target->state == TARGET_RUNNING || target->state == TARGET_HALTED)) { ... } }if (target->smp) { ... } if (old_state != TARGET_HALTED && target->state == TARGET_HALTED) { if (target->smp) { ret = esp_xtensa_smp_update_halt_gdb(target, &other_core_resume_req); if (ret != ERROR_OK) return ret; }if (target->smp) { ... } /* Call any event callbacks that are applicable */ if (old_state == TARGET_DEBUG_RUNNING) { target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); }if (old_state == TARGET_DEBUG_RUNNING) { ... } else { if (esp_xtensa_semihosting(target, &ret) == SEMIHOSTING_HANDLED) { if (ret == ERROR_OK && esp_xtensa->semihost.need_resume && !esp_xtensa_smp->other_core_does_resume) { esp_xtensa->semihost.need_resume = false; /* Resume xtensa_resume will handle BREAK instruction. */ ret = target_resume(target, 1, 0, 1, 0); if (ret != ERROR_OK) { LOG_ERROR("Failed to resume target"); return ret; }if (ret != ERROR_OK) { ... } }if (ret == ERROR_OK && esp_xtensa->semihost.need_resume && !esp_xtensa_smp->other_core_does_resume) { ... } return ret; }if (esp_xtensa_semihosting(target, &ret) == SEMIHOSTING_HANDLED) { ... } /* check whether any core polled by esp_xtensa_smp_update_halt_gdb() requested resume */ if (target->smp && other_core_resume_req) { /* Resume xtensa_resume will handle BREAK instruction. */ ret = target_resume(target, 1, 0, 1, 0); if (ret != ERROR_OK) { LOG_ERROR("Failed to resume target"); return ret; }if (ret != ERROR_OK) { ... } return ERROR_OK; }if (target->smp && other_core_resume_req) { ... } if (esp_xtensa_smp->chip_ops->on_halt) esp_xtensa_smp->chip_ops->on_halt(target); target_call_event_callbacks(target, TARGET_EVENT_HALTED); }else { ... } }if (old_state != TARGET_HALTED && target->state == TARGET_HALTED) { ... } return ERROR_OK; }{ ... } static int esp_xtensa_smp_update_halt_gdb(struct target *target, bool *need_resume) { struct esp_xtensa_smp_common *esp_xtensa_smp; struct target *gdb_target = NULL; struct target_list *head; struct target *curr; int ret = ERROR_OK; *need_resume = false; if (target->gdb_service && target->gdb_service->target) LOG_DEBUG("GDB target '%s'", target_name(target->gdb_service->target)); if (target->gdb_service && target->gdb_service->core[0] == -1) { target->gdb_service->target = target; target->gdb_service->core[0] = target->coreid; LOG_INFO("Set GDB target to '%s'", target_name(target)); }if (target->gdb_service && target->gdb_service->core[0] == -1) { ... } if (target->gdb_service) gdb_target = target->gdb_service->target; /* due to smpbreak config other cores can also go to HALTED state */ foreach_smp_target(head, target->smp_targets) { curr = head->target; LOG_DEBUG("Check target '%s'", target_name(curr)); /* skip calling context */ if (curr == target) continue; if (!target_was_examined(curr)) { curr->state = TARGET_HALTED; continue; }if (!target_was_examined(curr)) { ... } /* skip targets that were already halted */ if (curr->state == TARGET_HALTED) continue; /* Skip gdb_target; it alerts GDB so has to be polled as last one */ if (curr == gdb_target) continue; LOG_DEBUG("Poll target '%s'", target_name(curr)); esp_xtensa_smp = target_to_esp_xtensa_smp(curr); /* avoid auto-resume after syscall, it will be done later */ esp_xtensa_smp->other_core_does_resume = true; /* avoid recursion in esp_xtensa_smp_poll() */ curr->smp = 0; if (esp_xtensa_smp->chip_ops->poll) ret = esp_xtensa_smp->chip_ops->poll(curr); else ret = esp_xtensa_smp_poll(curr); curr->smp = 1; if (ret != ERROR_OK) return ret; esp_xtensa_smp->other_core_does_resume = false; struct esp_xtensa_common *curr_esp_xtensa = target_to_esp_xtensa(curr); if (curr_esp_xtensa->semihost.need_resume) { curr_esp_xtensa->semihost.need_resume = false; *need_resume = true; }if (curr_esp_xtensa->semihost.need_resume) { ... } }foreach_smp_target (head, target->smp_targets) { ... } /* after all targets were updated, poll the gdb serving target */ if (gdb_target && gdb_target != target) { esp_xtensa_smp = target_to_esp_xtensa_smp(gdb_target); if (esp_xtensa_smp->chip_ops->poll) ret = esp_xtensa_smp->chip_ops->poll(gdb_target); else ret = esp_xtensa_smp_poll(gdb_target); }if (gdb_target && gdb_target != target) { ... } LOG_DEBUG("exit"); return ret; }{ ... } static inline int esp_xtensa_smp_smpbreak_disable(struct target *target, uint32_t *smp_break) { int res = xtensa_smpbreak_get(target, smp_break); if (res != ERROR_OK) return res; return xtensa_smpbreak_set(target, 0); }{ ... } static inline int esp_xtensa_smp_smpbreak_restore(struct target *target, uint32_t smp_break) { return xtensa_smpbreak_set(target, smp_break); }{ ... } static int esp_xtensa_smp_resume_cores(struct target *target, int handle_breakpoints, int debug_execution) { struct target_list *head; struct target *curr; LOG_TARGET_DEBUG(target, "begin"); foreach_smp_target(head, target->smp_targets) { curr = head->target; /* in single-core mode disabled core cannot be examined, but need to be resumed too*/ if ((curr != target) && (curr->state != TARGET_RUNNING) && target_was_examined(curr)) { /* resume current address, not in SMP mode */ curr->smp = 0; int res = esp_xtensa_smp_resume(curr, 1, 0, handle_breakpoints, debug_execution); curr->smp = 1; if (res != ERROR_OK) return res; }if ((curr != target) && (curr->state != TARGET_RUNNING) && target_was_examined(curr)) { ... } }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }{ ... } int esp_xtensa_smp_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution) { int res; uint32_t smp_break; xtensa_smpbreak_get(target, &smp_break); LOG_TARGET_DEBUG(target, "smp_break=0x%" PRIx32, smp_break); /* dummy resume for smp toggle in order to reduce gdb impact */ if ((target->smp) && (target->gdb_service) && (target->gdb_service->core[1] != -1)) { /* simulate a start and halt of target */ target->gdb_service->target = NULL; target->gdb_service->core[0] = target->gdb_service->core[1]; /* fake resume at next poll we play the target core[1], see poll*/ LOG_TARGET_DEBUG(target, "Fake resume"); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); return ERROR_OK; }if ((target->smp) && (target->gdb_service) && (target->gdb_service->core[1] != -1)) { ... } /* xtensa_prepare_resume() can step over breakpoint/watchpoint and generate signals on BreakInOut circuit for * other cores. So disconnect this core from BreakInOut circuit and do xtensa_prepare_resume(). *//* ... */ res = esp_xtensa_smp_smpbreak_disable(target, &smp_break); if (res != ERROR_OK) return res; res = xtensa_prepare_resume(target, current, address, handle_breakpoints, debug_execution); /* restore configured BreakInOut signals config */ int ret = esp_xtensa_smp_smpbreak_restore(target, smp_break); if (ret != ERROR_OK) return ret; if (res != ERROR_OK) { LOG_TARGET_ERROR(target, "Failed to prepare for resume!"); return res; }if (res != ERROR_OK) { ... } if (target->smp) { if (target->gdb_service) target->gdb_service->core[0] = -1; res = esp_xtensa_smp_resume_cores(target, handle_breakpoints, debug_execution); if (res != ERROR_OK) return res; }if (target->smp) { ... } res = xtensa_do_resume(target); if (res != ERROR_OK) { LOG_TARGET_ERROR(target, "Failed to resume!"); return res; }if (res != ERROR_OK) { ... } target->debug_reason = DBG_REASON_NOTHALTED; if (!debug_execution) target->state = TARGET_RUNNING; else target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); return ERROR_OK; }{ ... } int esp_xtensa_smp_step(struct target *target, int current, target_addr_t address, int handle_breakpoints) { int res; uint32_t smp_break = 0; struct esp_xtensa_smp_common *esp_xtensa_smp = target_to_esp_xtensa_smp(target); if (target->smp) { res = esp_xtensa_smp_smpbreak_disable(target, &smp_break); if (res != ERROR_OK) return res; }if (target->smp) { ... } res = xtensa_step(target, current, address, handle_breakpoints); if (res == ERROR_OK) { if (esp_xtensa_smp->chip_ops->on_halt) esp_xtensa_smp->chip_ops->on_halt(target); target_call_event_callbacks(target, TARGET_EVENT_HALTED); }if (res == ERROR_OK) { ... } if (target->smp) { int ret = esp_xtensa_smp_smpbreak_restore(target, smp_break); if (ret != ERROR_OK) return ret; }if (target->smp) { ... } return res; }{ ... } int esp_xtensa_smp_watchpoint_add(struct target *target, struct watchpoint *watchpoint) { int res = xtensa_watchpoint_add(target, watchpoint); if (res != ERROR_OK) return res; if (!target->smp) return ERROR_OK; struct target_list *head; foreach_smp_target(head, target->smp_targets) { struct target *curr = head->target; if (curr == target || !target_was_examined(curr)) continue; /* Need to use high level API here because every target for core contains list of watchpoints. * GDB works with active core only, so we need to duplicate every watchpoint on other cores, * otherwise watchpoint_free() on active core can fail if WP has been initially added on another core. *//* ... */ curr->smp = 0; res = watchpoint_add(curr, watchpoint->address, watchpoint->length, watchpoint->rw, watchpoint->value, watchpoint->mask); curr->smp = 1; if (res != ERROR_OK) return res; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }{ ... } int esp_xtensa_smp_watchpoint_remove(struct target *target, struct watchpoint *watchpoint) { int res = xtensa_watchpoint_remove(target, watchpoint); if (res != ERROR_OK) return res; if (!target->smp) return ERROR_OK; struct target_list *head; foreach_smp_target(head, target->smp_targets) { struct target *curr = head->target; if (curr == target) continue; /* see big comment in esp_xtensa_smp_watchpoint_add() */ curr->smp = 0; watchpoint_remove(curr, watchpoint->address); curr->smp = 1; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }{ ... } int esp_xtensa_smp_run_func_image(struct target *target, struct esp_algorithm_run_data *run, uint32_t num_args, ...) { struct target *run_target = target; struct target_list *head; va_list ap; uint32_t smp_break = 0; int res; if (target->smp) { /* find first HALTED and examined core */ foreach_smp_target(head, target->smp_targets) { run_target = head->target; if (target_was_examined(run_target) && run_target->state == TARGET_HALTED) break; }foreach_smp_target (head, target->smp_targets) { ... } if (!head) { LOG_ERROR("Failed to find HALTED core!"); return ERROR_FAIL; }if (!head) { ... } res = esp_xtensa_smp_smpbreak_disable(run_target, &smp_break); if (res != ERROR_OK) return res; }if (target->smp) { ... } va_start(ap, num_args); int algo_res = esp_algorithm_run_func_image_va(run_target, run, num_args, ap); va_end(ap); if (target->smp) { res = esp_xtensa_smp_smpbreak_restore(run_target, smp_break); if (res != ERROR_OK) return res; }if (target->smp) { ... } return algo_res; }{ ... } int esp_xtensa_smp_run_onboard_func(struct target *target, struct esp_algorithm_run_data *run, uint32_t func_addr, uint32_t num_args, ...) { struct target *run_target = target; struct target_list *head; va_list ap; uint32_t smp_break = 0; int res; if (target->smp) { /* find first HALTED and examined core */ foreach_smp_target(head, target->smp_targets) { run_target = head->target; if (target_was_examined(run_target) && run_target->state == TARGET_HALTED) break; }foreach_smp_target (head, target->smp_targets) { ... } if (!head) { LOG_ERROR("Failed to find HALTED core!"); return ERROR_FAIL; }if (!head) { ... } res = esp_xtensa_smp_smpbreak_disable(run_target, &smp_break); if (res != ERROR_OK) return res; }if (target->smp) { ... } va_start(ap, num_args); int algo_res = esp_algorithm_run_onboard_func_va(run_target, run, func_addr, num_args, ap); va_end(ap); if (target->smp) { res = esp_xtensa_smp_smpbreak_restore(run_target, smp_break); if (res != ERROR_OK) return res; }if (target->smp) { ... } return algo_res; }{ ... } int esp_xtensa_smp_init_arch_info(struct target *target, struct esp_xtensa_smp_common *esp_xtensa_smp, struct xtensa_debug_module_config *dm_cfg, const struct esp_xtensa_smp_chip_ops *chip_ops, const struct esp_semihost_ops *semihost_ops) { int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, dm_cfg, semihost_ops); if (ret != ERROR_OK) return ret; esp_xtensa_smp->chip_ops = chip_ops; esp_xtensa_smp->examine_other_cores = ESP_XTENSA_SMP_EXAMINE_OTHER_CORES; return ERROR_OK; }{ ... } int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *target) { int ret = esp_xtensa_target_init(cmd_ctx, target); if (ret != ERROR_OK) return ret; if (target->smp) { struct target_list *head; foreach_smp_target(head, target->smp_targets) { struct target *curr = head->target; ret = esp_xtensa_semihosting_init(curr); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } }if (target->smp) { ... } else { ret = esp_xtensa_semihosting_init(target); if (ret != ERROR_OK) return ret; }else { ... } return ERROR_OK; }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_xtdef) { struct target *target = get_current_target(CMD_CTX); if (target->smp && CMD_ARGC > 0) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do, target_to_xtensa(curr)); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp && CMD_ARGC > 0) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do, target_to_xtensa(target)); }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_xtopt) { struct target *target = get_current_target(CMD_CTX); if (target->smp && CMD_ARGC > 0) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do, target_to_xtensa(curr)); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp && CMD_ARGC > 0) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do, target_to_xtensa(target)); }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmem) { struct target *target = get_current_target(CMD_CTX); if (target->smp && CMD_ARGC > 0) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do, target_to_xtensa(curr)); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp && CMD_ARGC > 0) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do, target_to_xtensa(target)); }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmpu) { struct target *target = get_current_target(CMD_CTX); if (target->smp && CMD_ARGC > 0) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do, target_to_xtensa(curr)); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp && CMD_ARGC > 0) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do, target_to_xtensa(target)); }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmmu) { struct target *target = get_current_target(CMD_CTX); if (target->smp && CMD_ARGC > 0) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do, target_to_xtensa(curr)); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp && CMD_ARGC > 0) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do, target_to_xtensa(target)); }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_xtreg) { struct target *target = get_current_target(CMD_CTX); if (target->smp && CMD_ARGC > 0) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do, target_to_xtensa(curr)); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp && CMD_ARGC > 0) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do, target_to_xtensa(target)); }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_xtregfmt) { struct target *target = get_current_target(CMD_CTX); if (target->smp && CMD_ARGC > 0) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do, target_to_xtensa(curr)); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp && CMD_ARGC > 0) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do, target_to_xtensa(target)); }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_permissive_mode) { struct target *target = get_current_target(CMD_CTX); if (target->smp && CMD_ARGC > 0) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; int ret = CALL_COMMAND_HANDLER(xtensa_cmd_permissive_mode_do, target_to_xtensa(curr)); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp && CMD_ARGC > 0) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_permissive_mode_do, target_to_xtensa(target)); }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_smpbreak) { struct target *target = get_current_target(CMD_CTX); if (target->smp && CMD_ARGC > 0) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; int ret = CALL_COMMAND_HANDLER(xtensa_cmd_smpbreak_do, curr); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp && CMD_ARGC > 0) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_smpbreak_do, target); }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_mask_interrupts) { struct target *target = get_current_target(CMD_CTX); if (target->smp && CMD_ARGC > 0) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; int ret = CALL_COMMAND_HANDLER(xtensa_cmd_mask_interrupts_do, target_to_xtensa(curr)); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp && CMD_ARGC > 0) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_mask_interrupts_do, target_to_xtensa(target)); }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_perfmon_enable) { struct target *target = get_current_target(CMD_CTX); if (target->smp && CMD_ARGC > 0) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; int ret = CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_enable_do, target_to_xtensa(curr)); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp && CMD_ARGC > 0) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_enable_do, target_to_xtensa(target)); }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_perfmon_dump) { struct target *target = get_current_target(CMD_CTX); if (target->smp) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; LOG_TARGET_INFO(curr, ":"); int ret = CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_dump_do, target_to_xtensa(curr)); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_dump_do, target_to_xtensa(target)); }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_tracestart) { struct target *target = get_current_target(CMD_CTX); if (target->smp) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; int ret = CALL_COMMAND_HANDLER(xtensa_cmd_tracestart_do, target_to_xtensa(curr)); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_tracestart_do, target_to_xtensa(target)); }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_tracestop) { struct target *target = get_current_target(CMD_CTX); if (target->smp) { struct target_list *head; struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; int ret = CALL_COMMAND_HANDLER(xtensa_cmd_tracestop_do, target_to_xtensa(curr)); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_tracestop_do, target_to_xtensa(target)); }{ ... } COMMAND_HANDLER(esp_xtensa_smp_cmd_tracedump) { struct target *target = get_current_target(CMD_CTX); if (target->smp) { struct target_list *head; struct target *curr; int32_t cores_max_id = 0; /* assume that core IDs are assigned to SMP targets sequentially: 0,1,2... */ foreach_smp_target(head, target->smp_targets) { curr = head->target; if (cores_max_id < curr->coreid) cores_max_id = curr->coreid; }foreach_smp_target (head, target->smp_targets) { ... } if (CMD_ARGC < ((uint32_t)cores_max_id + 1)) { command_print(CMD, "Need %d filenames to dump to as output!", cores_max_id + 1); return ERROR_FAIL; }if (CMD_ARGC < ((uint32_t)cores_max_id + 1)) { ... } foreach_smp_target(head, target->smp_targets) { curr = head->target; int ret = CALL_COMMAND_HANDLER(xtensa_cmd_tracedump_do, target_to_xtensa(curr), CMD_ARGV[curr->coreid]); if (ret != ERROR_OK) return ret; }foreach_smp_target (head, target->smp_targets) { ... } return ERROR_OK; }if (target->smp) { ... } return CALL_COMMAND_HANDLER(xtensa_cmd_tracedump_do, target_to_xtensa(target), CMD_ARGV[0]); }{ ... } const struct command_registration esp_xtensa_smp_xtensa_command_handlers[] = { { .name = "xtdef", .handler = esp_xtensa_smp_cmd_xtdef, .mode = COMMAND_CONFIG, .help = "Configure Xtensa core type", .usage = "<type>", ...}, { .name = "xtopt", .handler = esp_xtensa_smp_cmd_xtopt, .mode = COMMAND_CONFIG, .help = "Configure Xtensa core option", .usage = "<name> <value>", ...}, { .name = "xtmem", .handler = esp_xtensa_smp_cmd_xtmem, .mode = COMMAND_CONFIG, .help = "Configure Xtensa memory/cache option", .usage = "<type> [parameters]", ...}, { .name = "xtmmu", .handler = esp_xtensa_smp_cmd_xtmmu, .mode = COMMAND_CONFIG, .help = "Configure Xtensa MMU option", .usage = "<NIREFILLENTRIES> <NDREFILLENTRIES> <IVARWAY56> <DVARWAY56>", ...}, { .name = "xtmpu", .handler = esp_xtensa_smp_cmd_xtmpu, .mode = COMMAND_CONFIG, .help = "Configure Xtensa MPU option", .usage = "<num FG seg> <min seg size> <lockable> <executeonly>", ...}, { .name = "xtreg", .handler = esp_xtensa_smp_cmd_xtreg, .mode = COMMAND_CONFIG, .help = "Configure Xtensa register", .usage = "<regname> <regnum>", ...}, { .name = "xtregs", .handler = esp_xtensa_smp_cmd_xtreg, .mode = COMMAND_CONFIG, .help = "Configure number of Xtensa registers", .usage = "<numregs>", ...}, { .name = "xtregfmt", .handler = esp_xtensa_smp_cmd_xtregfmt, .mode = COMMAND_CONFIG, .help = "Configure format of Xtensa register map", .usage = "<numgregs>", ...}, { .name = "set_permissive", .handler = esp_xtensa_smp_cmd_permissive_mode, .mode = COMMAND_ANY, .help = "When set to 1, enable Xtensa permissive mode (less client-side checks)", .usage = "[0|1]", ...}, { .name = "maskisr", .handler = esp_xtensa_smp_cmd_mask_interrupts, .mode = COMMAND_ANY, .help = "mask Xtensa interrupts at step", .usage = "['on'|'off']", ...}, { .name = "smpbreak", .handler = esp_xtensa_smp_cmd_smpbreak, .mode = COMMAND_ANY, .help = "Set the way the CPU chains OCD breaks", .usage = "[none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]", ...}, { .name = "perfmon_enable", .handler = esp_xtensa_smp_cmd_perfmon_enable, .mode = COMMAND_EXEC, .help = "Enable and start performance counter", .usage = "<counter_id> <select> [mask] [kernelcnt] [tracelevel]", ...}, { .name = "perfmon_dump", .handler = esp_xtensa_smp_cmd_perfmon_dump, .mode = COMMAND_EXEC, .help = "Dump performance counter value. If no argument specified, dumps all counters.", .usage = "[counter_id]", ...}, { .name = "tracestart", .handler = esp_xtensa_smp_cmd_tracestart, .mode = COMMAND_EXEC, .help = "Tracing: Set up and start a trace. Optionally set stop trigger address and amount of data captured after.", .usage = "[pc <pcval>/[maskbitcount]] [after <n> [ins|words]]", ...}, { .name = "tracestop", .handler = esp_xtensa_smp_cmd_tracestop, .mode = COMMAND_EXEC, .help = "Tracing: Stop current trace as started by the tracestart command", .usage = "", ...}, { .name = "tracedump", .handler = esp_xtensa_smp_cmd_tracedump, .mode = COMMAND_EXEC, .help = "Tracing: Dump trace memory to a files. One file per core.", .usage = "<outfile1> <outfile2>", ...}, COMMAND_REGISTRATION_DONE ...}; const struct command_registration esp_xtensa_smp_command_handlers[] = { { .name = "xtensa", .usage = "", .chain = esp_xtensa_smp_xtensa_command_handlers, ...}, COMMAND_REGISTRATION_DONE ...};
Details
Show:
from
Types: Columns:
Click anywhere in the source to view detailed information here...