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mcpwm_int_st_reg_t union
Type of int_st register Masked interrupt status
Syntax
typedef union
{
struct {
uint32_t timer0_stop_int_st: 1;
uint32_t timer1_stop_int_st: 1;
uint32_t timer2_stop_int_st: 1;
uint32_t timer0_tez_int_st: 1;
uint32_t timer1_tez_int_st: 1;
uint32_t timer2_tez_int_st: 1;
uint32_t timer0_tep_int_st: 1;
uint32_t timer1_tep_int_st: 1;
uint32_t timer2_tep_int_st: 1;
uint32_t fault0_int_st: 1;
uint32_t fault1_int_st: 1;
uint32_t fault2_int_st: 1;
uint32_t fault0_clr_int_st: 1;
uint32_t fault1_clr_int_st: 1;
uint32_t fault2_clr_int_st: 1;
uint32_t op0_tea_int_st: 1;
uint32_t op1_tea_int_st: 1;
uint32_t op2_tea_int_st: 1;
uint32_t op0_teb_int_st: 1;
uint32_t op1_teb_int_st: 1;
uint32_t op2_teb_int_st: 1;
uint32_t fh0_cbc_int_st: 1;
uint32_t fh1_cbc_int_st: 1;
uint32_t fh2_cbc_int_st: 1;
uint32_t fh0_ost_int_st: 1;
uint32_t fh1_ost_int_st: 1;
uint32_t fh2_ost_int_st: 1;
uint32_t cap0_int_st: 1;
uint32_t cap1_int_st: 1;
uint32_t cap2_int_st: 1;
uint32_t reserved_30: 2;
};
uint32_t val;
} mcpwm_int_st_reg_t;
Fields
Field
Declared as
uint32_t