FMC_SDRAM_TimingTypeDef struct

Defines the delay between a Load Mode Register command and an active or Refresh command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16.

Defines the delay from releasing the self refresh command to issuing the Activate command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16.

Defines the minimum Self Refresh period in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16.

Defines the delay between the Refresh command and the Activate command and the delay between two consecutive Refresh commands in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16.

Defines the Write recovery Time in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16.

Defines the delay between a Precharge Command and an other command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16.

Defines the delay between the Activate Command and a Read/Write command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16.