FMC_SDRAM_TimingTypeDef::LoadToActiveDelay field

Defines the delay between a Load Mode Register command and an active or Refresh command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16

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Declaration

from stm32f4xx_ll_fmc.h:470

uint32_t LoadToActiveDelay;

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FMC_SDRAM_TimingTypeDef::LoadToActiveDelay is referenced by 10 libraries and example projects:

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FMC_SDRAM_TimingTypeDef::LoadToActiveDelay field

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