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SourceVuSTM32 Libraries and SamplesHALFMC_SDRAM_TimingTypeDef::LoadToActiveDelay

FMC_SDRAM_TimingTypeDef::LoadToActiveDelay field

Defines the delay between a Load Mode Register command and an active or Refresh command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16

Syntax

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Summary

Declaration

from stm32f4xx_ll_fmc.h:470

uint32_t LoadToActiveDelay;

Examples

FMC_SDRAM_TimingTypeDef::LoadToActiveDelay is referenced by 10 libraries and example projects:

Drivers

Boards

Examples

STM32446E_EVAL

Examples

FMC

FMC_SDRAM

STM32469I-Discovery

Examples

FMC

FMC_SDRAM

STM32469I_EVAL

Examples

FMC

FMC_SDRAM

STM324x9I_EVAL

Examples

FMC

FMC_SDRAM

STM32F429I-Discovery

Examples

FMC

FMC_SDRAM

References

from 0/10 examples

Code

Location

Referrer

uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and

stm32f4xx_ll_fmc.h:470

assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));

stm32f4xx_ll_fmc.c:1248

FMC_SDRAM_Timing_Init()

(((Timing->LoadToActiveDelay) - 1U) |

stm32f4xx_ll_fmc.c:1262

FMC_SDRAM_Timing_Init()

(((Timing->LoadToActiveDelay) - 1U) |

stm32f4xx_ll_fmc.c:1280

FMC_SDRAM_Timing_Init()

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Data Use

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FMC_SDRAM_TimingTypeDef::LoadToActiveDelay is read by 1 function:

FMC_SDRAM_TimingTypeDef::LoadToActiveDelay

FMC_SDRAM_Timing_Init()

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