BIT - syntax, references, description

#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature

rtc.h:519

#define RTC_SLEEP_XTAL_AS_RTC_FAST BIT(19)

rtc.h:520

#define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup

rtc.h:570

#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup

rtc.h:571

#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup (light sleep only)

rtc.h:572

#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup

rtc.h:573

#define RTC_SDIO_TRIG_EN BIT(4) //!< SDIO wakeup (light sleep only)

rtc.h:574

#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only)

rtc.h:576

#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only)

rtc.h:577

#define RTC_TOUCH_TRIG_EN BIT(8) //!< Touch wakeup

rtc.h:578

#define RTC_ULP_TRIG_EN BIT(9) //!< ULP wakeup

rtc.h:579

#define RTC_CNTL_SW_SYS_RST (BIT(31))

rtc_cntl_reg.h:13

#define RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22))

rtc_cntl_reg.h:67

#define RTC_CNTL_BIAS_CORE_FOLW_8M (BIT(20))

rtc_cntl_reg.h:79

#define RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19))

rtc_cntl_reg.h:85

#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18))

rtc_cntl_reg.h:91

#define RTC_CNTL_BIAS_I2C_FOLW_8M (BIT(17))

rtc_cntl_reg.h:97

#define RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16))

rtc_cntl_reg.h:103

#define RTC_CNTL_BIAS_SLEEP_FOLW_8M (BIT(14))

rtc_cntl_reg.h:115

#define RTC_CNTL_XTL_FORCE_PU (BIT(13))

rtc_cntl_reg.h:121

#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11))

rtc_cntl_reg.h:133

#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10))

rtc_cntl_reg.h:139

#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9))

rtc_cntl_reg.h:145

#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8))

rtc_cntl_reg.h:151

#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7))

rtc_cntl_reg.h:157

#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6))

rtc_cntl_reg.h:163

#define RTC_CNTL_SW_PROCPU_RST (BIT(5))

rtc_cntl_reg.h:169

#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5))

rtc_cntl_reg.h:170

#define RTC_CNTL_SW_APPCPU_RST (BIT(4))

rtc_cntl_reg.h:175

#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4))

rtc_cntl_reg.h:176

#define RTC_CNTL_TIME_UPDATE (BIT(31))

rtc_cntl_reg.h:219

#define RTC_CNTL_TIME_VALID (BIT(30))

rtc_cntl_reg.h:225

#define RTC_CNTL_SLEEP_EN (BIT(31))

rtc_cntl_reg.h:249

#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(24))

rtc_cntl_reg.h:273

#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN (BIT(21))

rtc_cntl_reg.h:291

#define RTC_CNTL_PLL_I2C_PU (BIT(31))

rtc_cntl_reg.h:432

#define RTC_CNTL_CKGEN_I2C_PU (BIT(30))

rtc_cntl_reg.h:438

#define RTC_CNTL_RFRX_PBUS_PU (BIT(28))

rtc_cntl_reg.h:444

#define RTC_CNTL_TXRF_I2C_PU (BIT(27))

rtc_cntl_reg.h:450

#define RTC_CNTL_PVTMON_PU (BIT(26))

rtc_cntl_reg.h:456

#define RTC_CNTL_PLLA_FORCE_PU (BIT(24))

rtc_cntl_reg.h:468

#define RTC_CNTL_PLLA_FORCE_PD (BIT(23))

rtc_cntl_reg.h:474

#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(7))

rtc_cntl_reg.h:535

#define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5))

rtc_cntl_reg.h:547

#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1))

rtc_cntl_reg.h:626

#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0))

rtc_cntl_reg.h:632

#define RTC_CNTL_TOUCH_INT_ST_M (BIT(6))

rtc_cntl_reg.h:653

#define RTC_CNTL_SAR_INT_ST_M (BIT(5))

rtc_cntl_reg.h:659

#define RTC_CNTL_SAR_INT_CLR (BIT(5))

rtc_cntl_reg.h:714

#define RTC_CNTL_TIME_VALID_INT_CLR (BIT(4))

rtc_cntl_reg.h:720

#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1))

rtc_cntl_reg.h:738

#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0))

rtc_cntl_reg.h:744

#define RTC_CNTL_CK8M_FORCE_PU (BIT(26))

rtc_cntl_reg.h:884

#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10))

rtc_cntl_reg.h:928

#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9))

rtc_cntl_reg.h:934

#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8))

rtc_cntl_reg.h:940

#define RTC_CNTL_ENB_CK8M_DIV (BIT(7))

rtc_cntl_reg.h:945

#define RTC_CNTL_ENB_CK8M (BIT(6))

rtc_cntl_reg.h:951

#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31))

rtc_cntl_reg.h:966

#define RTC_CNTL_SDIO_TIEH_M (BIT(23))

rtc_cntl_reg.h:996

#define RTC_CNTL_SDIO_FORCE (BIT(22))

rtc_cntl_reg.h:1001

#define RTC_CNTL_SDIO_PD_EN (BIT(21))

rtc_cntl_reg.h:1007

#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30))

rtc_cntl_reg.h:1021

#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29))

rtc_cntl_reg.h:1027

#define RTC_CNTL_FORCE_PU (BIT(31))

rtc_cntl_reg.h:1060

#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29))

rtc_cntl_reg.h:1073

#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28))

rtc_cntl_reg.h:1079

#define RTC_CNTL_PD_EN (BIT(20))

rtc_cntl_reg.h:1137

#define RTC_CNTL_PWC_FORCE_PU (BIT(19))

rtc_cntl_reg.h:1143

#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17))

rtc_cntl_reg.h:1155

#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16))

rtc_cntl_reg.h:1161

#define RTC_CNTL_FASTMEM_PD_EN (BIT(14))

rtc_cntl_reg.h:1173

#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13))

rtc_cntl_reg.h:1179

#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9))

rtc_cntl_reg.h:1203

#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6))

rtc_cntl_reg.h:1222

#define RTC_CNTL_FORCE_NOISO (BIT(5))

rtc_cntl_reg.h:1228

#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2))

rtc_cntl_reg.h:1246

#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0))

rtc_cntl_reg.h:1258

#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31))

rtc_cntl_reg.h:1284

#define RTC_CNTL_WIFI_PD_EN (BIT(30))

rtc_cntl_reg.h:1290

#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29))

rtc_cntl_reg.h:1296

#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28))

rtc_cntl_reg.h:1302

#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27))

rtc_cntl_reg.h:1308

#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26))

rtc_cntl_reg.h:1314

#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25))

rtc_cntl_reg.h:1320

#define RTC_CNTL_ROM0_PD_EN (BIT(24))

rtc_cntl_reg.h:1326

#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20))

rtc_cntl_reg.h:1332

#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19))

rtc_cntl_reg.h:1338

#define RTC_CNTL_WIFI_FORCE_PU (BIT(18))

rtc_cntl_reg.h:1344

#define RTC_CNTL_WIFI_FORCE_PD (BIT(17))

rtc_cntl_reg.h:1350

#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16))

rtc_cntl_reg.h:1356

#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14))

rtc_cntl_reg.h:1368

#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12))

rtc_cntl_reg.h:1380

#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10))

rtc_cntl_reg.h:1392

#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8))

rtc_cntl_reg.h:1404

#define RTC_CNTL_ROM0_FORCE_PU (BIT(6))

rtc_cntl_reg.h:1416

#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4))

rtc_cntl_reg.h:1428

#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31))

rtc_cntl_reg.h:1456

#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29))

rtc_cntl_reg.h:1468

#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28))

rtc_cntl_reg.h:1474

#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27))

rtc_cntl_reg.h:1480

#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25))

rtc_cntl_reg.h:1492

#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23))

rtc_cntl_reg.h:1504

#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21))

rtc_cntl_reg.h:1516

#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19))

rtc_cntl_reg.h:1528

#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17))

rtc_cntl_reg.h:1540

#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14))

rtc_cntl_reg.h:1558

#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13))

rtc_cntl_reg.h:1564

#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12))

rtc_cntl_reg.h:1570

#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11))

rtc_cntl_reg.h:1577

#define RTC_CNTL_WDT_EN (BIT(31))

rtc_cntl_reg.h:1618

#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(10))

rtc_cntl_reg.h:1676

#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(7))

rtc_cntl_reg.h:1694

#define RTC_CNTL_WDT_FEED (BIT(31))

rtc_cntl_reg.h:1741

#define RTC_CNTL_ENT_RTC (BIT(29))

rtc_cntl_reg.h:1763

#define RTC_CNTL_X32N_HOLD_FORCE_M (BIT(17))

rtc_cntl_reg.h:1845

#define RTC_CNTL_X32P_HOLD_FORCE_M (BIT(16))

rtc_cntl_reg.h:1851

#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M (BIT(15))

rtc_cntl_reg.h:1857

#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M (BIT(14))

rtc_cntl_reg.h:1863

#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M (BIT(13))

rtc_cntl_reg.h:1869

#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M (BIT(12))

rtc_cntl_reg.h:1875

#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M (BIT(11))

rtc_cntl_reg.h:1881

#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M (BIT(10))

rtc_cntl_reg.h:1887

#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M (BIT(9))

rtc_cntl_reg.h:1893

#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M (BIT(8))

rtc_cntl_reg.h:1899

#define RTC_CNTL_SENSE4_HOLD_FORCE_M (BIT(7))

rtc_cntl_reg.h:1905

#define RTC_CNTL_SENSE3_HOLD_FORCE_M (BIT(6))

rtc_cntl_reg.h:1911

#define RTC_CNTL_SENSE2_HOLD_FORCE_M (BIT(5))

rtc_cntl_reg.h:1917

#define RTC_CNTL_SENSE1_HOLD_FORCE_M (BIT(4))

rtc_cntl_reg.h:1923

#define RTC_CNTL_PDAC2_HOLD_FORCE_M (BIT(3))

rtc_cntl_reg.h:1929

#define RTC_CNTL_PDAC1_HOLD_FORCE_M (BIT(2))

rtc_cntl_reg.h:1935

#define RTC_CNTL_ADC2_HOLD_FORCE_M (BIT(1))

rtc_cntl_reg.h:1941

#define RTC_CNTL_ADC1_HOLD_FORCE_M (BIT(0))

rtc_cntl_reg.h:1947

#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18))

rtc_cntl_reg.h:1954

#define RTC_MEM_CRC_START (BIT(8))

rtc_cntl_reg.h:2030

#define RTC_INTR_FLAG_IRAM (BIT(0)) /*< Some rtc interrupts can be called with cache disabled */

rtc_ctrl.h:17

result.tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V : RTC_VDDSDIO_TIEH_3_3V;

rtc_init.c:152

#define RTC_IO_SENSE1_HOLD_M (BIT(31))

rtc_io_reg.h:536

#define RTC_IO_SENSE2_HOLD_M (BIT(30))

rtc_io_reg.h:542

#define RTC_IO_SENSE3_HOLD_M (BIT(29))

rtc_io_reg.h:548

#define RTC_IO_SENSE4_HOLD_M (BIT(28))

rtc_io_reg.h:554

#define RTC_IO_SENSE1_MUX_SEL_M (BIT(27))

rtc_io_reg.h:560

#define RTC_IO_SENSE2_MUX_SEL_M (BIT(26))

rtc_io_reg.h:566

#define RTC_IO_SENSE3_MUX_SEL_M (BIT(25))

rtc_io_reg.h:572

#define RTC_IO_SENSE4_MUX_SEL_M (BIT(24))

rtc_io_reg.h:578

#define RTC_IO_SENSE1_SLP_SEL_M (BIT(21))

rtc_io_reg.h:590

#define RTC_IO_SENSE1_SLP_IE_M (BIT(20))

rtc_io_reg.h:596

#define RTC_IO_SENSE1_FUN_IE_M (BIT(19))

rtc_io_reg.h:602

#define RTC_IO_SENSE2_SLP_SEL_M (BIT(16))

rtc_io_reg.h:614

#define RTC_IO_SENSE2_SLP_IE_M (BIT(15))

rtc_io_reg.h:620

#define RTC_IO_SENSE2_FUN_IE_M (BIT(14))

rtc_io_reg.h:626

#define RTC_IO_SENSE3_SLP_SEL_M (BIT(11))

rtc_io_reg.h:638

#define RTC_IO_SENSE3_SLP_IE_M (BIT(10))

rtc_io_reg.h:644

#define RTC_IO_SENSE3_FUN_IE_M (BIT(9))

rtc_io_reg.h:650

#define RTC_IO_SENSE4_SLP_SEL_M (BIT(6))

rtc_io_reg.h:662

#define RTC_IO_SENSE4_SLP_IE_M (BIT(5))

rtc_io_reg.h:668

#define RTC_IO_SENSE4_FUN_IE_M (BIT(4))

rtc_io_reg.h:674

#define RTC_IO_ADC1_HOLD_M (BIT(31))

rtc_io_reg.h:682

#define RTC_IO_ADC2_HOLD_M (BIT(30))

rtc_io_reg.h:688

#define RTC_IO_ADC1_MUX_SEL_M (BIT(29))

rtc_io_reg.h:694

#define RTC_IO_ADC2_MUX_SEL_M (BIT(28))

rtc_io_reg.h:700

#define RTC_IO_ADC1_SLP_SEL_M (BIT(25))

rtc_io_reg.h:712

#define RTC_IO_ADC1_SLP_IE_M (BIT(24))

rtc_io_reg.h:718

#define RTC_IO_ADC1_FUN_IE_M (BIT(23))

rtc_io_reg.h:724

#define RTC_IO_ADC2_SLP_SEL_M (BIT(20))

rtc_io_reg.h:736

#define RTC_IO_ADC2_SLP_IE_M (BIT(19))

rtc_io_reg.h:742

#define RTC_IO_ADC2_FUN_IE_M (BIT(18))

rtc_io_reg.h:748

#define RTC_IO_PDAC1_HOLD_M (BIT(29))

rtc_io_reg.h:762

#define RTC_IO_PDAC1_RDE_M (BIT(28))

rtc_io_reg.h:768

#define RTC_IO_PDAC1_RUE_M (BIT(27))

rtc_io_reg.h:774

#define RTC_IO_PDAC1_MUX_SEL_M (BIT(17))

rtc_io_reg.h:793

#define RTC_IO_PDAC1_SLP_SEL_M (BIT(14))

rtc_io_reg.h:805

#define RTC_IO_PDAC1_SLP_IE_M (BIT(13))

rtc_io_reg.h:811

#define RTC_IO_PDAC1_FUN_IE_M (BIT(11))

rtc_io_reg.h:823

#define RTC_IO_PDAC2_HOLD_M (BIT(29))

rtc_io_reg.h:844

#define RTC_IO_PDAC2_RDE_M (BIT(28))

rtc_io_reg.h:850

#define RTC_IO_PDAC2_RUE_M (BIT(27))

rtc_io_reg.h:856

#define RTC_IO_PDAC2_MUX_SEL_M (BIT(17))

rtc_io_reg.h:875

#define RTC_IO_PDAC2_SLP_SEL_M (BIT(14))

rtc_io_reg.h:887

#define RTC_IO_PDAC2_SLP_IE_M (BIT(13))

rtc_io_reg.h:893

#define RTC_IO_PDAC2_FUN_IE_M (BIT(11))

rtc_io_reg.h:905

#define RTC_IO_X32N_HOLD_M (BIT(29))

rtc_io_reg.h:926

#define RTC_IO_X32N_RDE (BIT(28))

rtc_io_reg.h:931

#define RTC_IO_X32N_RDE_M (BIT(28))

rtc_io_reg.h:932

#define RTC_IO_X32N_RUE (BIT(27))

rtc_io_reg.h:937

#define RTC_IO_X32N_RUE_M (BIT(27))

rtc_io_reg.h:938

#define RTC_IO_X32P_HOLD_M (BIT(24))

rtc_io_reg.h:950

#define RTC_IO_X32P_RDE (BIT(23))

rtc_io_reg.h:955

#define RTC_IO_X32P_RDE_M (BIT(23))

rtc_io_reg.h:956

#define RTC_IO_X32P_RUE (BIT(22))

rtc_io_reg.h:961

#define RTC_IO_X32P_RUE_M (BIT(22))

rtc_io_reg.h:962

#define RTC_IO_XPD_XTAL_32K (BIT(19))

rtc_io_reg.h:973

#define RTC_IO_XPD_XTAL_32K_M (BIT(19))

rtc_io_reg.h:974

#define RTC_IO_X32N_MUX_SEL (BIT(18))

rtc_io_reg.h:979

#define RTC_IO_X32N_MUX_SEL_M (BIT(18))

rtc_io_reg.h:980

#define RTC_IO_X32P_MUX_SEL (BIT(17))

rtc_io_reg.h:985

#define RTC_IO_X32P_MUX_SEL_M (BIT(17))

rtc_io_reg.h:986

#define RTC_IO_X32N_SLP_SEL_M (BIT(14))

rtc_io_reg.h:998

#define RTC_IO_X32N_SLP_IE_M (BIT(13))

rtc_io_reg.h:1004

#define RTC_IO_X32N_FUN_IE (BIT(11))

rtc_io_reg.h:1015

#define RTC_IO_X32N_FUN_IE_M (BIT(11))

rtc_io_reg.h:1016

#define RTC_IO_X32P_SLP_SEL_M (BIT(8))

rtc_io_reg.h:1028

#define RTC_IO_X32P_SLP_IE_M (BIT(7))

rtc_io_reg.h:1034

#define RTC_IO_X32P_FUN_IE (BIT(5))

rtc_io_reg.h:1045

#define RTC_IO_X32P_FUN_IE_M (BIT(5))

rtc_io_reg.h:1046

#define RTC_IO_TOUCH_PAD0_HOLD_M (BIT(31))

rtc_io_reg.h:1099

#define RTC_IO_TOUCH_PAD0_RDE_M (BIT(28))

rtc_io_reg.h:1111

#define RTC_IO_TOUCH_PAD0_RUE_M (BIT(27))

rtc_io_reg.h:1117

#define RTC_IO_TOUCH_PAD0_MUX_SEL_M (BIT(19))

rtc_io_reg.h:1147

#define RTC_IO_TOUCH_PAD0_SLP_SEL_M (BIT(16))

rtc_io_reg.h:1159

#define RTC_IO_TOUCH_PAD0_SLP_IE_M (BIT(15))

rtc_io_reg.h:1165

#define RTC_IO_TOUCH_PAD0_FUN_IE_M (BIT(13))

rtc_io_reg.h:1177

#define RTC_IO_TOUCH_PAD1_HOLD_M (BIT(31))

rtc_io_reg.h:1191

#define RTC_IO_TOUCH_PAD1_RDE_M (BIT(28))

rtc_io_reg.h:1203

#define RTC_IO_TOUCH_PAD1_RUE_M (BIT(27))

rtc_io_reg.h:1209

#define RTC_IO_TOUCH_PAD1_MUX_SEL_M (BIT(19))

rtc_io_reg.h:1239

#define RTC_IO_TOUCH_PAD1_SLP_SEL_M (BIT(16))

rtc_io_reg.h:1251

#define RTC_IO_TOUCH_PAD1_SLP_IE_M (BIT(15))

rtc_io_reg.h:1257

#define RTC_IO_TOUCH_PAD1_FUN_IE_M (BIT(13))

rtc_io_reg.h:1269

#define RTC_IO_TOUCH_PAD2_HOLD_M (BIT(31))

rtc_io_reg.h:1283

#define RTC_IO_TOUCH_PAD2_RDE_M (BIT(28))

rtc_io_reg.h:1295

#define RTC_IO_TOUCH_PAD2_RUE_M (BIT(27))

rtc_io_reg.h:1301

#define RTC_IO_TOUCH_PAD2_MUX_SEL_M (BIT(19))

rtc_io_reg.h:1331

#define RTC_IO_TOUCH_PAD2_SLP_SEL_M (BIT(16))

rtc_io_reg.h:1343

#define RTC_IO_TOUCH_PAD2_SLP_IE_M (BIT(15))

rtc_io_reg.h:1349

#define RTC_IO_TOUCH_PAD2_FUN_IE_M (BIT(13))

rtc_io_reg.h:1361

#define RTC_IO_TOUCH_PAD3_HOLD_M (BIT(31))

rtc_io_reg.h:1375

#define RTC_IO_TOUCH_PAD3_RDE_M (BIT(28))

rtc_io_reg.h:1387

#define RTC_IO_TOUCH_PAD3_RUE_M (BIT(27))

rtc_io_reg.h:1393

#define RTC_IO_TOUCH_PAD3_MUX_SEL_M (BIT(19))

rtc_io_reg.h:1423

#define RTC_IO_TOUCH_PAD3_SLP_SEL_M (BIT(16))

rtc_io_reg.h:1435

#define RTC_IO_TOUCH_PAD3_SLP_IE_M (BIT(15))

rtc_io_reg.h:1441

#define RTC_IO_TOUCH_PAD3_FUN_IE_M (BIT(13))

rtc_io_reg.h:1453

#define RTC_IO_TOUCH_PAD4_HOLD_M (BIT(31))

rtc_io_reg.h:1467

#define RTC_IO_TOUCH_PAD4_RDE_M (BIT(28))

rtc_io_reg.h:1479

#define RTC_IO_TOUCH_PAD4_RUE_M (BIT(27))

rtc_io_reg.h:1485

#define RTC_IO_TOUCH_PAD4_MUX_SEL_M (BIT(19))

rtc_io_reg.h:1515

#define RTC_IO_TOUCH_PAD4_SLP_SEL_M (BIT(16))

rtc_io_reg.h:1527

#define RTC_IO_TOUCH_PAD4_SLP_IE_M (BIT(15))

rtc_io_reg.h:1533

#define RTC_IO_TOUCH_PAD4_FUN_IE_M (BIT(13))

rtc_io_reg.h:1545

#define RTC_IO_TOUCH_PAD5_HOLD_M (BIT(31))

rtc_io_reg.h:1559

#define RTC_IO_TOUCH_PAD5_RDE_M (BIT(28))

rtc_io_reg.h:1571

#define RTC_IO_TOUCH_PAD5_RUE_M (BIT(27))

rtc_io_reg.h:1577

#define RTC_IO_TOUCH_PAD5_MUX_SEL_M (BIT(19))

rtc_io_reg.h:1607

#define RTC_IO_TOUCH_PAD5_SLP_SEL_M (BIT(16))

rtc_io_reg.h:1619

#define RTC_IO_TOUCH_PAD5_SLP_IE_M (BIT(15))

rtc_io_reg.h:1625

#define RTC_IO_TOUCH_PAD5_FUN_IE_M (BIT(13))

rtc_io_reg.h:1637

#define RTC_IO_TOUCH_PAD6_HOLD_M (BIT(31))

rtc_io_reg.h:1651

#define RTC_IO_TOUCH_PAD6_RDE_M (BIT(28))

rtc_io_reg.h:1663

#define RTC_IO_TOUCH_PAD6_RUE_M (BIT(27))

rtc_io_reg.h:1669

#define RTC_IO_TOUCH_PAD6_MUX_SEL_M (BIT(19))

rtc_io_reg.h:1699

#define RTC_IO_TOUCH_PAD6_SLP_SEL_M (BIT(16))

rtc_io_reg.h:1711

#define RTC_IO_TOUCH_PAD6_SLP_IE_M (BIT(15))

rtc_io_reg.h:1717

#define RTC_IO_TOUCH_PAD6_FUN_IE_M (BIT(13))

rtc_io_reg.h:1729

#define RTC_IO_TOUCH_PAD7_HOLD_M (BIT(31))

rtc_io_reg.h:1743

#define RTC_IO_TOUCH_PAD7_RDE_M (BIT(28))

rtc_io_reg.h:1755

#define RTC_IO_TOUCH_PAD7_RUE_M (BIT(27))

rtc_io_reg.h:1761

#define RTC_IO_TOUCH_PAD7_MUX_SEL_M (BIT(19))

rtc_io_reg.h:1791

#define RTC_IO_TOUCH_PAD7_SLP_SEL_M (BIT(16))

rtc_io_reg.h:1803

#define RTC_IO_TOUCH_PAD7_SLP_IE_M (BIT(15))

rtc_io_reg.h:1809

#define RTC_IO_TOUCH_PAD7_FUN_IE_M (BIT(13))

rtc_io_reg.h:1821

sec_1b = dtable[(u8) pw[0]] & BIT(4);

sae_pk.c:194

if (sec_1b != (dtable[(u8) pw[i]] & BIT(4))) {

sae_pk.c:196

tmp->sec = (pw[0] & BIT(7)) ? 3 : 5;

sae_pk.c:407

#define BLE_MESH_STORE_UNPROV_INFO_QUERY_TYPE_UUID BIT(0)

scan.h:21

#define BLE_MESH_STORE_UNPROV_INFO_QUERY_TYPE_EXISTS BIT(1)

scan.h:22

#define CCCR_CARD_CAP_LSC BIT(6)

sd_protocol_defs.h:522

#define CCCR_CARD_CAP_4BLS BIT(7)

sd_protocol_defs.h:523

#define CCCR_HIGHSPEED_SUPPORT BIT(0)

sd_protocol_defs.h:528

#define CCCR_HIGHSPEED_ENABLE BIT(1)

sd_protocol_defs.h:529

#define SDMMC_HOST_FLAG_1BIT BIT(0) /*!< host supports 1-line SD and MMC protocol */

sd_protocol_types.h:202

#define SDMMC_HOST_FLAG_4BIT BIT(1) /*!< host supports 4-line SD and MMC protocol */

sd_protocol_types.h:203

#define SDMMC_HOST_FLAG_8BIT BIT(2) /*!< host supports 8-line MMC protocol */

sd_protocol_types.h:204

#define SDMMC_HOST_FLAG_SPI BIT(3) /*!< host supports SPI protocol */

sd_protocol_types.h:205

#define SDMMC_HOST_FLAG_DDR BIT(4) /*!< host supports DDR mode for SD/MMC */

sd_protocol_types.h:206

#define SDMMC_HOST_FLAG_DEINIT_ARG BIT(5) /*!< host `deinit` function called with the slot argument */

sd_protocol_types.h:207

BIT(6) /*!< Allocate internal buffer of 512 bytes that meets DMA's requirements.

sd_protocol_types.h:209

if (BIT(i) & int_val) {

sdio_slave.c:485

return (sdio_slave_hostint_t)BIT(pos);

sdio_slave.c:550

#define SDIO_SLAVE_FLAG_DAT2_DISABLED BIT(0) /**< It is required by the SD specification that all 4 data

sdio_slave.h:34

#define SDIO_SLAVE_FLAG_HOST_INTR_DISABLED BIT(1) /**< The DAT1 line is used as the interrupt line in SDIO

sdio_slave.h:39

#define SDIO_SLAVE_FLAG_INTERNAL_PULLUP BIT(2) /**< Enable internal pullups for enabled pins. It is required

sdio_slave.h:45

#define SDIO_SLAVE_FLAG_DEFAULT_SPEED BIT(3) /**< Disable the highspeed support of the hardware. */

sdio_slave.h:50

SDIO_SLAVE_LL_SLVINT_0 = BIT(0), ///< General purpose interrupt bit 0.

sdio_slave_ll.h:69

SDIO_SLAVE_LL_SLVINT_1 = BIT(1),

sdio_slave_ll.h:70

SDIO_SLAVE_LL_SLVINT_2 = BIT(2),

sdio_slave_ll.h:71

SDIO_SLAVE_LL_SLVINT_3 = BIT(3),

sdio_slave_ll.h:72

SDIO_SLAVE_LL_SLVINT_4 = BIT(4),

sdio_slave_ll.h:73

SDIO_SLAVE_LL_SLVINT_5 = BIT(5),

sdio_slave_ll.h:74

SDIO_SLAVE_LL_SLVINT_6 = BIT(6),

sdio_slave_ll.h:75

SDIO_SLAVE_LL_SLVINT_7 = BIT(7),

sdio_slave_ll.h:76

SDIO_SLAVE_HOSTINT_BIT0 = BIT(0), ///< General purpose interrupt bit 0.

sdio_slave_types.h:17

SDIO_SLAVE_HOSTINT_BIT1 = BIT(1),

sdio_slave_types.h:18

SDIO_SLAVE_HOSTINT_BIT2 = BIT(2),

sdio_slave_types.h:19

SDIO_SLAVE_HOSTINT_BIT3 = BIT(3),

sdio_slave_types.h:20

SDIO_SLAVE_HOSTINT_BIT4 = BIT(4),

sdio_slave_types.h:21

SDIO_SLAVE_HOSTINT_BIT5 = BIT(5),

sdio_slave_types.h:22

SDIO_SLAVE_HOSTINT_BIT6 = BIT(6),

sdio_slave_types.h:23

SDIO_SLAVE_HOSTINT_BIT7 = BIT(7),

sdio_slave_types.h:24

SDIO_SLAVE_HOSTINT_SEND_NEW_PACKET = BIT(23), ///< New packet available

sdio_slave_types.h:25

#define SDMMC_IO_FIXED_ADDR BIT(31)

sdmmc_cmd.h:19

#define SDMMC_SLOT_FLAG_INTERNAL_PULLUP BIT(0)

sdmmc_host.h:47

#define SDMMC_SLOT_FLAG_WP_ACTIVE_HIGH BIT(1)

sdmmc_host.h:52

#define SDMMC_SLOT_FLAG_UHS1 BIT(2)

sdmmc_host.h:57

bool interface = data[0] & BIT(7);

sdmmc_io.c:555

bool def = data[0] & BIT(6);

sdmmc_io.c:556

bool misc = data[0] & BIT(7);

sdmmc_io.c:566

bool irq = data[0] & BIT(4);

sdmmc_io.c:568

bool io_sp = data[0] & BIT(3);

sdmmc_io.c:569

bool timing = data[0] & BIT(2);

sdmmc_io.c:570

bool mask = data[0] & BIT(4);

sdmmc_io.c:580

reg_val |= BIT(slot);

sdmmc_ll.h:213

reg_val &= ~BIT(slot);

sdmmc_ll.h:215

reg_val |= BIT(slot);

sdmmc_ll.h:276

reg_val &= ~BIT(slot);

sdmmc_ll.h:278

return ((hw->cdetect.cards & BIT(slot)) == 0);

sdmmc_ll.h:394

bool is_protected = hw->wrtprt.cards & BIT(slot);

sdmmc_ll.h:407

ddr_reg_val|= BIT(slot);

sdmmc_ll.h:434

hw->emmc_ddr_reg |= BIT(slot);

sdmmc_ll.h:436

ddr_reg_val&= ~BIT(slot);

sdmmc_ll.h:438

hw->emmc_ddr_reg &= ~BIT(slot);

sdmmc_ll.h:440

#define SDMMC_INTMASK_IO_SLOT1 BIT(17)

sdmmc_reg.h:61

#define SDMMC_INTMASK_IO_SLOT0 BIT(16)

sdmmc_reg.h:62

#define SDMMC_INTMASK_EBE BIT(15)

sdmmc_reg.h:63

#define SDMMC_INTMASK_SBE BIT(13)

sdmmc_reg.h:65

#define SDMMC_INTMASK_HTO BIT(10)

sdmmc_reg.h:69

#define SDMMC_INTMASK_DTO BIT(9)

sdmmc_reg.h:71

#define SDMMC_INTMASK_RTO BIT(8)

sdmmc_reg.h:72

#define SDMMC_INTMASK_DCRC BIT(7)

sdmmc_reg.h:73

#define SDMMC_INTMASK_RCRC BIT(6)

sdmmc_reg.h:74

#define SDMMC_INTMASK_DATA_OVER BIT(3)

sdmmc_reg.h:77

#define SDMMC_INTMASK_CMD_DONE BIT(2)

sdmmc_reg.h:78

#define SDMMC_INTMASK_RESP_ERR BIT(1)

sdmmc_reg.h:79

#define SDMMC_INTMASK_CD BIT(0)

sdmmc_reg.h:80

#define SDMMC_IDMAC_INTMASK_NI BIT(8)

sdmmc_reg.h:83

#define SDMMC_IDMAC_INTMASK_RI BIT(1)

sdmmc_reg.h:87

#define SDMMC_IDMAC_INTMASK_TI BIT(0)

sdmmc_reg.h:88

if ((supported_mask & BIT(SD_ACCESS_MODE_DDR50)) == 0) {

sdmmc_sd.c:264

if ((supported_mask & BIT(SD_ACCESS_MODE_SDR104)) == 0) {

sdmmc_sd.c:283

if ((supported_mask & BIT(SD_ACCESS_MODE_SDR50)) == 0) {

sdmmc_sd.c:295

if ((supported_mask & BIT(SD_ACCESS_MODE_SDR25)) == 0) {

sdmmc_sd.c:306

#define SDSPI_CMD_FLAG_DATA BIT(0) //!< Command has data transfer

sdspi_private.h:83

#define SDSPI_CMD_FLAG_WRITE BIT(1) //!< Data is written to the card

sdspi_private.h:84

#define SDSPI_CMD_FLAG_RSP_R1 BIT(2) //!< Response format R1 (1 byte)

sdspi_private.h:85

#define SDSPI_CMD_FLAG_RSP_R1B BIT(3) //!< Response format R1 (1 byte), with busy polling

sdspi_private.h:86

#define SDSPI_CMD_FLAG_RSP_R2 BIT(4) //!< Response format R2 (2 bytes)

sdspi_private.h:87

#define SDSPI_CMD_FLAG_RSP_R3 BIT(5) //!< Response format R3 (5 bytes)

sdspi_private.h:88

#define SDSPI_CMD_FLAG_RSP_R4 BIT(6) //!< Response format R4 (5 bytes)

sdspi_private.h:89

#define SDSPI_CMD_FLAG_RSP_R5 BIT(7) //!< Response format R5 (2 bytes)

sdspi_private.h:90

#define SDSPI_CMD_FLAG_RSP_R7 BIT(8) //!< Response format R7 (5 bytes)

sdspi_private.h:91

#define SDSPI_CMD_FLAG_NORSP BIT(9) //!< Don't expect response (used when sending CMD0 first time).

sdspi_private.h:92

#define SDSPI_CMD_FLAG_MULTI_BLK BIT(10) //!< For the write multiblock commands, the start token should be different

sdspi_private.h:93

#define SENS_SAR1_DIG_FORCE (BIT(27))

sens_reg.h:20

#define SENS_ULP_CP_START_TOP (BIT(9))

sens_reg.h:237

#define SENS_ULP_CP_FORCE_START_TOP (BIT(8))

sens_reg.h:243

#define SENS_ULP_CP_FORCE_START_TOP_M (BIT(8))

sens_reg.h:244

#define SENS_SAR2_EN_TEST (BIT(4))

sens_reg.h:255

#define SENS_SAR2_DIG_FORCE (BIT(28))

sens_reg.h:772

#define NO_WAIT_PENDING_BITS (BIT(BLE_MESH_NET_PENDING) | \

settings.c:1514

BIT(BLE_MESH_IV_PENDING) | \

settings.c:1515

BIT(BLE_MESH_SEQ_PENDING))

settings.c:1516

#define GENERIC_PENDING_BITS (BIT(BLE_MESH_KEYS_PENDING) | \

settings.c:1519

BIT(BLE_MESH_HB_PUB_PENDING) | \

settings.c:1520

BIT(BLE_MESH_CFG_PENDING) | \

settings.c:1521

BIT(BLE_MESH_MOD_PENDING))

settings.c:1522

#define BLE_MESH_SETTINGS_ROLE_NODE (BIT(BLE_MESH_NODE))

settings.h:19

#define BLE_MESH_SETTINGS_ROLE_PROV (BIT(BLE_MESH_PROVISIONER))

settings.h:20

#define BLE_MESH_SETTINGS_ROLE_BIT_MASK (BIT(BLE_MESH_NODE) | BIT(BLE_MESH_PROVISIONER))

settings.h:21

#define SLC_SLC0_TOKEN1_INC_MORE (BIT(14))

slc_reg.h:1766

#define SLC_SLC0_TOKEN1_WR (BIT(12))

slc_reg.h:1778

#define SLC_SLC0_LEN_WR (BIT(20))

slc_reg.h:2384

if ((rtc_io_mask & BIT(rtcio_num)) == 0) {

sleep_gpio.c:165

rtc_io_mask &= ~BIT(rtcio_num);

sleep_gpio.c:169

ESP_SYSTEM_INIT_FN(esp_sleep_startup_init, SECONDARY, BIT(0), 105)

sleep_gpio.c:193

s_suspended_uarts_bmap |= BIT(i);

sleep_modes.c:588

rtc_gpio_mask |= BIT(rtc_io_number_get(gpio));

sleep_modes.c:1883

rtc_gpio_mask |= BIT(rtc_io_number_get(gpio));

sleep_modes.c:1928

if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) {

sleep_modes.c:1975

rtc_gpio_mask &= ~BIT(rtc_pin);

sleep_modes.c:2005

if ((status & BIT(rtc_pin)) == 0) {

sleep_modes.c:2027

#define WEAK_BG_FLAG BIT(30) /**< The bus is permanently requested by background operations.

spi_bus_lock.c:167

bool is_used = (BIT(dma_chan) & spi_dma_chan_enabled);

spi_common.c:132

spi_dma_chan_enabled |= BIT(dma_chan);

spi_common.c:134

assert(spi_dma_chan_enabled & BIT(dma_chan));

spi_common.c:346

spi_dma_chan_enabled &= ~BIT(dma_chan);

spi_common.c:349

SPI_FLASH_CHIP_CAP_SUSPEND = BIT(0), ///< Flash chip support suspend feature.

spi_flash_chip_driver.h:30

SPI_FLASH_CHIP_CAP_32MB_SUPPORT = BIT(1), ///< Flash chip driver support flash size larger than 32M Bytes.

spi_flash_chip_driver.h:31

SPI_FLASH_CHIP_CAP_UNIQUE_ID = BIT(2), ///< Flash chip driver support read the flash unique id.

spi_flash_chip_driver.h:32

#define SPI_FLASH_CONFIG_IO_MODE_32B_ADDR BIT(0)

spi_flash_chip_generic.h:381

while(!(REG_READ(FLASH_ENCRYPTION_DONE_REG) & BIT(0))) {

spi_flash_encrypted_ll.h:57

REG_WRITE(FLASH_ENCRYPTION_START_REG, BIT(0));

spi_flash_encrypted_ll.h:66

#define SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND BIT(0) ///< When the auto-suspend is setup in configuration.

spi_flash_hal.h:48

#define SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_RESUME BIT(1) ///< Setup auto-resume feature.

spi_flash_hal.h:49

#define SPI_FLASH_HOST_CONTEXT_SLICER_FLAG_DTR BIT(0) ///< Slice data according to DTR mode, the address and length must be even (A0=0).

spi_flash_hal.h:53

#define SPI_FLASH_TRANS_FLAG_IGNORE_BASEIO BIT(1) ///< Not applying the basic io mode configuration for this transaction

spi_flash_types.h:28

#define SPI_FLASH_TRANS_FLAG_PE_CMD BIT(3) ///< Indicates that this transaction is to erase/program flash chip.

spi_flash_types.h:30

#define SPI_FLASH_CONFIG_CONF_BITS BIT(31) ///< OR the io_mode with this mask, to enable the dummy output feature or replace the first several dummy bits into address to meet the requirements of conf bits. (Used in DIO/QIO/OIO mode)

spi_flash_types.h:56

#define SPI_FLASH_READ_M (BIT(31))

spi_reg.h:18

#define SPI_FLASH_WREN (BIT(30))

spi_reg.h:24

#define SPI_FLASH_WRDI (BIT(29))

spi_reg.h:31

#define SPI_FLASH_RDSR (BIT(27))

spi_reg.h:45

#define SPI_FLASH_WRSR (BIT(26))

spi_reg.h:52

#define SPI_FLASH_PP (BIT(25))