LL_TIM_ConfigDMABurst() function

Timer instance

This parameter can be one of the following values: @arg LL_TIM_DMABURST_BASEADDR_CR1 @arg LL_TIM_DMABURST_BASEADDR_CR2 @arg LL_TIM_DMABURST_BASEADDR_SMCR @arg LL_TIM_DMABURST_BASEADDR_DIER @arg LL_TIM_DMABURST_BASEADDR_SR @arg LL_TIM_DMABURST_BASEADDR_EGR @arg LL_TIM_DMABURST_BASEADDR_CCMR1 @arg LL_TIM_DMABURST_BASEADDR_CCMR2 @arg LL_TIM_DMABURST_BASEADDR_CCER @arg LL_TIM_DMABURST_BASEADDR_CNT @arg LL_TIM_DMABURST_BASEADDR_PSC @arg LL_TIM_DMABURST_BASEADDR_ARR @arg LL_TIM_DMABURST_BASEADDR_RCR @arg LL_TIM_DMABURST_BASEADDR_CCR1 @arg LL_TIM_DMABURST_BASEADDR_CCR2 @arg LL_TIM_DMABURST_BASEADDR_CCR3 @arg LL_TIM_DMABURST_BASEADDR_CCR4 @arg LL_TIM_DMABURST_BASEADDR_BDTR

This parameter can be one of the following values: @arg LL_TIM_DMABURST_LENGTH_1TRANSFER @arg LL_TIM_DMABURST_LENGTH_2TRANSFERS @arg LL_TIM_DMABURST_LENGTH_3TRANSFERS @arg LL_TIM_DMABURST_LENGTH_4TRANSFERS @arg LL_TIM_DMABURST_LENGTH_5TRANSFERS @arg LL_TIM_DMABURST_LENGTH_6TRANSFERS @arg LL_TIM_DMABURST_LENGTH_7TRANSFERS @arg LL_TIM_DMABURST_LENGTH_8TRANSFERS @arg LL_TIM_DMABURST_LENGTH_9TRANSFERS @arg LL_TIM_DMABURST_LENGTH_10TRANSFERS @arg LL_TIM_DMABURST_LENGTH_11TRANSFERS @arg LL_TIM_DMABURST_LENGTH_12TRANSFERS @arg LL_TIM_DMABURST_LENGTH_13TRANSFERS @arg LL_TIM_DMABURST_LENGTH_14TRANSFERS @arg LL_TIM_DMABURST_LENGTH_15TRANSFERS @arg LL_TIM_DMABURST_LENGTH_16TRANSFERS @arg LL_TIM_DMABURST_LENGTH_17TRANSFERS @arg LL_TIM_DMABURST_LENGTH_18TRANSFERS

Enables or disables the TIM Capture Compare Channel x.

Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived. CCMR1 OC2M LL_TIM_OC_SetMode\n CCMR2 OC3M LL_TIM_OC_SetMode\n CCMR2 OC4M LL_TIM_OC_SetMode

Enables or disables the TIM Capture Compare Channel xN.

Get the auto-reload value.

Enable capture/compare channels. CCER CC1NE LL_TIM_CC_EnableChannel\n CCER CC2E LL_TIM_CC_EnableChannel\n CCER CC2NE LL_TIM_CC_EnableChannel\n CCER CC3E LL_TIM_CC_EnableChannel\n CCER CC3NE LL_TIM_CC_EnableChannel\n CCER CC4E LL_TIM_CC_EnableChannel

Set the auto-reload value.

Enable timer counter.

Get the prescaler value.

Set the prescaler value.

Set compare value for output channel 1 (TIMx_CCR1).

Generate an update event.

Time Base configuration

Set the timer counter counting mode.

Disable capture/compare channels. CCER CC1NE LL_TIM_CC_DisableChannel\n CCER CC2E LL_TIM_CC_DisableChannel\n CCER CC2NE LL_TIM_CC_DisableChannel\n CCER CC3E LL_TIM_CC_DisableChannel\n CCER CC3NE LL_TIM_CC_DisableChannel\n CCER CC4E LL_TIM_CC_DisableChannel

Enable compare register (TIMx_CCRx) preload for the output channel. CCMR1 OC2PE LL_TIM_OC_EnablePreload\n CCMR2 OC3PE LL_TIM_OC_EnablePreload\n CCMR2 OC4PE LL_TIM_OC_EnablePreload

Configure an output channel. CCMR1 CC2S LL_TIM_OC_ConfigOutput\n CCMR2 CC3S LL_TIM_OC_ConfigOutput\n CCMR2 CC4S LL_TIM_OC_ConfigOutput\n CCER CC1P LL_TIM_OC_ConfigOutput\n CCER CC2P LL_TIM_OC_ConfigOutput\n CCER CC3P LL_TIM_OC_ConfigOutput\n CCER CC4P LL_TIM_OC_ConfigOutput\n CR2 OIS1 LL_TIM_OC_ConfigOutput\n CR2 OIS2 LL_TIM_OC_ConfigOutput\n CR2 OIS3 LL_TIM_OC_ConfigOutput\n CR2 OIS4 LL_TIM_OC_ConfigOutput

Timer Output Compare 2 configuration

Configures the TIMx External Trigger (ETR).

Selects the Input Trigger source

Enable auto-reload (ARR) preload.

Enable capture/compare 1 interrupt (CC1IE).

Clear the Capture/Compare 1 interrupt flag (CC1F).

Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).

Configure the TI1 as Input.

Timer Output Compare 1 configuration

Configure the Polarity and Filter for TI1.

Get the counter value.

Set the repetition counter value.

Set the trigger output (TRGO) used for timer synchronization .

Configure the Polarity and Filter for TI2.

Configure the TI2 as Input.

Timer Output Compare 3 configuration

Timer Output Compare 4 configuration

Set compare value for output channel 2 (TIMx_CCR2).

Set compare value for output channel 3 (TIMx_CCR3).

Get captured value for input channel 1.

Enable the outputs (set the MOE bit in TIMx_BDTR register).

Configure the TI3 as Input.

Configure the TI4 as Input.

Set one pulse mode (one shot v.s. repetitive).

Clear the update interrupt flag (UIF).

Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).

Set the input channel polarity. CCER CC1NP LL_TIM_IC_SetPolarity\n CCER CC2P LL_TIM_IC_SetPolarity\n CCER CC2NP LL_TIM_IC_SetPolarity\n CCER CC3P LL_TIM_IC_SetPolarity\n CCER CC3NP LL_TIM_IC_SetPolarity\n CCER CC4P LL_TIM_IC_SetPolarity\n CCER CC4NP LL_TIM_IC_SetPolarity

Get compare value (TIMx_CCR3) set for output channel 3.

Set the active input. CCMR1 CC2S LL_TIM_IC_SetActiveInput\n CCMR2 CC3S LL_TIM_IC_SetActiveInput\n CCMR2 CC4S LL_TIM_IC_SetActiveInput

Configure the TIMx time base unit.

Configure the TIMx output channel.

Configure the TIMx output channel 3.

Configure the TIMx output channel 2.

Configure the TIMx output channel 1.

Configure the TIMx input channel 3.

Configure the TIMx input channel 4.

Configure the TIMx input channel 2.

Configure the TIMx input channel 1.

Configure the TIMx output channel 4.

Disable timer counter.

Enable update interrupt (UIE).

Enable update DMA request (UDE).

Enable capture/compare 3 DMA request (CC3DE).

Clear the Capture/Compare 2 interrupt flag (CC2F).

Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).

Clear the commutation interrupt flag (COMIF).

Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).

Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Set the counter value.

Set the lock level to freeze the configuration of several capture/compare parameters.

Set the polarity of an output channel. CCER CC1NP LL_TIM_OC_SetPolarity\n CCER CC2P LL_TIM_OC_SetPolarity\n CCER CC2NP LL_TIM_OC_SetPolarity\n CCER CC3P LL_TIM_OC_SetPolarity\n CCER CC3NP LL_TIM_OC_SetPolarity\n CCER CC4P LL_TIM_OC_SetPolarity

Get the current input channel polarity. CCER CC1NP LL_TIM_IC_GetPolarity\n CCER CC2P LL_TIM_IC_GetPolarity\n CCER CC2NP LL_TIM_IC_GetPolarity\n CCER CC3P LL_TIM_IC_GetPolarity\n CCER CC3NP LL_TIM_IC_GetPolarity\n CCER CC4P LL_TIM_IC_GetPolarity\n CCER CC4NP LL_TIM_IC_GetPolarity

Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).

Set compare value for output channel 4 (TIMx_CCR4).

Get compare value (TIMx_CCR1) set for output channel 1.

Set the prescaler of input channel. CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n CCMR2 IC4PSC LL_TIM_IC_SetPrescaler

Get the current prescaler value acting on an input channel. CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n CCMR2 IC4PSC LL_TIM_IC_GetPrescaler

Set the input filter duration. CCMR1 IC2F LL_TIM_IC_SetFilter\n CCMR2 IC3F LL_TIM_IC_SetFilter\n CCMR2 IC4F LL_TIM_IC_SetFilter

Get captured value for input channel 2.

Set the encoder interface mode.

Set the synchronization mode of a slave timer.

Set the selects the trigger input to be used to synchronize the counter.

Enable the break function.

Configure the break input.

Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.

Enable automatic output (MOE can be set by software or automatically when a break input is active).

Generate commutation event.

Configure the TIMx input channel.

Configure the encoder interface of the timer instance.

Configure the Hall sensor interface of the timer instance.

Configure the Break and Dead Time feature of the timer instance.

Set TIMx registers to their reset values.

Get actual event update source

Get actual one pulse mode.

Get actual counter mode.

Indicates whether the timer counter is enabled.

Enable update event generation.

Disable update event generation.

Indicates whether update event generation is enabled.

Set update event source

Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).

Clear the break interrupt flag (BIF).

Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).

Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).

Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).

Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).

Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).

Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).

Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).

Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).

Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).

Disable update interrupt (UIE).

Indicates whether the update interrupt (UIE) is enabled.

Disable capture/compare 1 interrupt (CC1IE).

Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.

Enable capture/compare 2 interrupt (CC2IE).

Disable capture/compare 2 interrupt (CC2IE).

Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.

Enable capture/compare 3 interrupt (CC3IE).

Disable capture/compare 3 interrupt (CC3IE).

Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.

Enable capture/compare 4 interrupt (CC4IE).

Disable capture/compare 4 interrupt (CC4IE).

Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.

Enable commutation interrupt (COMIE).

Disable commutation interrupt (COMIE).

Indicates whether the commutation interrupt (COMIE) is enabled.

Enable trigger interrupt (TIE).

Disable trigger interrupt (TIE).

Indicates whether the trigger interrupt (TIE) is enabled.

Enable break interrupt (BIE).

Disable break interrupt (BIE).

Indicates whether the break interrupt (BIE) is enabled.

Disable update DMA request (UDE).

Indicates whether the update DMA request (UDE) is enabled.

Enable capture/compare 1 DMA request (CC1DE).

Disable capture/compare 1 DMA request (CC1DE).

Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.

Enable capture/compare 2 DMA request (CC2DE).

Disable capture/compare 2 DMA request (CC2DE).

Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.

Disable capture/compare 3 DMA request (CC3DE).

Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.

Enable capture/compare 4 DMA request (CC4DE).

Remap TIM inputs (input channel, internal/external triggers). Below description summarizes "Timer Instance" and "Remap" param combinations: TIM1: one of the following values ITR2_RMP can be one of the following values @arg LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO (*) @arg LL_TIM_TIM1_ITR2_RMP_LPTIM (*) TIM2: one of the following values ITR1_RMP can be one of the following values @arg LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO @arg LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF @arg LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF TIM5: one of the following values @arg LL_TIM_TIM5_TI4_RMP_GPIO @arg LL_TIM_TIM5_TI4_RMP_LSI @arg LL_TIM_TIM5_TI4_RMP_LSE @arg LL_TIM_TIM5_TI4_RMP_RTC @arg LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO (*) @arg LL_TIM_TIM5_ITR1_RMP_LPTIM (*) TIM9: one of the following values ITR1_RMP can be one of the following values @arg LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO (*) @arg LL_TIM_TIM9_ITR1_RMP_LPTIM (*) TIM11: one of the following values @arg LL_TIM_TIM11_TI1_RMP_GPIO @arg LL_TIM_TIM11_TI1_RMP_GPIO1 (*) @arg LL_TIM_TIM11_TI1_RMP_HSE_RTC @arg LL_TIM_TIM11_TI1_RMP_GPIO2 @arg LL_TIM_TIM11_TI1_RMP_SPDIFRX (*) (*) Value not defined in all devices. \n

Clear the Capture/Compare 3 interrupt flag (CC3F).

Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).

Clear the Capture/Compare 4 interrupt flag (CC4F).

Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).

Clear the trigger interrupt flag (TIF).

Get the polarity of an output channel. CCER CC1NP LL_TIM_OC_GetPolarity\n CCER CC2P LL_TIM_OC_GetPolarity\n CCER CC2NP LL_TIM_OC_GetPolarity\n CCER CC3P LL_TIM_OC_GetPolarity\n CCER CC3NP LL_TIM_OC_GetPolarity\n CCER CC4P LL_TIM_OC_GetPolarity

Set the IDLE state of an output channel

Disable auto-reload (ARR) preload.

Indicates whether auto-reload (ARR) preload is enabled.

Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Get the current direction of the counter

Get the output compare mode of an output channel. CCMR1 OC2M LL_TIM_OC_GetMode\n CCMR2 OC3M LL_TIM_OC_GetMode\n CCMR2 OC4M LL_TIM_OC_GetMode

Disable compare register (TIMx_CCRx) preload for the output channel. CCMR1 OC2PE LL_TIM_OC_DisablePreload\n CCMR2 OC3PE LL_TIM_OC_DisablePreload\n CCMR2 OC4PE LL_TIM_OC_DisablePreload

Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n

Set the trigger of the capture/compare DMA request.

Get actual trigger of the capture/compare DMA request.

Indicate whether channel(s) is(are) enabled. CCER CC1NE LL_TIM_CC_IsEnabledChannel\n CCER CC2E LL_TIM_CC_IsEnabledChannel\n CCER CC2NE LL_TIM_CC_IsEnabledChannel\n CCER CC3E LL_TIM_CC_IsEnabledChannel\n CCER CC3NE LL_TIM_CC_IsEnabledChannel\n CCER CC4E LL_TIM_CC_IsEnabledChannel

Get the repetition counter value.

Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.

Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).

Get compare value (TIMx_CCR4) set for output channel 4.

Configure input channel. CCMR1 IC1PSC LL_TIM_IC_Config\n CCMR1 IC1F LL_TIM_IC_Config\n CCMR1 CC2S LL_TIM_IC_Config\n CCMR1 IC2PSC LL_TIM_IC_Config\n CCMR1 IC2F LL_TIM_IC_Config\n CCMR2 CC3S LL_TIM_IC_Config\n CCMR2 IC3PSC LL_TIM_IC_Config\n CCMR2 IC3F LL_TIM_IC_Config\n CCMR2 CC4S LL_TIM_IC_Config\n CCMR2 IC4PSC LL_TIM_IC_Config\n CCMR2 IC4F LL_TIM_IC_Config\n CCER CC1P LL_TIM_IC_Config\n CCER CC1NP LL_TIM_IC_Config\n CCER CC2P LL_TIM_IC_Config\n CCER CC2NP LL_TIM_IC_Config\n CCER CC3P LL_TIM_IC_Config\n CCER CC3NP LL_TIM_IC_Config\n CCER CC4P LL_TIM_IC_Config\n CCER CC4NP LL_TIM_IC_Config

Get the IDLE state of an output channel CR2 OIS1N LL_TIM_OC_GetIdleState\n CR2 OIS2 LL_TIM_OC_GetIdleState\n CR2 OIS2N LL_TIM_OC_GetIdleState\n CR2 OIS3 LL_TIM_OC_GetIdleState\n CR2 OIS3N LL_TIM_OC_GetIdleState\n CR2 OIS4 LL_TIM_OC_GetIdleState

Enable fast mode for the output channel.

Disable fast mode for the output channel. CCMR1 OC2FE LL_TIM_OC_DisableFast\n CCMR2 OC3FE LL_TIM_OC_DisableFast\n CCMR2 OC4FE LL_TIM_OC_DisableFast

Indicates whether fast mode is enabled for the output channel. CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n

Get compare value (TIMx_CCR2) set for output channel 2.

Enable clearing the output channel on an external event.

Disable clearing the output channel on an external event.

Indicates clearing the output channel on an external event is enabled for the output channel.

Get the current active input. CCMR1 CC2S LL_TIM_IC_GetActiveInput\n CCMR2 CC3S LL_TIM_IC_GetActiveInput\n CCMR2 CC4S LL_TIM_IC_GetActiveInput

Get the input filter duration. CCMR1 IC2F LL_TIM_IC_GetFilter\n CCMR2 IC3F LL_TIM_IC_GetFilter\n CCMR2 IC4F LL_TIM_IC_GetFilter

Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).

Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.

Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.

Get captured value for input channel 3.

Get captured value for input channel 4.

Enable external clock mode 2.

Disable external clock mode 2.

Indicate whether external clock mode 2 is enabled.

Set the clock source of the counter clock.

Enable the Master/Slave mode.

Disable the Master/Slave mode.

Indicates whether the Master/Slave mode is enabled.

Configure the external trigger (ETR) input.

Disable the break function.

Disable automatic output (MOE can be set only by software).

Indicate whether automatic output is enabled.

Disable the outputs (reset the MOE bit in TIMx_BDTR register).

Indicates whether outputs are enabled.

Disable capture/compare 4 DMA request (CC4DE).

Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.

Enable commutation DMA request (COMDE).

Disable commutation DMA request (COMDE).

Indicates whether the commutation DMA request (COMDE) is enabled.

Enable trigger interrupt (TDE).

Disable trigger interrupt (TDE).

Indicates whether the trigger interrupt (TDE) is enabled.

Generate Capture/Compare 1 event.

Generate Capture/Compare 2 event.

Generate Capture/Compare 3 event.

Generate Capture/Compare 4 event.

Generate trigger event.

Generate break event.