uart_ll_get_stop_bits() function

Beginning address of the peripheral registers.

The pointer to accept the stop bit configuration

Clear the UART interrupt status based on the given mask.

Enable the UART interrupt based on the given mask.

Disable the UART interrupt based on the given mask.

Check if the UART sending state machine is in the IDLE state.

Get the length of readable data in UART rxfifo.

Get the writable data length of UART txfifo.

Configure the baud-rate.

Read the UART rxfifo.

Get status of enabled interrupt.

Write byte to the UART txfifo.

Set the rts active level.

Set the UART source clock.

Configure the UART stop bit.

Configure the UART parity check mode.

Get the UART parity check mode configuration.

Configure the duration time between transfers.

Configure the UART hardware flow control.

Set uart mode.

Get the UART data bit configuration.

Set the UART data bit mode.

Enable the UART clock.

Disable the UART clock.

Get the UART source clock type.

Get the current baud-rate.

Get the UART raw interrupt status.

Get the UART interrupt status.

Reset the UART hw txfifo. Note: Due to hardware issue, reset UART1's txfifo will also reset UART2's txfifo. So reserve this function for UART1 and UART2. Please do DPORT reset for UART and its memory at chip startup to ensure the TX FIFO is reset correctly at the beginning.

Reset the UART hw rxfifo.

Set the UART rxfifo full threshold value. When the data in rxfifo is more than the threshold value, it will produce rxfifo_full_int_raw interrupt.

Set the txfifo empty threshold. when the data length in txfifo is less than threshold value, it will produce txfifo_empty_int_raw interrupt.

Configure the transmitter to send break chars.

Configure the hardware flow control.

Configure the AT cmd char. When the receiver receives a continuous AT cmd char, it will produce at_cmd_char_det interrupt.

Configure the UART work in rs485_half_duplex mode.

Configure the UART work in collision_detect mode.

Configure the UART work in irda mode.

Check if the UART rts flow control is enabled.

Configure TX signal loop back to RX module, just for the testing purposes

Inverse the UART signal with the given mask.

Configure the software flow control.

Set the dtr active level.

Set the UART wakeup threshold.

Enable/disable the UART pad clock in sleep_state

Configure the UART work in normal mode.

Configure the UART work in rs485_app_ctrl mode.

Get the UART AT cmd char configuration.

Get the UART wakeup threshold value.

Configure the timeout value for receiver receiving a byte, and enable rx timeout function.

Get the timeout value for receiver receiving a byte.

Get UART maximum timeout threshold.

Set the UART rx-idle threshold value. when receiver takes more time than rx_idle_thrhd to receive a byte data, it will produce frame end signal for uhci to stop receiving data.

Check if the UART cts flow control is enabled.

Get the low pulse minimum count.

Configure the auto baudrate.

Get the RXD edge count.

Get the positive pulse minimum count.

Get the negative pulse minimum count.

Get the high pulse minimum count.

Configure UART whether to discard when receiving wrong data