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uart_dev_s struct
Syntax
struct uart_dev_s
{
union {
struct {
uint32_t rw_byte: 8;
uint32_t reserved: 24;
};
uint32_t val;
} fifo;
union {
struct {
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t reserved19: 13;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t reserved19: 13;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t reserved19: 13;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t reserved19: 13;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t div_int: 20;
uint32_t div_frag: 4;
uint32_t reserved24: 8;
};
uint32_t val;
} clk_div;
union {
struct {
uint32_t en: 1;
uint32_t reserved1: 7;
uint32_t glitch_filt: 8;
uint32_t reserved16: 16;
};
uint32_t val;
} auto_baud;
union {
struct {
uint32_t rxfifo_cnt: 8;
uint32_t st_urx_out: 4;
uint32_t reserved12: 1;
uint32_t dsrn: 1;
uint32_t ctsn: 1;
uint32_t rxd: 1;
uint32_t txfifo_cnt: 8;
uint32_t st_utx_out: 4;
uint32_t reserved28: 1;
uint32_t dtrn: 1;
uint32_t rtsn: 1;
uint32_t txd: 1;
};
uint32_t val;
} status;
union {
struct {
uint32_t parity: 1;
uint32_t parity_en: 1;
uint32_t bit_num: 2;
uint32_t stop_bit_num: 2;
uint32_t sw_rts: 1;
uint32_t sw_dtr: 1;
uint32_t txd_brk: 1;
uint32_t irda_dplx: 1;
uint32_t irda_tx_en: 1;
uint32_t irda_wctl: 1;
uint32_t irda_tx_inv: 1;
uint32_t irda_rx_inv: 1;
uint32_t loopback: 1;
uint32_t tx_flow_en: 1;
uint32_t irda_en: 1;
uint32_t rxfifo_rst: 1;
uint32_t txfifo_rst: 1;
uint32_t rxd_inv: 1;
uint32_t cts_inv: 1;
uint32_t dsr_inv: 1;
uint32_t txd_inv: 1;
uint32_t rts_inv: 1;
uint32_t dtr_inv: 1;
uint32_t clk_en: 1;
uint32_t err_wr_mask: 1;
uint32_t tick_ref_always_on: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t rxfifo_full_thrhd: 7;
uint32_t reserved7: 1;
uint32_t txfifo_empty_thrhd: 7;
uint32_t reserved15: 1;
uint32_t rx_flow_thrhd: 7;
uint32_t rx_flow_en: 1;
uint32_t rx_tout_thrhd: 7;
uint32_t rx_tout_en: 1;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t min_cnt: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} lowpulse;
union {
struct {
uint32_t min_cnt: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} highpulse;
union {
struct {
uint32_t edge_cnt: 10;
uint32_t reserved10: 22;
};
uint32_t val;
} rxd_cnt;
union {
struct {
uint32_t sw_flow_con_en: 1;
uint32_t xonoff_del: 1;
uint32_t force_xon: 1;
uint32_t force_xoff: 1;
uint32_t send_xon: 1;
uint32_t send_xoff: 1;
uint32_t reserved6: 26;
};
uint32_t val;
} flow_conf;
union {
struct {
uint32_t active_threshold:10;
uint32_t reserved10: 22;
};
uint32_t val;
} sleep_conf;
union {
struct {
uint32_t xon_threshold: 8;
uint32_t xoff_threshold: 8;
uint32_t xon_character: 8;
uint32_t xoff_character: 8;
};
uint32_t val;
} swfc_conf;
union {
struct {
uint32_t rx_idle_thrhd:10;
uint32_t tx_idle_num: 10;
uint32_t tx_brk_num: 8;
uint32_t reserved28: 4;
};
uint32_t val;
} idle_conf;
union {
struct {
uint32_t en: 1;
uint32_t dl0_en: 1;
uint32_t dl1_en: 1;
uint32_t tx_rx_en: 1;
uint32_t rx_busy_tx_en: 1;
uint32_t rx_dly_num: 1;
uint32_t tx_dly_num: 4;
uint32_t reserved10: 22;
};
uint32_t val;
} rs485_conf;
union {
struct {
uint32_t pre_idle_num:24;
uint32_t reserved24: 8;
};
uint32_t val;
} at_cmd_precnt;
union {
struct {
uint32_t post_idle_num:24;
uint32_t reserved24: 8;
};
uint32_t val;
} at_cmd_postcnt;
union {
struct {
uint32_t rx_gap_tout:24;
uint32_t reserved24: 8;
};
uint32_t val;
} at_cmd_gaptout;
union {
struct {
uint32_t data: 8;
uint32_t at_char_num: 8;
uint32_t reserved16: 16;
};
uint32_t val;
} at_cmd_char;
union {
struct {
uint32_t mem_pd: 1;
uint32_t reserved1: 1;
uint32_t reserved2: 1;
uint32_t rx_size: 4;
uint32_t tx_size: 4;
uint32_t reserved11: 4;
uint32_t rx_flow_thrhd_h3: 3;
uint32_t rx_tout_thrhd_h3: 3;
uint32_t xon_threshold_h2: 2;
uint32_t xoff_threshold_h2: 2;
uint32_t rx_mem_full_thrhd: 3;
uint32_t tx_mem_empty_thrhd: 3;
uint32_t reserved31: 1;
};
uint32_t val;
} mem_conf;
union {
struct {
uint32_t status:24;
uint32_t reserved24: 8;
};
uint32_t val;
} mem_tx_status;
union {
struct {
uint32_t status: 24;
uint32_t reserved24: 8;
};
struct {
uint32_t reserved0: 2;
uint32_t rd_addr: 11;
uint32_t wr_addr: 11;
uint32_t reserved: 8;
};
uint32_t val;
} mem_rx_status;
union {
struct {
uint32_t rx_cnt: 3;
uint32_t tx_cnt: 3;
uint32_t reserved6: 26;
};
uint32_t val;
} mem_cnt_status;
union {
struct {
uint32_t min_cnt: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} pospulse;
union {
struct {
uint32_t min_cnt: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} negpulse;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t date;
uint32_t id;
};
Fields
Field
Declared as
uint32_t
uint32_t
uint32_t
uint32_t
union {
struct {
uint32_t data: 8;
uint32_t at_char_num: 8;
uint32_t reserved16: 16;
};
uint32_t val;
}
union {
struct {
uint32_t mem_pd: 1;
uint32_t reserved1: 1;
uint32_t reserved2: 1;
uint32_t rx_size: 4;
uint32_t tx_size: 4;
uint32_t reserved11: 4;
uint32_t rx_flow_thrhd_h3: 3;
uint32_t rx_tout_thrhd_h3: 3;
uint32_t xon_threshold_h2: 2;
uint32_t xoff_threshold_h2: 2;
uint32_t rx_mem_full_thrhd: 3;
uint32_t tx_mem_empty_thrhd: 3;
uint32_t reserved31: 1;
};
uint32_t val;
}
union {
struct {
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t reserved19: 13;
};
uint32_t val;
}
union {
struct {
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t reserved19: 13;
};
uint32_t val;
}
union {
struct {
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t reserved19: 13;
};
uint32_t val;
}
union {
struct {
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t reserved19: 13;
};
uint32_t val;
}
union {
struct {
uint32_t div_int: 20;
uint32_t div_frag: 4;
uint32_t reserved24: 8;
};
uint32_t val;
}
union {
struct {
uint32_t parity: 1;
uint32_t parity_en: 1;
uint32_t bit_num: 2;
uint32_t stop_bit_num: 2;
uint32_t sw_rts: 1;
uint32_t sw_dtr: 1;
uint32_t txd_brk: 1;
uint32_t irda_dplx: 1;
uint32_t irda_tx_en: 1;
uint32_t irda_wctl: 1;
uint32_t irda_tx_inv: 1;
uint32_t irda_rx_inv: 1;
uint32_t loopback: 1;
uint32_t tx_flow_en: 1;
uint32_t irda_en: 1;
uint32_t rxfifo_rst: 1;
uint32_t txfifo_rst: 1;
uint32_t rxd_inv: 1;
uint32_t cts_inv: 1;
uint32_t dsr_inv: 1;
uint32_t txd_inv: 1;
uint32_t rts_inv: 1;
uint32_t dtr_inv: 1;
uint32_t clk_en: 1;
uint32_t err_wr_mask: 1;
uint32_t tick_ref_always_on: 1;
uint32_t reserved28: 4;
};
uint32_t val;
}
union {
struct {
uint32_t en: 1;
uint32_t reserved1: 7;
uint32_t glitch_filt: 8;
uint32_t reserved16: 16;
};
uint32_t val;
}
union {
struct {
uint32_t rxfifo_cnt: 8;
uint32_t st_urx_out: 4;
uint32_t reserved12: 1;
uint32_t dsrn: 1;
uint32_t ctsn: 1;
uint32_t rxd: 1;
uint32_t txfifo_cnt: 8;
uint32_t st_utx_out: 4;
uint32_t reserved28: 1;
uint32_t dtrn: 1;
uint32_t rtsn: 1;
uint32_t txd: 1;
};
uint32_t val;
}
union {
struct {
uint32_t rxfifo_full_thrhd: 7;
uint32_t reserved7: 1;
uint32_t txfifo_empty_thrhd: 7;
uint32_t reserved15: 1;
uint32_t rx_flow_thrhd: 7;
uint32_t rx_flow_en: 1;
uint32_t rx_tout_thrhd: 7;
uint32_t rx_tout_en: 1;
};
uint32_t val;
}
union {
struct {
uint32_t sw_flow_con_en: 1;
uint32_t xonoff_del: 1;
uint32_t force_xon: 1;
uint32_t force_xoff: 1;
uint32_t send_xon: 1;
uint32_t send_xoff: 1;
uint32_t reserved6: 26;
};
uint32_t val;
}
union {
struct {
uint32_t xon_threshold: 8;
uint32_t xoff_threshold: 8;
uint32_t xon_character: 8;
uint32_t xoff_character: 8;
};
uint32_t val;
}
union {
struct {
uint32_t rx_idle_thrhd:10;
uint32_t tx_idle_num: 10;
uint32_t tx_brk_num: 8;
uint32_t reserved28: 4;
};
uint32_t val;
}
union {
struct {
uint32_t en: 1;
uint32_t dl0_en: 1;
uint32_t dl1_en: 1;
uint32_t tx_rx_en: 1;
uint32_t rx_busy_tx_en: 1;
uint32_t rx_dly_num: 1;
uint32_t tx_dly_num: 4;
uint32_t reserved10: 22;
};
uint32_t val;
}
Related Functions
Found 60 other functions taking a uart_dev_s
argument:
Function
Description
Clear the UART interrupt status based on the given mask.
Enable the UART interrupt based on the given mask.
Disable the UART interrupt based on the given mask.
Check if the UART sending state machine is in the IDLE state.
Get the length of readable data in UART rxfifo.
Get the writable data length of UART txfifo.
Configure the baud-rate.
Read the UART rxfifo.
Get status of enabled interrupt.
Write byte to the UART txfifo.
Set the rts active level.
Set the UART source clock.
Configure the UART stop bit.
Get the configuration of the UART stop bit.
Configure the UART parity check mode.
Get the UART parity check mode configuration.
Configure the duration time between transfers.
Configure the UART hardware flow control.
Set uart mode.
Get the UART data bit configuration.
Set the UART data bit mode.
Enable the UART clock.
Disable the UART clock.
Get the UART source clock type.
Get the current baud-rate.
Get the UART raw interrupt status.
Get the UART interrupt status.
Reset the UART hw txfifo. Note: Due to hardware issue, reset UART1's txfifo will also reset UART2's txfifo. So reserve this function for UART1 and UART2. Please do DPORT reset for UART and its memory at chip startup to ensure the TX FIFO is reset correctly at the beginning.
Reset the UART hw rxfifo.
Set the UART rxfifo full threshold value. When the data in rxfifo is more than the threshold value, it will produce rxfifo_full_int_raw interrupt.
Set the txfifo empty threshold. when the data length in txfifo is less than threshold value, it will produce txfifo_empty_int_raw interrupt.
Configure the transmitter to send break chars.
Configure the hardware flow control.
Configure the AT cmd char. When the receiver receives a continuous AT cmd char, it will produce at_cmd_char_det interrupt.
Configure the UART work in rs485_half_duplex mode.
Configure the UART work in collision_detect mode.
Configure the UART work in irda mode.
Check if the UART rts flow control is enabled.
Configure TX signal loop back to RX module, just for the testing purposes
Inverse the UART signal with the given mask.
Configure the software flow control.
Set the dtr active level.
Set the UART wakeup threshold.
Enable/disable the UART pad clock in sleep_state
Configure the UART work in normal mode.
Configure the UART work in rs485_app_ctrl mode.
Get the UART AT cmd char configuration.
Get the UART wakeup threshold value.
Configure the timeout value for receiver receiving a byte, and enable rx timeout function.
Get the timeout value for receiver receiving a byte.
Get UART maximum timeout threshold.
Set the UART rx-idle threshold value. when receiver takes more time than rx_idle_thrhd to receive a byte data, it will produce frame end signal for uhci to stop receiving data.
Check if the UART cts flow control is enabled.
Get the low pulse minimum count.
Configure the auto baudrate.
Get the RXD edge count.
Get the positive pulse minimum count.
Get the negative pulse minimum count.
Get the high pulse minimum count.
Configure UART whether to discard when receiving wrong data
References
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