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SourceVuESP-IDF Framework and ExamplesESP-IDFuart_dev_s::conf0

uart_dev_s::conf0 field

Syntax

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Summary

Declaration

from uart_struct.h:157

union { struct { uint32_t parity: 1; uint32_t parity_en: 1; uint32_t bit_num: 2; uint32_t stop_bit_num: 2; uint32_t sw_rts: 1; uint32_t sw_dtr: 1; uint32_t txd_brk: 1; uint32_t irda_dplx: 1; uint32_t irda_tx_en: 1; uint32_t irda_wctl: 1; uint32_t irda_tx_inv: 1; uint32_t irda_rx_inv: 1; uint32_t loopback: 1; uint32_t tx_flow_en: 1; uint32_t irda_en: 1; uint32_t rxfifo_rst: 1; uint32_t txfifo_rst: 1; uint32_t rxd_inv: 1; uint32_t cts_inv: 1; uint32_t dsr_inv: 1; uint32_t txd_inv: 1; uint32_t rts_inv: 1; uint32_t dtr_inv: 1; uint32_t clk_en: 1; uint32_t err_wr_mask: 1; uint32_t tick_ref_always_on: 1; uint32_t reserved28: 4; }; uint32_t val; } conf0;

References

Code

Location

Referrer

} conf0;

uart_struct.h:188

hw->conf0.tick_ref_always_on = 0;

uart_ll_set_sclk()

hw->conf0.tick_ref_always_on = 1;

uart_ll_set_sclk()

switch (hw->conf0.tick_ref_always_on) {

uart_ll_get_sclk()

hw->conf0.txfifo_rst = 1;

uart_ll_txfifo_rst()

hw->conf0.txfifo_rst = 0;

uart_ll_txfifo_rst()

hw->conf0.stop_bit_num = 0x1;

uart_ll_set_stop_bits()

hw->conf0.stop_bit_num = stop_bit;

uart_ll_set_stop_bits()

if(hw->rs485_conf.dl1_en == 1 && hw->conf0.stop_bit_num == 0x1) {

uart_ll_get_stop_bits()

*stop_bit = (uart_stop_bits_t)hw->conf0.stop_bit_num;

uart_ll_get_stop_bits()

hw->conf0.parity = parity_mode & 0x1;

uart_ll_set_parity()

hw->conf0.parity_en = (parity_mode >> 1) & 0x1;

uart_ll_set_parity()

if(hw->conf0.parity_en) {

uart_ll_get_parity()

*parity_mode = (uart_parity_t)(0x2 | hw->conf0.parity);

uart_ll_get_parity()

hw->conf0.txd_brk = 1;

uart_ll_tx_break()

hw->conf0.txd_brk = 0;

uart_ll_tx_break()

hw->conf0.tx_flow_en = 1;

uart_ll_set_hw_flow_ctrl()

hw->conf0.tx_flow_en = 0;

uart_ll_set_hw_flow_ctrl()

if(hw->conf0.tx_flow_en) {

uart_ll_get_hw_flow_ctrl()

hw->conf0.bit_num = data_bit;

uart_ll_set_data_bit_num()

hw->conf0.sw_rts = level & 0x1;

uart_ll_set_rts_active_level()

hw->conf0.sw_dtr = level & 0x1;

uart_ll_set_dtr_active_level()

hw->conf0.irda_en = 0;

uart_ll_set_mode_normal()

hw->conf0.irda_en = 0;

uart_ll_set_mode_rs485_app_ctrl()

hw->conf0.sw_rts = 0;

uart_ll_set_mode_rs485_app_ctrl()

hw->conf0.irda_en = 0;

uart_ll_set_mode_rs485_app_ctrl()

hw->conf0.sw_rts = 1;

uart_ll_set_mode_rs485_half_duplex()

hw->conf0.irda_en = 0;

uart_ll_set_mode_rs485_half_duplex()

hw->conf0.irda_en = 0;

uart_ll_set_mode_collision_detect()

hw->conf0.sw_rts = 0;

uart_ll_set_mode_collision_detect()

hw->conf0.sw_rts = 0;

uart_ll_set_mode_irda()

hw->conf0.irda_en = 1;

uart_ll_set_mode_irda()

*data_bit = (uart_word_length_t)hw->conf0.bit_num;

uart_ll_get_data_bit_num()

return hw->conf0.tx_flow_en;

uart_ll_is_hw_cts_en()

hw->conf0.loopback = loop_back_en;

uart_ll_set_loop_back()

typeof(hw->conf0) conf0_reg;

uart_ll_inverse_signal()

conf0_reg.val = hw->conf0.val;

uart_ll_inverse_signal()

hw->conf0.val = conf0_reg.val;

uart_ll_inverse_signal()

if (hw->conf0.tick_ref_always_on == 0) {

uart_ll_set_rx_tout()

if (hw->conf0.tick_ref_always_on == 0) {

uart_ll_get_rx_tout_thr()

if (hw->conf0.tick_ref_always_on == 0) {

uart_ll_max_tout_thrd()

hw->conf0.err_wr_mask = discard ? 1 : 0;

uart_ll_discard_error_data()

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