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spi_dev_s struct
Syntax
struct spi_dev_s
{
union {
struct {
uint32_t reserved0: 16;
uint32_t flash_per: 1;
uint32_t flash_pes: 1;
uint32_t usr: 1;
uint32_t flash_hpm: 1;
uint32_t flash_res: 1;
uint32_t flash_dp: 1;
uint32_t flash_ce: 1;
uint32_t flash_be: 1;
uint32_t flash_se: 1;
uint32_t flash_pp: 1;
uint32_t flash_wrsr: 1;
uint32_t flash_rdsr: 1;
uint32_t flash_rdid: 1;
uint32_t flash_wrdi: 1;
uint32_t flash_wren: 1;
uint32_t flash_read: 1;
};
uint32_t val;
} cmd;
uint32_t addr;
union {
struct {
uint32_t reserved0: 10;
uint32_t fcs_crc_en: 1;
uint32_t tx_crc_en: 1;
uint32_t wait_flash_idle_en: 1;
uint32_t fastrd_mode: 1;
uint32_t fread_dual: 1;
uint32_t resandres: 1;
uint32_t reserved16: 4;
uint32_t fread_quad: 1;
uint32_t wp: 1;
uint32_t wrsr_2b: 1;
uint32_t fread_dio: 1;
uint32_t fread_qio: 1;
uint32_t rd_bit_order: 1;
uint32_t wr_bit_order: 1;
uint32_t reserved27: 5;
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t reserved0: 16;
uint32_t cs_hold_delay_res:12;
uint32_t cs_hold_delay: 4;
};
uint32_t val;
} ctrl1;
union {
struct {
uint32_t status: 16;
uint32_t wb_mode: 8;
uint32_t status_ext: 8;
};
uint32_t val;
} rd_status;
union {
struct {
uint32_t setup_time: 4;
uint32_t hold_time: 4;
uint32_t reserved8_15: 8;
uint32_t miso_delay_mode: 2;
uint32_t miso_delay_num: 3;
uint32_t mosi_delay_mode: 2;
uint32_t mosi_delay_num: 3;
uint32_t cs_delay_mode: 2;
uint32_t cs_delay_num: 4;
};
uint32_t val;
} ctrl2;
union {
struct {
uint32_t clkcnt_l: 6;
uint32_t clkcnt_h: 6;
uint32_t clkcnt_n: 6;
uint32_t clkdiv_pre: 13;
uint32_t clk_equ_sysclk: 1;
};
uint32_t val;
} clock;
union {
struct {
uint32_t doutdin: 1;
uint32_t reserved1: 3;
uint32_t cs_hold: 1;
uint32_t cs_setup: 1;
uint32_t ck_i_edge: 1;
uint32_t ck_out_edge: 1;
uint32_t reserved8: 2;
uint32_t rd_byte_order: 1;
uint32_t wr_byte_order: 1;
uint32_t fwrite_dual: 1;
uint32_t fwrite_quad: 1;
uint32_t fwrite_dio: 1;
uint32_t fwrite_qio: 1;
uint32_t sio: 1;
uint32_t usr_hold_pol: 1;
uint32_t usr_dout_hold: 1;
uint32_t usr_din_hold: 1;
uint32_t usr_dummy_hold: 1;
uint32_t usr_addr_hold: 1;
uint32_t usr_cmd_hold: 1;
uint32_t usr_prep_hold: 1;
uint32_t usr_miso_highpart: 1;
uint32_t usr_mosi_highpart: 1;
uint32_t usr_dummy_idle: 1;
uint32_t usr_mosi: 1;
uint32_t usr_miso: 1;
uint32_t usr_dummy: 1;
uint32_t usr_addr: 1;
uint32_t usr_command: 1;
};
uint32_t val;
} user;
union {
struct {
uint32_t usr_dummy_cyclelen: 8;
uint32_t reserved8: 18;
uint32_t usr_addr_bitlen: 6;
};
uint32_t val;
} user1;
union {
struct {
uint32_t usr_command_value: 16;
uint32_t reserved16: 12;
uint32_t usr_command_bitlen: 4;
};
uint32_t val;
} user2;
union {
struct {
uint32_t usr_mosi_dbitlen:24;
uint32_t reserved24: 8;
};
uint32_t val;
} mosi_dlen;
union {
struct {
uint32_t usr_miso_dbitlen:24;
uint32_t reserved24: 8;
};
uint32_t val;
} miso_dlen;
uint32_t slv_wr_status;
union {
struct {
uint32_t cs0_dis: 1;
uint32_t cs1_dis: 1;
uint32_t cs2_dis: 1;
uint32_t reserved3: 2;
uint32_t ck_dis: 1;
uint32_t master_cs_pol: 3;
uint32_t reserved9: 2;
uint32_t master_ck_sel: 3;
uint32_t reserved14: 15;
uint32_t ck_idle_edge: 1;
uint32_t cs_keep_active: 1;
uint32_t reserved31: 1;
};
uint32_t val;
} pin;
union {
struct {
uint32_t rd_buf_done: 1;
uint32_t wr_buf_done: 1;
uint32_t rd_sta_done: 1;
uint32_t wr_sta_done: 1;
uint32_t trans_done: 1;
uint32_t rd_buf_inten: 1;
uint32_t wr_buf_inten: 1;
uint32_t rd_sta_inten: 1;
uint32_t wr_sta_inten: 1;
uint32_t trans_inten: 1;
uint32_t cs_i_mode: 2;
uint32_t reserved12: 5;
uint32_t last_command: 3;
uint32_t last_state: 3;
uint32_t trans_cnt: 4;
uint32_t cmd_define: 1;
uint32_t wr_rd_sta_en: 1;
uint32_t wr_rd_buf_en: 1;
uint32_t slave_mode: 1;
uint32_t sync_reset: 1;
};
uint32_t val;
} slave;
union {
struct {
uint32_t rdbuf_dummy_en: 1;
uint32_t wrbuf_dummy_en: 1;
uint32_t rdsta_dummy_en: 1;
uint32_t wrsta_dummy_en: 1;
uint32_t wr_addr_bitlen: 6;
uint32_t rd_addr_bitlen: 6;
uint32_t reserved16: 9;
uint32_t status_readback: 1;
uint32_t status_fast_en: 1;
uint32_t status_bitlen: 5;
};
uint32_t val;
} slave1;
union {
struct {
uint32_t rdsta_dummy_cyclelen: 8;
uint32_t wrsta_dummy_cyclelen: 8;
uint32_t rdbuf_dummy_cyclelen: 8;
uint32_t wrbuf_dummy_cyclelen: 8;
};
uint32_t val;
} slave2;
union {
struct {
uint32_t rdbuf_cmd_value: 8;
uint32_t wrbuf_cmd_value: 8;
uint32_t rdsta_cmd_value: 8;
uint32_t wrsta_cmd_value: 8;
};
uint32_t val;
} slave3;
union {
struct {
uint32_t bit_len: 24;
uint32_t reserved24: 8;
};
uint32_t val;
} slv_wrbuf_dlen;
union {
struct {
uint32_t bit_len: 24;
uint32_t reserved24: 8;
};
uint32_t val;
} slv_rdbuf_dlen;
union {
struct {
uint32_t req_en: 1;
uint32_t usr_cmd_4byte: 1;
uint32_t flash_usr_cmd: 1;
uint32_t flash_pes_en: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} cache_fctrl;
union {
struct {
uint32_t reserved0: 1;
uint32_t usr_sram_dio: 1;
uint32_t usr_sram_qio: 1;
uint32_t usr_wr_sram_dummy: 1;
uint32_t usr_rd_sram_dummy: 1;
uint32_t cache_sram_usr_rcmd: 1;
uint32_t sram_bytes_len: 8;
uint32_t sram_dummy_cyclelen: 8;
uint32_t sram_addr_bitlen: 6;
uint32_t cache_sram_usr_wcmd: 1;
uint32_t reserved29: 3;
};
uint32_t val;
} cache_sctrl;
union {
struct {
uint32_t dio: 1;
uint32_t qio: 1;
uint32_t reserved2: 2;
uint32_t rst_io: 1;
uint32_t reserved5:27;
};
uint32_t val;
} sram_cmd;
union {
struct {
uint32_t usr_rd_cmd_value: 16;
uint32_t reserved16: 12;
uint32_t usr_rd_cmd_bitlen: 4;
};
uint32_t val;
} sram_drd_cmd;
union {
struct {
uint32_t usr_wr_cmd_value: 16;
uint32_t reserved16: 12;
uint32_t usr_wr_cmd_bitlen: 4;
};
uint32_t val;
} sram_dwr_cmd;
union {
struct {
uint32_t slv_rdata_bit:24;
uint32_t reserved24: 8;
};
uint32_t val;
} slv_rd_bit;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t data_buf[16];
uint32_t tx_crc;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
union {
struct {
uint32_t t_pp_time: 12;
uint32_t reserved12: 4;
uint32_t t_pp_shift: 4;
uint32_t reserved20:11;
uint32_t t_pp_ena: 1;
};
uint32_t val;
} ext0;
union {
struct {
uint32_t t_erase_time: 12;
uint32_t reserved12: 4;
uint32_t t_erase_shift: 4;
uint32_t reserved20: 11;
uint32_t t_erase_ena: 1;
};
uint32_t val;
} ext1;
union {
struct {
uint32_t st: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} ext2;
union {
struct {
uint32_t int_hold_ena: 2;
uint32_t reserved2: 30;
};
uint32_t val;
} ext3;
union {
struct {
uint32_t reserved0: 2;
uint32_t in_rst: 1;
uint32_t out_rst: 1;
uint32_t ahbm_fifo_rst: 1;
uint32_t ahbm_rst: 1;
uint32_t in_loop_test: 1;
uint32_t out_loop_test: 1;
uint32_t out_auto_wrback: 1;
uint32_t out_eof_mode: 1;
uint32_t outdscr_burst_en: 1;
uint32_t indscr_burst_en: 1;
uint32_t out_data_burst_en: 1;
uint32_t reserved13: 1;
uint32_t dma_rx_stop: 1;
uint32_t dma_tx_stop: 1;
uint32_t dma_continue: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} dma_conf;
union {
struct {
uint32_t addr: 20;
uint32_t reserved20: 8;
uint32_t stop: 1;
uint32_t start: 1;
uint32_t restart: 1;
uint32_t reserved31: 1;
};
uint32_t val;
} dma_out_link;
union {
struct {
uint32_t addr: 20;
uint32_t auto_ret: 1;
uint32_t reserved21: 7;
uint32_t stop: 1;
uint32_t start: 1;
uint32_t restart: 1;
uint32_t reserved31: 1;
};
uint32_t val;
} dma_in_link;
union {
struct {
uint32_t rx_en: 1;
uint32_t tx_en: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} dma_status;
union {
struct {
uint32_t inlink_dscr_empty: 1;
uint32_t outlink_dscr_error: 1;
uint32_t inlink_dscr_error: 1;
uint32_t in_done: 1;
uint32_t in_err_eof: 1;
uint32_t in_suc_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t out_total_eof: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} dma_int_ena;
union {
struct {
uint32_t inlink_dscr_empty: 1;
uint32_t outlink_dscr_error: 1;
uint32_t inlink_dscr_error: 1;
uint32_t in_done: 1;
uint32_t in_err_eof: 1;
uint32_t in_suc_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t out_total_eof: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} dma_int_raw;
union {
struct {
uint32_t inlink_dscr_empty: 1;
uint32_t outlink_dscr_error: 1;
uint32_t inlink_dscr_error: 1;
uint32_t in_done: 1;
uint32_t in_err_eof: 1;
uint32_t in_suc_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t out_total_eof: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} dma_int_st;
union {
struct {
uint32_t inlink_dscr_empty: 1;
uint32_t outlink_dscr_error: 1;
uint32_t inlink_dscr_error: 1;
uint32_t in_done: 1;
uint32_t in_err_eof: 1;
uint32_t in_suc_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t out_total_eof: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} dma_int_clr;
uint32_t dma_in_err_eof_des_addr;
uint32_t dma_in_suc_eof_des_addr;
uint32_t dma_inlink_dscr;
uint32_t dma_inlink_dscr_bf0;
uint32_t dma_inlink_dscr_bf1;
uint32_t dma_out_eof_bfr_des_addr;
uint32_t dma_out_eof_des_addr;
uint32_t dma_outlink_dscr;
uint32_t dma_outlink_dscr_bf0;
uint32_t dma_outlink_dscr_bf1;
uint32_t dma_rx_status;
uint32_t dma_tx_status;
uint32_t reserved_150[171];
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} date;
};
Fields
Field
Declared as
union {
struct {
uint32_t reserved0: 16;
uint32_t cs_hold_delay_res:12;
uint32_t cs_hold_delay: 4;
};
uint32_t val;
}
union {
struct {
uint32_t status: 16;
uint32_t wb_mode: 8;
uint32_t status_ext: 8;
};
uint32_t val;
}
union {
struct {
uint32_t setup_time: 4;
uint32_t hold_time: 4;
uint32_t reserved8_15: 8;
uint32_t miso_delay_mode: 2;
uint32_t miso_delay_num: 3;
uint32_t mosi_delay_mode: 2;
uint32_t mosi_delay_num: 3;
uint32_t cs_delay_mode: 2;
uint32_t cs_delay_num: 4;
};
uint32_t val;
}
union {
struct {
uint32_t clkcnt_l: 6;
uint32_t clkcnt_h: 6;
uint32_t clkcnt_n: 6;
uint32_t clkdiv_pre: 13;
uint32_t clk_equ_sysclk: 1;
};
uint32_t val;
}
union {
struct {
uint32_t reserved0: 16;
uint32_t flash_per: 1;
uint32_t flash_pes: 1;
uint32_t usr: 1;
uint32_t flash_hpm: 1;
uint32_t flash_res: 1;
uint32_t flash_dp: 1;
uint32_t flash_ce: 1;
uint32_t flash_be: 1;
uint32_t flash_se: 1;
uint32_t flash_pp: 1;
uint32_t flash_wrsr: 1;
uint32_t flash_rdsr: 1;
uint32_t flash_rdid: 1;
uint32_t flash_wrdi: 1;
uint32_t flash_wren: 1;
uint32_t flash_read: 1;
};
uint32_t val;
}
uint32_t
union {
struct {
uint32_t reserved0: 10;
uint32_t fcs_crc_en: 1;
uint32_t tx_crc_en: 1;
uint32_t wait_flash_idle_en: 1;
uint32_t fastrd_mode: 1;
uint32_t fread_dual: 1;
uint32_t resandres: 1;
uint32_t reserved16: 4;
uint32_t fread_quad: 1;
uint32_t wp: 1;
uint32_t wrsr_2b: 1;
uint32_t fread_dio: 1;
uint32_t fread_qio: 1;
uint32_t rd_bit_order: 1;
uint32_t wr_bit_order: 1;
uint32_t reserved27: 5;
};
uint32_t val;
}
union {
struct {
uint32_t doutdin: 1;
uint32_t reserved1: 3;
uint32_t cs_hold: 1;
uint32_t cs_setup: 1;
uint32_t ck_i_edge: 1;
uint32_t ck_out_edge: 1;
uint32_t reserved8: 2;
uint32_t rd_byte_order: 1;
uint32_t wr_byte_order: 1;
uint32_t fwrite_dual: 1;
uint32_t fwrite_quad: 1;
uint32_t fwrite_dio: 1;
uint32_t fwrite_qio: 1;
uint32_t sio: 1;
uint32_t usr_hold_pol: 1;
uint32_t usr_dout_hold: 1;
uint32_t usr_din_hold: 1;
uint32_t usr_dummy_hold: 1;
uint32_t usr_addr_hold: 1;
uint32_t usr_cmd_hold: 1;
uint32_t usr_prep_hold: 1;
uint32_t usr_miso_highpart: 1;
uint32_t usr_mosi_highpart: 1;
uint32_t usr_dummy_idle: 1;
uint32_t usr_mosi: 1;
uint32_t usr_miso: 1;
uint32_t usr_dummy: 1;
uint32_t usr_addr: 1;
uint32_t usr_command: 1;
};
uint32_t val;
}
union {
struct {
uint32_t usr_dummy_cyclelen: 8;
uint32_t reserved8: 18;
uint32_t usr_addr_bitlen: 6;
};
uint32_t val;
}
union {
struct {
uint32_t usr_command_value: 16;
uint32_t reserved16: 12;
uint32_t usr_command_bitlen: 4;
};
uint32_t val;
}
uint32_t
union {
struct {
uint32_t cs0_dis: 1;
uint32_t cs1_dis: 1;
uint32_t cs2_dis: 1;
uint32_t reserved3: 2;
uint32_t ck_dis: 1;
uint32_t master_cs_pol: 3;
uint32_t reserved9: 2;
uint32_t master_ck_sel: 3;
uint32_t reserved14: 15;
uint32_t ck_idle_edge: 1;
uint32_t cs_keep_active: 1;
uint32_t reserved31: 1;
};
uint32_t val;
}
union {
struct {
uint32_t rd_buf_done: 1;
uint32_t wr_buf_done: 1;
uint32_t rd_sta_done: 1;
uint32_t wr_sta_done: 1;
uint32_t trans_done: 1;
uint32_t rd_buf_inten: 1;
uint32_t wr_buf_inten: 1;
uint32_t rd_sta_inten: 1;
uint32_t wr_sta_inten: 1;
uint32_t trans_inten: 1;
uint32_t cs_i_mode: 2;
uint32_t reserved12: 5;
uint32_t last_command: 3;
uint32_t last_state: 3;
uint32_t trans_cnt: 4;
uint32_t cmd_define: 1;
uint32_t wr_rd_sta_en: 1;
uint32_t wr_rd_buf_en: 1;
uint32_t slave_mode: 1;
uint32_t sync_reset: 1;
};
uint32_t val;
}
union {
struct {
uint32_t rdbuf_dummy_en: 1;
uint32_t wrbuf_dummy_en: 1;
uint32_t rdsta_dummy_en: 1;
uint32_t wrsta_dummy_en: 1;
uint32_t wr_addr_bitlen: 6;
uint32_t rd_addr_bitlen: 6;
uint32_t reserved16: 9;
uint32_t status_readback: 1;
uint32_t status_fast_en: 1;
uint32_t status_bitlen: 5;
};
uint32_t val;
}
union {
struct {
uint32_t rdsta_dummy_cyclelen: 8;
uint32_t wrsta_dummy_cyclelen: 8;
uint32_t rdbuf_dummy_cyclelen: 8;
uint32_t wrbuf_dummy_cyclelen: 8;
};
uint32_t val;
}
union {
struct {
uint32_t rdbuf_cmd_value: 8;
uint32_t wrbuf_cmd_value: 8;
uint32_t rdsta_cmd_value: 8;
uint32_t wrsta_cmd_value: 8;
};
uint32_t val;
}
uint32_t
uint32_t
uint32_t[16]
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
union {
struct {
uint32_t t_pp_time: 12;
uint32_t reserved12: 4;
uint32_t t_pp_shift: 4;
uint32_t reserved20:11;
uint32_t t_pp_ena: 1;
};
uint32_t val;
}
union {
struct {
uint32_t t_erase_time: 12;
uint32_t reserved12: 4;
uint32_t t_erase_shift: 4;
uint32_t reserved20: 11;
uint32_t t_erase_ena: 1;
};
uint32_t val;
}
union {
struct {
uint32_t addr: 20;
uint32_t reserved20: 8;
uint32_t stop: 1;
uint32_t start: 1;
uint32_t restart: 1;
uint32_t reserved31: 1;
};
uint32_t val;
}
union {
struct {
uint32_t addr: 20;
uint32_t auto_ret: 1;
uint32_t reserved21: 7;
uint32_t stop: 1;
uint32_t start: 1;
uint32_t restart: 1;
uint32_t reserved31: 1;
};
uint32_t val;
}
union {
struct {
uint32_t reserved0: 1;
uint32_t usr_sram_dio: 1;
uint32_t usr_sram_qio: 1;
uint32_t usr_wr_sram_dummy: 1;
uint32_t usr_rd_sram_dummy: 1;
uint32_t cache_sram_usr_rcmd: 1;
uint32_t sram_bytes_len: 8;
uint32_t sram_dummy_cyclelen: 8;
uint32_t sram_addr_bitlen: 6;
uint32_t cache_sram_usr_wcmd: 1;
uint32_t reserved29: 3;
};
uint32_t val;
}
union {
struct {
uint32_t usr_rd_cmd_value: 16;
uint32_t reserved16: 12;
uint32_t usr_rd_cmd_bitlen: 4;
};
uint32_t val;
}
union {
struct {
uint32_t usr_wr_cmd_value: 16;
uint32_t reserved16: 12;
uint32_t usr_wr_cmd_bitlen: 4;
};
uint32_t val;
}
uint32_t
uint32_t
uint32_t
uint32_t
union {
struct {
uint32_t req_en: 1;
uint32_t usr_cmd_4byte: 1;
uint32_t flash_usr_cmd: 1;
uint32_t flash_pes_en: 1;
uint32_t reserved4: 28;
};
uint32_t val;
}
union {
struct {
uint32_t reserved0: 2;
uint32_t in_rst: 1;
uint32_t out_rst: 1;
uint32_t ahbm_fifo_rst: 1;
uint32_t ahbm_rst: 1;
uint32_t in_loop_test: 1;
uint32_t out_loop_test: 1;
uint32_t out_auto_wrback: 1;
uint32_t out_eof_mode: 1;
uint32_t outdscr_burst_en: 1;
uint32_t indscr_burst_en: 1;
uint32_t out_data_burst_en: 1;
uint32_t reserved13: 1;
uint32_t dma_rx_stop: 1;
uint32_t dma_tx_stop: 1;
uint32_t dma_continue: 1;
uint32_t reserved17: 15;
};
uint32_t val;
}
union {
struct {
uint32_t inlink_dscr_empty: 1;
uint32_t outlink_dscr_error: 1;
uint32_t inlink_dscr_error: 1;
uint32_t in_done: 1;
uint32_t in_err_eof: 1;
uint32_t in_suc_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t out_total_eof: 1;
uint32_t reserved9: 23;
};
uint32_t val;
}
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t[171]
union {
struct {
uint32_t inlink_dscr_empty: 1;
uint32_t outlink_dscr_error: 1;
uint32_t inlink_dscr_error: 1;
uint32_t in_done: 1;
uint32_t in_err_eof: 1;
uint32_t in_suc_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t out_total_eof: 1;
uint32_t reserved9: 23;
};
uint32_t val;
}
union {
struct {
uint32_t inlink_dscr_empty: 1;
uint32_t outlink_dscr_error: 1;
uint32_t inlink_dscr_error: 1;
uint32_t in_done: 1;
uint32_t in_err_eof: 1;
uint32_t in_suc_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t out_total_eof: 1;
uint32_t reserved9: 23;
};
uint32_t val;
}
union {
struct {
uint32_t inlink_dscr_empty: 1;
uint32_t outlink_dscr_error: 1;
uint32_t inlink_dscr_error: 1;
uint32_t in_done: 1;
uint32_t in_err_eof: 1;
uint32_t in_suc_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t out_total_eof: 1;
uint32_t reserved9: 23;
};
uint32_t val;
}
Related Functions
Found 98 other functions taking a spi_dev_s
argument:
Function
Description
Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write...
Set the input length, in bits.
Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases, should be configured before this is called.
Set the data to be written in the data buffer.
Get the read data from the buffer after ``spi_flash_ll_read`` is done.
Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write...
Set the length of dummy cycles.
Set the output length, in bits (not including command, address and dummy phases)
Set the command.
Set the address to send in user command mode. Should be called before commands that requires the address e.g. erase sector, read, write...
Enable/Disable RX DMA (Peripherals->DMA->RAM)
Clear the trans_done interrupt.
Set the trans_done interrupt.
Check whether the previous operation is done.
Check whether the host is idle to perform new commands.
Check whether user-defined transaction is done.
Apply the register configurations and wait until it's done
Trigger start of user-defined transaction.
Reset SPI DMA TX FIFO On ESP32, this function is not separated
Reset SPI DMA RX FIFO On ESP32, this function is not separated
Clear in fifo full error
Clear out fifo empty error
Enable/Disable TX DMA (RAM->DMA->Peripherals)
Write to SPI buffer.
Read from SPI buffer.
Enable/disable the LSBFIRST feature for TX data.
Enable/disable the LSBFIRST feature for RX data.
Set the clock for master by stored value.
Set the input length (master).
Enable/disable the RX data phase.
Enable/disable the TX data phase.
Enable the trans_done interrupt.
Enable/Disable miso/mosi signals on peripheral side
Prepare tx hardware for a new DMA trans
Prepare tx hardware for a new DMA trans
Prepare rx hardware for a new DMA trans
Prepare tx hardware for a new DMA trans
Reset peripheral registers before configuration and starting control
Select which pin to use for the flash
Program a page of the flash chip. Call ``spi_flash_ll_set_address`` before this to set the address to program.
Set the read io mode.
Set clock frequency to work at.
Erase the flash chip.
Erase the sector, the address should be set by spi_flash_ll_set_address.
Erase the block, the address should be set by spi_flash_ll_set_address.
Enable/disable write protection for the flash chip.
Set extra address for bits M0-M7 in DIO/QIO mode.
Write protect signal output when SPI is idle
Get the ctrl value of mspi
Get the address length that is set in register, in bits.
Get common command related registers
Set common command related registers
Initialize SPI peripheral (slave).
Get current running command bit-mask. (Preview)
Reset SPI CPU TX FIFO
Reset SPI DMA FIFO
Enable/disable the postive-cs feature.
Set SPI mode for the peripheral as master.
Set SPI mode for the peripheral as slave.
Set SPI to work in full duplex or half duplex mode.
Set SPI to work in SIO mode or not. SIO is a mode which MOSI and MISO share a line. The device MUST work in half-duplexmode.
Configure the SPI transaction line mode for the master to use.
Select one of the CS to use in current transaction.
Keep Chip Select activated after the current transaction.
Set the standard clock mode for master.
Enable/disable the CK sel feature for a CS pin. CK sel is a feature to toggle the CS line along with the clock.
Set the mosi delay after the output edge to the signal. (Preview) The delay mode/num is a Espressif conception, may change in the new chips.
Set the miso delay applied to the input signal before the internal peripheral. (Preview) The delay mode/num is a Espressif conception, may change in the new chips.
Set dummy clocks to output before RX phase (master), or clocks to skip before the data phase and after the address phase (slave). Note this phase is also used to compensate RX timing in half duplex mode.
Set the delay of SPI clocks before the CS inactive edge after the last SPI clock.
Set the delay of SPI clocks before the first SPI clock after the CS active edge. Note ESP32 doesn't support to use this feature when command/address phases are used in full duplex mode.
Set the output length (master).
Set the maximum input length (slave).
Set the maximum output length (slave).
Set the length of command phase. When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit command phases takes 4 cycles in 4-bit mode.
Set the length of address phase. When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit address phases takes 4 cycles in 4-bit mode.
Set the address value in an intuitive way. The length and lsbfirst is required to shift and swap the address to the right place.
Set the command value in an intuitive way. The length and lsbfirst is required to shift and swap the command to the right place.
Reset the slave peripheral before next transaction.
Get the received bit length of the slave.
Disable the trans_done interrupt.
Reset RX DMA which stores the data received from a peripheral into RAM.
Start RX DMA.
Enable DMA RX channel burst for data
Enable DMA RX channel burst for descriptor
Reset TX DMA which transmits the data from RAM to a peripheral.
Start TX DMA.
Enable DMA TX channel burst for data
Enable DMA TX channel burst for descriptor
Select SPI peripheral clock source (master).
Initialize SPI peripheral (master).
Write a word to the data buffer.
Configuration of RX DMA EOF interrupt generation way
Calculate and set clock for SPI master according to desired parameters. This takes long, suggest to calculate the configuration during initialization by ``spi_ll_master_cal_clock`` and store the result, then configure the clock by stored value when used by ``spi_ll_msater_set_clock_by_reg``.
Configuration of OUT EOF flag generation way
Enable automatic outlink-writeback