spi_ll_infifo_full_clr() function

Beginning address of the peripheral registers.

Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write...

Set the input length, in bits.

Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases, should be configured before this is called.

Set the data to be written in the data buffer.

Get the read data from the buffer after ``spi_flash_ll_read`` is done.

Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write...

Set the length of dummy cycles.

Set the output length, in bits (not including command, address and dummy phases)

Set the command.

Set the address to send in user command mode. Should be called before commands that requires the address e.g. erase sector, read, write...

Enable/Disable RX DMA (Peripherals->DMA->RAM)

Clear the trans_done interrupt.

Set the trans_done interrupt.

Check whether the previous operation is done.

Check whether the host is idle to perform new commands.

Check whether user-defined transaction is done.

Apply the register configurations and wait until it's done

Trigger start of user-defined transaction.

Reset SPI DMA TX FIFO On ESP32, this function is not separated

Reset SPI DMA RX FIFO On ESP32, this function is not separated

Clear out fifo empty error

Enable/Disable TX DMA (RAM->DMA->Peripherals)

Write to SPI buffer.

Read from SPI buffer.

Enable/disable the LSBFIRST feature for TX data.

Enable/disable the LSBFIRST feature for RX data.

Set the clock for master by stored value.

Set the input length (master).

Enable/disable the RX data phase.

Enable/disable the TX data phase.

Enable the trans_done interrupt.

Enable/Disable miso/mosi signals on peripheral side

Prepare tx hardware for a new DMA trans

Prepare tx hardware for a new DMA trans

Prepare rx hardware for a new DMA trans

Prepare tx hardware for a new DMA trans

Reset peripheral registers before configuration and starting control

Select which pin to use for the flash

Program a page of the flash chip. Call ``spi_flash_ll_set_address`` before this to set the address to program.

Set the read io mode.

Set clock frequency to work at.

Erase the flash chip.

Erase the sector, the address should be set by spi_flash_ll_set_address.

Erase the block, the address should be set by spi_flash_ll_set_address.

Enable/disable write protection for the flash chip.

Set extra address for bits M0-M7 in DIO/QIO mode.

Write protect signal output when SPI is idle

Get the ctrl value of mspi

Get the address length that is set in register, in bits.

Get common command related registers

Set common command related registers

Initialize SPI peripheral (slave).

Get current running command bit-mask. (Preview)

Reset SPI CPU TX FIFO

Reset SPI DMA FIFO

Enable/disable the postive-cs feature.

Set SPI mode for the peripheral as master.

Set SPI mode for the peripheral as slave.

Set SPI to work in full duplex or half duplex mode.

Set SPI to work in SIO mode or not. SIO is a mode which MOSI and MISO share a line. The device MUST work in half-duplexmode.

Configure the SPI transaction line mode for the master to use.

Select one of the CS to use in current transaction.

Keep Chip Select activated after the current transaction.

Set the standard clock mode for master.

Enable/disable the CK sel feature for a CS pin. CK sel is a feature to toggle the CS line along with the clock.

Set the mosi delay after the output edge to the signal. (Preview) The delay mode/num is a Espressif conception, may change in the new chips.

Set the miso delay applied to the input signal before the internal peripheral. (Preview) The delay mode/num is a Espressif conception, may change in the new chips.

Set dummy clocks to output before RX phase (master), or clocks to skip before the data phase and after the address phase (slave). Note this phase is also used to compensate RX timing in half duplex mode.

Set the delay of SPI clocks before the CS inactive edge after the last SPI clock.

Set the delay of SPI clocks before the first SPI clock after the CS active edge. Note ESP32 doesn't support to use this feature when command/address phases are used in full duplex mode.

Set the output length (master).

Set the maximum input length (slave).

Set the maximum output length (slave).

Set the length of command phase. When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit command phases takes 4 cycles in 4-bit mode.

Set the length of address phase. When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit address phases takes 4 cycles in 4-bit mode.

Set the address value in an intuitive way. The length and lsbfirst is required to shift and swap the address to the right place.

Set the command value in an intuitive way. The length and lsbfirst is required to shift and swap the command to the right place.

Reset the slave peripheral before next transaction.

Get the received bit length of the slave.

Disable the trans_done interrupt.

Reset RX DMA which stores the data received from a peripheral into RAM.

Start RX DMA.

Enable DMA RX channel burst for data

Enable DMA RX channel burst for descriptor

Reset TX DMA which transmits the data from RAM to a peripheral.

Start TX DMA.

Enable DMA TX channel burst for data

Enable DMA TX channel burst for descriptor

Select SPI peripheral clock source (master).

Initialize SPI peripheral (master).

Write a word to the data buffer.

Configuration of RX DMA EOF interrupt generation way

Calculate and set clock for SPI master according to desired parameters. This takes long, suggest to calculate the configuration during initialization by ``spi_ll_master_cal_clock`` and store the result, then configure the clock by stored value when used by ``spi_ll_msater_set_clock_by_reg``.

Configuration of OUT EOF flag generation way

Enable automatic outlink-writeback