spi_dev_s::::::usr_wr_cmd_bitlen field

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from spi_struct.h:302

uint32_t usr_wr_cmd_bitlen: 4;

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uint32_t usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/

spi_struct.h:302

spi_dev_s::::::usr_wr_cmd_bitlen field

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