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rmt_dev_t struct
Syntax
Implemented in ![]()
rmt_struct.h:14
Fields
Field
Declared as
volatile uint32_t[8]
volatile struct {
union {
struct {
uint32_t div_cnt: 8;
uint32_t idle_thres: 16;
uint32_t mem_size: 4;
uint32_t carrier_en: 1;
uint32_t carrier_out_lv: 1;
uint32_t mem_pd: 1;
uint32_t clk_en: 1;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t tx_start: 1;
uint32_t rx_en: 1;
uint32_t mem_wr_rst: 1;
uint32_t mem_rd_rst: 1;
uint32_t apb_mem_rst: 1;
uint32_t mem_owner: 1;
uint32_t tx_conti_mode: 1;
uint32_t rx_filter_en: 1;
uint32_t rx_filter_thres: 8;
uint32_t ref_cnt_rst: 1;
uint32_t ref_always_on: 1;
uint32_t idle_out_lv: 1;
uint32_t idle_out_en: 1;
uint32_t reserved20: 12;
};
uint32_t val;
} conf1;
}[8]
volatile uint32_t[8]
volatile uint32_t[8]
volatile union {
struct {
uint32_t ch0_tx_end: 1;
uint32_t ch0_rx_end: 1;
uint32_t ch0_err: 1;
uint32_t ch1_tx_end: 1;
uint32_t ch1_rx_end: 1;
uint32_t ch1_err: 1;
uint32_t ch2_tx_end: 1;
uint32_t ch2_rx_end: 1;
uint32_t ch2_err: 1;
uint32_t ch3_tx_end: 1;
uint32_t ch3_rx_end: 1;
uint32_t ch3_err: 1;
uint32_t ch4_tx_end: 1;
uint32_t ch4_rx_end: 1;
uint32_t ch4_err: 1;
uint32_t ch5_tx_end: 1;
uint32_t ch5_rx_end: 1;
uint32_t ch5_err: 1;
uint32_t ch6_tx_end: 1;
uint32_t ch6_rx_end: 1;
uint32_t ch6_err: 1;
uint32_t ch7_tx_end: 1;
uint32_t ch7_rx_end: 1;
uint32_t ch7_err: 1;
uint32_t ch0_tx_thr_event: 1;
uint32_t ch1_tx_thr_event: 1;
uint32_t ch2_tx_thr_event: 1;
uint32_t ch3_tx_thr_event: 1;
uint32_t ch4_tx_thr_event: 1;
uint32_t ch5_tx_thr_event: 1;
uint32_t ch6_tx_thr_event: 1;
uint32_t ch7_tx_thr_event: 1;
};
uint32_t val;
}
volatile union {
struct {
uint32_t ch0_tx_end: 1;
uint32_t ch0_rx_end: 1;
uint32_t ch0_err: 1;
uint32_t ch1_tx_end: 1;
uint32_t ch1_rx_end: 1;
uint32_t ch1_err: 1;
uint32_t ch2_tx_end: 1;
uint32_t ch2_rx_end: 1;
uint32_t ch2_err: 1;
uint32_t ch3_tx_end: 1;
uint32_t ch3_rx_end: 1;
uint32_t ch3_err: 1;
uint32_t ch4_tx_end: 1;
uint32_t ch4_rx_end: 1;
uint32_t ch4_err: 1;
uint32_t ch5_tx_end: 1;
uint32_t ch5_rx_end: 1;
uint32_t ch5_err: 1;
uint32_t ch6_tx_end: 1;
uint32_t ch6_rx_end: 1;
uint32_t ch6_err: 1;
uint32_t ch7_tx_end: 1;
uint32_t ch7_rx_end: 1;
uint32_t ch7_err: 1;
uint32_t ch0_tx_thr_event: 1;
uint32_t ch1_tx_thr_event: 1;
uint32_t ch2_tx_thr_event: 1;
uint32_t ch3_tx_thr_event: 1;
uint32_t ch4_tx_thr_event: 1;
uint32_t ch5_tx_thr_event: 1;
uint32_t ch6_tx_thr_event: 1;
uint32_t ch7_tx_thr_event: 1;
};
uint32_t val;
}
volatile union {
struct {
uint32_t ch0_tx_end: 1;
uint32_t ch0_rx_end: 1;
uint32_t ch0_err: 1;
uint32_t ch1_tx_end: 1;
uint32_t ch1_rx_end: 1;
uint32_t ch1_err: 1;
uint32_t ch2_tx_end: 1;
uint32_t ch2_rx_end: 1;
uint32_t ch2_err: 1;
uint32_t ch3_tx_end: 1;
uint32_t ch3_rx_end: 1;
uint32_t ch3_err: 1;
uint32_t ch4_tx_end: 1;
uint32_t ch4_rx_end: 1;
uint32_t ch4_err: 1;
uint32_t ch5_tx_end: 1;
uint32_t ch5_rx_end: 1;
uint32_t ch5_err: 1;
uint32_t ch6_tx_end: 1;
uint32_t ch6_rx_end: 1;
uint32_t ch6_err: 1;
uint32_t ch7_tx_end: 1;
uint32_t ch7_rx_end: 1;
uint32_t ch7_err: 1;
uint32_t ch0_tx_thr_event: 1;
uint32_t ch1_tx_thr_event: 1;
uint32_t ch2_tx_thr_event: 1;
uint32_t ch3_tx_thr_event: 1;
uint32_t ch4_tx_thr_event: 1;
uint32_t ch5_tx_thr_event: 1;
uint32_t ch6_tx_thr_event: 1;
uint32_t ch7_tx_thr_event: 1;
};
uint32_t val;
}
volatile union {
struct {
uint32_t ch0_tx_end: 1;
uint32_t ch0_rx_end: 1;
uint32_t ch0_err: 1;
uint32_t ch1_tx_end: 1;
uint32_t ch1_rx_end: 1;
uint32_t ch1_err: 1;
uint32_t ch2_tx_end: 1;
uint32_t ch2_rx_end: 1;
uint32_t ch2_err: 1;
uint32_t ch3_tx_end: 1;
uint32_t ch3_rx_end: 1;
uint32_t ch3_err: 1;
uint32_t ch4_tx_end: 1;
uint32_t ch4_rx_end: 1;
uint32_t ch4_err: 1;
uint32_t ch5_tx_end: 1;
uint32_t ch5_rx_end: 1;
uint32_t ch5_err: 1;
uint32_t ch6_tx_end: 1;
uint32_t ch6_rx_end: 1;
uint32_t ch6_err: 1;
uint32_t ch7_tx_end: 1;
uint32_t ch7_rx_end: 1;
uint32_t ch7_err: 1;
uint32_t ch0_tx_thr_event: 1;
uint32_t ch1_tx_thr_event: 1;
uint32_t ch2_tx_thr_event: 1;
uint32_t ch3_tx_thr_event: 1;
uint32_t ch4_tx_thr_event: 1;
uint32_t ch5_tx_thr_event: 1;
uint32_t ch6_tx_thr_event: 1;
uint32_t ch7_tx_thr_event: 1;
};
uint32_t val;
}
volatile union {
struct {
uint32_t fifo_mask: 1;
uint32_t mem_tx_wrap_en: 1;
uint32_t reserved2: 30;
};
uint32_t val;
}
uint32_t
uint32_t
volatile uint32_t
Related Functions
Found 55 other functions taking a rmt_dev_t
argument:
Function
Description
Enable RMT interrupt for specific event mask
Clear RMT interrupt status by mask
Reset RMT writing pointer for RX channel
Reset RMT reading pointer for TX channel
Enable receiving for RX channel
Set RMT memory owner for RX channel
Enable transmitting in a loop
Fix the output level when TX channel is in IDLE state
Enable modulating carrier signal to TX channel
Set on high or low to modulate the carrier signal
Set clock source and divider for RMT channel group
Enable RMT peripheral source clock
Set TX channel clock divider
Force power off the RMT memory block, regardless of the outside PMU logic
Power control the RMT memory block by the outside PMU logic
Set high and low duration of carrier signal
Set RX channel clock divider
Set memory block number for TX channel
Set RX channel filter threshold (i.e. the maximum width of one pulse signal that would be treated as a noise)
Set memory block number for RX channel
Set the time length for RX channel before going into IDLE state
Enable filter for RX channel
Enable APB accessing RMT memory in nonfifo mode
Enable TX wrap
Set the amount of RMT symbols that can trigger the limitation interrupt
Start transmitting for TX channel
Get RMT memory write cursor offset
Get interrupt status register address
Reset clock divider for TX channels by mask
Reset clock divider for RX channels by mask
Get interrupt status for TX channel
Get interrupt raw status for TX channel
Get interrupt raw status for RX channel
Get interrupt status for RX channel
Enable clock gate for register and memory
Force power on the RMT memory block, regardless of the outside PMU logic
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