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SourceVuESP-IDF Framework and ExamplesESP-IDFrmt_dev_t::conf_ch

rmt_dev_t::conf_ch field

Syntax

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Summary

Declaration

from rmt_struct.h:18

volatile struct { union { struct { uint32_t div_cnt: 8; uint32_t idle_thres: 16; uint32_t mem_size: 4; uint32_t carrier_en: 1; uint32_t carrier_out_lv: 1; uint32_t mem_pd: 1; uint32_t clk_en: 1; }; uint32_t val; } conf0; union { struct { uint32_t tx_start: 1; uint32_t rx_en: 1; uint32_t mem_wr_rst: 1; uint32_t mem_rd_rst: 1; uint32_t apb_mem_rst: 1; uint32_t mem_owner: 1; uint32_t tx_conti_mode: 1; uint32_t rx_filter_en: 1; uint32_t rx_filter_thres: 8; uint32_t ref_cnt_rst: 1; uint32_t ref_always_on: 1; uint32_t idle_out_lv: 1; uint32_t idle_out_en: 1; uint32_t reserved20: 12; }; uint32_t val; } conf1; } conf_ch[8];

References

Code

Location

Referrer

} conf_ch[8];

rmt_struct.h:50

dev->conf_ch[0].conf0.clk_en = enable; // register clock gating

rmt_ll_enable_periph_clock()

dev->conf_ch[0].conf0.mem_pd = 1;

rmt_ll_mem_force_power_off()

dev->conf_ch[0].conf0.mem_pd = 0;

rmt_ll_mem_power_by_pmu()

dev->conf_ch[channel].conf1.ref_always_on = 1;

rmt_ll_set_group_clock_src()

dev->conf_ch[channel].conf1.ref_always_on = 0;

rmt_ll_set_group_clock_src()

dev->conf_ch[i].conf1.ref_cnt_rst = 1;

rmt_ll_tx_reset_channels_clock_div()

HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);

rmt_ll_tx_set_channel_clock_div()

dev->conf_ch[channel].conf1.mem_rd_rst = 1;

rmt_ll_tx_reset_pointer()

dev->conf_ch[channel].conf1.mem_rd_rst = 0;

rmt_ll_tx_reset_pointer()

dev->conf_ch[channel].conf1.apb_mem_rst = 1;

rmt_ll_tx_reset_pointer()

dev->conf_ch[channel].conf1.apb_mem_rst = 0;

rmt_ll_tx_reset_pointer()

dev->conf_ch[channel].conf1.tx_start = 1;

rmt_ll_tx_start()

dev->conf_ch[channel].conf0.mem_size = block_num;

rmt_ll_tx_set_mem_blocks()

dev->conf_ch[channel].conf1.tx_conti_mode = enable;

rmt_ll_tx_enable_loop()

dev->conf_ch[channel].conf1.idle_out_en = enable;

rmt_ll_tx_fix_idle_level()

dev->conf_ch[channel].conf1.idle_out_lv = level;

rmt_ll_tx_fix_idle_level()

dev->conf_ch[channel].conf0.carrier_en = enable;

rmt_ll_tx_enable_carrier_modulation()

dev->conf_ch[channel].conf0.carrier_out_lv = level;

rmt_ll_tx_set_carrier_level()

dev->conf_ch[i].conf1.ref_cnt_rst = 1;

rmt_ll_rx_reset_channels_clock_div()

HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);

rmt_ll_rx_set_channel_clock_div()

dev->conf_ch[channel].conf1.mem_wr_rst = 1;

rmt_ll_rx_reset_pointer()

dev->conf_ch[channel].conf1.mem_wr_rst = 0;

rmt_ll_rx_reset_pointer()

dev->conf_ch[channel].conf1.apb_mem_rst = 1;

rmt_ll_rx_reset_pointer()

dev->conf_ch[channel].conf1.apb_mem_rst = 0;

rmt_ll_rx_reset_pointer()

dev->conf_ch[channel].conf1.rx_en = enable;

rmt_ll_rx_enable()

dev->conf_ch[channel].conf0.mem_size = block_num;

rmt_ll_rx_set_mem_blocks()

HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres, thres);

rmt_ll_rx_set_idle_thres()

dev->conf_ch[channel].conf1.mem_owner = owner;

rmt_ll_rx_set_mem_owner()

dev->conf_ch[channel].conf1.rx_filter_en = enable;

rmt_ll_rx_enable_filter()

HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf1, rx_filter_thres, thres);

rmt_ll_rx_set_filter_thres()

uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);

rmt_ll_tx_get_channel_clock_div()

uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);

rmt_ll_rx_get_channel_clock_div()

return HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres);

rmt_ll_rx_get_idle_thres()

return dev->conf_ch[channel].conf0.mem_size;

rmt_ll_tx_get_mem_blocks()

return dev->conf_ch[channel].conf0.mem_size;

rmt_ll_rx_get_mem_blocks()

return dev->conf_ch[channel].conf1.tx_conti_mode;

rmt_ll_tx_is_loop_enabled()

if (dev->conf_ch[channel].conf1.ref_always_on) {

rmt_ll_get_group_clock_src()

return dev->conf_ch[channel].conf1.idle_out_en;

rmt_ll_tx_is_idle_enabled()

return dev->conf_ch[channel].conf1.idle_out_lv;

rmt_ll_tx_get_idle_level()

return dev->conf_ch[0].conf0.mem_pd;

rmt_ll_is_mem_force_powered_down()

return dev->conf_ch[channel].conf1.mem_owner;

rmt_ll_rx_get_mem_owner()

Call Tree

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Data Use

rmt_dev_t::conf_ch is read by 33 functions:

rmt_dev_t::conf_ch

rmt_ll_enable_periph_clock()

rmt_ll_mem_force_power_off()

rmt_ll_mem_power_by_pmu()

rmt_ll_set_group_clock_src()

rmt_ll_tx_reset_channels_clock_div()

rmt_ll_tx_set_channel_clock_div()

rmt_ll_tx_reset_pointer()

rmt_ll_tx_start()

rmt_ll_tx_set_mem_blocks()

rmt_ll_tx_enable_loop()

rmt_ll_tx_fix_idle_level()

rmt_ll_tx_enable_carrier_modulation()

rmt_ll_tx_set_carrier_level()

rmt_ll_rx_reset_channels_clock_div()

rmt_ll_rx_set_channel_clock_div()

rmt_ll_rx_reset_pointer()

rmt_ll_rx_enable()

rmt_ll_rx_set_mem_blocks()

rmt_ll_rx_set_idle_thres()

rmt_ll_rx_set_mem_owner()

rmt_ll_rx_enable_filter()

rmt_ll_rx_set_filter_thres()

rmt_ll_tx_get_channel_clock_div()

rmt_ll_rx_get_channel_clock_div()

rmt_ll_rx_get_idle_thres()

rmt_ll_tx_get_mem_blocks()

rmt_ll_rx_get_mem_blocks()

rmt_ll_tx_is_loop_enabled()

rmt_ll_get_group_clock_src()

rmt_ll_tx_is_idle_enabled()

rmt_ll_tx_get_idle_level()

rmt_ll_is_mem_force_powered_down()

rmt_ll_rx_get_mem_owner()

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