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SourceVuESP-IDF Framework and ExamplesESP-IDFclk_ll_ref_tick_set_divider()

clk_ll_ref_tick_set_divider() function

Set REF_TICK divider to make REF_TICK frequency at 1MHz Divider = APB_CLK freq in Hz / 1MHz. Value in register = divider - 1.

Syntax

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Summary

Declaration

from clk_tree_ll.h:679

static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(soc_cpu_clk_src_t cpu_clk_src, uint32_t cpu_freq_mhz);

Arguments

Argument

Description

cpu_clk_src

Selected CPU clock source (one of soc_cpu_clk_src_t values)

cpu_freq_mhz

CPU frequency value, in MHz

References

Code

Location

Referrer

static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(soc_cpu_clk_src_t cpu_clk_src, uint32_t cpu_freq_mhz)

clk_tree_ll.h:679

clk_ll_ref_tick_set_divider(SOC_CPU_CLK_SRC_XTAL, cpu_freq);

rtc_clk.c:369

rtc_clk_cpu_freq_to_xtal()

clk_ll_ref_tick_set_divider(SOC_CPU_CLK_SRC_RC_FAST, 8);

rtc_clk.c:384

rtc_clk_cpu_freq_to_8m()

clk_ll_ref_tick_set_divider(SOC_CPU_CLK_SRC_PLL, cpu_freq_mhz);

rtc_clk.c:401

rtc_clk_cpu_freq_to_pll_mhz()

clk_ll_ref_tick_set_divider(SOC_CPU_CLK_SRC_XTAL, xtal_freq);

rtc_clk_init.c:119

rtc_clk_init()

clk_ll_ref_tick_set_divider(SOC_CPU_CLK_SRC_PLL, new_config.freq_mhz);

rtc_clk_init.c:120

rtc_clk_init()

Call Tree

clk_ll_ref_tick_set_divider() is called by 4 functions and calls 2 functions:

rtc_clk_cpu_freq_to_xtal()

rtc_clk_cpu_freq_to_8m()

rtc_clk_cpu_freq_to_pll_mhz()

rtc_clk_init()

clk_ll_ref_tick_set_divider()

__assert_func()

abort()

Data Use

clk_ll_ref_tick_set_divider() reads 4 variables:

soc_cpu_clk_src_t::SOC_CPU_CLK_SRC_PLL

soc_cpu_clk_src_t::SOC_CPU_CLK_SRC_RC_FAST

soc_cpu_clk_src_t::SOC_CPU_CLK_SRC_APLL

soc_cpu_clk_src_t::SOC_CPU_CLK_SRC_XTAL

clk_ll_ref_tick_set_divider()

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