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Summary Syntax Values References

SourceVuESP-IDF Framework and ExamplesESP-IDFsoc_cpu_clk_src_t

soc_cpu_clk_src_t enum

Syntax

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Summary

Declaration

from clk_tree_defs.h:64

enum { SOC_CPU_CLK_SRC_XTAL = 0, SOC_CPU_CLK_SRC_PLL = 1, SOC_CPU_CLK_SRC_RC_FAST = 2, SOC_CPU_CLK_SRC_APLL = 3, SOC_CPU_CLK_SRC_INVALID, };

Values

Value

Declared as

Description

soc_cpu_clk_src_t::SOC_CPU_CLK_SRC_PLL

= 1

Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz).

soc_cpu_clk_src_t::SOC_CPU_CLK_SRC_RC_FAST

= 2

Select RC_FAST_CLK as CPU_CLK source.

soc_cpu_clk_src_t::SOC_CPU_CLK_SRC_APLL

= 3

Select APLL_CLK as CPU_CLK source.

soc_cpu_clk_src_t::SOC_CPU_CLK_SRC_INVALID

Invalid CPU_CLK source.

soc_cpu_clk_src_t::SOC_CPU_CLK_SRC_XTAL

= 0

Select XTAL_CLK as CPU_CLK source.

Examples

References

from examples