arm_dpm struct
This wraps an implementation of DPM primitives. Each interface provider supplies a structure like this, which is the glue between upper level code and the lower level hardware access. It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with support for CPU register access.
Fields
Invoke before a series of instruction operations.
Invoke after a series of instruction operations.
int (*)(struct arm_dpm *dpm, uint32_t opcode) Runs one instruction.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t data)
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t data)
Runs two instructions, writing data to R0 and R1 before execution.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t data)
Runs one instruction, writing data to R0 before execution.
Optional core-specific operation invoked after CPSR writes.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from dcc after execution.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t *data)
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t *data)
Runs two instructions, reading data from r0 and r1 after execution.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t *data)
struct reg *(*)(struct arm *arm,
unsigned regnum)
int (*)(struct arm_dpm *dpm, unsigned index_value,
uint32_t addr, uint32_t control)
Enables one breakpoint or watchpoint by writing to the hardware registers. The specified breakpoint/watchpoint must currently be disabled. Indices 0..15 are used for breakpoints; indices 16..31 are for watchpoints.
int (*)(struct arm_dpm *dpm, unsigned index_value) Disables one breakpoint or watchpoint by clearing its hardware control registers. Indices are the same ones accepted by bpwp_enable().
Target dependent watchpoint address. Either the address of the instruction which triggered a watchpoint or the memory address whose access triggered a watchpoint.
Recent exception level on armv8.