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arm_dpm struct
This wraps an implementation of DPM primitives. Each interface provider supplies a structure like this, which is the glue between upper level code and the lower level hardware access. It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with support for CPU register access.
Syntax
struct arm_dpm;
Implemented in ![]()
arm_dpm.h:47
Fields
Field
Declared as
Description
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t data)
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t data)
Runs two instructions, writing data to R0 and R1 before execution.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t data)
Runs one instruction, writing data to R0 before execution.
Optional core-specific operation invoked after CPSR writes.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from dcc after execution.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t *data)
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t *data)
Runs two instructions, reading data from r0 and r1 after execution.
int (*)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t *data)
int (*)(struct arm_dpm *dpm, unsigned index_value,
uint32_t addr, uint32_t control)
Enables one breakpoint or watchpoint by writing to the hardware registers. The specified breakpoint/watchpoint must currently be disabled. Indices 0..15 are used for breakpoints; indices 16..31 are for watchpoints.
Disables one breakpoint or watchpoint by clearing its hardware control registers. Indices are the same ones accepted by bpwp_enable().
unsigned
unsigned
Target dependent watchpoint address. Either the address of the instruction which triggered a watchpoint or the memory address whose access triggered a watchpoint.
Related Functions
Found 68 other functions taking a arm_dpm
argument:
Function
Description
Hooks up this DPM to its associated target; call only once. Initially this only covers the register cache. Oh, and watchpoints. Yeah.
Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affected the debug module.
Read basic registers of the current context: R0 to R15, and CPSR; sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb). In normal operation this is called on entry to halting debug state, possibly after some other operations supporting restore of debug state or making sure the CPU is fully idle (drain write buffer, etc).
Writes all modified core registers for all processor modes. In normal operation this is called on exit from halting debug state.
Hooks up this DPM to its associated target; call only once. Initially this only covers the register cache. Oh, and watchpoints. Yeah.
Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affected the debug module.
Read basic registers of the current context: R0 to R15, and CPSR in AArch32 state or R0 to R31, PC and CPSR in AArch64 state; sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb). In normal operation this is called on entry to halting debug state, possibly after some other operations supporting restore of debug state or making sure the CPU is fully idle (drain write buffer, etc).
Writes all modified core registers for all processor modes. In normal operation this is called on exit from halting debug state.
@file Implements various ARM DPM operations using architectural debug registers. These routines layer over core-specific communication methods to cope with implementation differences between cores like ARM1136 and Cortex-A8. The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by Part C (Debug Architecture) of the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition (ARM DDI 0406B). In OpenOCD, DPM operations are abstracted through internal programming interfaces to share code and to minimize needless differences in debug behavior between cores. Get core state from EDSCR, without necessity to retrieve CPSR
Write to program counter and switch the core state (arm/thumb) according to the address.