dpmv8_instr_write_data_r0() function

Hooks up this DPM to its associated target; call only once. Initially this only covers the register cache. Oh, and watchpoints. Yeah.

Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affected the debug module.

Read basic registers of the current context: R0 to R15, and CPSR; sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb). In normal operation this is called on entry to halting debug state, possibly after some other operations supporting restore of debug state or making sure the CPU is fully idle (drain write buffer, etc).

Writes all modified core registers for all processor modes. In normal operation this is called on exit from halting debug state.

Hooks up this DPM to its associated target; call only once. Initially this only covers the register cache. Oh, and watchpoints. Yeah.

Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affected the debug module.

Read basic registers of the current context: R0 to R15, and CPSR in AArch32 state or R0 to R31, PC and CPSR in AArch64 state; sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb). In normal operation this is called on entry to halting debug state, possibly after some other operations supporting restore of debug state or making sure the CPU is fully idle (drain write buffer, etc).

Writes all modified core registers for all processor modes. In normal operation this is called on exit from halting debug state.

@file Implements various ARM DPM operations using architectural debug registers. These routines layer over core-specific communication methods to cope with implementation differences between cores like ARM1136 and Cortex-A8. The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by Part C (Debug Architecture) of the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition (ARM DDI 0406B). In OpenOCD, DPM operations are abstracted through internal programming interfaces to share code and to minimize needless differences in debug behavior between cores. Get core state from EDSCR, without necessity to retrieve CPSR

Write to program counter and switch the core state (arm/thumb) according to the address.