/* SPDX-License-Identifier: GPL-2.0-or-later *//* * Copyright (C) 2009 by David Brownell *//* ... */#ifndefOPENOCD_TARGET_ARM_DPM_H#defineOPENOCD_TARGET_ARM_DPM_H/** * @file * This is the interface to the Debug Programmers Model for ARMv6 and * ARMv7 processors. ARMv6 processors (such as ARM11xx implementations) * introduced a model which became part of the ARMv7-AR architecture * which is most familiar through the Cortex-A series parts. While * specific details differ (like how to write the instruction register), * the high level models easily support shared code because those * registers are compatible. *//* ... */structdpm_bpwp{unsignednumber;uint32_taddress;uint32_tcontrol;/* true if hardware state needs flushing */booldirty;...};structdpm_bp{structbreakpoint*bp;structdpm_bpwpbpwp;...};structdpm_wp{structwatchpoint*wp;structdpm_bpwpbpwp;...};/** * This wraps an implementation of DPM primitives. Each interface * provider supplies a structure like this, which is the glue between * upper level code and the lower level hardware access. * * It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with * support for CPU register access. *//* ... */structarm_dpm{structarm*arm;/** Cache of DIDR */uint64_tdidr;/** Invoke before a series of instruction operations */int(*prepare)(structarm_dpm*dpm);/** Invoke after a series of instruction operations */int(*finish)(structarm_dpm*dpm);/** Runs one instruction. */int(*instr_execute)(structarm_dpm*dpm,uint32_topcode);/* WRITE TO CPU *//** Runs one instruction, writing data to DCC before execution. */int(*instr_write_data_dcc)(structarm_dpm*dpm,uint32_topcode,uint32_tdata);int(*instr_write_data_dcc_64)(structarm_dpm*dpm,uint32_topcode,uint64_tdata);/** Runs one instruction, writing data to R0 before execution. */int(*instr_write_data_r0)(structarm_dpm*dpm,uint32_topcode,uint32_tdata);/** * Runs two instructions, writing data to R0 and R1 before execution. *//* ... */int(*instr_write_data_r0_r1)(structarm_dpm*dpm,uint32_topcode,uint64_tdata);/** Runs one instruction, writing data to R0 before execution. */int(*instr_write_data_r0_64)(structarm_dpm*dpm,uint32_topcode,uint64_tdata);/** Optional core-specific operation invoked after CPSR writes. */int(*instr_cpsr_sync)(structarm_dpm*dpm);/* READ FROM CPU *//** Runs one instruction, reading data from dcc after execution. */int(*instr_read_data_dcc)(structarm_dpm*dpm,uint32_topcode,uint32_t*data);int(*instr_read_data_dcc_64)(structarm_dpm*dpm,uint32_topcode,uint64_t*data);/** Runs one instruction, reading data from r0 after execution. */int(*instr_read_data_r0)(structarm_dpm*dpm,uint32_topcode,uint32_t*data);/** * Runs two instructions, reading data from r0 and r1 after * execution. *//* ... */int(*instr_read_data_r0_r1)(structarm_dpm*dpm,uint32_topcode,uint64_t*data);int(*instr_read_data_r0_64)(structarm_dpm*dpm,uint32_topcode,uint64_t*data);structreg*(*arm_reg_current)(structarm*arm,unsignedregnum);/* BREAKPOINT/WATCHPOINT SUPPORT *//** * Enables one breakpoint or watchpoint by writing to the * hardware registers. The specified breakpoint/watchpoint * must currently be disabled. Indices 0..15 are used for * breakpoints; indices 16..31 are for watchpoints. *//* ... */int(*bpwp_enable)(structarm_dpm*dpm,unsignedindex_value,uint32_taddr,uint32_tcontrol);/** * Disables one breakpoint or watchpoint by clearing its * hardware control registers. Indices are the same ones * accepted by bpwp_enable(). *//* ... */int(*bpwp_disable)(structarm_dpm*dpm,unsignedindex_value);/* The breakpoint and watchpoint arrays are private to the * DPM infrastructure. There are nbp indices in the dbp * array. There are nwp indices in the dwp array. *//* ... */unsignednbp;unsignednwp;structdpm_bp*dbp;structdpm_wp*dwp;/** * Target dependent watchpoint address. * Either the address of the instruction which triggered a watchpoint * or the memory address whose access triggered a watchpoint. *//* ... */target_addr_twp_addr;/** Recent value of DSCR. */uint32_tdscr;/** Recent exception level on armv8 */unsignedintlast_el;/* FIXME -- read/write DCSR methods and symbols */...};intarm_dpm_setup(structarm_dpm*dpm);intarm_dpm_initialize(structarm_dpm*dpm);intarm_dpm_read_reg(structarm_dpm*dpm,structreg*r,unsignedregnum);intarm_dpm_read_current_registers(structarm_dpm*dpm);intarm_dpm_modeswitch(structarm_dpm*dpm,enumarm_modemode);intarm_dpm_write_dirty_registers(structarm_dpm*dpm,boolbpwp);voidarm_dpm_report_wfar(structarm_dpm*dpm,uint32_twfar);/* DSCR bits; see ARMv7a arch spec section C10.3.1. * Not all v7 bits are valid in v6. *//* ... */#defineDSCR_CORE_HALTED(0x1<<0)#defineDSCR_CORE_RESTARTED(0x1<<1)#defineDSCR_ENTRY_MASK(0xF<<2)#defineDSCR_STICKY_ABORT_PRECISE(0x1<<6)#defineDSCR_STICKY_ABORT_IMPRECISE(0x1<<7)#defineDSCR_STICKY_UNDEFINED(0x1<<8)#defineDSCR_DBG_NOPWRDWN(0x1<<9)/* v6 only */#defineDSCR_DBG_ACK(0x1<<10)#defineDSCR_INT_DIS(0x1<<11)#defineDSCR_CP14_USR_COMMS(0x1<<12)#defineDSCR_ITR_EN(0x1<<13)#defineDSCR_HALT_DBG_MODE(0x1<<14)#defineDSCR_MON_DBG_MODE(0x1<<15)#defineDSCR_SEC_PRIV_INVASV_DIS(0x1<<16)#defineDSCR_SEC_PRIV_NINVASV_DIS(0x1<<17)#defineDSCR_NON_SECURE(0x1<<18)#defineDSCR_DSCRD_IMPRECISE_ABORT(0x1<<19)#defineDSCR_EXT_DCC_MASK(0x3<<20)/* DTR mode *//* bits 22, 23 are reserved */#defineDSCR_INSTR_COMP(0x1<<24)#defineDSCR_PIPE_ADVANCE(0x1<<25)#defineDSCR_DTRTX_FULL_LATCHED(0x1<<26)#defineDSCR_DTRRX_FULL_LATCHED(0x1<<27)/* bit 28 is reserved */#defineDSCR_DTR_TX_FULL(0x1<<29)#defineDSCR_DTR_RX_FULL(0x1<<30)/* bit 31 is reserved */#defineDSCR_ENTRY(dscr)((dscr)&0x3f)#defineDSCR_RUN_MODE(dscr)((dscr)&0x03)/* Methods of entry into debug mode */#defineDSCR_ENTRY_HALT_REQ(0x03)#defineDSCR_ENTRY_BREAKPOINT(0x07)#defineDSCR_ENTRY_IMPRECISE_WATCHPT(0x0B)#defineDSCR_ENTRY_BKPT_INSTR(0x0F)#defineDSCR_ENTRY_EXT_DBG_REQ(0x13)#defineDSCR_ENTRY_VECT_CATCH(0x17)#defineDSCR_ENTRY_D_SIDE_ABORT(0x1B)/* v6 only */#defineDSCR_ENTRY_I_SIDE_ABORT(0x1F)/* v6 only */#defineDSCR_ENTRY_OS_UNLOCK(0x23)#defineDSCR_ENTRY_PRECISE_WATCHPT(0x2B)/* DTR modes */#defineDSCR_EXT_DCC_NON_BLOCKING(0x0<<20)#defineDSCR_EXT_DCC_STALL_MODE(0x1<<20)#defineDSCR_EXT_DCC_FAST_MODE(0x2<<20)/* bits 22, 23 are reserved *//* DRCR (debug run control register) bits */#defineDRCR_HALT(1<<0)#defineDRCR_RESTART(1<<1)#defineDRCR_CLEAR_EXCEPTIONS(1<<2)42 definesvoidarm_dpm_report_dscr(structarm_dpm*dpm,uint32_tdcsr);/* PRCR (Device Power-down and Reset Control Register) bits */#definePRCR_DEBUG_NO_POWER_DOWN(1<<0)#definePRCR_WARM_RESET(1<<1)#definePRCR_HOLD_NON_DEBUG_RESET(1<<2)/* PRSR (Device Power-down and Reset Status Register) bits */#definePRSR_POWERUP_STATUS(1<<0)#definePRSR_STICKY_POWERDOWN_STATUS(1<<1)#definePRSR_RESET_STATUS(1<<2)#definePRSR_STICKY_RESET_STATUS(1<<3)#definePRSR_HALTED(1<<4)/* v7.1 Debug only */#definePRSR_OSLK(1<<5)/* v7.1 Debug only */#definePRSR_DLK(1<<6)/* v7.1 Debug only *//* OSLSR (OS Lock Status Register) bits */#defineOSLSR_OSLM0(1<<0)#defineOSLSR_OSLK(1<<1)#defineOSLSR_NTT(1<<2)#defineOSLSR_OSLM1(1<<3)#defineOSLSR_OSLM(OSLSR_OSLM0|OSLSR_OSLM1)15 defines/* ... */#endif/* OPENOCD_TARGET_ARM_DPM_H */
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