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usbx

common

core

usbx_device_classes

usbx_host_classes

usbx_network

usbx_stm32_device_controllers

usbx_stm32_host_controllers

ux_hcd_stm32_callback.c

ux_hcd_stm32_controller_disable.c

ux_hcd_stm32_ed_obtain.c

ux_hcd_stm32_endpoint_create.c

ux_hcd_stm32_endpoint_destroy.c

ux_hcd_stm32_endpoint_reset.c

ux_hcd_stm32_entry.c

ux_hcd_stm32_frame_number_get.c

ux_hcd_stm32_initialize.c

ux_hcd_stm32_interrupt_handler.c

ux_hcd_stm32_least_traffic_list_get.c

ux_hcd_stm32_periodic_schedule.c

ux_hcd_stm32_port_disable.c

ux_hcd_stm32_port_enable.c

ux_hcd_stm32_port_reset.c

ux_hcd_stm32_port_resume.c

ux_hcd_stm32_port_status_get.c

ux_hcd_stm32_port_suspend.c

ux_hcd_stm32_power_down_port.c

ux_hcd_stm32_power_on_port.c

ux_hcd_stm32_request_bulk_transfer.c

ux_hcd_stm32_request_control_transfer.c

ux_hcd_stm32_request_periodic_transfer.c

ux_hcd_stm32_request_transfer.c

ux_hcd_stm32_transfer_abort.c

UX_HCD_STM32_ED

UX_HCD_STM32_ED

_ux_hcd_stm32_controller_disable()

_ux_hcd_stm32_ed_obtain()

_ux_hcd_stm32_endpoint_create()

_ux_hcd_stm32_endpoint_destroy()

_ux_hcd_stm32_endpoint_reset()

_ux_hcd_stm32_entry()

_ux_hcd_stm32_frame_number_get()

_ux_hcd_stm32_initialize()

_ux_hcd_stm32_interrupt_handler()

_ux_hcd_stm32_least_traffic_list_get()

_ux_hcd_stm32_periodic_schedule()

_ux_hcd_stm32_port_disable()

_ux_hcd_stm32_port_enable()

_ux_hcd_stm32_port_reset()

_ux_hcd_stm32_port_resume()

_ux_hcd_stm32_port_status_get()

_ux_hcd_stm32_port_suspend()

_ux_hcd_stm32_power_down_port()

_ux_hcd_stm32_power_on_port()

_ux_hcd_stm32_request_bulk_transfer()

_ux_hcd_stm32_request_control_transfer()

_ux_hcd_stm32_request_periodic_transfer()

_ux_hcd_stm32_request_transfer()

_ux_hcd_stm32_transfer_abort()

ports

HAL

threadx

netxduo

filex

Summary Syntax Related References Instances

SourceVuSTM32 Libraries and SamplesusbxUX_HCD_STM32

UX_HCD_STM32 struct

Syntax

Show:

Summary

Declaration

from ux_hcd_stm32.h:91

typedef struct UX_HCD_STM32_STRUCT { struct UX_HCD_STRUCT *ux_hcd_stm32_hcd_owner; struct UX_HCD_STM32_ED_STRUCT *ux_hcd_stm32_ed_list; struct UX_HCD_STM32_ED_STRUCT *ux_hcd_stm32_channels_ed[UX_HCD_STM32_MAX_NB_CHANNELS]; ULONG ux_hcd_stm32_nb_channels; UINT ux_hcd_stm32_queue_empty; UINT ux_hcd_stm32_periodic_scheduler_active; ULONG ux_hcd_stm32_controller_flag; HCD_HandleTypeDef *hcd_handle; struct UX_HCD_STM32_ED_STRUCT *ux_hcd_stm32_periodic_ed_head; } UX_HCD_STM32;

Fields

Field

Declared as

UX_HCD_STM32_STRUCT::ux_hcd_stm32_hcd_owner

struct UX_HCD_STRUCT *

UX_HCD_STM32_STRUCT::ux_hcd_stm32_ed_list

struct UX_HCD_STM32_ED_STRUCT *

UX_HCD_STM32_STRUCT::ux_hcd_stm32_channels_ed

struct UX_HCD_STM32_ED_STRUCT *[UX_HCD_STM32_MAX_NB_CHANNELS]

UX_HCD_STM32_STRUCT::ux_hcd_stm32_nb_channels

UX_HCD_STM32_STRUCT::ux_hcd_stm32_queue_empty

UX_HCD_STM32_STRUCT::ux_hcd_stm32_periodic_scheduler_active

UX_HCD_STM32_STRUCT::ux_hcd_stm32_controller_flag

UX_HCD_STM32_STRUCT::hcd_handle

HCD_HandleTypeDef *

UX_HCD_STM32_STRUCT::ux_hcd_stm32_periodic_ed_head

struct UX_HCD_STM32_ED_STRUCT *

References

Code

Location

Scope

Referrer

typedef struct UX_HCD_STM32_STRUCT

ux_hcd_stm32.h:91

} UX_HCD_STM32;

ux_hcd_stm32.h:103

UINT _ux_hcd_stm32_controller_disable(UX_HCD_STM32 *hcd_stm32);

ux_hcd_stm32.h:127

_ux_hcd_stm32_controller_disable()

_ux_hcd_stm32_controller_disable()::hcd_stm32

UX_HCD_STM32_ED * _ux_hcd_stm32_ed_obtain(UX_HCD_STM32 *hcd_stm32);

ux_hcd_stm32.h:128

_ux_hcd_stm32_ed_obtain()

_ux_hcd_stm32_ed_obtain()::hcd_stm32

UINT _ux_hcd_stm32_endpoint_create(UX_HCD_STM32 *hcd_stm32, UX_ENDPOINT *endpoint);

ux_hcd_stm32.h:129

_ux_hcd_stm32_endpoint_create()

_ux_hcd_stm32_endpoint_create()::hcd_stm32

UINT _ux_hcd_stm32_endpoint_destroy(UX_HCD_STM32 *hcd_stm32, UX_ENDPOINT *endpoint);

ux_hcd_stm32.h:130

_ux_hcd_stm32_endpoint_destroy()

_ux_hcd_stm32_endpoint_destroy()::hcd_stm32

UINT _ux_hcd_stm32_endpoint_reset(UX_HCD_STM32 *hcd_stm32, UX_ENDPOINT *endpoint);

ux_hcd_stm32.h:131

_ux_hcd_stm32_endpoint_reset()

_ux_hcd_stm32_endpoint_reset()::hcd_stm32

UINT _ux_hcd_stm32_frame_number_get(UX_HCD_STM32 *hcd_stm32, ULONG *frame_number);

ux_hcd_stm32.h:133

_ux_hcd_stm32_frame_number_get()

_ux_hcd_stm32_frame_number_get()::hcd_stm32

UINT _ux_hcd_stm32_least_traffic_list_get(UX_HCD_STM32 *hcd_stm32);

ux_hcd_stm32.h:136

_ux_hcd_stm32_least_traffic_list_get()

_ux_hcd_stm32_least_traffic_list_get()::hcd_stm32

UINT _ux_hcd_stm32_periodic_schedule(UX_HCD_STM32 *hcd_stm32);

ux_hcd_stm32.h:137

_ux_hcd_stm32_periodic_schedule()

_ux_hcd_stm32_periodic_schedule()::hcd_stm32

UINT _ux_hcd_stm32_port_disable(UX_HCD_STM32 *hcd_stm32, ULONG port_index);

ux_hcd_stm32.h:138

_ux_hcd_stm32_port_disable()

_ux_hcd_stm32_port_disable()::hcd_stm32

UINT _ux_hcd_stm32_port_enable(UX_HCD_STM32 *hcd_stm32, ULONG port_index);

ux_hcd_stm32.h:139

_ux_hcd_stm32_port_enable()

_ux_hcd_stm32_port_enable()::hcd_stm32

UINT _ux_hcd_stm32_port_reset(UX_HCD_STM32 *hcd_stm32, ULONG port_index);

ux_hcd_stm32.h:140

_ux_hcd_stm32_port_reset()

_ux_hcd_stm32_port_reset()::hcd_stm32

UINT _ux_hcd_stm32_port_resume(UX_HCD_STM32 *hcd_stm32, UINT port_index);

ux_hcd_stm32.h:141

_ux_hcd_stm32_port_resume()

_ux_hcd_stm32_port_resume()::hcd_stm32

ULONG _ux_hcd_stm32_port_status_get(UX_HCD_STM32 *hcd_stm32, ULONG port_index);

ux_hcd_stm32.h:142

_ux_hcd_stm32_port_status_get()

_ux_hcd_stm32_port_status_get()::hcd_stm32

UINT _ux_hcd_stm32_port_suspend(UX_HCD_STM32 *hcd_stm32, ULONG port_index);

ux_hcd_stm32.h:143

_ux_hcd_stm32_port_suspend()

_ux_hcd_stm32_port_suspend()::hcd_stm32

UINT _ux_hcd_stm32_power_down_port(UX_HCD_STM32 *hcd_stm32, ULONG port_index);

ux_hcd_stm32.h:144

_ux_hcd_stm32_power_down_port()

_ux_hcd_stm32_power_down_port()::hcd_stm32

UINT _ux_hcd_stm32_power_on_port(UX_HCD_STM32 *hcd_stm32, ULONG port_index);

ux_hcd_stm32.h:145

_ux_hcd_stm32_power_on_port()

_ux_hcd_stm32_power_on_port()::hcd_stm32

UINT _ux_hcd_stm32_request_bulk_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request);

ux_hcd_stm32.h:146

_ux_hcd_stm32_request_bulk_transfer()

_ux_hcd_stm32_request_bulk_transfer()::hcd_stm32

UINT _ux_hcd_stm32_request_control_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request);

ux_hcd_stm32.h:147

_ux_hcd_stm32_request_control_transfer()

_ux_hcd_stm32_request_control_transfer()::hcd_stm32

UINT _ux_hcd_stm32_request_periodic_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request);

ux_hcd_stm32.h:148

_ux_hcd_stm32_request_periodic_transfer()

_ux_hcd_stm32_request_periodic_transfer()::hcd_stm32

UINT _ux_hcd_stm32_request_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request);

ux_hcd_stm32.h:149

_ux_hcd_stm32_request_transfer()

_ux_hcd_stm32_request_transfer()::hcd_stm32

UINT _ux_hcd_stm32_transfer_abort(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request);

ux_hcd_stm32.h:150

_ux_hcd_stm32_transfer_abort()

_ux_hcd_stm32_transfer_abort()::hcd_stm32

UX_HCD_STM32 *hcd_stm32;

ux_hcd_stm32_callback.c:75

HAL_HCD_Connect_Callback()

hcd_stm32 = (UX_HCD_STM32*)hcd -> ux_hcd_controller_hardware;

ux_hcd_stm32_callback.c:80

HAL_HCD_Connect_Callback()

UX_HCD_STM32 *hcd_stm32;

ux_hcd_stm32_callback.c:135

HAL_HCD_Disconnect_Callback()

hcd_stm32 = (UX_HCD_STM32*)hcd -> ux_hcd_controller_hardware;

ux_hcd_stm32_callback.c:140

HAL_HCD_Disconnect_Callback()

UX_HCD_STM32 *hcd_stm32;

ux_hcd_stm32_callback.c:198

HAL_HCD_HC_NotifyURBChange_Callback()

hcd_stm32 = (UX_HCD_STM32*)hcd -> ux_hcd_controller_hardware;

ux_hcd_stm32_callback.c:209

HAL_HCD_HC_NotifyURBChange_Callback()

UX_HCD_STM32 *hcd_stm32;

ux_hcd_stm32_callback.c:368

HAL_HCD_SOF_Callback()

hcd_stm32 = (UX_HCD_STM32*)hcd -> ux_hcd_controller_hardware;

ux_hcd_stm32_callback.c:373

HAL_HCD_SOF_Callback()

UINT _ux_hcd_stm32_controller_disable(UX_HCD_STM32 *hcd_stm32)

ux_hcd_stm32_controller_disable.c:75

_ux_hcd_stm32_controller_disable()

_ux_hcd_stm32_controller_disable()::hcd_stm32

UX_HCD_STM32_ED *_ux_hcd_stm32_ed_obtain(UX_HCD_STM32 *hcd_stm32)

ux_hcd_stm32_ed_obtain.c:71

_ux_hcd_stm32_ed_obtain()

_ux_hcd_stm32_ed_obtain()::hcd_stm32

UINT _ux_hcd_stm32_endpoint_create(UX_HCD_STM32 *hcd_stm32, UX_ENDPOINT *endpoint)

ux_hcd_stm32_endpoint_create.c:73

_ux_hcd_stm32_endpoint_create()

_ux_hcd_stm32_endpoint_create()::hcd_stm32

UINT _ux_hcd_stm32_endpoint_destroy(UX_HCD_STM32 *hcd_stm32, UX_ENDPOINT *endpoint)

ux_hcd_stm32_endpoint_destroy.c:73

_ux_hcd_stm32_endpoint_destroy()

_ux_hcd_stm32_endpoint_destroy()::hcd_stm32

UINT _ux_hcd_stm32_endpoint_reset(UX_HCD_STM32 *hcd_stm32, UX_ENDPOINT *endpoint)

ux_hcd_stm32_endpoint_reset.c:72

_ux_hcd_stm32_endpoint_reset()

_ux_hcd_stm32_endpoint_reset()::hcd_stm32

UX_HCD_STM32 *hcd_stm32;

ux_hcd_stm32_entry.c:96

_ux_hcd_stm32_entry()

hcd_stm32 = (UX_HCD_STM32 *) hcd -> ux_hcd_controller_hardware;

ux_hcd_stm32_entry.c:114

_ux_hcd_stm32_entry()

UINT _ux_hcd_stm32_frame_number_get(UX_HCD_STM32 *hcd_stm32, ULONG *frame_number)

ux_hcd_stm32_frame_number_get.c:74

_ux_hcd_stm32_frame_number_get()

_ux_hcd_stm32_frame_number_get()::hcd_stm32

UX_HCD_STM32 *hcd_stm32;

ux_hcd_stm32_initialize.c:77

_ux_hcd_stm32_initialize()

hcd_stm32 = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, sizeof(UX_HCD_STM32));

ux_hcd_stm32_initialize.c:90

_ux_hcd_stm32_initialize()

UX_HCD_STM32 *hcd_stm32;

ux_hcd_stm32_interrupt_handler.c:76

_ux_hcd_stm32_interrupt_handler()

hcd_stm32 = (UX_HCD_STM32 *) hcd -> ux_hcd_controller_hardware;

ux_hcd_stm32_interrupt_handler.c:90

_ux_hcd_stm32_interrupt_handler()

UINT _ux_hcd_stm32_least_traffic_list_get(UX_HCD_STM32 *hcd_stm32)

ux_hcd_stm32_least_traffic_list_get.c:72

_ux_hcd_stm32_least_traffic_list_get()

_ux_hcd_stm32_least_traffic_list_get()::hcd_stm32

UINT _ux_hcd_stm32_periodic_schedule(UX_HCD_STM32 *hcd_stm32)

ux_hcd_stm32_periodic_schedule.c:72

_ux_hcd_stm32_periodic_schedule()

_ux_hcd_stm32_periodic_schedule()::hcd_stm32

UINT _ux_hcd_stm32_port_disable(UX_HCD_STM32 *hcd_stm32, ULONG port_index)

ux_hcd_stm32_port_disable.c:72

_ux_hcd_stm32_port_disable()

_ux_hcd_stm32_port_disable()::hcd_stm32

UINT _ux_hcd_stm32_port_enable(UX_HCD_STM32 *hcd_stm32, ULONG port_index)

ux_hcd_stm32_port_enable.c:71

_ux_hcd_stm32_port_enable()

_ux_hcd_stm32_port_enable()::hcd_stm32

UINT _ux_hcd_stm32_port_reset(UX_HCD_STM32 *hcd_stm32, ULONG port_index)

ux_hcd_stm32_port_reset.c:78

_ux_hcd_stm32_port_reset()

_ux_hcd_stm32_port_reset()::hcd_stm32

UINT _ux_hcd_stm32_port_resume(UX_HCD_STM32 *hcd_stm32, UINT port_index)

ux_hcd_stm32_port_resume.c:73

_ux_hcd_stm32_port_resume()

_ux_hcd_stm32_port_resume()::hcd_stm32

ULONG _ux_hcd_stm32_port_status_get(UX_HCD_STM32 *hcd_stm32, ULONG port_index)

ux_hcd_stm32_port_status_get.c:98

_ux_hcd_stm32_port_status_get()

_ux_hcd_stm32_port_status_get()::hcd_stm32

UINT _ux_hcd_stm32_port_suspend(UX_HCD_STM32 *hcd_stm32, ULONG port_index)

ux_hcd_stm32_port_suspend.c:73

_ux_hcd_stm32_port_suspend()

_ux_hcd_stm32_port_suspend()::hcd_stm32

UINT _ux_hcd_stm32_power_down_port(UX_HCD_STM32 *hcd_stm32, ULONG port_index)

ux_hcd_stm32_power_down_port.c:73

_ux_hcd_stm32_power_down_port()

_ux_hcd_stm32_power_down_port()::hcd_stm32

UINT _ux_hcd_stm32_power_on_port(UX_HCD_STM32 *hcd_stm32, ULONG port_index)

ux_hcd_stm32_power_on_port.c:72

_ux_hcd_stm32_power_on_port()

_ux_hcd_stm32_power_on_port()::hcd_stm32

UINT _ux_hcd_stm32_request_bulk_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request)

ux_hcd_stm32_request_bulk_transfer.c:76

_ux_hcd_stm32_request_bulk_transfer()

_ux_hcd_stm32_request_bulk_transfer()::hcd_stm32

UINT _ux_hcd_stm32_request_control_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request)

ux_hcd_stm32_request_control_transfer.c:83

_ux_hcd_stm32_request_control_transfer()

_ux_hcd_stm32_request_control_transfer()::hcd_stm32

UINT _ux_hcd_stm32_request_periodic_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request)

ux_hcd_stm32_request_periodic_transfer.c:76

_ux_hcd_stm32_request_periodic_transfer()

_ux_hcd_stm32_request_periodic_transfer()::hcd_stm32

UINT _ux_hcd_stm32_request_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request)

ux_hcd_stm32_request_transfer.c:80

_ux_hcd_stm32_request_transfer()

_ux_hcd_stm32_request_transfer()::hcd_stm32

UINT _ux_hcd_stm32_transfer_abort(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request)

ux_hcd_stm32_transfer_abort.c:77

_ux_hcd_stm32_transfer_abort()

_ux_hcd_stm32_transfer_abort()::hcd_stm32

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Implementations

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Instances

Instance

Scope

Location

Project

_ux_hcd_stm32_controller_disable()::hcd_stm32

_ux_hcd_stm32_controller_disable()

ux_hcd_stm32.h:127

_ux_hcd_stm32_ed_obtain()::hcd_stm32

_ux_hcd_stm32_ed_obtain()

ux_hcd_stm32.h:128

_ux_hcd_stm32_endpoint_create()::hcd_stm32

_ux_hcd_stm32_endpoint_create()

ux_hcd_stm32.h:129

_ux_hcd_stm32_endpoint_destroy()::hcd_stm32

_ux_hcd_stm32_endpoint_destroy()

ux_hcd_stm32.h:130

_ux_hcd_stm32_endpoint_reset()::hcd_stm32

_ux_hcd_stm32_endpoint_reset()

ux_hcd_stm32.h:131

_ux_hcd_stm32_frame_number_get()::hcd_stm32

_ux_hcd_stm32_frame_number_get()

ux_hcd_stm32.h:133

_ux_hcd_stm32_least_traffic_list_get()::hcd_stm32

_ux_hcd_stm32_least_traffic_list_get()

ux_hcd_stm32.h:136

_ux_hcd_stm32_periodic_schedule()::hcd_stm32

_ux_hcd_stm32_periodic_schedule()

ux_hcd_stm32.h:137

_ux_hcd_stm32_port_disable()::hcd_stm32

_ux_hcd_stm32_port_disable()

ux_hcd_stm32.h:138

_ux_hcd_stm32_port_enable()::hcd_stm32

_ux_hcd_stm32_port_enable()

ux_hcd_stm32.h:139

_ux_hcd_stm32_port_reset()::hcd_stm32

_ux_hcd_stm32_port_reset()

ux_hcd_stm32.h:140

_ux_hcd_stm32_port_resume()::hcd_stm32

_ux_hcd_stm32_port_resume()

ux_hcd_stm32.h:141

_ux_hcd_stm32_port_status_get()::hcd_stm32

_ux_hcd_stm32_port_status_get()

ux_hcd_stm32.h:142

_ux_hcd_stm32_port_suspend()::hcd_stm32

_ux_hcd_stm32_port_suspend()

ux_hcd_stm32.h:143

_ux_hcd_stm32_power_down_port()::hcd_stm32

_ux_hcd_stm32_power_down_port()

ux_hcd_stm32.h:144

_ux_hcd_stm32_power_on_port()::hcd_stm32

_ux_hcd_stm32_power_on_port()

ux_hcd_stm32.h:145

_ux_hcd_stm32_request_bulk_transfer()::hcd_stm32

_ux_hcd_stm32_request_bulk_transfer()

ux_hcd_stm32.h:146

_ux_hcd_stm32_request_control_transfer()::hcd_stm32

_ux_hcd_stm32_request_control_transfer()

ux_hcd_stm32.h:147

_ux_hcd_stm32_request_periodic_transfer()::hcd_stm32

_ux_hcd_stm32_request_periodic_transfer()

ux_hcd_stm32.h:148

_ux_hcd_stm32_request_transfer()::hcd_stm32

_ux_hcd_stm32_request_transfer()

ux_hcd_stm32.h:149

_ux_hcd_stm32_transfer_abort()::hcd_stm32

_ux_hcd_stm32_transfer_abort()

ux_hcd_stm32.h:150

_ux_hcd_stm32_controller_disable()::hcd_stm32

_ux_hcd_stm32_controller_disable()

ux_hcd_stm32_controller_disable.c:75

_ux_hcd_stm32_ed_obtain()::hcd_stm32

_ux_hcd_stm32_ed_obtain()

ux_hcd_stm32_ed_obtain.c:71

_ux_hcd_stm32_endpoint_create()::hcd_stm32

_ux_hcd_stm32_endpoint_create()

ux_hcd_stm32_endpoint_create.c:73

_ux_hcd_stm32_endpoint_destroy()::hcd_stm32

_ux_hcd_stm32_endpoint_destroy()

ux_hcd_stm32_endpoint_destroy.c:73

_ux_hcd_stm32_endpoint_reset()::hcd_stm32

_ux_hcd_stm32_endpoint_reset()

ux_hcd_stm32_endpoint_reset.c:72

_ux_hcd_stm32_frame_number_get()::hcd_stm32

_ux_hcd_stm32_frame_number_get()

ux_hcd_stm32_frame_number_get.c:74

_ux_hcd_stm32_least_traffic_list_get()::hcd_stm32

_ux_hcd_stm32_least_traffic_list_get()

ux_hcd_stm32_least_traffic_list_get.c:72

_ux_hcd_stm32_periodic_schedule()::hcd_stm32

_ux_hcd_stm32_periodic_schedule()

ux_hcd_stm32_periodic_schedule.c:72

_ux_hcd_stm32_port_disable()::hcd_stm32

_ux_hcd_stm32_port_disable()

ux_hcd_stm32_port_disable.c:72

_ux_hcd_stm32_port_enable()::hcd_stm32

_ux_hcd_stm32_port_enable()

ux_hcd_stm32_port_enable.c:71

_ux_hcd_stm32_port_reset()::hcd_stm32

_ux_hcd_stm32_port_reset()

ux_hcd_stm32_port_reset.c:78

_ux_hcd_stm32_port_resume()::hcd_stm32

_ux_hcd_stm32_port_resume()

ux_hcd_stm32_port_resume.c:73

_ux_hcd_stm32_port_status_get()::hcd_stm32

_ux_hcd_stm32_port_status_get()

ux_hcd_stm32_port_status_get.c:98

_ux_hcd_stm32_port_suspend()::hcd_stm32

_ux_hcd_stm32_port_suspend()

ux_hcd_stm32_port_suspend.c:73

_ux_hcd_stm32_power_down_port()::hcd_stm32

_ux_hcd_stm32_power_down_port()

ux_hcd_stm32_power_down_port.c:73

_ux_hcd_stm32_power_on_port()::hcd_stm32

_ux_hcd_stm32_power_on_port()

ux_hcd_stm32_power_on_port.c:72

_ux_hcd_stm32_request_bulk_transfer()::hcd_stm32

_ux_hcd_stm32_request_bulk_transfer()

ux_hcd_stm32_request_bulk_transfer.c:76

_ux_hcd_stm32_request_control_transfer()::hcd_stm32

_ux_hcd_stm32_request_control_transfer()

ux_hcd_stm32_request_control_transfer.c:83

_ux_hcd_stm32_request_periodic_transfer()::hcd_stm32

_ux_hcd_stm32_request_periodic_transfer()

ux_hcd_stm32_request_periodic_transfer.c:76

_ux_hcd_stm32_request_transfer()::hcd_stm32

_ux_hcd_stm32_request_transfer()

ux_hcd_stm32_request_transfer.c:80

_ux_hcd_stm32_transfer_abort()::hcd_stm32

_ux_hcd_stm32_transfer_abort()

ux_hcd_stm32_transfer_abort.c:77

Lifecycle

All items filtered out

All items filtered out