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RCC_PLLInitTypeDef struct
RCC PLL configuration structure definition
Syntax
typedef struct
{
uint32_t PLLState;
uint32_t PLLSource;
uint32_t PLLM;
uint32_t PLLN;
uint32_t PLLP;
uint32_t PLLQ;
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
defined(STM32F413xx) || defined(STM32F423xx)
uint32_t PLLR;
#endif
}RCC_PLLInitTypeDef;
Fields
Field
Declared as
Description
uint32_t
The new state of the PLL. This parameter can be a value of RCC_PLL_Config.
uint32_t
RCC_PLLSource: PLL entry clock source. This parameter must be a value of RCC_PLL_Clock_Source.
uint32_t
PLLM: Division factor for PLL VCO input clock. This parameter must be a number between Min_Data = 0 and Max_Data = 63.
uint32_t
PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432 except for STM32F411xE devices where the Min_Data = 192.
uint32_t
PLLP: Division factor for main system clock (SYSCLK). This parameter must be a value of RCC_PLLP_Clock_Divider.
uint32_t
PLLQ: Division factor for OTG FS, SDIO and RNG clocks. This parameter must be a number between Min_Data = 2 and Max_Data = 15.
uint32_t
PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. This parameter must be a number between Min_Data = 2 and Max_Data = 7.