PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. This parameter must be a number between Min_Data = 2 and Max_Data = 7

Syntax

Show:

Summary

Declaration

from stm32f4xx_hal_rcc_ex.h:68

uint32_t PLLR;

Examples

RCC_PLLInitTypeDef::PLLR is referenced by 638 libraries and example projects:

References

from examples

RCC_PLLInitTypeDef::PLLR field

Syntax

Examples

References

Call Tree

Data Use

Class Tree

Override Tree

Implementations

Instances

Lifecycle