Device/ST/STM32F4xx/Include/stm32f429xx.h (CMSIS)

Outline

#define __STM32F429xx_H

#define __CM4_REV

#define __MPU_PRESENT

#define __NVIC_PRIO_BITS

#define __Vendor_SysTickConfig

#define __FPU_PRESENT

IRQn_Type

#include "core_cm4.h"

#include "system_stm32f4xx.h"

#include <stdint.h>

ADC_TypeDef

ADC_Common_TypeDef

CAN_TxMailBox_TypeDef

CAN_FIFOMailBox_TypeDef

CAN_FilterRegister_TypeDef

CAN_TypeDef

CRC_TypeDef

DAC_TypeDef

DBGMCU_TypeDef

DCMI_TypeDef

DMA_Stream_TypeDef

DMA_TypeDef

DMA2D_TypeDef

ETH_TypeDef

EXTI_TypeDef

FLASH_TypeDef

FMC_Bank1_TypeDef

FMC_Bank1E_TypeDef

FMC_Bank2_3_TypeDef

FMC_Bank4_TypeDef

FMC_Bank5_6_TypeDef

GPIO_TypeDef

SYSCFG_TypeDef

I2C_TypeDef

IWDG_TypeDef

LTDC_TypeDef

LTDC_Layer_TypeDef

PWR_TypeDef

RCC_TypeDef

RTC_TypeDef

SAI_TypeDef

SAI_Block_TypeDef

SDIO_TypeDef

SPI_TypeDef

TIM_TypeDef

USART_TypeDef

WWDG_TypeDef

RNG_TypeDef

USB_OTG_GlobalTypeDef

USB_OTG_DeviceTypeDef

USB_OTG_INEndpointTypeDef

USB_OTG_OUTEndpointTypeDef

USB_OTG_HostTypeDef

USB_OTG_HostChannelTypeDef

#define FLASH_BASE

#define CCMDATARAM_BASE

#define SRAM1_BASE

#define SRAM2_BASE

#define SRAM3_BASE

#define PERIPH_BASE

#define BKPSRAM_BASE

#define FMC_R_BASE

#define SRAM1_BB_BASE

#define SRAM2_BB_BASE

#define SRAM3_BB_BASE

#define PERIPH_BB_BASE

#define BKPSRAM_BB_BASE

#define FLASH_END

#define FLASH_OTP_BASE

#define FLASH_OTP_END

#define CCMDATARAM_END

#define SRAM_BASE

#define SRAM_BB_BASE

#define APB1PERIPH_BASE

#define APB2PERIPH_BASE

#define AHB1PERIPH_BASE

#define AHB2PERIPH_BASE

#define TIM2_BASE

#define TIM3_BASE

#define TIM4_BASE

#define TIM5_BASE

#define TIM6_BASE

#define TIM7_BASE

#define TIM12_BASE

#define TIM13_BASE

#define TIM14_BASE

#define RTC_BASE

#define WWDG_BASE

#define IWDG_BASE

#define I2S2ext_BASE

#define SPI2_BASE

#define SPI3_BASE

#define I2S3ext_BASE

#define USART2_BASE

#define USART3_BASE

#define UART4_BASE

#define UART5_BASE

#define I2C1_BASE

#define I2C2_BASE

#define I2C3_BASE

#define CAN1_BASE

#define CAN2_BASE

#define PWR_BASE

#define DAC_BASE

#define UART7_BASE

#define UART8_BASE

#define TIM1_BASE

#define TIM8_BASE

#define USART1_BASE

#define USART6_BASE

#define ADC1_BASE

#define ADC2_BASE

#define ADC3_BASE

#define ADC123_COMMON_BASE

#define ADC_BASE

#define SDIO_BASE

#define SPI1_BASE

#define SPI4_BASE

#define SYSCFG_BASE

#define EXTI_BASE

#define TIM9_BASE

#define TIM10_BASE

#define TIM11_BASE

#define SPI5_BASE

#define SPI6_BASE

#define SAI1_BASE

#define SAI1_Block_A_BASE

#define SAI1_Block_B_BASE

#define LTDC_BASE

#define LTDC_Layer1_BASE

#define LTDC_Layer2_BASE

#define GPIOA_BASE

#define GPIOB_BASE

#define GPIOC_BASE

#define GPIOD_BASE

#define GPIOE_BASE

#define GPIOF_BASE

#define GPIOG_BASE

#define GPIOH_BASE

#define GPIOI_BASE

#define GPIOJ_BASE

#define GPIOK_BASE

#define CRC_BASE

#define RCC_BASE

#define FLASH_R_BASE

#define DMA1_BASE

#define DMA1_Stream0_BASE

#define DMA1_Stream1_BASE

#define DMA1_Stream2_BASE

#define DMA1_Stream3_BASE

#define DMA1_Stream4_BASE

#define DMA1_Stream5_BASE

#define DMA1_Stream6_BASE

#define DMA1_Stream7_BASE

#define DMA2_BASE

#define DMA2_Stream0_BASE

#define DMA2_Stream1_BASE

#define DMA2_Stream2_BASE

#define DMA2_Stream3_BASE

#define DMA2_Stream4_BASE

#define DMA2_Stream5_BASE

#define DMA2_Stream6_BASE

#define DMA2_Stream7_BASE

#define ETH_BASE

#define ETH_MAC_BASE

#define ETH_MMC_BASE

#define ETH_PTP_BASE

#define ETH_DMA_BASE

#define DMA2D_BASE

#define DCMI_BASE

#define RNG_BASE

#define FMC_Bank1_R_BASE

#define FMC_Bank1E_R_BASE

#define FMC_Bank2_3_R_BASE

#define FMC_Bank4_R_BASE

#define FMC_Bank5_6_R_BASE

#define DBGMCU_BASE

#define USB_OTG_HS_PERIPH_BASE

#define USB_OTG_FS_PERIPH_BASE

#define USB_OTG_GLOBAL_BASE

#define USB_OTG_DEVICE_BASE

#define USB_OTG_IN_ENDPOINT_BASE

#define USB_OTG_OUT_ENDPOINT_BASE

#define USB_OTG_EP_REG_SIZE

#define USB_OTG_HOST_BASE

#define USB_OTG_HOST_PORT_BASE

#define USB_OTG_HOST_CHANNEL_BASE

#define USB_OTG_HOST_CHANNEL_SIZE

#define USB_OTG_PCGCCTL_BASE

#define USB_OTG_FIFO_BASE

#define USB_OTG_FIFO_SIZE

#define UID_BASE

#define FLASHSIZE_BASE

#define PACKAGE_BASE

#define TIM2

#define TIM3

#define TIM4

#define TIM5

#define TIM6

#define TIM7

#define TIM12

#define TIM13

#define TIM14

#define RTC

#define WWDG

#define IWDG

#define I2S2ext

#define SPI2

#define SPI3

#define I2S3ext

#define USART2

#define USART3

#define UART4

#define UART5

#define I2C1

#define I2C2

#define I2C3

#define CAN1

#define CAN2

#define PWR

#define DAC1

#define DAC

#define UART7

#define UART8

#define TIM1

#define TIM8

#define USART1

#define USART6

#define ADC1

#define ADC2

#define ADC3

#define ADC123_COMMON

#define ADC

#define SDIO

#define SPI1

#define SPI4

#define SYSCFG

#define EXTI

#define TIM9

#define TIM10

#define TIM11

#define SPI5

#define SPI6

#define SAI1

#define SAI1_Block_A

#define SAI1_Block_B

#define LTDC

#define LTDC_Layer1

#define LTDC_Layer2

#define GPIOA

#define GPIOB

#define GPIOC

#define GPIOD

#define GPIOE

#define GPIOF

#define GPIOG

#define GPIOH

#define GPIOI

#define GPIOJ

#define GPIOK

#define CRC

#define RCC

#define FLASH

#define DMA1

#define DMA1_Stream0

#define DMA1_Stream1

#define DMA1_Stream2

#define DMA1_Stream3

#define DMA1_Stream4

#define DMA1_Stream5

#define DMA1_Stream6

#define DMA1_Stream7

#define DMA2

#define DMA2_Stream0

#define DMA2_Stream1

#define DMA2_Stream2

#define DMA2_Stream3

#define DMA2_Stream4

#define DMA2_Stream5

#define DMA2_Stream6

#define DMA2_Stream7

#define ETH

#define DMA2D

#define DCMI

#define RNG

#define FMC_Bank1

#define FMC_Bank1E

#define FMC_Bank2_3

#define FMC_Bank4

#define FMC_Bank5_6

#define DBGMCU

#define USB_OTG_FS

#define USB_OTG_HS

#define LSI_STARTUP_TIME

...

#define ADC_MULTIMODE_SUPPORT

Bit definition for ADC_SR register

#define ADC_SR_AWD_Pos

#define ADC_SR_AWD_Msk

#define ADC_SR_AWD

#define ADC_SR_EOC_Pos

#define ADC_SR_EOC_Msk

#define ADC_SR_EOC

#define ADC_SR_JEOC_Pos

#define ADC_SR_JEOC_Msk

#define ADC_SR_JEOC

#define ADC_SR_JSTRT_Pos

#define ADC_SR_JSTRT_Msk

#define ADC_SR_JSTRT

#define ADC_SR_STRT_Pos

#define ADC_SR_STRT_Msk

#define ADC_SR_STRT

#define ADC_SR_OVR_Pos

#define ADC_SR_OVR_Msk

#define ADC_SR_OVR

Bit definition for ADC_CR1 register

#define ADC_CR1_AWDCH_Pos

#define ADC_CR1_AWDCH_Msk

#define ADC_CR1_AWDCH

#define ADC_CR1_AWDCH_0

#define ADC_CR1_AWDCH_1

#define ADC_CR1_AWDCH_2

#define ADC_CR1_AWDCH_3

#define ADC_CR1_AWDCH_4

#define ADC_CR1_EOCIE_Pos

#define ADC_CR1_EOCIE_Msk

#define ADC_CR1_EOCIE

#define ADC_CR1_AWDIE_Pos

#define ADC_CR1_AWDIE_Msk

#define ADC_CR1_AWDIE

#define ADC_CR1_JEOCIE_Pos

#define ADC_CR1_JEOCIE_Msk

#define ADC_CR1_JEOCIE

#define ADC_CR1_SCAN_Pos

#define ADC_CR1_SCAN_Msk

#define ADC_CR1_SCAN

#define ADC_CR1_AWDSGL_Pos

#define ADC_CR1_AWDSGL_Msk

#define ADC_CR1_AWDSGL

#define ADC_CR1_JAUTO_Pos

#define ADC_CR1_JAUTO_Msk

#define ADC_CR1_JAUTO

#define ADC_CR1_DISCEN_Pos

#define ADC_CR1_DISCEN_Msk

#define ADC_CR1_DISCEN

#define ADC_CR1_JDISCEN_Pos

#define ADC_CR1_JDISCEN_Msk

#define ADC_CR1_JDISCEN

#define ADC_CR1_DISCNUM_Pos

#define ADC_CR1_DISCNUM_Msk

#define ADC_CR1_DISCNUM

#define ADC_CR1_DISCNUM_0

#define ADC_CR1_DISCNUM_1

#define ADC_CR1_DISCNUM_2

#define ADC_CR1_JAWDEN_Pos

#define ADC_CR1_JAWDEN_Msk

#define ADC_CR1_JAWDEN

#define ADC_CR1_AWDEN_Pos

#define ADC_CR1_AWDEN_Msk

#define ADC_CR1_AWDEN

#define ADC_CR1_RES_Pos

#define ADC_CR1_RES_Msk

#define ADC_CR1_RES

#define ADC_CR1_RES_0

#define ADC_CR1_RES_1

#define ADC_CR1_OVRIE_Pos

#define ADC_CR1_OVRIE_Msk

#define ADC_CR1_OVRIE

Bit definition for ADC_CR2 register

#define ADC_CR2_ADON_Pos

#define ADC_CR2_ADON_Msk

#define ADC_CR2_ADON

#define ADC_CR2_CONT_Pos

#define ADC_CR2_CONT_Msk

#define ADC_CR2_CONT

#define ADC_CR2_DMA_Pos

#define ADC_CR2_DMA_Msk

#define ADC_CR2_DMA

#define ADC_CR2_DDS_Pos

#define ADC_CR2_DDS_Msk

#define ADC_CR2_DDS

#define ADC_CR2_EOCS_Pos

#define ADC_CR2_EOCS_Msk

#define ADC_CR2_EOCS

#define ADC_CR2_ALIGN_Pos

#define ADC_CR2_ALIGN_Msk

#define ADC_CR2_ALIGN

#define ADC_CR2_JEXTSEL_Pos

#define ADC_CR2_JEXTSEL_Msk

#define ADC_CR2_JEXTSEL

#define ADC_CR2_JEXTSEL_0

#define ADC_CR2_JEXTSEL_1

#define ADC_CR2_JEXTSEL_2

#define ADC_CR2_JEXTSEL_3

#define ADC_CR2_JEXTEN_Pos

#define ADC_CR2_JEXTEN_Msk

#define ADC_CR2_JEXTEN

#define ADC_CR2_JEXTEN_0

#define ADC_CR2_JEXTEN_1

#define ADC_CR2_JSWSTART_Pos

#define ADC_CR2_JSWSTART_Msk

#define ADC_CR2_JSWSTART

#define ADC_CR2_EXTSEL_Pos

#define ADC_CR2_EXTSEL_Msk

#define ADC_CR2_EXTSEL

#define ADC_CR2_EXTSEL_0

#define ADC_CR2_EXTSEL_1

#define ADC_CR2_EXTSEL_2

#define ADC_CR2_EXTSEL_3

#define ADC_CR2_EXTEN_Pos

#define ADC_CR2_EXTEN_Msk

#define ADC_CR2_EXTEN

#define ADC_CR2_EXTEN_0

#define ADC_CR2_EXTEN_1

#define ADC_CR2_SWSTART_Pos

#define ADC_CR2_SWSTART_Msk

#define ADC_CR2_SWSTART

Bit definition for ADC_SMPR1 register

#define ADC_SMPR1_SMP10_Pos

#define ADC_SMPR1_SMP10_Msk

#define ADC_SMPR1_SMP10

#define ADC_SMPR1_SMP10_0

#define ADC_SMPR1_SMP10_1

#define ADC_SMPR1_SMP10_2

#define ADC_SMPR1_SMP11_Pos

#define ADC_SMPR1_SMP11_Msk

#define ADC_SMPR1_SMP11

#define ADC_SMPR1_SMP11_0

#define ADC_SMPR1_SMP11_1

#define ADC_SMPR1_SMP11_2

#define ADC_SMPR1_SMP12_Pos

#define ADC_SMPR1_SMP12_Msk

#define ADC_SMPR1_SMP12

#define ADC_SMPR1_SMP12_0

#define ADC_SMPR1_SMP12_1

#define ADC_SMPR1_SMP12_2

#define ADC_SMPR1_SMP13_Pos

#define ADC_SMPR1_SMP13_Msk

#define ADC_SMPR1_SMP13

#define ADC_SMPR1_SMP13_0

#define ADC_SMPR1_SMP13_1

#define ADC_SMPR1_SMP13_2

#define ADC_SMPR1_SMP14_Pos

#define ADC_SMPR1_SMP14_Msk

#define ADC_SMPR1_SMP14

#define ADC_SMPR1_SMP14_0

#define ADC_SMPR1_SMP14_1

#define ADC_SMPR1_SMP14_2

#define ADC_SMPR1_SMP15_Pos

#define ADC_SMPR1_SMP15_Msk

#define ADC_SMPR1_SMP15

#define ADC_SMPR1_SMP15_0

#define ADC_SMPR1_SMP15_1

#define ADC_SMPR1_SMP15_2

#define ADC_SMPR1_SMP16_Pos

#define ADC_SMPR1_SMP16_Msk

#define ADC_SMPR1_SMP16

#define ADC_SMPR1_SMP16_0

#define ADC_SMPR1_SMP16_1

#define ADC_SMPR1_SMP16_2

#define ADC_SMPR1_SMP17_Pos

#define ADC_SMPR1_SMP17_Msk

#define ADC_SMPR1_SMP17

#define ADC_SMPR1_SMP17_0

#define ADC_SMPR1_SMP17_1

#define ADC_SMPR1_SMP17_2

#define ADC_SMPR1_SMP18_Pos

#define ADC_SMPR1_SMP18_Msk

#define ADC_SMPR1_SMP18

#define ADC_SMPR1_SMP18_0

#define ADC_SMPR1_SMP18_1

#define ADC_SMPR1_SMP18_2

Bit definition for ADC_SMPR2 register

#define ADC_SMPR2_SMP0_Pos

#define ADC_SMPR2_SMP0_Msk

#define ADC_SMPR2_SMP0

#define ADC_SMPR2_SMP0_0

#define ADC_SMPR2_SMP0_1

#define ADC_SMPR2_SMP0_2

#define ADC_SMPR2_SMP1_Pos

#define ADC_SMPR2_SMP1_Msk

#define ADC_SMPR2_SMP1

#define ADC_SMPR2_SMP1_0

#define ADC_SMPR2_SMP1_1

#define ADC_SMPR2_SMP1_2

#define ADC_SMPR2_SMP2_Pos

#define ADC_SMPR2_SMP2_Msk

#define ADC_SMPR2_SMP2

#define ADC_SMPR2_SMP2_0

#define ADC_SMPR2_SMP2_1

#define ADC_SMPR2_SMP2_2

#define ADC_SMPR2_SMP3_Pos

#define ADC_SMPR2_SMP3_Msk

#define ADC_SMPR2_SMP3

#define ADC_SMPR2_SMP3_0

#define ADC_SMPR2_SMP3_1

#define ADC_SMPR2_SMP3_2

#define ADC_SMPR2_SMP4_Pos

#define ADC_SMPR2_SMP4_Msk

#define ADC_SMPR2_SMP4

#define ADC_SMPR2_SMP4_0

#define ADC_SMPR2_SMP4_1

#define ADC_SMPR2_SMP4_2

#define ADC_SMPR2_SMP5_Pos

#define ADC_SMPR2_SMP5_Msk

#define ADC_SMPR2_SMP5

#define ADC_SMPR2_SMP5_0

#define ADC_SMPR2_SMP5_1

#define ADC_SMPR2_SMP5_2

#define ADC_SMPR2_SMP6_Pos

#define ADC_SMPR2_SMP6_Msk

#define ADC_SMPR2_SMP6

#define ADC_SMPR2_SMP6_0

#define ADC_SMPR2_SMP6_1

#define ADC_SMPR2_SMP6_2

#define ADC_SMPR2_SMP7_Pos

#define ADC_SMPR2_SMP7_Msk

#define ADC_SMPR2_SMP7

#define ADC_SMPR2_SMP7_0

#define ADC_SMPR2_SMP7_1

#define ADC_SMPR2_SMP7_2

#define ADC_SMPR2_SMP8_Pos

#define ADC_SMPR2_SMP8_Msk

#define ADC_SMPR2_SMP8

#define ADC_SMPR2_SMP8_0

#define ADC_SMPR2_SMP8_1

#define ADC_SMPR2_SMP8_2

#define ADC_SMPR2_SMP9_Pos

#define ADC_SMPR2_SMP9_Msk

#define ADC_SMPR2_SMP9

#define ADC_SMPR2_SMP9_0

#define ADC_SMPR2_SMP9_1

#define ADC_SMPR2_SMP9_2

Bit definition for ADC_JOFR1 register

#define ADC_JOFR1_JOFFSET1_Pos

#define ADC_JOFR1_JOFFSET1_Msk

#define ADC_JOFR1_JOFFSET1

Bit definition for ADC_JOFR2 register

#define ADC_JOFR2_JOFFSET2_Pos

#define ADC_JOFR2_JOFFSET2_Msk

#define ADC_JOFR2_JOFFSET2

Bit definition for ADC_JOFR3 register

#define ADC_JOFR3_JOFFSET3_Pos

#define ADC_JOFR3_JOFFSET3_Msk

#define ADC_JOFR3_JOFFSET3

Bit definition for ADC_JOFR4 register

#define ADC_JOFR4_JOFFSET4_Pos

#define ADC_JOFR4_JOFFSET4_Msk

#define ADC_JOFR4_JOFFSET4

Bit definition for ADC_HTR register

#define ADC_HTR_HT_Pos

#define ADC_HTR_HT_Msk

#define ADC_HTR_HT

Bit definition for ADC_LTR register

#define ADC_LTR_LT_Pos

#define ADC_LTR_LT_Msk

#define ADC_LTR_LT

Bit definition for ADC_SQR1 register

#define ADC_SQR1_SQ13_Pos

#define ADC_SQR1_SQ13_Msk

#define ADC_SQR1_SQ13

#define ADC_SQR1_SQ13_0

#define ADC_SQR1_SQ13_1

#define ADC_SQR1_SQ13_2

#define ADC_SQR1_SQ13_3

#define ADC_SQR1_SQ13_4

#define ADC_SQR1_SQ14_Pos

#define ADC_SQR1_SQ14_Msk

#define ADC_SQR1_SQ14

#define ADC_SQR1_SQ14_0

#define ADC_SQR1_SQ14_1

#define ADC_SQR1_SQ14_2

#define ADC_SQR1_SQ14_3

#define ADC_SQR1_SQ14_4

#define ADC_SQR1_SQ15_Pos

#define ADC_SQR1_SQ15_Msk

#define ADC_SQR1_SQ15

#define ADC_SQR1_SQ15_0

#define ADC_SQR1_SQ15_1

#define ADC_SQR1_SQ15_2

#define ADC_SQR1_SQ15_3

#define ADC_SQR1_SQ15_4

#define ADC_SQR1_SQ16_Pos

#define ADC_SQR1_SQ16_Msk

#define ADC_SQR1_SQ16

#define ADC_SQR1_SQ16_0

#define ADC_SQR1_SQ16_1

#define ADC_SQR1_SQ16_2

#define ADC_SQR1_SQ16_3

#define ADC_SQR1_SQ16_4

#define ADC_SQR1_L_Pos

#define ADC_SQR1_L_Msk

#define ADC_SQR1_L

#define ADC_SQR1_L_0

#define ADC_SQR1_L_1

#define ADC_SQR1_L_2

#define ADC_SQR1_L_3

Bit definition for ADC_SQR2 register

#define ADC_SQR2_SQ7_Pos

#define ADC_SQR2_SQ7_Msk

#define ADC_SQR2_SQ7

#define ADC_SQR2_SQ7_0

#define ADC_SQR2_SQ7_1

#define ADC_SQR2_SQ7_2

#define ADC_SQR2_SQ7_3

#define ADC_SQR2_SQ7_4

#define ADC_SQR2_SQ8_Pos

#define ADC_SQR2_SQ8_Msk

#define ADC_SQR2_SQ8

#define ADC_SQR2_SQ8_0

#define ADC_SQR2_SQ8_1

#define ADC_SQR2_SQ8_2

#define ADC_SQR2_SQ8_3

#define ADC_SQR2_SQ8_4

#define ADC_SQR2_SQ9_Pos

#define ADC_SQR2_SQ9_Msk

#define ADC_SQR2_SQ9

#define ADC_SQR2_SQ9_0

#define ADC_SQR2_SQ9_1

#define ADC_SQR2_SQ9_2

#define ADC_SQR2_SQ9_3

#define ADC_SQR2_SQ9_4

#define ADC_SQR2_SQ10_Pos

#define ADC_SQR2_SQ10_Msk

#define ADC_SQR2_SQ10

#define ADC_SQR2_SQ10_0

#define ADC_SQR2_SQ10_1

#define ADC_SQR2_SQ10_2

#define ADC_SQR2_SQ10_3

#define ADC_SQR2_SQ10_4

#define ADC_SQR2_SQ11_Pos

#define ADC_SQR2_SQ11_Msk

#define ADC_SQR2_SQ11

#define ADC_SQR2_SQ11_0

#define ADC_SQR2_SQ11_1

#define ADC_SQR2_SQ11_2

#define ADC_SQR2_SQ11_3

#define ADC_SQR2_SQ11_4

#define ADC_SQR2_SQ12_Pos

#define ADC_SQR2_SQ12_Msk

#define ADC_SQR2_SQ12

#define ADC_SQR2_SQ12_0

#define ADC_SQR2_SQ12_1

#define ADC_SQR2_SQ12_2

#define ADC_SQR2_SQ12_3

#define ADC_SQR2_SQ12_4

Bit definition for ADC_SQR3 register

#define ADC_SQR3_SQ1_Pos

#define ADC_SQR3_SQ1_Msk

#define ADC_SQR3_SQ1

#define ADC_SQR3_SQ1_0

#define ADC_SQR3_SQ1_1

#define ADC_SQR3_SQ1_2

#define ADC_SQR3_SQ1_3

#define ADC_SQR3_SQ1_4

#define ADC_SQR3_SQ2_Pos

#define ADC_SQR3_SQ2_Msk

#define ADC_SQR3_SQ2

#define ADC_SQR3_SQ2_0

#define ADC_SQR3_SQ2_1

#define ADC_SQR3_SQ2_2

#define ADC_SQR3_SQ2_3

#define ADC_SQR3_SQ2_4

#define ADC_SQR3_SQ3_Pos

#define ADC_SQR3_SQ3_Msk

#define ADC_SQR3_SQ3

#define ADC_SQR3_SQ3_0

#define ADC_SQR3_SQ3_1

#define ADC_SQR3_SQ3_2

#define ADC_SQR3_SQ3_3

#define ADC_SQR3_SQ3_4

#define ADC_SQR3_SQ4_Pos

#define ADC_SQR3_SQ4_Msk

#define ADC_SQR3_SQ4

#define ADC_SQR3_SQ4_0

#define ADC_SQR3_SQ4_1

#define ADC_SQR3_SQ4_2

#define ADC_SQR3_SQ4_3

#define ADC_SQR3_SQ4_4

#define ADC_SQR3_SQ5_Pos

#define ADC_SQR3_SQ5_Msk

#define ADC_SQR3_SQ5

#define ADC_SQR3_SQ5_0

#define ADC_SQR3_SQ5_1

#define ADC_SQR3_SQ5_2

#define ADC_SQR3_SQ5_3

#define ADC_SQR3_SQ5_4

#define ADC_SQR3_SQ6_Pos

#define ADC_SQR3_SQ6_Msk

#define ADC_SQR3_SQ6

#define ADC_SQR3_SQ6_0

#define ADC_SQR3_SQ6_1

#define ADC_SQR3_SQ6_2

#define ADC_SQR3_SQ6_3

#define ADC_SQR3_SQ6_4

Bit definition for ADC_JSQR register

#define ADC_JSQR_JSQ1_Pos

#define ADC_JSQR_JSQ1_Msk

#define ADC_JSQR_JSQ1

#define ADC_JSQR_JSQ1_0

#define ADC_JSQR_JSQ1_1

#define ADC_JSQR_JSQ1_2

#define ADC_JSQR_JSQ1_3

#define ADC_JSQR_JSQ1_4

#define ADC_JSQR_JSQ2_Pos

#define ADC_JSQR_JSQ2_Msk

#define ADC_JSQR_JSQ2

#define ADC_JSQR_JSQ2_0

#define ADC_JSQR_JSQ2_1

#define ADC_JSQR_JSQ2_2

#define ADC_JSQR_JSQ2_3

#define ADC_JSQR_JSQ2_4

#define ADC_JSQR_JSQ3_Pos

#define ADC_JSQR_JSQ3_Msk

#define ADC_JSQR_JSQ3

#define ADC_JSQR_JSQ3_0

#define ADC_JSQR_JSQ3_1

#define ADC_JSQR_JSQ3_2

#define ADC_JSQR_JSQ3_3

#define ADC_JSQR_JSQ3_4

#define ADC_JSQR_JSQ4_Pos

#define ADC_JSQR_JSQ4_Msk

#define ADC_JSQR_JSQ4

#define ADC_JSQR_JSQ4_0

#define ADC_JSQR_JSQ4_1

#define ADC_JSQR_JSQ4_2

#define ADC_JSQR_JSQ4_3

#define ADC_JSQR_JSQ4_4

#define ADC_JSQR_JL_Pos

#define ADC_JSQR_JL_Msk

#define ADC_JSQR_JL

#define ADC_JSQR_JL_0

#define ADC_JSQR_JL_1

Bit definition for ADC_JDR1 register

#define ADC_JDR1_JDATA_Pos

#define ADC_JDR1_JDATA_Msk

#define ADC_JDR1_JDATA

Bit definition for ADC_JDR2 register

#define ADC_JDR2_JDATA_Pos

#define ADC_JDR2_JDATA_Msk

#define ADC_JDR2_JDATA

Bit definition for ADC_JDR3 register

#define ADC_JDR3_JDATA_Pos

#define ADC_JDR3_JDATA_Msk

#define ADC_JDR3_JDATA

Bit definition for ADC_JDR4 register

#define ADC_JDR4_JDATA_Pos

#define ADC_JDR4_JDATA_Msk

#define ADC_JDR4_JDATA

Bit definition for ADC_DR register

#define ADC_DR_DATA_Pos

#define ADC_DR_DATA_Msk

#define ADC_DR_DATA

#define ADC_DR_ADC2DATA_Pos

#define ADC_DR_ADC2DATA_Msk

#define ADC_DR_ADC2DATA

Bit definition for ADC_CSR register

#define ADC_CSR_AWD1_Pos

#define ADC_CSR_AWD1_Msk

#define ADC_CSR_AWD1

#define ADC_CSR_EOC1_Pos

#define ADC_CSR_EOC1_Msk

#define ADC_CSR_EOC1

#define ADC_CSR_JEOC1_Pos

#define ADC_CSR_JEOC1_Msk

#define ADC_CSR_JEOC1

#define ADC_CSR_JSTRT1_Pos

#define ADC_CSR_JSTRT1_Msk

#define ADC_CSR_JSTRT1

#define ADC_CSR_STRT1_Pos

#define ADC_CSR_STRT1_Msk

#define ADC_CSR_STRT1

#define ADC_CSR_OVR1_Pos

#define ADC_CSR_OVR1_Msk

#define ADC_CSR_OVR1

#define ADC_CSR_AWD2_Pos

#define ADC_CSR_AWD2_Msk

#define ADC_CSR_AWD2

#define ADC_CSR_EOC2_Pos

#define ADC_CSR_EOC2_Msk

#define ADC_CSR_EOC2

#define ADC_CSR_JEOC2_Pos

#define ADC_CSR_JEOC2_Msk

#define ADC_CSR_JEOC2

#define ADC_CSR_JSTRT2_Pos

#define ADC_CSR_JSTRT2_Msk

#define ADC_CSR_JSTRT2

#define ADC_CSR_STRT2_Pos

#define ADC_CSR_STRT2_Msk

#define ADC_CSR_STRT2

#define ADC_CSR_OVR2_Pos

#define ADC_CSR_OVR2_Msk

#define ADC_CSR_OVR2

#define ADC_CSR_AWD3_Pos

#define ADC_CSR_AWD3_Msk

#define ADC_CSR_AWD3

#define ADC_CSR_EOC3_Pos

#define ADC_CSR_EOC3_Msk

#define ADC_CSR_EOC3

#define ADC_CSR_JEOC3_Pos

#define ADC_CSR_JEOC3_Msk

#define ADC_CSR_JEOC3

#define ADC_CSR_JSTRT3_Pos

#define ADC_CSR_JSTRT3_Msk

#define ADC_CSR_JSTRT3

#define ADC_CSR_STRT3_Pos

#define ADC_CSR_STRT3_Msk

#define ADC_CSR_STRT3

#define ADC_CSR_OVR3_Pos

#define ADC_CSR_OVR3_Msk

#define ADC_CSR_OVR3

#define ADC_CSR_DOVR1

#define ADC_CSR_DOVR2

#define ADC_CSR_DOVR3

Bit definition for ADC_CCR register

#define ADC_CCR_MULTI_Pos

#define ADC_CCR_MULTI_Msk

#define ADC_CCR_MULTI

#define ADC_CCR_MULTI_0

#define ADC_CCR_MULTI_1

#define ADC_CCR_MULTI_2

#define ADC_CCR_MULTI_3

#define ADC_CCR_MULTI_4

#define ADC_CCR_DELAY_Pos

#define ADC_CCR_DELAY_Msk

#define ADC_CCR_DELAY

#define ADC_CCR_DELAY_0

#define ADC_CCR_DELAY_1

#define ADC_CCR_DELAY_2

#define ADC_CCR_DELAY_3

#define ADC_CCR_DDS_Pos

#define ADC_CCR_DDS_Msk

#define ADC_CCR_DDS

#define ADC_CCR_DMA_Pos

#define ADC_CCR_DMA_Msk

#define ADC_CCR_DMA

#define ADC_CCR_DMA_0

#define ADC_CCR_DMA_1

#define ADC_CCR_ADCPRE_Pos

#define ADC_CCR_ADCPRE_Msk

#define ADC_CCR_ADCPRE

#define ADC_CCR_ADCPRE_0

#define ADC_CCR_ADCPRE_1

#define ADC_CCR_VBATE_Pos

#define ADC_CCR_VBATE_Msk

#define ADC_CCR_VBATE

#define ADC_CCR_TSVREFE_Pos

#define ADC_CCR_TSVREFE_Msk

#define ADC_CCR_TSVREFE

Bit definition for ADC_CDR register

#define ADC_CDR_DATA1_Pos

#define ADC_CDR_DATA1_Msk

#define ADC_CDR_DATA1

#define ADC_CDR_DATA2_Pos

#define ADC_CDR_DATA2_Msk

#define ADC_CDR_DATA2

#define ADC_CDR_RDATA_MST

#define ADC_CDR_RDATA_SLV

...

Bit definition for CAN_MCR register

#define CAN_MCR_INRQ_Pos

#define CAN_MCR_INRQ_Msk

#define CAN_MCR_INRQ

#define CAN_MCR_SLEEP_Pos

#define CAN_MCR_SLEEP_Msk

#define CAN_MCR_SLEEP

#define CAN_MCR_TXFP_Pos

#define CAN_MCR_TXFP_Msk

#define CAN_MCR_TXFP

#define CAN_MCR_RFLM_Pos

#define CAN_MCR_RFLM_Msk

#define CAN_MCR_RFLM

#define CAN_MCR_NART_Pos

#define CAN_MCR_NART_Msk

#define CAN_MCR_NART

#define CAN_MCR_AWUM_Pos

#define CAN_MCR_AWUM_Msk

#define CAN_MCR_AWUM

#define CAN_MCR_ABOM_Pos

#define CAN_MCR_ABOM_Msk

#define CAN_MCR_ABOM

#define CAN_MCR_TTCM_Pos

#define CAN_MCR_TTCM_Msk

#define CAN_MCR_TTCM

#define CAN_MCR_RESET_Pos

#define CAN_MCR_RESET_Msk

#define CAN_MCR_RESET

#define CAN_MCR_DBF_Pos

#define CAN_MCR_DBF_Msk

#define CAN_MCR_DBF

Bit definition for CAN_MSR register

#define CAN_MSR_INAK_Pos

#define CAN_MSR_INAK_Msk

#define CAN_MSR_INAK

#define CAN_MSR_SLAK_Pos

#define CAN_MSR_SLAK_Msk

#define CAN_MSR_SLAK

#define CAN_MSR_ERRI_Pos

#define CAN_MSR_ERRI_Msk

#define CAN_MSR_ERRI

#define CAN_MSR_WKUI_Pos

#define CAN_MSR_WKUI_Msk

#define CAN_MSR_WKUI

#define CAN_MSR_SLAKI_Pos

#define CAN_MSR_SLAKI_Msk

#define CAN_MSR_SLAKI

#define CAN_MSR_TXM_Pos

#define CAN_MSR_TXM_Msk

#define CAN_MSR_TXM

#define CAN_MSR_RXM_Pos

#define CAN_MSR_RXM_Msk

#define CAN_MSR_RXM

#define CAN_MSR_SAMP_Pos

#define CAN_MSR_SAMP_Msk

#define CAN_MSR_SAMP

#define CAN_MSR_RX_Pos

#define CAN_MSR_RX_Msk

#define CAN_MSR_RX

Bit definition for CAN_TSR register

#define CAN_TSR_RQCP0_Pos

#define CAN_TSR_RQCP0_Msk

#define CAN_TSR_RQCP0

#define CAN_TSR_TXOK0_Pos

#define CAN_TSR_TXOK0_Msk

#define CAN_TSR_TXOK0

#define CAN_TSR_ALST0_Pos

#define CAN_TSR_ALST0_Msk

#define CAN_TSR_ALST0

#define CAN_TSR_TERR0_Pos

#define CAN_TSR_TERR0_Msk

#define CAN_TSR_TERR0

#define CAN_TSR_ABRQ0_Pos

#define CAN_TSR_ABRQ0_Msk

#define CAN_TSR_ABRQ0

#define CAN_TSR_RQCP1_Pos

#define CAN_TSR_RQCP1_Msk

#define CAN_TSR_RQCP1

#define CAN_TSR_TXOK1_Pos

#define CAN_TSR_TXOK1_Msk

#define CAN_TSR_TXOK1

#define CAN_TSR_ALST1_Pos

#define CAN_TSR_ALST1_Msk

#define CAN_TSR_ALST1

#define CAN_TSR_TERR1_Pos

#define CAN_TSR_TERR1_Msk

#define CAN_TSR_TERR1

#define CAN_TSR_ABRQ1_Pos

#define CAN_TSR_ABRQ1_Msk

#define CAN_TSR_ABRQ1

#define CAN_TSR_RQCP2_Pos

#define CAN_TSR_RQCP2_Msk

#define CAN_TSR_RQCP2

#define CAN_TSR_TXOK2_Pos

#define CAN_TSR_TXOK2_Msk

#define CAN_TSR_TXOK2

#define CAN_TSR_ALST2_Pos

#define CAN_TSR_ALST2_Msk

#define CAN_TSR_ALST2

#define CAN_TSR_TERR2_Pos

#define CAN_TSR_TERR2_Msk

#define CAN_TSR_TERR2

#define CAN_TSR_ABRQ2_Pos

#define CAN_TSR_ABRQ2_Msk

#define CAN_TSR_ABRQ2

#define CAN_TSR_CODE_Pos

#define CAN_TSR_CODE_Msk

#define CAN_TSR_CODE

#define CAN_TSR_TME_Pos

#define CAN_TSR_TME_Msk

#define CAN_TSR_TME

#define CAN_TSR_TME0_Pos

#define CAN_TSR_TME0_Msk

#define CAN_TSR_TME0

#define CAN_TSR_TME1_Pos

#define CAN_TSR_TME1_Msk

#define CAN_TSR_TME1

#define CAN_TSR_TME2_Pos

#define CAN_TSR_TME2_Msk

#define CAN_TSR_TME2

#define CAN_TSR_LOW_Pos

#define CAN_TSR_LOW_Msk

#define CAN_TSR_LOW

#define CAN_TSR_LOW0_Pos

#define CAN_TSR_LOW0_Msk

#define CAN_TSR_LOW0

#define CAN_TSR_LOW1_Pos

#define CAN_TSR_LOW1_Msk

#define CAN_TSR_LOW1

#define CAN_TSR_LOW2_Pos

#define CAN_TSR_LOW2_Msk

#define CAN_TSR_LOW2

Bit definition for CAN_RF0R register

#define CAN_RF0R_FMP0_Pos

#define CAN_RF0R_FMP0_Msk

#define CAN_RF0R_FMP0

#define CAN_RF0R_FULL0_Pos

#define CAN_RF0R_FULL0_Msk

#define CAN_RF0R_FULL0

#define CAN_RF0R_FOVR0_Pos

#define CAN_RF0R_FOVR0_Msk

#define CAN_RF0R_FOVR0

#define CAN_RF0R_RFOM0_Pos

#define CAN_RF0R_RFOM0_Msk

#define CAN_RF0R_RFOM0

Bit definition for CAN_RF1R register

#define CAN_RF1R_FMP1_Pos

#define CAN_RF1R_FMP1_Msk

#define CAN_RF1R_FMP1

#define CAN_RF1R_FULL1_Pos

#define CAN_RF1R_FULL1_Msk

#define CAN_RF1R_FULL1

#define CAN_RF1R_FOVR1_Pos

#define CAN_RF1R_FOVR1_Msk

#define CAN_RF1R_FOVR1

#define CAN_RF1R_RFOM1_Pos

#define CAN_RF1R_RFOM1_Msk

#define CAN_RF1R_RFOM1

Bit definition for CAN_IER register

#define CAN_IER_TMEIE_Pos

#define CAN_IER_TMEIE_Msk

#define CAN_IER_TMEIE

#define CAN_IER_FMPIE0_Pos

#define CAN_IER_FMPIE0_Msk

#define CAN_IER_FMPIE0

#define CAN_IER_FFIE0_Pos

#define CAN_IER_FFIE0_Msk

#define CAN_IER_FFIE0

#define CAN_IER_FOVIE0_Pos

#define CAN_IER_FOVIE0_Msk

#define CAN_IER_FOVIE0

#define CAN_IER_FMPIE1_Pos

#define CAN_IER_FMPIE1_Msk

#define CAN_IER_FMPIE1

#define CAN_IER_FFIE1_Pos

#define CAN_IER_FFIE1_Msk

#define CAN_IER_FFIE1

#define CAN_IER_FOVIE1_Pos

#define CAN_IER_FOVIE1_Msk

#define CAN_IER_FOVIE1

#define CAN_IER_EWGIE_Pos

#define CAN_IER_EWGIE_Msk

#define CAN_IER_EWGIE

#define CAN_IER_EPVIE_Pos

#define CAN_IER_EPVIE_Msk

#define CAN_IER_EPVIE

#define CAN_IER_BOFIE_Pos

#define CAN_IER_BOFIE_Msk

#define CAN_IER_BOFIE

#define CAN_IER_LECIE_Pos

#define CAN_IER_LECIE_Msk

#define CAN_IER_LECIE

#define CAN_IER_ERRIE_Pos

#define CAN_IER_ERRIE_Msk

#define CAN_IER_ERRIE

#define CAN_IER_WKUIE_Pos

#define CAN_IER_WKUIE_Msk

#define CAN_IER_WKUIE

#define CAN_IER_SLKIE_Pos

#define CAN_IER_SLKIE_Msk

#define CAN_IER_SLKIE

#define CAN_IER_EWGIE_Pos

Bit definition for CAN_ESR register

#define CAN_ESR_EWGF_Pos

#define CAN_ESR_EWGF_Msk

#define CAN_ESR_EWGF

#define CAN_ESR_EPVF_Pos

#define CAN_ESR_EPVF_Msk

#define CAN_ESR_EPVF

#define CAN_ESR_BOFF_Pos

#define CAN_ESR_BOFF_Msk

#define CAN_ESR_BOFF

#define CAN_ESR_LEC_Pos

#define CAN_ESR_LEC_Msk

#define CAN_ESR_LEC

#define CAN_ESR_LEC_0

#define CAN_ESR_LEC_1

#define CAN_ESR_LEC_2

#define CAN_ESR_TEC_Pos

#define CAN_ESR_TEC_Msk

#define CAN_ESR_TEC

#define CAN_ESR_REC_Pos

#define CAN_ESR_REC_Msk

#define CAN_ESR_REC

Bit definition for CAN_BTR register

#define CAN_BTR_BRP_Pos

#define CAN_BTR_BRP_Msk

#define CAN_BTR_BRP

#define CAN_BTR_TS1_Pos

#define CAN_BTR_TS1_Msk

#define CAN_BTR_TS1

#define CAN_BTR_TS1_0

#define CAN_BTR_TS1_1

#define CAN_BTR_TS1_2

#define CAN_BTR_TS1_3

#define CAN_BTR_TS2_Pos

#define CAN_BTR_TS2_Msk

#define CAN_BTR_TS2

#define CAN_BTR_TS2_0

#define CAN_BTR_TS2_1

#define CAN_BTR_TS2_2

#define CAN_BTR_SJW_Pos

#define CAN_BTR_SJW_Msk

#define CAN_BTR_SJW

#define CAN_BTR_SJW_0

#define CAN_BTR_SJW_1

#define CAN_BTR_LBKM_Pos

#define CAN_BTR_LBKM_Msk

#define CAN_BTR_LBKM

#define CAN_BTR_SILM_Pos

#define CAN_BTR_SILM_Msk

#define CAN_BTR_SILM

Bit definition for CAN_TI0R register

#define CAN_TI0R_TXRQ_Pos

#define CAN_TI0R_TXRQ_Msk

#define CAN_TI0R_TXRQ

#define CAN_TI0R_RTR_Pos

#define CAN_TI0R_RTR_Msk

#define CAN_TI0R_RTR

#define CAN_TI0R_IDE_Pos

#define CAN_TI0R_IDE_Msk

#define CAN_TI0R_IDE

#define CAN_TI0R_EXID_Pos

#define CAN_TI0R_EXID_Msk

#define CAN_TI0R_EXID

#define CAN_TI0R_STID_Pos

#define CAN_TI0R_STID_Msk

#define CAN_TI0R_STID

Bit definition for CAN_TDT0R register

#define CAN_TDT0R_DLC_Pos

#define CAN_TDT0R_DLC_Msk

#define CAN_TDT0R_DLC

#define CAN_TDT0R_TGT_Pos

#define CAN_TDT0R_TGT_Msk

#define CAN_TDT0R_TGT

#define CAN_TDT0R_TIME_Pos

#define CAN_TDT0R_TIME_Msk

#define CAN_TDT0R_TIME

Bit definition for CAN_TDL0R register

#define CAN_TDL0R_DATA0_Pos

#define CAN_TDL0R_DATA0_Msk

#define CAN_TDL0R_DATA0

#define CAN_TDL0R_DATA1_Pos

#define CAN_TDL0R_DATA1_Msk

#define CAN_TDL0R_DATA1

#define CAN_TDL0R_DATA2_Pos

#define CAN_TDL0R_DATA2_Msk

#define CAN_TDL0R_DATA2

#define CAN_TDL0R_DATA3_Pos

#define CAN_TDL0R_DATA3_Msk

#define CAN_TDL0R_DATA3

Bit definition for CAN_TDH0R register

#define CAN_TDH0R_DATA4_Pos

#define CAN_TDH0R_DATA4_Msk

#define CAN_TDH0R_DATA4

#define CAN_TDH0R_DATA5_Pos

#define CAN_TDH0R_DATA5_Msk

#define CAN_TDH0R_DATA5

#define CAN_TDH0R_DATA6_Pos

#define CAN_TDH0R_DATA6_Msk

#define CAN_TDH0R_DATA6

#define CAN_TDH0R_DATA7_Pos

#define CAN_TDH0R_DATA7_Msk

#define CAN_TDH0R_DATA7

Bit definition for CAN_TI1R register

#define CAN_TI1R_TXRQ_Pos

#define CAN_TI1R_TXRQ_Msk

#define CAN_TI1R_TXRQ

#define CAN_TI1R_RTR_Pos

#define CAN_TI1R_RTR_Msk

#define CAN_TI1R_RTR

#define CAN_TI1R_IDE_Pos

#define CAN_TI1R_IDE_Msk

#define CAN_TI1R_IDE

#define CAN_TI1R_EXID_Pos

#define CAN_TI1R_EXID_Msk

#define CAN_TI1R_EXID

#define CAN_TI1R_STID_Pos

#define CAN_TI1R_STID_Msk

#define CAN_TI1R_STID

Bit definition for CAN_TDT1R register

#define CAN_TDT1R_DLC_Pos

#define CAN_TDT1R_DLC_Msk

#define CAN_TDT1R_DLC

#define CAN_TDT1R_TGT_Pos

#define CAN_TDT1R_TGT_Msk

#define CAN_TDT1R_TGT

#define CAN_TDT1R_TIME_Pos

#define CAN_TDT1R_TIME_Msk

#define CAN_TDT1R_TIME

Bit definition for CAN_TDL1R register

#define CAN_TDL1R_DATA0_Pos

#define CAN_TDL1R_DATA0_Msk

#define CAN_TDL1R_DATA0

#define CAN_TDL1R_DATA1_Pos

#define CAN_TDL1R_DATA1_Msk

#define CAN_TDL1R_DATA1

#define CAN_TDL1R_DATA2_Pos

#define CAN_TDL1R_DATA2_Msk

#define CAN_TDL1R_DATA2

#define CAN_TDL1R_DATA3_Pos

#define CAN_TDL1R_DATA3_Msk

#define CAN_TDL1R_DATA3

Bit definition for CAN_TDH1R register

#define CAN_TDH1R_DATA4_Pos

#define CAN_TDH1R_DATA4_Msk

#define CAN_TDH1R_DATA4

#define CAN_TDH1R_DATA5_Pos

#define CAN_TDH1R_DATA5_Msk

#define CAN_TDH1R_DATA5

#define CAN_TDH1R_DATA6_Pos

#define CAN_TDH1R_DATA6_Msk

#define CAN_TDH1R_DATA6

#define CAN_TDH1R_DATA7_Pos

#define CAN_TDH1R_DATA7_Msk

#define CAN_TDH1R_DATA7

Bit definition for CAN_TI2R register

#define CAN_TI2R_TXRQ_Pos

#define CAN_TI2R_TXRQ_Msk

#define CAN_TI2R_TXRQ

#define CAN_TI2R_RTR_Pos

#define CAN_TI2R_RTR_Msk

#define CAN_TI2R_RTR

#define CAN_TI2R_IDE_Pos

#define CAN_TI2R_IDE_Msk

#define CAN_TI2R_IDE

#define CAN_TI2R_EXID_Pos

#define CAN_TI2R_EXID_Msk

#define CAN_TI2R_EXID

#define CAN_TI2R_STID_Pos

#define CAN_TI2R_STID_Msk

#define CAN_TI2R_STID

Bit definition for CAN_TDT2R register

#define CAN_TDT2R_DLC_Pos

#define CAN_TDT2R_DLC_Msk

#define CAN_TDT2R_DLC

#define CAN_TDT2R_TGT_Pos

#define CAN_TDT2R_TGT_Msk

#define CAN_TDT2R_TGT

#define CAN_TDT2R_TIME_Pos

#define CAN_TDT2R_TIME_Msk

#define CAN_TDT2R_TIME

Bit definition for CAN_TDL2R register

#define CAN_TDL2R_DATA0_Pos

#define CAN_TDL2R_DATA0_Msk

#define CAN_TDL2R_DATA0

#define CAN_TDL2R_DATA1_Pos

#define CAN_TDL2R_DATA1_Msk

#define CAN_TDL2R_DATA1

#define CAN_TDL2R_DATA2_Pos

#define CAN_TDL2R_DATA2_Msk

#define CAN_TDL2R_DATA2

#define CAN_TDL2R_DATA3_Pos

#define CAN_TDL2R_DATA3_Msk

#define CAN_TDL2R_DATA3

Bit definition for CAN_TDH2R register

#define CAN_TDH2R_DATA4_Pos

#define CAN_TDH2R_DATA4_Msk

#define CAN_TDH2R_DATA4

#define CAN_TDH2R_DATA5_Pos

#define CAN_TDH2R_DATA5_Msk

#define CAN_TDH2R_DATA5

#define CAN_TDH2R_DATA6_Pos

#define CAN_TDH2R_DATA6_Msk

#define CAN_TDH2R_DATA6

#define CAN_TDH2R_DATA7_Pos

#define CAN_TDH2R_DATA7_Msk

#define CAN_TDH2R_DATA7

Bit definition for CAN_RI0R register

#define CAN_RI0R_RTR_Pos

#define CAN_RI0R_RTR_Msk

#define CAN_RI0R_RTR

#define CAN_RI0R_IDE_Pos

#define CAN_RI0R_IDE_Msk

#define CAN_RI0R_IDE

#define CAN_RI0R_EXID_Pos

#define CAN_RI0R_EXID_Msk

#define CAN_RI0R_EXID

#define CAN_RI0R_STID_Pos

#define CAN_RI0R_STID_Msk

#define CAN_RI0R_STID

Bit definition for CAN_RDT0R register

#define CAN_RDT0R_DLC_Pos

#define CAN_RDT0R_DLC_Msk

#define CAN_RDT0R_DLC

#define CAN_RDT0R_FMI_Pos

#define CAN_RDT0R_FMI_Msk

#define CAN_RDT0R_FMI

#define CAN_RDT0R_TIME_Pos

#define CAN_RDT0R_TIME_Msk

#define CAN_RDT0R_TIME

Bit definition for CAN_RDL0R register

#define CAN_RDL0R_DATA0_Pos

#define CAN_RDL0R_DATA0_Msk

#define CAN_RDL0R_DATA0

#define CAN_RDL0R_DATA1_Pos

#define CAN_RDL0R_DATA1_Msk

#define CAN_RDL0R_DATA1

#define CAN_RDL0R_DATA2_Pos

#define CAN_RDL0R_DATA2_Msk

#define CAN_RDL0R_DATA2

#define CAN_RDL0R_DATA3_Pos

#define CAN_RDL0R_DATA3_Msk

#define CAN_RDL0R_DATA3

Bit definition for CAN_RDH0R register

#define CAN_RDH0R_DATA4_Pos

#define CAN_RDH0R_DATA4_Msk

#define CAN_RDH0R_DATA4

#define CAN_RDH0R_DATA5_Pos

#define CAN_RDH0R_DATA5_Msk

#define CAN_RDH0R_DATA5

#define CAN_RDH0R_DATA6_Pos

#define CAN_RDH0R_DATA6_Msk

#define CAN_RDH0R_DATA6

#define CAN_RDH0R_DATA7_Pos

#define CAN_RDH0R_DATA7_Msk

#define CAN_RDH0R_DATA7

Bit definition for CAN_RI1R register

#define CAN_RI1R_RTR_Pos

#define CAN_RI1R_RTR_Msk

#define CAN_RI1R_RTR

#define CAN_RI1R_IDE_Pos

#define CAN_RI1R_IDE_Msk

#define CAN_RI1R_IDE

#define CAN_RI1R_EXID_Pos

#define CAN_RI1R_EXID_Msk

#define CAN_RI1R_EXID

#define CAN_RI1R_STID_Pos

#define CAN_RI1R_STID_Msk

#define CAN_RI1R_STID

Bit definition for CAN_RDT1R register

#define CAN_RDT1R_DLC_Pos

#define CAN_RDT1R_DLC_Msk

#define CAN_RDT1R_DLC

#define CAN_RDT1R_FMI_Pos

#define CAN_RDT1R_FMI_Msk

#define CAN_RDT1R_FMI

#define CAN_RDT1R_TIME_Pos

#define CAN_RDT1R_TIME_Msk

#define CAN_RDT1R_TIME

Bit definition for CAN_RDL1R register

#define CAN_RDL1R_DATA0_Pos

#define CAN_RDL1R_DATA0_Msk

#define CAN_RDL1R_DATA0

#define CAN_RDL1R_DATA1_Pos

#define CAN_RDL1R_DATA1_Msk

#define CAN_RDL1R_DATA1

#define CAN_RDL1R_DATA2_Pos

#define CAN_RDL1R_DATA2_Msk

#define CAN_RDL1R_DATA2

#define CAN_RDL1R_DATA3_Pos

#define CAN_RDL1R_DATA3_Msk

#define CAN_RDL1R_DATA3

Bit definition for CAN_RDH1R register

#define CAN_RDH1R_DATA4_Pos

#define CAN_RDH1R_DATA4_Msk

#define CAN_RDH1R_DATA4

#define CAN_RDH1R_DATA5_Pos

#define CAN_RDH1R_DATA5_Msk

#define CAN_RDH1R_DATA5

#define CAN_RDH1R_DATA6_Pos

#define CAN_RDH1R_DATA6_Msk

#define CAN_RDH1R_DATA6

#define CAN_RDH1R_DATA7_Pos

#define CAN_RDH1R_DATA7_Msk

#define CAN_RDH1R_DATA7

Bit definition for CAN_FMR register

#define CAN_FMR_FINIT_Pos

#define CAN_FMR_FINIT_Msk

#define CAN_FMR_FINIT

#define CAN_FMR_CAN2SB_Pos

#define CAN_FMR_CAN2SB_Msk

#define CAN_FMR_CAN2SB

Bit definition for CAN_FM1R register

#define CAN_FM1R_FBM_Pos

#define CAN_FM1R_FBM_Msk

#define CAN_FM1R_FBM

#define CAN_FM1R_FBM0_Pos

#define CAN_FM1R_FBM0_Msk

#define CAN_FM1R_FBM0

#define CAN_FM1R_FBM1_Pos

#define CAN_FM1R_FBM1_Msk

#define CAN_FM1R_FBM1

#define CAN_FM1R_FBM2_Pos

#define CAN_FM1R_FBM2_Msk

#define CAN_FM1R_FBM2

#define CAN_FM1R_FBM3_Pos

#define CAN_FM1R_FBM3_Msk

#define CAN_FM1R_FBM3

#define CAN_FM1R_FBM4_Pos

#define CAN_FM1R_FBM4_Msk

#define CAN_FM1R_FBM4

#define CAN_FM1R_FBM5_Pos

#define CAN_FM1R_FBM5_Msk

#define CAN_FM1R_FBM5

#define CAN_FM1R_FBM6_Pos

#define CAN_FM1R_FBM6_Msk

#define CAN_FM1R_FBM6

#define CAN_FM1R_FBM7_Pos

#define CAN_FM1R_FBM7_Msk

#define CAN_FM1R_FBM7

#define CAN_FM1R_FBM8_Pos

#define CAN_FM1R_FBM8_Msk

#define CAN_FM1R_FBM8

#define CAN_FM1R_FBM9_Pos

#define CAN_FM1R_FBM9_Msk

#define CAN_FM1R_FBM9

#define CAN_FM1R_FBM10_Pos

#define CAN_FM1R_FBM10_Msk

#define CAN_FM1R_FBM10

#define CAN_FM1R_FBM11_Pos

#define CAN_FM1R_FBM11_Msk

#define CAN_FM1R_FBM11

#define CAN_FM1R_FBM12_Pos

#define CAN_FM1R_FBM12_Msk

#define CAN_FM1R_FBM12

#define CAN_FM1R_FBM13_Pos

#define CAN_FM1R_FBM13_Msk

#define CAN_FM1R_FBM13

#define CAN_FM1R_FBM14_Pos

#define CAN_FM1R_FBM14_Msk

#define CAN_FM1R_FBM14

#define CAN_FM1R_FBM15_Pos

#define CAN_FM1R_FBM15_Msk

#define CAN_FM1R_FBM15

#define CAN_FM1R_FBM16_Pos

#define CAN_FM1R_FBM16_Msk

#define CAN_FM1R_FBM16

#define CAN_FM1R_FBM17_Pos

#define CAN_FM1R_FBM17_Msk

#define CAN_FM1R_FBM17

#define CAN_FM1R_FBM18_Pos

#define CAN_FM1R_FBM18_Msk

#define CAN_FM1R_FBM18

#define CAN_FM1R_FBM19_Pos

#define CAN_FM1R_FBM19_Msk

#define CAN_FM1R_FBM19

#define CAN_FM1R_FBM20_Pos

#define CAN_FM1R_FBM20_Msk

#define CAN_FM1R_FBM20

#define CAN_FM1R_FBM21_Pos

#define CAN_FM1R_FBM21_Msk

#define CAN_FM1R_FBM21

#define CAN_FM1R_FBM22_Pos

#define CAN_FM1R_FBM22_Msk

#define CAN_FM1R_FBM22

#define CAN_FM1R_FBM23_Pos

#define CAN_FM1R_FBM23_Msk

#define CAN_FM1R_FBM23

#define CAN_FM1R_FBM24_Pos

#define CAN_FM1R_FBM24_Msk

#define CAN_FM1R_FBM24

#define CAN_FM1R_FBM25_Pos

#define CAN_FM1R_FBM25_Msk

#define CAN_FM1R_FBM25

#define CAN_FM1R_FBM26_Pos

#define CAN_FM1R_FBM26_Msk

#define CAN_FM1R_FBM26

#define CAN_FM1R_FBM27_Pos

#define CAN_FM1R_FBM27_Msk

#define CAN_FM1R_FBM27

Bit definition for CAN_FS1R register

#define CAN_FS1R_FSC_Pos

#define CAN_FS1R_FSC_Msk

#define CAN_FS1R_FSC

#define CAN_FS1R_FSC0_Pos

#define CAN_FS1R_FSC0_Msk

#define CAN_FS1R_FSC0

#define CAN_FS1R_FSC1_Pos

#define CAN_FS1R_FSC1_Msk

#define CAN_FS1R_FSC1

#define CAN_FS1R_FSC2_Pos

#define CAN_FS1R_FSC2_Msk

#define CAN_FS1R_FSC2

#define CAN_FS1R_FSC3_Pos

#define CAN_FS1R_FSC3_Msk

#define CAN_FS1R_FSC3

#define CAN_FS1R_FSC4_Pos

#define CAN_FS1R_FSC4_Msk

#define CAN_FS1R_FSC4

#define CAN_FS1R_FSC5_Pos

#define CAN_FS1R_FSC5_Msk

#define CAN_FS1R_FSC5

#define CAN_FS1R_FSC6_Pos

#define CAN_FS1R_FSC6_Msk

#define CAN_FS1R_FSC6

#define CAN_FS1R_FSC7_Pos

#define CAN_FS1R_FSC7_Msk

#define CAN_FS1R_FSC7

#define CAN_FS1R_FSC8_Pos

#define CAN_FS1R_FSC8_Msk

#define CAN_FS1R_FSC8

#define CAN_FS1R_FSC9_Pos

#define CAN_FS1R_FSC9_Msk

#define CAN_FS1R_FSC9

#define CAN_FS1R_FSC10_Pos

#define CAN_FS1R_FSC10_Msk

#define CAN_FS1R_FSC10

#define CAN_FS1R_FSC11_Pos

#define CAN_FS1R_FSC11_Msk

#define CAN_FS1R_FSC11

#define CAN_FS1R_FSC12_Pos

#define CAN_FS1R_FSC12_Msk

#define CAN_FS1R_FSC12

#define CAN_FS1R_FSC13_Pos

#define CAN_FS1R_FSC13_Msk

#define CAN_FS1R_FSC13

#define CAN_FS1R_FSC14_Pos

#define CAN_FS1R_FSC14_Msk

#define CAN_FS1R_FSC14

#define CAN_FS1R_FSC15_Pos

#define CAN_FS1R_FSC15_Msk

#define CAN_FS1R_FSC15

#define CAN_FS1R_FSC16_Pos

#define CAN_FS1R_FSC16_Msk

#define CAN_FS1R_FSC16

#define CAN_FS1R_FSC17_Pos

#define CAN_FS1R_FSC17_Msk

#define CAN_FS1R_FSC17

#define CAN_FS1R_FSC18_Pos

#define CAN_FS1R_FSC18_Msk

#define CAN_FS1R_FSC18

#define CAN_FS1R_FSC19_Pos

#define CAN_FS1R_FSC19_Msk

#define CAN_FS1R_FSC19

#define CAN_FS1R_FSC20_Pos

#define CAN_FS1R_FSC20_Msk

#define CAN_FS1R_FSC20

#define CAN_FS1R_FSC21_Pos

#define CAN_FS1R_FSC21_Msk

#define CAN_FS1R_FSC21

#define CAN_FS1R_FSC22_Pos

#define CAN_FS1R_FSC22_Msk

#define CAN_FS1R_FSC22

#define CAN_FS1R_FSC23_Pos

#define CAN_FS1R_FSC23_Msk

#define CAN_FS1R_FSC23

#define CAN_FS1R_FSC24_Pos

#define CAN_FS1R_FSC24_Msk

#define CAN_FS1R_FSC24

#define CAN_FS1R_FSC25_Pos

#define CAN_FS1R_FSC25_Msk

#define CAN_FS1R_FSC25

#define CAN_FS1R_FSC26_Pos

#define CAN_FS1R_FSC26_Msk

#define CAN_FS1R_FSC26

#define CAN_FS1R_FSC27_Pos

#define CAN_FS1R_FSC27_Msk

#define CAN_FS1R_FSC27

Bit definition for CAN_FFA1R register

#define CAN_FFA1R_FFA_Pos

#define CAN_FFA1R_FFA_Msk

#define CAN_FFA1R_FFA

#define CAN_FFA1R_FFA0_Pos

#define CAN_FFA1R_FFA0_Msk

#define CAN_FFA1R_FFA0

#define CAN_FFA1R_FFA1_Pos

#define CAN_FFA1R_FFA1_Msk

#define CAN_FFA1R_FFA1

#define CAN_FFA1R_FFA2_Pos

#define CAN_FFA1R_FFA2_Msk

#define CAN_FFA1R_FFA2

#define CAN_FFA1R_FFA3_Pos

#define CAN_FFA1R_FFA3_Msk

#define CAN_FFA1R_FFA3

#define CAN_FFA1R_FFA4_Pos

#define CAN_FFA1R_FFA4_Msk

#define CAN_FFA1R_FFA4

#define CAN_FFA1R_FFA5_Pos

#define CAN_FFA1R_FFA5_Msk

#define CAN_FFA1R_FFA5

#define CAN_FFA1R_FFA6_Pos

#define CAN_FFA1R_FFA6_Msk

#define CAN_FFA1R_FFA6

#define CAN_FFA1R_FFA7_Pos

#define CAN_FFA1R_FFA7_Msk

#define CAN_FFA1R_FFA7

#define CAN_FFA1R_FFA8_Pos

#define CAN_FFA1R_FFA8_Msk

#define CAN_FFA1R_FFA8

#define CAN_FFA1R_FFA9_Pos

#define CAN_FFA1R_FFA9_Msk

#define CAN_FFA1R_FFA9

#define CAN_FFA1R_FFA10_Pos

#define CAN_FFA1R_FFA10_Msk

#define CAN_FFA1R_FFA10

#define CAN_FFA1R_FFA11_Pos

#define CAN_FFA1R_FFA11_Msk

#define CAN_FFA1R_FFA11

#define CAN_FFA1R_FFA12_Pos

#define CAN_FFA1R_FFA12_Msk

#define CAN_FFA1R_FFA12

#define CAN_FFA1R_FFA13_Pos

#define CAN_FFA1R_FFA13_Msk

#define CAN_FFA1R_FFA13

#define CAN_FFA1R_FFA14_Pos

#define CAN_FFA1R_FFA14_Msk

#define CAN_FFA1R_FFA14

#define CAN_FFA1R_FFA15_Pos

#define CAN_FFA1R_FFA15_Msk

#define CAN_FFA1R_FFA15

#define CAN_FFA1R_FFA16_Pos

#define CAN_FFA1R_FFA16_Msk

#define CAN_FFA1R_FFA16

#define CAN_FFA1R_FFA17_Pos

#define CAN_FFA1R_FFA17_Msk

#define CAN_FFA1R_FFA17

#define CAN_FFA1R_FFA18_Pos

#define CAN_FFA1R_FFA18_Msk

#define CAN_FFA1R_FFA18

#define CAN_FFA1R_FFA19_Pos

#define CAN_FFA1R_FFA19_Msk

#define CAN_FFA1R_FFA19

#define CAN_FFA1R_FFA20_Pos

#define CAN_FFA1R_FFA20_Msk

#define CAN_FFA1R_FFA20

#define CAN_FFA1R_FFA21_Pos

#define CAN_FFA1R_FFA21_Msk

#define CAN_FFA1R_FFA21

#define CAN_FFA1R_FFA22_Pos

#define CAN_FFA1R_FFA22_Msk

#define CAN_FFA1R_FFA22

#define CAN_FFA1R_FFA23_Pos

#define CAN_FFA1R_FFA23_Msk

#define CAN_FFA1R_FFA23

#define CAN_FFA1R_FFA24_Pos

#define CAN_FFA1R_FFA24_Msk

#define CAN_FFA1R_FFA24

#define CAN_FFA1R_FFA25_Pos

#define CAN_FFA1R_FFA25_Msk

#define CAN_FFA1R_FFA25

#define CAN_FFA1R_FFA26_Pos

#define CAN_FFA1R_FFA26_Msk

#define CAN_FFA1R_FFA26

#define CAN_FFA1R_FFA27_Pos

#define CAN_FFA1R_FFA27_Msk

#define CAN_FFA1R_FFA27

Bit definition for CAN_FA1R register

#define CAN_FA1R_FACT_Pos

#define CAN_FA1R_FACT_Msk

#define CAN_FA1R_FACT

#define CAN_FA1R_FACT0_Pos

#define CAN_FA1R_FACT0_Msk

#define CAN_FA1R_FACT0

#define CAN_FA1R_FACT1_Pos

#define CAN_FA1R_FACT1_Msk

#define CAN_FA1R_FACT1

#define CAN_FA1R_FACT2_Pos

#define CAN_FA1R_FACT2_Msk

#define CAN_FA1R_FACT2

#define CAN_FA1R_FACT3_Pos

#define CAN_FA1R_FACT3_Msk

#define CAN_FA1R_FACT3

#define CAN_FA1R_FACT4_Pos

#define CAN_FA1R_FACT4_Msk

#define CAN_FA1R_FACT4

#define CAN_FA1R_FACT5_Pos

#define CAN_FA1R_FACT5_Msk

#define CAN_FA1R_FACT5

#define CAN_FA1R_FACT6_Pos

#define CAN_FA1R_FACT6_Msk

#define CAN_FA1R_FACT6

#define CAN_FA1R_FACT7_Pos

#define CAN_FA1R_FACT7_Msk

#define CAN_FA1R_FACT7

#define CAN_FA1R_FACT8_Pos

#define CAN_FA1R_FACT8_Msk

#define CAN_FA1R_FACT8

#define CAN_FA1R_FACT9_Pos

#define CAN_FA1R_FACT9_Msk

#define CAN_FA1R_FACT9

#define CAN_FA1R_FACT10_Pos

#define CAN_FA1R_FACT10_Msk

#define CAN_FA1R_FACT10

#define CAN_FA1R_FACT11_Pos

#define CAN_FA1R_FACT11_Msk

#define CAN_FA1R_FACT11

#define CAN_FA1R_FACT12_Pos

#define CAN_FA1R_FACT12_Msk

#define CAN_FA1R_FACT12

#define CAN_FA1R_FACT13_Pos

#define CAN_FA1R_FACT13_Msk

#define CAN_FA1R_FACT13

#define CAN_FA1R_FACT14_Pos

#define CAN_FA1R_FACT14_Msk

#define CAN_FA1R_FACT14

#define CAN_FA1R_FACT15_Pos

#define CAN_FA1R_FACT15_Msk

#define CAN_FA1R_FACT15

#define CAN_FA1R_FACT16_Pos

#define CAN_FA1R_FACT16_Msk

#define CAN_FA1R_FACT16

#define CAN_FA1R_FACT17_Pos

#define CAN_FA1R_FACT17_Msk

#define CAN_FA1R_FACT17

#define CAN_FA1R_FACT18_Pos

#define CAN_FA1R_FACT18_Msk

#define CAN_FA1R_FACT18

#define CAN_FA1R_FACT19_Pos

#define CAN_FA1R_FACT19_Msk

#define CAN_FA1R_FACT19

#define CAN_FA1R_FACT20_Pos

#define CAN_FA1R_FACT20_Msk

#define CAN_FA1R_FACT20

#define CAN_FA1R_FACT21_Pos

#define CAN_FA1R_FACT21_Msk

#define CAN_FA1R_FACT21

#define CAN_FA1R_FACT22_Pos

#define CAN_FA1R_FACT22_Msk

#define CAN_FA1R_FACT22

#define CAN_FA1R_FACT23_Pos

#define CAN_FA1R_FACT23_Msk

#define CAN_FA1R_FACT23

#define CAN_FA1R_FACT24_Pos

#define CAN_FA1R_FACT24_Msk

#define CAN_FA1R_FACT24

#define CAN_FA1R_FACT25_Pos

#define CAN_FA1R_FACT25_Msk

#define CAN_FA1R_FACT25

#define CAN_FA1R_FACT26_Pos

#define CAN_FA1R_FACT26_Msk

#define CAN_FA1R_FACT26

#define CAN_FA1R_FACT27_Pos

#define CAN_FA1R_FACT27_Msk

#define CAN_FA1R_FACT27

Bit definition for CAN_F0R1 register

#define CAN_F0R1_FB0_Pos

#define CAN_F0R1_FB0_Msk

#define CAN_F0R1_FB0

#define CAN_F0R1_FB1_Pos

#define CAN_F0R1_FB1_Msk

#define CAN_F0R1_FB1

#define CAN_F0R1_FB2_Pos

#define CAN_F0R1_FB2_Msk

#define CAN_F0R1_FB2

#define CAN_F0R1_FB3_Pos

#define CAN_F0R1_FB3_Msk

#define CAN_F0R1_FB3

#define CAN_F0R1_FB4_Pos

#define CAN_F0R1_FB4_Msk

#define CAN_F0R1_FB4

#define CAN_F0R1_FB5_Pos

#define CAN_F0R1_FB5_Msk

#define CAN_F0R1_FB5

#define CAN_F0R1_FB6_Pos

#define CAN_F0R1_FB6_Msk

#define CAN_F0R1_FB6

#define CAN_F0R1_FB7_Pos

#define CAN_F0R1_FB7_Msk

#define CAN_F0R1_FB7

#define CAN_F0R1_FB8_Pos

#define CAN_F0R1_FB8_Msk

#define CAN_F0R1_FB8

#define CAN_F0R1_FB9_Pos

#define CAN_F0R1_FB9_Msk

#define CAN_F0R1_FB9

#define CAN_F0R1_FB10_Pos

#define CAN_F0R1_FB10_Msk

#define CAN_F0R1_FB10

#define CAN_F0R1_FB11_Pos

#define CAN_F0R1_FB11_Msk

#define CAN_F0R1_FB11

#define CAN_F0R1_FB12_Pos

#define CAN_F0R1_FB12_Msk

#define CAN_F0R1_FB12

#define CAN_F0R1_FB13_Pos

#define CAN_F0R1_FB13_Msk

#define CAN_F0R1_FB13

#define CAN_F0R1_FB14_Pos

#define CAN_F0R1_FB14_Msk

#define CAN_F0R1_FB14

#define CAN_F0R1_FB15_Pos

#define CAN_F0R1_FB15_Msk

#define CAN_F0R1_FB15

#define CAN_F0R1_FB16_Pos

#define CAN_F0R1_FB16_Msk

#define CAN_F0R1_FB16

#define CAN_F0R1_FB17_Pos

#define CAN_F0R1_FB17_Msk

#define CAN_F0R1_FB17

#define CAN_F0R1_FB18_Pos

#define CAN_F0R1_FB18_Msk

#define CAN_F0R1_FB18

#define CAN_F0R1_FB19_Pos

#define CAN_F0R1_FB19_Msk

#define CAN_F0R1_FB19

#define CAN_F0R1_FB20_Pos

#define CAN_F0R1_FB20_Msk

#define CAN_F0R1_FB20

#define CAN_F0R1_FB21_Pos

#define CAN_F0R1_FB21_Msk

#define CAN_F0R1_FB21

#define CAN_F0R1_FB22_Pos

#define CAN_F0R1_FB22_Msk

#define CAN_F0R1_FB22

#define CAN_F0R1_FB23_Pos

#define CAN_F0R1_FB23_Msk

#define CAN_F0R1_FB23

#define CAN_F0R1_FB24_Pos

#define CAN_F0R1_FB24_Msk

#define CAN_F0R1_FB24

#define CAN_F0R1_FB25_Pos

#define CAN_F0R1_FB25_Msk

#define CAN_F0R1_FB25

#define CAN_F0R1_FB26_Pos

#define CAN_F0R1_FB26_Msk

#define CAN_F0R1_FB26

#define CAN_F0R1_FB27_Pos

#define CAN_F0R1_FB27_Msk

#define CAN_F0R1_FB27

#define CAN_F0R1_FB28_Pos

#define CAN_F0R1_FB28_Msk

#define CAN_F0R1_FB28

#define CAN_F0R1_FB29_Pos

#define CAN_F0R1_FB29_Msk

#define CAN_F0R1_FB29

#define CAN_F0R1_FB30_Pos

#define CAN_F0R1_FB30_Msk

#define CAN_F0R1_FB30

#define CAN_F0R1_FB31_Pos

#define CAN_F0R1_FB31_Msk

#define CAN_F0R1_FB31

Bit definition for CAN_F1R1 register

#define CAN_F1R1_FB0_Pos

#define CAN_F1R1_FB0_Msk

#define CAN_F1R1_FB0

#define CAN_F1R1_FB1_Pos

#define CAN_F1R1_FB1_Msk

#define CAN_F1R1_FB1

#define CAN_F1R1_FB2_Pos

#define CAN_F1R1_FB2_Msk

#define CAN_F1R1_FB2

#define CAN_F1R1_FB3_Pos

#define CAN_F1R1_FB3_Msk

#define CAN_F1R1_FB3

#define CAN_F1R1_FB4_Pos

#define CAN_F1R1_FB4_Msk

#define CAN_F1R1_FB4

#define CAN_F1R1_FB5_Pos

#define CAN_F1R1_FB5_Msk

#define CAN_F1R1_FB5

#define CAN_F1R1_FB6_Pos

#define CAN_F1R1_FB6_Msk

#define CAN_F1R1_FB6

#define CAN_F1R1_FB7_Pos

#define CAN_F1R1_FB7_Msk

#define CAN_F1R1_FB7

#define CAN_F1R1_FB8_Pos

#define CAN_F1R1_FB8_Msk

#define CAN_F1R1_FB8

#define CAN_F1R1_FB9_Pos

#define CAN_F1R1_FB9_Msk

#define CAN_F1R1_FB9

#define CAN_F1R1_FB10_Pos

#define CAN_F1R1_FB10_Msk

#define CAN_F1R1_FB10

#define CAN_F1R1_FB11_Pos

#define CAN_F1R1_FB11_Msk

#define CAN_F1R1_FB11

#define CAN_F1R1_FB12_Pos

#define CAN_F1R1_FB12_Msk

#define CAN_F1R1_FB12

#define CAN_F1R1_FB13_Pos

#define CAN_F1R1_FB13_Msk

#define CAN_F1R1_FB13

#define CAN_F1R1_FB14_Pos

#define CAN_F1R1_FB14_Msk

#define CAN_F1R1_FB14

#define CAN_F1R1_FB15_Pos

#define CAN_F1R1_FB15_Msk

#define CAN_F1R1_FB15

#define CAN_F1R1_FB16_Pos

#define CAN_F1R1_FB16_Msk

#define CAN_F1R1_FB16

#define CAN_F1R1_FB17_Pos

#define CAN_F1R1_FB17_Msk

#define CAN_F1R1_FB17

#define CAN_F1R1_FB18_Pos

#define CAN_F1R1_FB18_Msk

#define CAN_F1R1_FB18

#define CAN_F1R1_FB19_Pos

#define CAN_F1R1_FB19_Msk

#define CAN_F1R1_FB19

#define CAN_F1R1_FB20_Pos

#define CAN_F1R1_FB20_Msk

#define CAN_F1R1_FB20

#define CAN_F1R1_FB21_Pos

#define CAN_F1R1_FB21_Msk

#define CAN_F1R1_FB21

#define CAN_F1R1_FB22_Pos

#define CAN_F1R1_FB22_Msk

#define CAN_F1R1_FB22

#define CAN_F1R1_FB23_Pos

#define CAN_F1R1_FB23_Msk

#define CAN_F1R1_FB23

#define CAN_F1R1_FB24_Pos

#define CAN_F1R1_FB24_Msk

#define CAN_F1R1_FB24

#define CAN_F1R1_FB25_Pos

#define CAN_F1R1_FB25_Msk

#define CAN_F1R1_FB25

#define CAN_F1R1_FB26_Pos

#define CAN_F1R1_FB26_Msk

#define CAN_F1R1_FB26

#define CAN_F1R1_FB27_Pos

#define CAN_F1R1_FB27_Msk

#define CAN_F1R1_FB27

#define CAN_F1R1_FB28_Pos

#define CAN_F1R1_FB28_Msk

#define CAN_F1R1_FB28

#define CAN_F1R1_FB29_Pos

#define CAN_F1R1_FB29_Msk

#define CAN_F1R1_FB29

#define CAN_F1R1_FB30_Pos

#define CAN_F1R1_FB30_Msk

#define CAN_F1R1_FB30

#define CAN_F1R1_FB31_Pos

#define CAN_F1R1_FB31_Msk

#define CAN_F1R1_FB31

Bit definition for CAN_F2R1 register

#define CAN_F2R1_FB0_Pos

#define CAN_F2R1_FB0_Msk

#define CAN_F2R1_FB0

#define CAN_F2R1_FB1_Pos

#define CAN_F2R1_FB1_Msk

#define CAN_F2R1_FB1

#define CAN_F2R1_FB2_Pos

#define CAN_F2R1_FB2_Msk

#define CAN_F2R1_FB2

#define CAN_F2R1_FB3_Pos

#define CAN_F2R1_FB3_Msk

#define CAN_F2R1_FB3

#define CAN_F2R1_FB4_Pos

#define CAN_F2R1_FB4_Msk

#define CAN_F2R1_FB4

#define CAN_F2R1_FB5_Pos

#define CAN_F2R1_FB5_Msk

#define CAN_F2R1_FB5

#define CAN_F2R1_FB6_Pos

#define CAN_F2R1_FB6_Msk

#define CAN_F2R1_FB6

#define CAN_F2R1_FB7_Pos

#define CAN_F2R1_FB7_Msk

#define CAN_F2R1_FB7

#define CAN_F2R1_FB8_Pos

#define CAN_F2R1_FB8_Msk

#define CAN_F2R1_FB8

#define CAN_F2R1_FB9_Pos

#define CAN_F2R1_FB9_Msk

#define CAN_F2R1_FB9

#define CAN_F2R1_FB10_Pos

#define CAN_F2R1_FB10_Msk

#define CAN_F2R1_FB10

#define CAN_F2R1_FB11_Pos

#define CAN_F2R1_FB11_Msk

#define CAN_F2R1_FB11

#define CAN_F2R1_FB12_Pos

#define CAN_F2R1_FB12_Msk

#define CAN_F2R1_FB12

#define CAN_F2R1_FB13_Pos

#define CAN_F2R1_FB13_Msk

#define CAN_F2R1_FB13

#define CAN_F2R1_FB14_Pos

#define CAN_F2R1_FB14_Msk

#define CAN_F2R1_FB14

#define CAN_F2R1_FB15_Pos

#define CAN_F2R1_FB15_Msk

#define CAN_F2R1_FB15

#define CAN_F2R1_FB16_Pos

#define CAN_F2R1_FB16_Msk

#define CAN_F2R1_FB16

#define CAN_F2R1_FB17_Pos

#define CAN_F2R1_FB17_Msk

#define CAN_F2R1_FB17

#define CAN_F2R1_FB18_Pos

#define CAN_F2R1_FB18_Msk

#define CAN_F2R1_FB18

#define CAN_F2R1_FB19_Pos

#define CAN_F2R1_FB19_Msk

#define CAN_F2R1_FB19

#define CAN_F2R1_FB20_Pos

#define CAN_F2R1_FB20_Msk

#define CAN_F2R1_FB20

#define CAN_F2R1_FB21_Pos

#define CAN_F2R1_FB21_Msk

#define CAN_F2R1_FB21

#define CAN_F2R1_FB22_Pos

#define CAN_F2R1_FB22_Msk

#define CAN_F2R1_FB22

#define CAN_F2R1_FB23_Pos

#define CAN_F2R1_FB23_Msk

#define CAN_F2R1_FB23

#define CAN_F2R1_FB24_Pos

#define CAN_F2R1_FB24_Msk

#define CAN_F2R1_FB24

#define CAN_F2R1_FB25_Pos

#define CAN_F2R1_FB25_Msk

#define CAN_F2R1_FB25

#define CAN_F2R1_FB26_Pos

#define CAN_F2R1_FB26_Msk

#define CAN_F2R1_FB26

#define CAN_F2R1_FB27_Pos

#define CAN_F2R1_FB27_Msk

#define CAN_F2R1_FB27

#define CAN_F2R1_FB28_Pos

#define CAN_F2R1_FB28_Msk

#define CAN_F2R1_FB28

#define CAN_F2R1_FB29_Pos

#define CAN_F2R1_FB29_Msk

#define CAN_F2R1_FB29

#define CAN_F2R1_FB30_Pos

#define CAN_F2R1_FB30_Msk

#define CAN_F2R1_FB30

#define CAN_F2R1_FB31_Pos

#define CAN_F2R1_FB31_Msk

#define CAN_F2R1_FB31

Bit definition for CAN_F3R1 register

#define CAN_F3R1_FB0_Pos

#define CAN_F3R1_FB0_Msk

#define CAN_F3R1_FB0

#define CAN_F3R1_FB1_Pos

#define CAN_F3R1_FB1_Msk

#define CAN_F3R1_FB1

#define CAN_F3R1_FB2_Pos

#define CAN_F3R1_FB2_Msk

#define CAN_F3R1_FB2

#define CAN_F3R1_FB3_Pos

#define CAN_F3R1_FB3_Msk

#define CAN_F3R1_FB3

#define CAN_F3R1_FB4_Pos

#define CAN_F3R1_FB4_Msk

#define CAN_F3R1_FB4

#define CAN_F3R1_FB5_Pos

#define CAN_F3R1_FB5_Msk

#define CAN_F3R1_FB5

#define CAN_F3R1_FB6_Pos

#define CAN_F3R1_FB6_Msk

#define CAN_F3R1_FB6

#define CAN_F3R1_FB7_Pos

#define CAN_F3R1_FB7_Msk

#define CAN_F3R1_FB7

#define CAN_F3R1_FB8_Pos

#define CAN_F3R1_FB8_Msk

#define CAN_F3R1_FB8

#define CAN_F3R1_FB9_Pos

#define CAN_F3R1_FB9_Msk

#define CAN_F3R1_FB9

#define CAN_F3R1_FB10_Pos

#define CAN_F3R1_FB10_Msk

#define CAN_F3R1_FB10

#define CAN_F3R1_FB11_Pos

#define CAN_F3R1_FB11_Msk

#define CAN_F3R1_FB11

#define CAN_F3R1_FB12_Pos

#define CAN_F3R1_FB12_Msk

#define CAN_F3R1_FB12

#define CAN_F3R1_FB13_Pos

#define CAN_F3R1_FB13_Msk

#define CAN_F3R1_FB13

#define CAN_F3R1_FB14_Pos

#define CAN_F3R1_FB14_Msk

#define CAN_F3R1_FB14

#define CAN_F3R1_FB15_Pos

#define CAN_F3R1_FB15_Msk

#define CAN_F3R1_FB15

#define CAN_F3R1_FB16_Pos

#define CAN_F3R1_FB16_Msk

#define CAN_F3R1_FB16

#define CAN_F3R1_FB17_Pos

#define CAN_F3R1_FB17_Msk

#define CAN_F3R1_FB17

#define CAN_F3R1_FB18_Pos

#define CAN_F3R1_FB18_Msk

#define CAN_F3R1_FB18

#define CAN_F3R1_FB19_Pos

#define CAN_F3R1_FB19_Msk

#define CAN_F3R1_FB19

#define CAN_F3R1_FB20_Pos

#define CAN_F3R1_FB20_Msk

#define CAN_F3R1_FB20

#define CAN_F3R1_FB21_Pos

#define CAN_F3R1_FB21_Msk

#define CAN_F3R1_FB21

#define CAN_F3R1_FB22_Pos

#define CAN_F3R1_FB22_Msk

#define CAN_F3R1_FB22

#define CAN_F3R1_FB23_Pos

#define CAN_F3R1_FB23_Msk

#define CAN_F3R1_FB23

#define CAN_F3R1_FB24_Pos

#define CAN_F3R1_FB24_Msk

#define CAN_F3R1_FB24

#define CAN_F3R1_FB25_Pos

#define CAN_F3R1_FB25_Msk

#define CAN_F3R1_FB25

#define CAN_F3R1_FB26_Pos

#define CAN_F3R1_FB26_Msk

#define CAN_F3R1_FB26

#define CAN_F3R1_FB27_Pos

#define CAN_F3R1_FB27_Msk

#define CAN_F3R1_FB27

#define CAN_F3R1_FB28_Pos

#define CAN_F3R1_FB28_Msk

#define CAN_F3R1_FB28

#define CAN_F3R1_FB29_Pos

#define CAN_F3R1_FB29_Msk

#define CAN_F3R1_FB29

#define CAN_F3R1_FB30_Pos

#define CAN_F3R1_FB30_Msk

#define CAN_F3R1_FB30

#define CAN_F3R1_FB31_Pos

#define CAN_F3R1_FB31_Msk

#define CAN_F3R1_FB31

Bit definition for CAN_F4R1 register

#define CAN_F4R1_FB0_Pos

#define CAN_F4R1_FB0_Msk

#define CAN_F4R1_FB0

#define CAN_F4R1_FB1_Pos

#define CAN_F4R1_FB1_Msk

#define CAN_F4R1_FB1

#define CAN_F4R1_FB2_Pos

#define CAN_F4R1_FB2_Msk

#define CAN_F4R1_FB2

#define CAN_F4R1_FB3_Pos

#define CAN_F4R1_FB3_Msk

#define CAN_F4R1_FB3

#define CAN_F4R1_FB4_Pos

#define CAN_F4R1_FB4_Msk

#define CAN_F4R1_FB4

#define CAN_F4R1_FB5_Pos

#define CAN_F4R1_FB5_Msk

#define CAN_F4R1_FB5

#define CAN_F4R1_FB6_Pos

#define CAN_F4R1_FB6_Msk

#define CAN_F4R1_FB6

#define CAN_F4R1_FB7_Pos

#define CAN_F4R1_FB7_Msk

#define CAN_F4R1_FB7

#define CAN_F4R1_FB8_Pos

#define CAN_F4R1_FB8_Msk

#define CAN_F4R1_FB8

#define CAN_F4R1_FB9_Pos

#define CAN_F4R1_FB9_Msk

#define CAN_F4R1_FB9

#define CAN_F4R1_FB10_Pos

#define CAN_F4R1_FB10_Msk

#define CAN_F4R1_FB10

#define CAN_F4R1_FB11_Pos

#define CAN_F4R1_FB11_Msk

#define CAN_F4R1_FB11

#define CAN_F4R1_FB12_Pos

#define CAN_F4R1_FB12_Msk

#define CAN_F4R1_FB12

#define CAN_F4R1_FB13_Pos

#define CAN_F4R1_FB13_Msk

#define CAN_F4R1_FB13

#define CAN_F4R1_FB14_Pos

#define CAN_F4R1_FB14_Msk

#define CAN_F4R1_FB14

#define CAN_F4R1_FB15_Pos

#define CAN_F4R1_FB15_Msk

#define CAN_F4R1_FB15

#define CAN_F4R1_FB16_Pos

#define CAN_F4R1_FB16_Msk

#define CAN_F4R1_FB16

#define CAN_F4R1_FB17_Pos

#define CAN_F4R1_FB17_Msk

#define CAN_F4R1_FB17

#define CAN_F4R1_FB18_Pos

#define CAN_F4R1_FB18_Msk

#define CAN_F4R1_FB18

#define CAN_F4R1_FB19_Pos

#define CAN_F4R1_FB19_Msk

#define CAN_F4R1_FB19

#define CAN_F4R1_FB20_Pos

#define CAN_F4R1_FB20_Msk

#define CAN_F4R1_FB20

#define CAN_F4R1_FB21_Pos

#define CAN_F4R1_FB21_Msk

#define CAN_F4R1_FB21

#define CAN_F4R1_FB22_Pos

#define CAN_F4R1_FB22_Msk

#define CAN_F4R1_FB22

#define CAN_F4R1_FB23_Pos

#define CAN_F4R1_FB23_Msk

#define CAN_F4R1_FB23

#define CAN_F4R1_FB24_Pos

#define CAN_F4R1_FB24_Msk

#define CAN_F4R1_FB24

#define CAN_F4R1_FB25_Pos

#define CAN_F4R1_FB25_Msk

#define CAN_F4R1_FB25

#define CAN_F4R1_FB26_Pos

#define CAN_F4R1_FB26_Msk

#define CAN_F4R1_FB26

#define CAN_F4R1_FB27_Pos

#define CAN_F4R1_FB27_Msk

#define CAN_F4R1_FB27

#define CAN_F4R1_FB28_Pos

#define CAN_F4R1_FB28_Msk

#define CAN_F4R1_FB28

#define CAN_F4R1_FB29_Pos

#define CAN_F4R1_FB29_Msk

#define CAN_F4R1_FB29

#define CAN_F4R1_FB30_Pos

#define CAN_F4R1_FB30_Msk

#define CAN_F4R1_FB30

#define CAN_F4R1_FB31_Pos

#define CAN_F4R1_FB31_Msk

#define CAN_F4R1_FB31

Bit definition for CAN_F5R1 register

#define CAN_F5R1_FB0_Pos

#define CAN_F5R1_FB0_Msk

#define CAN_F5R1_FB0

#define CAN_F5R1_FB1_Pos

#define CAN_F5R1_FB1_Msk

#define CAN_F5R1_FB1

#define CAN_F5R1_FB2_Pos

#define CAN_F5R1_FB2_Msk

#define CAN_F5R1_FB2

#define CAN_F5R1_FB3_Pos

#define CAN_F5R1_FB3_Msk

#define CAN_F5R1_FB3

#define CAN_F5R1_FB4_Pos

#define CAN_F5R1_FB4_Msk

#define CAN_F5R1_FB4

#define CAN_F5R1_FB5_Pos

#define CAN_F5R1_FB5_Msk

#define CAN_F5R1_FB5

#define CAN_F5R1_FB6_Pos

#define CAN_F5R1_FB6_Msk

#define CAN_F5R1_FB6

#define CAN_F5R1_FB7_Pos

#define CAN_F5R1_FB7_Msk

#define CAN_F5R1_FB7

#define CAN_F5R1_FB8_Pos

#define CAN_F5R1_FB8_Msk

#define CAN_F5R1_FB8

#define CAN_F5R1_FB9_Pos

#define CAN_F5R1_FB9_Msk

#define CAN_F5R1_FB9

#define CAN_F5R1_FB10_Pos

#define CAN_F5R1_FB10_Msk

#define CAN_F5R1_FB10

#define CAN_F5R1_FB11_Pos

#define CAN_F5R1_FB11_Msk

#define CAN_F5R1_FB11

#define CAN_F5R1_FB12_Pos

#define CAN_F5R1_FB12_Msk

#define CAN_F5R1_FB12

#define CAN_F5R1_FB13_Pos

#define CAN_F5R1_FB13_Msk

#define CAN_F5R1_FB13

#define CAN_F5R1_FB14_Pos

#define CAN_F5R1_FB14_Msk

#define CAN_F5R1_FB14

#define CAN_F5R1_FB15_Pos

#define CAN_F5R1_FB15_Msk

#define CAN_F5R1_FB15

#define CAN_F5R1_FB16_Pos

#define CAN_F5R1_FB16_Msk

#define CAN_F5R1_FB16

#define CAN_F5R1_FB17_Pos

#define CAN_F5R1_FB17_Msk

#define CAN_F5R1_FB17

#define CAN_F5R1_FB18_Pos

#define CAN_F5R1_FB18_Msk

#define CAN_F5R1_FB18

#define CAN_F5R1_FB19_Pos

#define CAN_F5R1_FB19_Msk

#define CAN_F5R1_FB19

#define CAN_F5R1_FB20_Pos

#define CAN_F5R1_FB20_Msk

#define CAN_F5R1_FB20

#define CAN_F5R1_FB21_Pos

#define CAN_F5R1_FB21_Msk

#define CAN_F5R1_FB21

#define CAN_F5R1_FB22_Pos

#define CAN_F5R1_FB22_Msk

#define CAN_F5R1_FB22

#define CAN_F5R1_FB23_Pos

#define CAN_F5R1_FB23_Msk

#define CAN_F5R1_FB23

#define CAN_F5R1_FB24_Pos

#define CAN_F5R1_FB24_Msk

#define CAN_F5R1_FB24

#define CAN_F5R1_FB25_Pos

#define CAN_F5R1_FB25_Msk

#define CAN_F5R1_FB25

#define CAN_F5R1_FB26_Pos

#define CAN_F5R1_FB26_Msk

#define CAN_F5R1_FB26

#define CAN_F5R1_FB27_Pos

#define CAN_F5R1_FB27_Msk

#define CAN_F5R1_FB27

#define CAN_F5R1_FB28_Pos

#define CAN_F5R1_FB28_Msk

#define CAN_F5R1_FB28

#define CAN_F5R1_FB29_Pos

#define CAN_F5R1_FB29_Msk

#define CAN_F5R1_FB29

#define CAN_F5R1_FB30_Pos

#define CAN_F5R1_FB30_Msk

#define CAN_F5R1_FB30

#define CAN_F5R1_FB31_Pos

#define CAN_F5R1_FB31_Msk

#define CAN_F5R1_FB31

Bit definition for CAN_F6R1 register

#define CAN_F6R1_FB0_Pos

#define CAN_F6R1_FB0_Msk

#define CAN_F6R1_FB0

#define CAN_F6R1_FB1_Pos

#define CAN_F6R1_FB1_Msk

#define CAN_F6R1_FB1

#define CAN_F6R1_FB2_Pos

#define CAN_F6R1_FB2_Msk

#define CAN_F6R1_FB2

#define CAN_F6R1_FB3_Pos

#define CAN_F6R1_FB3_Msk

#define CAN_F6R1_FB3

#define CAN_F6R1_FB4_Pos

#define CAN_F6R1_FB4_Msk

#define CAN_F6R1_FB4

#define CAN_F6R1_FB5_Pos

#define CAN_F6R1_FB5_Msk

#define CAN_F6R1_FB5

#define CAN_F6R1_FB6_Pos

#define CAN_F6R1_FB6_Msk

#define CAN_F6R1_FB6

#define CAN_F6R1_FB7_Pos

#define CAN_F6R1_FB7_Msk

#define CAN_F6R1_FB7

#define CAN_F6R1_FB8_Pos

#define CAN_F6R1_FB8_Msk

#define CAN_F6R1_FB8

#define CAN_F6R1_FB9_Pos

#define CAN_F6R1_FB9_Msk

#define CAN_F6R1_FB9

#define CAN_F6R1_FB10_Pos

#define CAN_F6R1_FB10_Msk

#define CAN_F6R1_FB10

#define CAN_F6R1_FB11_Pos

#define CAN_F6R1_FB11_Msk

#define CAN_F6R1_FB11

#define CAN_F6R1_FB12_Pos

#define CAN_F6R1_FB12_Msk

#define CAN_F6R1_FB12

#define CAN_F6R1_FB13_Pos

#define CAN_F6R1_FB13_Msk

#define CAN_F6R1_FB13

#define CAN_F6R1_FB14_Pos

#define CAN_F6R1_FB14_Msk

#define CAN_F6R1_FB14

#define CAN_F6R1_FB15_Pos

#define CAN_F6R1_FB15_Msk

#define CAN_F6R1_FB15

#define CAN_F6R1_FB16_Pos

#define CAN_F6R1_FB16_Msk

#define CAN_F6R1_FB16

#define CAN_F6R1_FB17_Pos

#define CAN_F6R1_FB17_Msk

#define CAN_F6R1_FB17

#define CAN_F6R1_FB18_Pos

#define CAN_F6R1_FB18_Msk

#define CAN_F6R1_FB18

#define CAN_F6R1_FB19_Pos

#define CAN_F6R1_FB19_Msk

#define CAN_F6R1_FB19

#define CAN_F6R1_FB20_Pos

#define CAN_F6R1_FB20_Msk

#define CAN_F6R1_FB20

#define CAN_F6R1_FB21_Pos

#define CAN_F6R1_FB21_Msk

#define CAN_F6R1_FB21

#define CAN_F6R1_FB22_Pos

#define CAN_F6R1_FB22_Msk

#define CAN_F6R1_FB22

#define CAN_F6R1_FB23_Pos

#define CAN_F6R1_FB23_Msk

#define CAN_F6R1_FB23

#define CAN_F6R1_FB24_Pos

#define CAN_F6R1_FB24_Msk

#define CAN_F6R1_FB24

#define CAN_F6R1_FB25_Pos

#define CAN_F6R1_FB25_Msk

#define CAN_F6R1_FB25

#define CAN_F6R1_FB26_Pos

#define CAN_F6R1_FB26_Msk

#define CAN_F6R1_FB26

#define CAN_F6R1_FB27_Pos

#define CAN_F6R1_FB27_Msk

#define CAN_F6R1_FB27

#define CAN_F6R1_FB28_Pos

#define CAN_F6R1_FB28_Msk

#define CAN_F6R1_FB28

#define CAN_F6R1_FB29_Pos

#define CAN_F6R1_FB29_Msk

#define CAN_F6R1_FB29

#define CAN_F6R1_FB30_Pos

#define CAN_F6R1_FB30_Msk

#define CAN_F6R1_FB30

#define CAN_F6R1_FB31_Pos

#define CAN_F6R1_FB31_Msk

#define CAN_F6R1_FB31

Bit definition for CAN_F7R1 register

#define CAN_F7R1_FB0_Pos

#define CAN_F7R1_FB0_Msk

#define CAN_F7R1_FB0

#define CAN_F7R1_FB1_Pos

#define CAN_F7R1_FB1_Msk

#define CAN_F7R1_FB1

#define CAN_F7R1_FB2_Pos

#define CAN_F7R1_FB2_Msk

#define CAN_F7R1_FB2

#define CAN_F7R1_FB3_Pos

#define CAN_F7R1_FB3_Msk

#define CAN_F7R1_FB3

#define CAN_F7R1_FB4_Pos

#define CAN_F7R1_FB4_Msk

#define CAN_F7R1_FB4

#define CAN_F7R1_FB5_Pos

#define CAN_F7R1_FB5_Msk

#define CAN_F7R1_FB5

#define CAN_F7R1_FB6_Pos

#define CAN_F7R1_FB6_Msk

#define CAN_F7R1_FB6

#define CAN_F7R1_FB7_Pos

#define CAN_F7R1_FB7_Msk

#define CAN_F7R1_FB7

#define CAN_F7R1_FB8_Pos

#define CAN_F7R1_FB8_Msk

#define CAN_F7R1_FB8

#define CAN_F7R1_FB9_Pos

#define CAN_F7R1_FB9_Msk

#define CAN_F7R1_FB9

#define CAN_F7R1_FB10_Pos

#define CAN_F7R1_FB10_Msk

#define CAN_F7R1_FB10

#define CAN_F7R1_FB11_Pos

#define CAN_F7R1_FB11_Msk

#define CAN_F7R1_FB11

#define CAN_F7R1_FB12_Pos

#define CAN_F7R1_FB12_Msk

#define CAN_F7R1_FB12

#define CAN_F7R1_FB13_Pos

#define CAN_F7R1_FB13_Msk

#define CAN_F7R1_FB13

#define CAN_F7R1_FB14_Pos

#define CAN_F7R1_FB14_Msk

#define CAN_F7R1_FB14

#define CAN_F7R1_FB15_Pos

#define CAN_F7R1_FB15_Msk

#define CAN_F7R1_FB15

#define CAN_F7R1_FB16_Pos

#define CAN_F7R1_FB16_Msk

#define CAN_F7R1_FB16

#define CAN_F7R1_FB17_Pos

#define CAN_F7R1_FB17_Msk

#define CAN_F7R1_FB17

#define CAN_F7R1_FB18_Pos

#define CAN_F7R1_FB18_Msk

#define CAN_F7R1_FB18

#define CAN_F7R1_FB19_Pos

#define CAN_F7R1_FB19_Msk

#define CAN_F7R1_FB19

#define CAN_F7R1_FB20_Pos

#define CAN_F7R1_FB20_Msk

#define CAN_F7R1_FB20

#define CAN_F7R1_FB21_Pos

#define CAN_F7R1_FB21_Msk

#define CAN_F7R1_FB21

#define CAN_F7R1_FB22_Pos

#define CAN_F7R1_FB22_Msk

#define CAN_F7R1_FB22

#define CAN_F7R1_FB23_Pos

#define CAN_F7R1_FB23_Msk

#define CAN_F7R1_FB23

#define CAN_F7R1_FB24_Pos

#define CAN_F7R1_FB24_Msk

#define CAN_F7R1_FB24

#define CAN_F7R1_FB25_Pos

#define CAN_F7R1_FB25_Msk

#define CAN_F7R1_FB25

#define CAN_F7R1_FB26_Pos

#define CAN_F7R1_FB26_Msk

#define CAN_F7R1_FB26

#define CAN_F7R1_FB27_Pos

#define CAN_F7R1_FB27_Msk

#define CAN_F7R1_FB27

#define CAN_F7R1_FB28_Pos

#define CAN_F7R1_FB28_Msk

#define CAN_F7R1_FB28

#define CAN_F7R1_FB29_Pos

#define CAN_F7R1_FB29_Msk

#define CAN_F7R1_FB29

#define CAN_F7R1_FB30_Pos

#define CAN_F7R1_FB30_Msk

#define CAN_F7R1_FB30

#define CAN_F7R1_FB31_Pos

#define CAN_F7R1_FB31_Msk

#define CAN_F7R1_FB31

Bit definition for CAN_F8R1 register

#define CAN_F8R1_FB0_Pos

#define CAN_F8R1_FB0_Msk

#define CAN_F8R1_FB0

#define CAN_F8R1_FB1_Pos

#define CAN_F8R1_FB1_Msk

#define CAN_F8R1_FB1

#define CAN_F8R1_FB2_Pos

#define CAN_F8R1_FB2_Msk

#define CAN_F8R1_FB2

#define CAN_F8R1_FB3_Pos

#define CAN_F8R1_FB3_Msk

#define CAN_F8R1_FB3

#define CAN_F8R1_FB4_Pos

#define CAN_F8R1_FB4_Msk

#define CAN_F8R1_FB4

#define CAN_F8R1_FB5_Pos

#define CAN_F8R1_FB5_Msk

#define CAN_F8R1_FB5

#define CAN_F8R1_FB6_Pos

#define CAN_F8R1_FB6_Msk

#define CAN_F8R1_FB6

#define CAN_F8R1_FB7_Pos

#define CAN_F8R1_FB7_Msk

#define CAN_F8R1_FB7

#define CAN_F8R1_FB8_Pos

#define CAN_F8R1_FB8_Msk

#define CAN_F8R1_FB8

#define CAN_F8R1_FB9_Pos

#define CAN_F8R1_FB9_Msk

#define CAN_F8R1_FB9

#define CAN_F8R1_FB10_Pos

#define CAN_F8R1_FB10_Msk

#define CAN_F8R1_FB10

#define CAN_F8R1_FB11_Pos

#define CAN_F8R1_FB11_Msk

#define CAN_F8R1_FB11

#define CAN_F8R1_FB12_Pos

#define CAN_F8R1_FB12_Msk

#define CAN_F8R1_FB12

#define CAN_F8R1_FB13_Pos

#define CAN_F8R1_FB13_Msk

#define CAN_F8R1_FB13

#define CAN_F8R1_FB14_Pos

#define CAN_F8R1_FB14_Msk

#define CAN_F8R1_FB14

#define CAN_F8R1_FB15_Pos

#define CAN_F8R1_FB15_Msk

#define CAN_F8R1_FB15

#define CAN_F8R1_FB16_Pos

#define CAN_F8R1_FB16_Msk

#define CAN_F8R1_FB16

#define CAN_F8R1_FB17_Pos

#define CAN_F8R1_FB17_Msk

#define CAN_F8R1_FB17

#define CAN_F8R1_FB18_Pos

#define CAN_F8R1_FB18_Msk

#define CAN_F8R1_FB18

#define CAN_F8R1_FB19_Pos

#define CAN_F8R1_FB19_Msk

#define CAN_F8R1_FB19

#define CAN_F8R1_FB20_Pos

#define CAN_F8R1_FB20_Msk

#define CAN_F8R1_FB20

#define CAN_F8R1_FB21_Pos

#define CAN_F8R1_FB21_Msk

#define CAN_F8R1_FB21

#define CAN_F8R1_FB22_Pos

#define CAN_F8R1_FB22_Msk

#define CAN_F8R1_FB22

#define CAN_F8R1_FB23_Pos

#define CAN_F8R1_FB23_Msk

#define CAN_F8R1_FB23

#define CAN_F8R1_FB24_Pos

#define CAN_F8R1_FB24_Msk

#define CAN_F8R1_FB24

#define CAN_F8R1_FB25_Pos

#define CAN_F8R1_FB25_Msk

#define CAN_F8R1_FB25

#define CAN_F8R1_FB26_Pos

#define CAN_F8R1_FB26_Msk

#define CAN_F8R1_FB26

#define CAN_F8R1_FB27_Pos

#define CAN_F8R1_FB27_Msk

#define CAN_F8R1_FB27

#define CAN_F8R1_FB28_Pos

#define CAN_F8R1_FB28_Msk

#define CAN_F8R1_FB28

#define CAN_F8R1_FB29_Pos

#define CAN_F8R1_FB29_Msk

#define CAN_F8R1_FB29

#define CAN_F8R1_FB30_Pos

#define CAN_F8R1_FB30_Msk

#define CAN_F8R1_FB30

#define CAN_F8R1_FB31_Pos

#define CAN_F8R1_FB31_Msk

#define CAN_F8R1_FB31

Bit definition for CAN_F9R1 register

#define CAN_F9R1_FB0_Pos

#define CAN_F9R1_FB0_Msk

#define CAN_F9R1_FB0

#define CAN_F9R1_FB1_Pos

#define CAN_F9R1_FB1_Msk

#define CAN_F9R1_FB1

#define CAN_F9R1_FB2_Pos

#define CAN_F9R1_FB2_Msk

#define CAN_F9R1_FB2

#define CAN_F9R1_FB3_Pos

#define CAN_F9R1_FB3_Msk

#define CAN_F9R1_FB3

#define CAN_F9R1_FB4_Pos

#define CAN_F9R1_FB4_Msk

#define CAN_F9R1_FB4

#define CAN_F9R1_FB5_Pos

#define CAN_F9R1_FB5_Msk

#define CAN_F9R1_FB5

#define CAN_F9R1_FB6_Pos

#define CAN_F9R1_FB6_Msk

#define CAN_F9R1_FB6

#define CAN_F9R1_FB7_Pos

#define CAN_F9R1_FB7_Msk

#define CAN_F9R1_FB7

#define CAN_F9R1_FB8_Pos

#define CAN_F9R1_FB8_Msk

#define CAN_F9R1_FB8

#define CAN_F9R1_FB9_Pos

#define CAN_F9R1_FB9_Msk

#define CAN_F9R1_FB9

#define CAN_F9R1_FB10_Pos

#define CAN_F9R1_FB10_Msk

#define CAN_F9R1_FB10

#define CAN_F9R1_FB11_Pos

#define CAN_F9R1_FB11_Msk

#define CAN_F9R1_FB11

#define CAN_F9R1_FB12_Pos

#define CAN_F9R1_FB12_Msk

#define CAN_F9R1_FB12

#define CAN_F9R1_FB13_Pos

#define CAN_F9R1_FB13_Msk

#define CAN_F9R1_FB13

#define CAN_F9R1_FB14_Pos

#define CAN_F9R1_FB14_Msk

#define CAN_F9R1_FB14

#define CAN_F9R1_FB15_Pos

#define CAN_F9R1_FB15_Msk

#define CAN_F9R1_FB15

#define CAN_F9R1_FB16_Pos

#define CAN_F9R1_FB16_Msk

#define CAN_F9R1_FB16

#define CAN_F9R1_FB17_Pos

#define CAN_F9R1_FB17_Msk

#define CAN_F9R1_FB17

#define CAN_F9R1_FB18_Pos

#define CAN_F9R1_FB18_Msk

#define CAN_F9R1_FB18

#define CAN_F9R1_FB19_Pos

#define CAN_F9R1_FB19_Msk

#define CAN_F9R1_FB19

#define CAN_F9R1_FB20_Pos

#define CAN_F9R1_FB20_Msk

#define CAN_F9R1_FB20

#define CAN_F9R1_FB21_Pos

#define CAN_F9R1_FB21_Msk

#define CAN_F9R1_FB21

#define CAN_F9R1_FB22_Pos

#define CAN_F9R1_FB22_Msk

#define CAN_F9R1_FB22

#define CAN_F9R1_FB23_Pos

#define CAN_F9R1_FB23_Msk

#define CAN_F9R1_FB23

#define CAN_F9R1_FB24_Pos

#define CAN_F9R1_FB24_Msk

#define CAN_F9R1_FB24

#define CAN_F9R1_FB25_Pos

#define CAN_F9R1_FB25_Msk

#define CAN_F9R1_FB25

#define CAN_F9R1_FB26_Pos

#define CAN_F9R1_FB26_Msk

#define CAN_F9R1_FB26

#define CAN_F9R1_FB27_Pos

#define CAN_F9R1_FB27_Msk

#define CAN_F9R1_FB27

#define CAN_F9R1_FB28_Pos

#define CAN_F9R1_FB28_Msk

#define CAN_F9R1_FB28

#define CAN_F9R1_FB29_Pos

#define CAN_F9R1_FB29_Msk

#define CAN_F9R1_FB29

#define CAN_F9R1_FB30_Pos

#define CAN_F9R1_FB30_Msk

#define CAN_F9R1_FB30

#define CAN_F9R1_FB31_Pos

#define CAN_F9R1_FB31_Msk

#define CAN_F9R1_FB31

Bit definition for CAN_F10R1 register

#define CAN_F10R1_FB0_Pos

#define CAN_F10R1_FB0_Msk

#define CAN_F10R1_FB0

#define CAN_F10R1_FB1_Pos

#define CAN_F10R1_FB1_Msk

#define CAN_F10R1_FB1

#define CAN_F10R1_FB2_Pos

#define CAN_F10R1_FB2_Msk

#define CAN_F10R1_FB2

#define CAN_F10R1_FB3_Pos

#define CAN_F10R1_FB3_Msk

#define CAN_F10R1_FB3

#define CAN_F10R1_FB4_Pos

#define CAN_F10R1_FB4_Msk

#define CAN_F10R1_FB4

#define CAN_F10R1_FB5_Pos

#define CAN_F10R1_FB5_Msk

#define CAN_F10R1_FB5

#define CAN_F10R1_FB6_Pos

#define CAN_F10R1_FB6_Msk

#define CAN_F10R1_FB6

#define CAN_F10R1_FB7_Pos

#define CAN_F10R1_FB7_Msk

#define CAN_F10R1_FB7

#define CAN_F10R1_FB8_Pos

#define CAN_F10R1_FB8_Msk

#define CAN_F10R1_FB8

#define CAN_F10R1_FB9_Pos

#define CAN_F10R1_FB9_Msk

#define CAN_F10R1_FB9

#define CAN_F10R1_FB10_Pos

#define CAN_F10R1_FB10_Msk

#define CAN_F10R1_FB10

#define CAN_F10R1_FB11_Pos

#define CAN_F10R1_FB11_Msk

#define CAN_F10R1_FB11

#define CAN_F10R1_FB12_Pos

#define CAN_F10R1_FB12_Msk

#define CAN_F10R1_FB12

#define CAN_F10R1_FB13_Pos

#define CAN_F10R1_FB13_Msk

#define CAN_F10R1_FB13

#define CAN_F10R1_FB14_Pos

#define CAN_F10R1_FB14_Msk

#define CAN_F10R1_FB14

#define CAN_F10R1_FB15_Pos

#define CAN_F10R1_FB15_Msk

#define CAN_F10R1_FB15

#define CAN_F10R1_FB16_Pos

#define CAN_F10R1_FB16_Msk

#define CAN_F10R1_FB16

#define CAN_F10R1_FB17_Pos

#define CAN_F10R1_FB17_Msk

#define CAN_F10R1_FB17

#define CAN_F10R1_FB18_Pos

#define CAN_F10R1_FB18_Msk

#define CAN_F10R1_FB18

#define CAN_F10R1_FB19_Pos

#define CAN_F10R1_FB19_Msk

#define CAN_F10R1_FB19

#define CAN_F10R1_FB20_Pos

#define CAN_F10R1_FB20_Msk

#define CAN_F10R1_FB20

#define CAN_F10R1_FB21_Pos

#define CAN_F10R1_FB21_Msk

#define CAN_F10R1_FB21

#define CAN_F10R1_FB22_Pos

#define CAN_F10R1_FB22_Msk

#define CAN_F10R1_FB22

#define CAN_F10R1_FB23_Pos

#define CAN_F10R1_FB23_Msk

#define CAN_F10R1_FB23

#define CAN_F10R1_FB24_Pos

#define CAN_F10R1_FB24_Msk

#define CAN_F10R1_FB24

#define CAN_F10R1_FB25_Pos

#define CAN_F10R1_FB25_Msk

#define CAN_F10R1_FB25

#define CAN_F10R1_FB26_Pos

#define CAN_F10R1_FB26_Msk

#define CAN_F10R1_FB26

#define CAN_F10R1_FB27_Pos

#define CAN_F10R1_FB27_Msk

#define CAN_F10R1_FB27

#define CAN_F10R1_FB28_Pos

#define CAN_F10R1_FB28_Msk

#define CAN_F10R1_FB28

#define CAN_F10R1_FB29_Pos

#define CAN_F10R1_FB29_Msk

#define CAN_F10R1_FB29

#define CAN_F10R1_FB30_Pos

#define CAN_F10R1_FB30_Msk

#define CAN_F10R1_FB30

#define CAN_F10R1_FB31_Pos

#define CAN_F10R1_FB31_Msk

#define CAN_F10R1_FB31

Bit definition for CAN_F11R1 register

#define CAN_F11R1_FB0_Pos

#define CAN_F11R1_FB0_Msk

#define CAN_F11R1_FB0

#define CAN_F11R1_FB1_Pos

#define CAN_F11R1_FB1_Msk

#define CAN_F11R1_FB1

#define CAN_F11R1_FB2_Pos

#define CAN_F11R1_FB2_Msk

#define CAN_F11R1_FB2

#define CAN_F11R1_FB3_Pos

#define CAN_F11R1_FB3_Msk

#define CAN_F11R1_FB3

#define CAN_F11R1_FB4_Pos

#define CAN_F11R1_FB4_Msk

#define CAN_F11R1_FB4

#define CAN_F11R1_FB5_Pos

#define CAN_F11R1_FB5_Msk

#define CAN_F11R1_FB5

#define CAN_F11R1_FB6_Pos

#define CAN_F11R1_FB6_Msk

#define CAN_F11R1_FB6

#define CAN_F11R1_FB7_Pos

#define CAN_F11R1_FB7_Msk

#define CAN_F11R1_FB7

#define CAN_F11R1_FB8_Pos

#define CAN_F11R1_FB8_Msk

#define CAN_F11R1_FB8

#define CAN_F11R1_FB9_Pos

#define CAN_F11R1_FB9_Msk

#define CAN_F11R1_FB9

#define CAN_F11R1_FB10_Pos

#define CAN_F11R1_FB10_Msk

#define CAN_F11R1_FB10

#define CAN_F11R1_FB11_Pos

#define CAN_F11R1_FB11_Msk

#define CAN_F11R1_FB11

#define CAN_F11R1_FB12_Pos

#define CAN_F11R1_FB12_Msk

#define CAN_F11R1_FB12

#define CAN_F11R1_FB13_Pos

#define CAN_F11R1_FB13_Msk

#define CAN_F11R1_FB13

#define CAN_F11R1_FB14_Pos

#define CAN_F11R1_FB14_Msk

#define CAN_F11R1_FB14

#define CAN_F11R1_FB15_Pos

#define CAN_F11R1_FB15_Msk

#define CAN_F11R1_FB15

#define CAN_F11R1_FB16_Pos

#define CAN_F11R1_FB16_Msk

#define CAN_F11R1_FB16

#define CAN_F11R1_FB17_Pos

#define CAN_F11R1_FB17_Msk

#define CAN_F11R1_FB17

#define CAN_F11R1_FB18_Pos

#define CAN_F11R1_FB18_Msk

#define CAN_F11R1_FB18

#define CAN_F11R1_FB19_Pos

#define CAN_F11R1_FB19_Msk

#define CAN_F11R1_FB19

#define CAN_F11R1_FB20_Pos

#define CAN_F11R1_FB20_Msk

#define CAN_F11R1_FB20

#define CAN_F11R1_FB21_Pos

#define CAN_F11R1_FB21_Msk

#define CAN_F11R1_FB21

#define CAN_F11R1_FB22_Pos

#define CAN_F11R1_FB22_Msk

#define CAN_F11R1_FB22

#define CAN_F11R1_FB23_Pos

#define CAN_F11R1_FB23_Msk

#define CAN_F11R1_FB23

#define CAN_F11R1_FB24_Pos

#define CAN_F11R1_FB24_Msk

#define CAN_F11R1_FB24

#define CAN_F11R1_FB25_Pos

#define CAN_F11R1_FB25_Msk

#define CAN_F11R1_FB25

#define CAN_F11R1_FB26_Pos

#define CAN_F11R1_FB26_Msk

#define CAN_F11R1_FB26

#define CAN_F11R1_FB27_Pos

#define CAN_F11R1_FB27_Msk

#define CAN_F11R1_FB27

#define CAN_F11R1_FB28_Pos

#define CAN_F11R1_FB28_Msk

#define CAN_F11R1_FB28

#define CAN_F11R1_FB29_Pos

#define CAN_F11R1_FB29_Msk

#define CAN_F11R1_FB29

#define CAN_F11R1_FB30_Pos

#define CAN_F11R1_FB30_Msk

#define CAN_F11R1_FB30

#define CAN_F11R1_FB31_Pos

#define CAN_F11R1_FB31_Msk

#define CAN_F11R1_FB31

Bit definition for CAN_F12R1 register

#define CAN_F12R1_FB0_Pos

#define CAN_F12R1_FB0_Msk

#define CAN_F12R1_FB0

#define CAN_F12R1_FB1_Pos

#define CAN_F12R1_FB1_Msk

#define CAN_F12R1_FB1

#define CAN_F12R1_FB2_Pos

#define CAN_F12R1_FB2_Msk

#define CAN_F12R1_FB2

#define CAN_F12R1_FB3_Pos

#define CAN_F12R1_FB3_Msk

#define CAN_F12R1_FB3

#define CAN_F12R1_FB4_Pos

#define CAN_F12R1_FB4_Msk

#define CAN_F12R1_FB4

#define CAN_F12R1_FB5_Pos

#define CAN_F12R1_FB5_Msk

#define CAN_F12R1_FB5

#define CAN_F12R1_FB6_Pos

#define CAN_F12R1_FB6_Msk

#define CAN_F12R1_FB6

#define CAN_F12R1_FB7_Pos

#define CAN_F12R1_FB7_Msk

#define CAN_F12R1_FB7

#define CAN_F12R1_FB8_Pos

#define CAN_F12R1_FB8_Msk

#define CAN_F12R1_FB8

#define CAN_F12R1_FB9_Pos

#define CAN_F12R1_FB9_Msk

#define CAN_F12R1_FB9

#define CAN_F12R1_FB10_Pos

#define CAN_F12R1_FB10_Msk

#define CAN_F12R1_FB10

#define CAN_F12R1_FB11_Pos

#define CAN_F12R1_FB11_Msk

#define CAN_F12R1_FB11

#define CAN_F12R1_FB12_Pos

#define CAN_F12R1_FB12_Msk

#define CAN_F12R1_FB12

#define CAN_F12R1_FB13_Pos

#define CAN_F12R1_FB13_Msk

#define CAN_F12R1_FB13

#define CAN_F12R1_FB14_Pos

#define CAN_F12R1_FB14_Msk

#define CAN_F12R1_FB14

#define CAN_F12R1_FB15_Pos

#define CAN_F12R1_FB15_Msk

#define CAN_F12R1_FB15

#define CAN_F12R1_FB16_Pos

#define CAN_F12R1_FB16_Msk

#define CAN_F12R1_FB16

#define CAN_F12R1_FB17_Pos

#define CAN_F12R1_FB17_Msk

#define CAN_F12R1_FB17

#define CAN_F12R1_FB18_Pos

#define CAN_F12R1_FB18_Msk

#define CAN_F12R1_FB18

#define CAN_F12R1_FB19_Pos

#define CAN_F12R1_FB19_Msk

#define CAN_F12R1_FB19

#define CAN_F12R1_FB20_Pos

#define CAN_F12R1_FB20_Msk

#define CAN_F12R1_FB20

#define CAN_F12R1_FB21_Pos

#define CAN_F12R1_FB21_Msk

#define CAN_F12R1_FB21

#define CAN_F12R1_FB22_Pos

#define CAN_F12R1_FB22_Msk

#define CAN_F12R1_FB22

#define CAN_F12R1_FB23_Pos

#define CAN_F12R1_FB23_Msk

#define CAN_F12R1_FB23

#define CAN_F12R1_FB24_Pos

#define CAN_F12R1_FB24_Msk

#define CAN_F12R1_FB24

#define CAN_F12R1_FB25_Pos

#define CAN_F12R1_FB25_Msk

#define CAN_F12R1_FB25

#define CAN_F12R1_FB26_Pos

#define CAN_F12R1_FB26_Msk

#define CAN_F12R1_FB26

#define CAN_F12R1_FB27_Pos

#define CAN_F12R1_FB27_Msk

#define CAN_F12R1_FB27

#define CAN_F12R1_FB28_Pos

#define CAN_F12R1_FB28_Msk

#define CAN_F12R1_FB28

#define CAN_F12R1_FB29_Pos

#define CAN_F12R1_FB29_Msk

#define CAN_F12R1_FB29

#define CAN_F12R1_FB30_Pos

#define CAN_F12R1_FB30_Msk

#define CAN_F12R1_FB30

#define CAN_F12R1_FB31_Pos

#define CAN_F12R1_FB31_Msk

#define CAN_F12R1_FB31

Bit definition for CAN_F13R1 register

#define CAN_F13R1_FB0_Pos

#define CAN_F13R1_FB0_Msk

#define CAN_F13R1_FB0

#define CAN_F13R1_FB1_Pos

#define CAN_F13R1_FB1_Msk

#define CAN_F13R1_FB1

#define CAN_F13R1_FB2_Pos

#define CAN_F13R1_FB2_Msk

#define CAN_F13R1_FB2

#define CAN_F13R1_FB3_Pos

#define CAN_F13R1_FB3_Msk

#define CAN_F13R1_FB3

#define CAN_F13R1_FB4_Pos

#define CAN_F13R1_FB4_Msk

#define CAN_F13R1_FB4

#define CAN_F13R1_FB5_Pos

#define CAN_F13R1_FB5_Msk

#define CAN_F13R1_FB5

#define CAN_F13R1_FB6_Pos

#define CAN_F13R1_FB6_Msk

#define CAN_F13R1_FB6

#define CAN_F13R1_FB7_Pos

#define CAN_F13R1_FB7_Msk

#define CAN_F13R1_FB7

#define CAN_F13R1_FB8_Pos

#define CAN_F13R1_FB8_Msk

#define CAN_F13R1_FB8

#define CAN_F13R1_FB9_Pos

#define CAN_F13R1_FB9_Msk

#define CAN_F13R1_FB9

#define CAN_F13R1_FB10_Pos

#define CAN_F13R1_FB10_Msk

#define CAN_F13R1_FB10

#define CAN_F13R1_FB11_Pos

#define CAN_F13R1_FB11_Msk

#define CAN_F13R1_FB11

#define CAN_F13R1_FB12_Pos

#define CAN_F13R1_FB12_Msk

#define CAN_F13R1_FB12

#define CAN_F13R1_FB13_Pos

#define CAN_F13R1_FB13_Msk

#define CAN_F13R1_FB13

#define CAN_F13R1_FB14_Pos

#define CAN_F13R1_FB14_Msk

#define CAN_F13R1_FB14

#define CAN_F13R1_FB15_Pos

#define CAN_F13R1_FB15_Msk

#define CAN_F13R1_FB15

#define CAN_F13R1_FB16_Pos

#define CAN_F13R1_FB16_Msk

#define CAN_F13R1_FB16

#define CAN_F13R1_FB17_Pos

#define CAN_F13R1_FB17_Msk

#define CAN_F13R1_FB17

#define CAN_F13R1_FB18_Pos

#define CAN_F13R1_FB18_Msk

#define CAN_F13R1_FB18

#define CAN_F13R1_FB19_Pos

#define CAN_F13R1_FB19_Msk

#define CAN_F13R1_FB19

#define CAN_F13R1_FB20_Pos

#define CAN_F13R1_FB20_Msk

#define CAN_F13R1_FB20

#define CAN_F13R1_FB21_Pos

#define CAN_F13R1_FB21_Msk

#define CAN_F13R1_FB21

#define CAN_F13R1_FB22_Pos

#define CAN_F13R1_FB22_Msk

#define CAN_F13R1_FB22

#define CAN_F13R1_FB23_Pos

#define CAN_F13R1_FB23_Msk

#define CAN_F13R1_FB23

#define CAN_F13R1_FB24_Pos

#define CAN_F13R1_FB24_Msk

#define CAN_F13R1_FB24

#define CAN_F13R1_FB25_Pos

#define CAN_F13R1_FB25_Msk

#define CAN_F13R1_FB25

#define CAN_F13R1_FB26_Pos

#define CAN_F13R1_FB26_Msk

#define CAN_F13R1_FB26

#define CAN_F13R1_FB27_Pos

#define CAN_F13R1_FB27_Msk

#define CAN_F13R1_FB27

#define CAN_F13R1_FB28_Pos

#define CAN_F13R1_FB28_Msk

#define CAN_F13R1_FB28

#define CAN_F13R1_FB29_Pos

#define CAN_F13R1_FB29_Msk

#define CAN_F13R1_FB29

#define CAN_F13R1_FB30_Pos

#define CAN_F13R1_FB30_Msk

#define CAN_F13R1_FB30

#define CAN_F13R1_FB31_Pos

#define CAN_F13R1_FB31_Msk

#define CAN_F13R1_FB31

Bit definition for CAN_F0R2 register

#define CAN_F0R2_FB0_Pos

#define CAN_F0R2_FB0_Msk

#define CAN_F0R2_FB0

#define CAN_F0R2_FB1_Pos

#define CAN_F0R2_FB1_Msk

#define CAN_F0R2_FB1

#define CAN_F0R2_FB2_Pos

#define CAN_F0R2_FB2_Msk

#define CAN_F0R2_FB2

#define CAN_F0R2_FB3_Pos

#define CAN_F0R2_FB3_Msk

#define CAN_F0R2_FB3

#define CAN_F0R2_FB4_Pos

#define CAN_F0R2_FB4_Msk

#define CAN_F0R2_FB4

#define CAN_F0R2_FB5_Pos

#define CAN_F0R2_FB5_Msk

#define CAN_F0R2_FB5

#define CAN_F0R2_FB6_Pos

#define CAN_F0R2_FB6_Msk

#define CAN_F0R2_FB6

#define CAN_F0R2_FB7_Pos

#define CAN_F0R2_FB7_Msk

#define CAN_F0R2_FB7

#define CAN_F0R2_FB8_Pos

#define CAN_F0R2_FB8_Msk

#define CAN_F0R2_FB8

#define CAN_F0R2_FB9_Pos

#define CAN_F0R2_FB9_Msk

#define CAN_F0R2_FB9

#define CAN_F0R2_FB10_Pos

#define CAN_F0R2_FB10_Msk

#define CAN_F0R2_FB10

#define CAN_F0R2_FB11_Pos

#define CAN_F0R2_FB11_Msk

#define CAN_F0R2_FB11

#define CAN_F0R2_FB12_Pos

#define CAN_F0R2_FB12_Msk

#define CAN_F0R2_FB12

#define CAN_F0R2_FB13_Pos

#define CAN_F0R2_FB13_Msk

#define CAN_F0R2_FB13

#define CAN_F0R2_FB14_Pos

#define CAN_F0R2_FB14_Msk

#define CAN_F0R2_FB14

#define CAN_F0R2_FB15_Pos

#define CAN_F0R2_FB15_Msk

#define CAN_F0R2_FB15

#define CAN_F0R2_FB16_Pos

#define CAN_F0R2_FB16_Msk

#define CAN_F0R2_FB16

#define CAN_F0R2_FB17_Pos

#define CAN_F0R2_FB17_Msk

#define CAN_F0R2_FB17

#define CAN_F0R2_FB18_Pos

#define CAN_F0R2_FB18_Msk

#define CAN_F0R2_FB18

#define CAN_F0R2_FB19_Pos

#define CAN_F0R2_FB19_Msk

#define CAN_F0R2_FB19

#define CAN_F0R2_FB20_Pos

#define CAN_F0R2_FB20_Msk

#define CAN_F0R2_FB20

#define CAN_F0R2_FB21_Pos

#define CAN_F0R2_FB21_Msk

#define CAN_F0R2_FB21

#define CAN_F0R2_FB22_Pos

#define CAN_F0R2_FB22_Msk

#define CAN_F0R2_FB22

#define CAN_F0R2_FB23_Pos

#define CAN_F0R2_FB23_Msk

#define CAN_F0R2_FB23

#define CAN_F0R2_FB24_Pos

#define CAN_F0R2_FB24_Msk

#define CAN_F0R2_FB24

#define CAN_F0R2_FB25_Pos

#define CAN_F0R2_FB25_Msk

#define CAN_F0R2_FB25

#define CAN_F0R2_FB26_Pos

#define CAN_F0R2_FB26_Msk

#define CAN_F0R2_FB26

#define CAN_F0R2_FB27_Pos

#define CAN_F0R2_FB27_Msk

#define CAN_F0R2_FB27

#define CAN_F0R2_FB28_Pos

#define CAN_F0R2_FB28_Msk

#define CAN_F0R2_FB28

#define CAN_F0R2_FB29_Pos

#define CAN_F0R2_FB29_Msk

#define CAN_F0R2_FB29

#define CAN_F0R2_FB30_Pos

#define CAN_F0R2_FB30_Msk

#define CAN_F0R2_FB30

#define CAN_F0R2_FB31_Pos

#define CAN_F0R2_FB31_Msk

#define CAN_F0R2_FB31

Bit definition for CAN_F1R2 register

#define CAN_F1R2_FB0_Pos

#define CAN_F1R2_FB0_Msk

#define CAN_F1R2_FB0

#define CAN_F1R2_FB1_Pos

#define CAN_F1R2_FB1_Msk

#define CAN_F1R2_FB1

#define CAN_F1R2_FB2_Pos

#define CAN_F1R2_FB2_Msk

#define CAN_F1R2_FB2

#define CAN_F1R2_FB3_Pos

#define CAN_F1R2_FB3_Msk

#define CAN_F1R2_FB3

#define CAN_F1R2_FB4_Pos

#define CAN_F1R2_FB4_Msk

#define CAN_F1R2_FB4

#define CAN_F1R2_FB5_Pos

#define CAN_F1R2_FB5_Msk

#define CAN_F1R2_FB5

#define CAN_F1R2_FB6_Pos

#define CAN_F1R2_FB6_Msk

#define CAN_F1R2_FB6

#define CAN_F1R2_FB7_Pos

#define CAN_F1R2_FB7_Msk

#define CAN_F1R2_FB7

#define CAN_F1R2_FB8_Pos

#define CAN_F1R2_FB8_Msk

#define CAN_F1R2_FB8

#define CAN_F1R2_FB9_Pos

#define CAN_F1R2_FB9_Msk

#define CAN_F1R2_FB9

#define CAN_F1R2_FB10_Pos

#define CAN_F1R2_FB10_Msk

#define CAN_F1R2_FB10

#define CAN_F1R2_FB11_Pos

#define CAN_F1R2_FB11_Msk

#define CAN_F1R2_FB11

#define CAN_F1R2_FB12_Pos

#define CAN_F1R2_FB12_Msk

#define CAN_F1R2_FB12

#define CAN_F1R2_FB13_Pos

#define CAN_F1R2_FB13_Msk

#define CAN_F1R2_FB13

#define CAN_F1R2_FB14_Pos

#define CAN_F1R2_FB14_Msk

#define CAN_F1R2_FB14

#define CAN_F1R2_FB15_Pos

#define CAN_F1R2_FB15_Msk

#define CAN_F1R2_FB15

#define CAN_F1R2_FB16_Pos

#define CAN_F1R2_FB16_Msk

#define CAN_F1R2_FB16

#define CAN_F1R2_FB17_Pos

#define CAN_F1R2_FB17_Msk

#define CAN_F1R2_FB17

#define CAN_F1R2_FB18_Pos

#define CAN_F1R2_FB18_Msk

#define CAN_F1R2_FB18

#define CAN_F1R2_FB19_Pos

#define CAN_F1R2_FB19_Msk

#define CAN_F1R2_FB19

#define CAN_F1R2_FB20_Pos

#define CAN_F1R2_FB20_Msk

#define CAN_F1R2_FB20

#define CAN_F1R2_FB21_Pos

#define CAN_F1R2_FB21_Msk

#define CAN_F1R2_FB21

#define CAN_F1R2_FB22_Pos

#define CAN_F1R2_FB22_Msk

#define CAN_F1R2_FB22

#define CAN_F1R2_FB23_Pos

#define CAN_F1R2_FB23_Msk

#define CAN_F1R2_FB23

#define CAN_F1R2_FB24_Pos

#define CAN_F1R2_FB24_Msk

#define CAN_F1R2_FB24

#define CAN_F1R2_FB25_Pos

#define CAN_F1R2_FB25_Msk

#define CAN_F1R2_FB25

#define CAN_F1R2_FB26_Pos

#define CAN_F1R2_FB26_Msk

#define CAN_F1R2_FB26

#define CAN_F1R2_FB27_Pos

#define CAN_F1R2_FB27_Msk

#define CAN_F1R2_FB27

#define CAN_F1R2_FB28_Pos

#define CAN_F1R2_FB28_Msk

#define CAN_F1R2_FB28

#define CAN_F1R2_FB29_Pos

#define CAN_F1R2_FB29_Msk

#define CAN_F1R2_FB29

#define CAN_F1R2_FB30_Pos

#define CAN_F1R2_FB30_Msk

#define CAN_F1R2_FB30

#define CAN_F1R2_FB31_Pos

#define CAN_F1R2_FB31_Msk

#define CAN_F1R2_FB31

Bit definition for CAN_F2R2 register

#define CAN_F2R2_FB0_Pos

#define CAN_F2R2_FB0_Msk

#define CAN_F2R2_FB0

#define CAN_F2R2_FB1_Pos

#define CAN_F2R2_FB1_Msk

#define CAN_F2R2_FB1

#define CAN_F2R2_FB2_Pos

#define CAN_F2R2_FB2_Msk

#define CAN_F2R2_FB2

#define CAN_F2R2_FB3_Pos

#define CAN_F2R2_FB3_Msk

#define CAN_F2R2_FB3

#define CAN_F2R2_FB4_Pos

#define CAN_F2R2_FB4_Msk

#define CAN_F2R2_FB4

#define CAN_F2R2_FB5_Pos

#define CAN_F2R2_FB5_Msk

#define CAN_F2R2_FB5

#define CAN_F2R2_FB6_Pos

#define CAN_F2R2_FB6_Msk

#define CAN_F2R2_FB6

#define CAN_F2R2_FB7_Pos

#define CAN_F2R2_FB7_Msk

#define CAN_F2R2_FB7

#define CAN_F2R2_FB8_Pos

#define CAN_F2R2_FB8_Msk

#define CAN_F2R2_FB8

#define CAN_F2R2_FB9_Pos

#define CAN_F2R2_FB9_Msk

#define CAN_F2R2_FB9

#define CAN_F2R2_FB10_Pos

#define CAN_F2R2_FB10_Msk

#define CAN_F2R2_FB10

#define CAN_F2R2_FB11_Pos

#define CAN_F2R2_FB11_Msk

#define CAN_F2R2_FB11

#define CAN_F2R2_FB12_Pos

#define CAN_F2R2_FB12_Msk

#define CAN_F2R2_FB12

#define CAN_F2R2_FB13_Pos

#define CAN_F2R2_FB13_Msk

#define CAN_F2R2_FB13

#define CAN_F2R2_FB14_Pos

#define CAN_F2R2_FB14_Msk

#define CAN_F2R2_FB14

#define CAN_F2R2_FB15_Pos

#define CAN_F2R2_FB15_Msk

#define CAN_F2R2_FB15

#define CAN_F2R2_FB16_Pos

#define CAN_F2R2_FB16_Msk

#define CAN_F2R2_FB16

#define CAN_F2R2_FB17_Pos

#define CAN_F2R2_FB17_Msk

#define CAN_F2R2_FB17

#define CAN_F2R2_FB18_Pos

#define CAN_F2R2_FB18_Msk

#define CAN_F2R2_FB18

#define CAN_F2R2_FB19_Pos

#define CAN_F2R2_FB19_Msk

#define CAN_F2R2_FB19

#define CAN_F2R2_FB20_Pos

#define CAN_F2R2_FB20_Msk

#define CAN_F2R2_FB20

#define CAN_F2R2_FB21_Pos

#define CAN_F2R2_FB21_Msk

#define CAN_F2R2_FB21

#define CAN_F2R2_FB22_Pos

#define CAN_F2R2_FB22_Msk

#define CAN_F2R2_FB22

#define CAN_F2R2_FB23_Pos

#define CAN_F2R2_FB23_Msk

#define CAN_F2R2_FB23

#define CAN_F2R2_FB24_Pos

#define CAN_F2R2_FB24_Msk

#define CAN_F2R2_FB24

#define CAN_F2R2_FB25_Pos

#define CAN_F2R2_FB25_Msk

#define CAN_F2R2_FB25

#define CAN_F2R2_FB26_Pos

#define CAN_F2R2_FB26_Msk

#define CAN_F2R2_FB26

#define CAN_F2R2_FB27_Pos

#define CAN_F2R2_FB27_Msk

#define CAN_F2R2_FB27

#define CAN_F2R2_FB28_Pos

#define CAN_F2R2_FB28_Msk

#define CAN_F2R2_FB28

#define CAN_F2R2_FB29_Pos

#define CAN_F2R2_FB29_Msk

#define CAN_F2R2_FB29

#define CAN_F2R2_FB30_Pos

#define CAN_F2R2_FB30_Msk

#define CAN_F2R2_FB30

#define CAN_F2R2_FB31_Pos

#define CAN_F2R2_FB31_Msk

#define CAN_F2R2_FB31

Bit definition for CAN_F3R2 register

#define CAN_F3R2_FB0_Pos

#define CAN_F3R2_FB0_Msk

#define CAN_F3R2_FB0

#define CAN_F3R2_FB1_Pos

#define CAN_F3R2_FB1_Msk

#define CAN_F3R2_FB1

#define CAN_F3R2_FB2_Pos

#define CAN_F3R2_FB2_Msk

#define CAN_F3R2_FB2

#define CAN_F3R2_FB3_Pos

#define CAN_F3R2_FB3_Msk

#define CAN_F3R2_FB3

#define CAN_F3R2_FB4_Pos

#define CAN_F3R2_FB4_Msk

#define CAN_F3R2_FB4

#define CAN_F3R2_FB5_Pos

#define CAN_F3R2_FB5_Msk

#define CAN_F3R2_FB5

#define CAN_F3R2_FB6_Pos

#define CAN_F3R2_FB6_Msk

#define CAN_F3R2_FB6

#define CAN_F3R2_FB7_Pos

#define CAN_F3R2_FB7_Msk

#define CAN_F3R2_FB7

#define CAN_F3R2_FB8_Pos

#define CAN_F3R2_FB8_Msk

#define CAN_F3R2_FB8

#define CAN_F3R2_FB9_Pos

#define CAN_F3R2_FB9_Msk

#define CAN_F3R2_FB9

#define CAN_F3R2_FB10_Pos

#define CAN_F3R2_FB10_Msk

#define CAN_F3R2_FB10

#define CAN_F3R2_FB11_Pos

#define CAN_F3R2_FB11_Msk

#define CAN_F3R2_FB11

#define CAN_F3R2_FB12_Pos

#define CAN_F3R2_FB12_Msk

#define CAN_F3R2_FB12

#define CAN_F3R2_FB13_Pos

#define CAN_F3R2_FB13_Msk

#define CAN_F3R2_FB13

#define CAN_F3R2_FB14_Pos

#define CAN_F3R2_FB14_Msk

#define CAN_F3R2_FB14

#define CAN_F3R2_FB15_Pos

#define CAN_F3R2_FB15_Msk

#define CAN_F3R2_FB15

#define CAN_F3R2_FB16_Pos

#define CAN_F3R2_FB16_Msk

#define CAN_F3R2_FB16

#define CAN_F3R2_FB17_Pos

#define CAN_F3R2_FB17_Msk

#define CAN_F3R2_FB17

#define CAN_F3R2_FB18_Pos

#define CAN_F3R2_FB18_Msk

#define CAN_F3R2_FB18

#define CAN_F3R2_FB19_Pos

#define CAN_F3R2_FB19_Msk

#define CAN_F3R2_FB19

#define CAN_F3R2_FB20_Pos

#define CAN_F3R2_FB20_Msk

#define CAN_F3R2_FB20

#define CAN_F3R2_FB21_Pos

#define CAN_F3R2_FB21_Msk

#define CAN_F3R2_FB21

#define CAN_F3R2_FB22_Pos

#define CAN_F3R2_FB22_Msk

#define CAN_F3R2_FB22

#define CAN_F3R2_FB23_Pos

#define CAN_F3R2_FB23_Msk

#define CAN_F3R2_FB23

#define CAN_F3R2_FB24_Pos

#define CAN_F3R2_FB24_Msk

#define CAN_F3R2_FB24

#define CAN_F3R2_FB25_Pos

#define CAN_F3R2_FB25_Msk

#define CAN_F3R2_FB25

#define CAN_F3R2_FB26_Pos

#define CAN_F3R2_FB26_Msk

#define CAN_F3R2_FB26

#define CAN_F3R2_FB27_Pos

#define CAN_F3R2_FB27_Msk

#define CAN_F3R2_FB27

#define CAN_F3R2_FB28_Pos

#define CAN_F3R2_FB28_Msk

#define CAN_F3R2_FB28

#define CAN_F3R2_FB29_Pos

#define CAN_F3R2_FB29_Msk

#define CAN_F3R2_FB29

#define CAN_F3R2_FB30_Pos

#define CAN_F3R2_FB30_Msk

#define CAN_F3R2_FB30

#define CAN_F3R2_FB31_Pos

#define CAN_F3R2_FB31_Msk

#define CAN_F3R2_FB31

Bit definition for CAN_F4R2 register

#define CAN_F4R2_FB0_Pos

#define CAN_F4R2_FB0_Msk

#define CAN_F4R2_FB0

#define CAN_F4R2_FB1_Pos

#define CAN_F4R2_FB1_Msk

#define CAN_F4R2_FB1

#define CAN_F4R2_FB2_Pos

#define CAN_F4R2_FB2_Msk

#define CAN_F4R2_FB2

#define CAN_F4R2_FB3_Pos

#define CAN_F4R2_FB3_Msk

#define CAN_F4R2_FB3

#define CAN_F4R2_FB4_Pos

#define CAN_F4R2_FB4_Msk

#define CAN_F4R2_FB4

#define CAN_F4R2_FB5_Pos

#define CAN_F4R2_FB5_Msk

#define CAN_F4R2_FB5

#define CAN_F4R2_FB6_Pos

#define CAN_F4R2_FB6_Msk

#define CAN_F4R2_FB6

#define CAN_F4R2_FB7_Pos

#define CAN_F4R2_FB7_Msk

#define CAN_F4R2_FB7

#define CAN_F4R2_FB8_Pos

#define CAN_F4R2_FB8_Msk

#define CAN_F4R2_FB8

#define CAN_F4R2_FB9_Pos

#define CAN_F4R2_FB9_Msk

#define CAN_F4R2_FB9

#define CAN_F4R2_FB10_Pos

#define CAN_F4R2_FB10_Msk

#define CAN_F4R2_FB10

#define CAN_F4R2_FB11_Pos

#define CAN_F4R2_FB11_Msk

#define CAN_F4R2_FB11

#define CAN_F4R2_FB12_Pos

#define CAN_F4R2_FB12_Msk

#define CAN_F4R2_FB12

#define CAN_F4R2_FB13_Pos

#define CAN_F4R2_FB13_Msk

#define CAN_F4R2_FB13

#define CAN_F4R2_FB14_Pos

#define CAN_F4R2_FB14_Msk

#define CAN_F4R2_FB14

#define CAN_F4R2_FB15_Pos

#define CAN_F4R2_FB15_Msk

#define CAN_F4R2_FB15

#define CAN_F4R2_FB16_Pos

#define CAN_F4R2_FB16_Msk

#define CAN_F4R2_FB16

#define CAN_F4R2_FB17_Pos

#define CAN_F4R2_FB17_Msk

#define CAN_F4R2_FB17

#define CAN_F4R2_FB18_Pos

#define CAN_F4R2_FB18_Msk

#define CAN_F4R2_FB18

#define CAN_F4R2_FB19_Pos

#define CAN_F4R2_FB19_Msk

#define CAN_F4R2_FB19

#define CAN_F4R2_FB20_Pos

#define CAN_F4R2_FB20_Msk

#define CAN_F4R2_FB20

#define CAN_F4R2_FB21_Pos

#define CAN_F4R2_FB21_Msk

#define CAN_F4R2_FB21

#define CAN_F4R2_FB22_Pos

#define CAN_F4R2_FB22_Msk

#define CAN_F4R2_FB22

#define CAN_F4R2_FB23_Pos

#define CAN_F4R2_FB23_Msk

#define CAN_F4R2_FB23

#define CAN_F4R2_FB24_Pos

#define CAN_F4R2_FB24_Msk

#define CAN_F4R2_FB24

#define CAN_F4R2_FB25_Pos

#define CAN_F4R2_FB25_Msk

#define CAN_F4R2_FB25

#define CAN_F4R2_FB26_Pos

#define CAN_F4R2_FB26_Msk

#define CAN_F4R2_FB26

#define CAN_F4R2_FB27_Pos

#define CAN_F4R2_FB27_Msk

#define CAN_F4R2_FB27

#define CAN_F4R2_FB28_Pos

#define CAN_F4R2_FB28_Msk

#define CAN_F4R2_FB28

#define CAN_F4R2_FB29_Pos

#define CAN_F4R2_FB29_Msk

#define CAN_F4R2_FB29

#define CAN_F4R2_FB30_Pos

#define CAN_F4R2_FB30_Msk

#define CAN_F4R2_FB30

#define CAN_F4R2_FB31_Pos

#define CAN_F4R2_FB31_Msk

#define CAN_F4R2_FB31

Bit definition for CAN_F5R2 register

#define CAN_F5R2_FB0_Pos

#define CAN_F5R2_FB0_Msk

#define CAN_F5R2_FB0

#define CAN_F5R2_FB1_Pos

#define CAN_F5R2_FB1_Msk

#define CAN_F5R2_FB1

#define CAN_F5R2_FB2_Pos

#define CAN_F5R2_FB2_Msk

#define CAN_F5R2_FB2

#define CAN_F5R2_FB3_Pos

#define CAN_F5R2_FB3_Msk

#define CAN_F5R2_FB3

#define CAN_F5R2_FB4_Pos

#define CAN_F5R2_FB4_Msk

#define CAN_F5R2_FB4

#define CAN_F5R2_FB5_Pos

#define CAN_F5R2_FB5_Msk

#define CAN_F5R2_FB5

#define CAN_F5R2_FB6_Pos

#define CAN_F5R2_FB6_Msk

#define CAN_F5R2_FB6

#define CAN_F5R2_FB7_Pos

#define CAN_F5R2_FB7_Msk

#define CAN_F5R2_FB7

#define CAN_F5R2_FB8_Pos

#define CAN_F5R2_FB8_Msk

#define CAN_F5R2_FB8

#define CAN_F5R2_FB9_Pos

#define CAN_F5R2_FB9_Msk

#define CAN_F5R2_FB9

#define CAN_F5R2_FB10_Pos

#define CAN_F5R2_FB10_Msk

#define CAN_F5R2_FB10

#define CAN_F5R2_FB11_Pos

#define CAN_F5R2_FB11_Msk

#define CAN_F5R2_FB11

#define CAN_F5R2_FB12_Pos

#define CAN_F5R2_FB12_Msk

#define CAN_F5R2_FB12

#define CAN_F5R2_FB13_Pos

#define CAN_F5R2_FB13_Msk

#define CAN_F5R2_FB13

#define CAN_F5R2_FB14_Pos

#define CAN_F5R2_FB14_Msk

#define CAN_F5R2_FB14

#define CAN_F5R2_FB15_Pos

#define CAN_F5R2_FB15_Msk

#define CAN_F5R2_FB15

#define CAN_F5R2_FB16_Pos

#define CAN_F5R2_FB16_Msk

#define CAN_F5R2_FB16

#define CAN_F5R2_FB17_Pos

#define CAN_F5R2_FB17_Msk

#define CAN_F5R2_FB17

#define CAN_F5R2_FB18_Pos

#define CAN_F5R2_FB18_Msk

#define CAN_F5R2_FB18

#define CAN_F5R2_FB19_Pos

#define CAN_F5R2_FB19_Msk

#define CAN_F5R2_FB19

#define CAN_F5R2_FB20_Pos

#define CAN_F5R2_FB20_Msk

#define CAN_F5R2_FB20

#define CAN_F5R2_FB21_Pos

#define CAN_F5R2_FB21_Msk

#define CAN_F5R2_FB21

#define CAN_F5R2_FB22_Pos

#define CAN_F5R2_FB22_Msk

#define CAN_F5R2_FB22

#define CAN_F5R2_FB23_Pos

#define CAN_F5R2_FB23_Msk

#define CAN_F5R2_FB23

#define CAN_F5R2_FB24_Pos

#define CAN_F5R2_FB24_Msk

#define CAN_F5R2_FB24

#define CAN_F5R2_FB25_Pos

#define CAN_F5R2_FB25_Msk

#define CAN_F5R2_FB25

#define CAN_F5R2_FB26_Pos

#define CAN_F5R2_FB26_Msk

#define CAN_F5R2_FB26

#define CAN_F5R2_FB27_Pos

#define CAN_F5R2_FB27_Msk

#define CAN_F5R2_FB27

#define CAN_F5R2_FB28_Pos

#define CAN_F5R2_FB28_Msk

#define CAN_F5R2_FB28

#define CAN_F5R2_FB29_Pos

#define CAN_F5R2_FB29_Msk

#define CAN_F5R2_FB29

#define CAN_F5R2_FB30_Pos

#define CAN_F5R2_FB30_Msk

#define CAN_F5R2_FB30

#define CAN_F5R2_FB31_Pos

#define CAN_F5R2_FB31_Msk

#define CAN_F5R2_FB31

Bit definition for CAN_F6R2 register

#define CAN_F6R2_FB0_Pos

#define CAN_F6R2_FB0_Msk

#define CAN_F6R2_FB0

#define CAN_F6R2_FB1_Pos

#define CAN_F6R2_FB1_Msk

#define CAN_F6R2_FB1

#define CAN_F6R2_FB2_Pos

#define CAN_F6R2_FB2_Msk

#define CAN_F6R2_FB2

#define CAN_F6R2_FB3_Pos

#define CAN_F6R2_FB3_Msk

#define CAN_F6R2_FB3

#define CAN_F6R2_FB4_Pos

#define CAN_F6R2_FB4_Msk

#define CAN_F6R2_FB4

#define CAN_F6R2_FB5_Pos

#define CAN_F6R2_FB5_Msk

#define CAN_F6R2_FB5

#define CAN_F6R2_FB6_Pos

#define CAN_F6R2_FB6_Msk

#define CAN_F6R2_FB6

#define CAN_F6R2_FB7_Pos

#define CAN_F6R2_FB7_Msk

#define CAN_F6R2_FB7

#define CAN_F6R2_FB8_Pos

#define CAN_F6R2_FB8_Msk

#define CAN_F6R2_FB8

#define CAN_F6R2_FB9_Pos

#define CAN_F6R2_FB9_Msk

#define CAN_F6R2_FB9

#define CAN_F6R2_FB10_Pos

#define CAN_F6R2_FB10_Msk

#define CAN_F6R2_FB10

#define CAN_F6R2_FB11_Pos

#define CAN_F6R2_FB11_Msk

#define CAN_F6R2_FB11

#define CAN_F6R2_FB12_Pos

#define CAN_F6R2_FB12_Msk

#define CAN_F6R2_FB12

#define CAN_F6R2_FB13_Pos

#define CAN_F6R2_FB13_Msk

#define CAN_F6R2_FB13

#define CAN_F6R2_FB14_Pos

#define CAN_F6R2_FB14_Msk

#define CAN_F6R2_FB14

#define CAN_F6R2_FB15_Pos

#define CAN_F6R2_FB15_Msk

#define CAN_F6R2_FB15

#define CAN_F6R2_FB16_Pos

#define CAN_F6R2_FB16_Msk

#define CAN_F6R2_FB16

#define CAN_F6R2_FB17_Pos

#define CAN_F6R2_FB17_Msk

#define CAN_F6R2_FB17

#define CAN_F6R2_FB18_Pos

#define CAN_F6R2_FB18_Msk

#define CAN_F6R2_FB18

#define CAN_F6R2_FB19_Pos

#define CAN_F6R2_FB19_Msk

#define CAN_F6R2_FB19

#define CAN_F6R2_FB20_Pos

#define CAN_F6R2_FB20_Msk

#define CAN_F6R2_FB20

#define CAN_F6R2_FB21_Pos

#define CAN_F6R2_FB21_Msk

#define CAN_F6R2_FB21

#define CAN_F6R2_FB22_Pos

#define CAN_F6R2_FB22_Msk

#define CAN_F6R2_FB22

#define CAN_F6R2_FB23_Pos

#define CAN_F6R2_FB23_Msk

#define CAN_F6R2_FB23

#define CAN_F6R2_FB24_Pos

#define CAN_F6R2_FB24_Msk

#define CAN_F6R2_FB24

#define CAN_F6R2_FB25_Pos

#define CAN_F6R2_FB25_Msk

#define CAN_F6R2_FB25

#define CAN_F6R2_FB26_Pos

#define CAN_F6R2_FB26_Msk

#define CAN_F6R2_FB26

#define CAN_F6R2_FB27_Pos

#define CAN_F6R2_FB27_Msk

#define CAN_F6R2_FB27

#define CAN_F6R2_FB28_Pos

#define CAN_F6R2_FB28_Msk

#define CAN_F6R2_FB28

#define CAN_F6R2_FB29_Pos

#define CAN_F6R2_FB29_Msk

#define CAN_F6R2_FB29

#define CAN_F6R2_FB30_Pos

#define CAN_F6R2_FB30_Msk

#define CAN_F6R2_FB30

#define CAN_F6R2_FB31_Pos

#define CAN_F6R2_FB31_Msk

#define CAN_F6R2_FB31

Bit definition for CAN_F7R2 register

#define CAN_F7R2_FB0_Pos

#define CAN_F7R2_FB0_Msk

#define CAN_F7R2_FB0

#define CAN_F7R2_FB1_Pos

#define CAN_F7R2_FB1_Msk

#define CAN_F7R2_FB1

#define CAN_F7R2_FB2_Pos

#define CAN_F7R2_FB2_Msk

#define CAN_F7R2_FB2

#define CAN_F7R2_FB3_Pos

#define CAN_F7R2_FB3_Msk

#define CAN_F7R2_FB3

#define CAN_F7R2_FB4_Pos

#define CAN_F7R2_FB4_Msk

#define CAN_F7R2_FB4

#define CAN_F7R2_FB5_Pos

#define CAN_F7R2_FB5_Msk

#define CAN_F7R2_FB5

#define CAN_F7R2_FB6_Pos

#define CAN_F7R2_FB6_Msk

#define CAN_F7R2_FB6

#define CAN_F7R2_FB7_Pos

#define CAN_F7R2_FB7_Msk

#define CAN_F7R2_FB7

#define CAN_F7R2_FB8_Pos

#define CAN_F7R2_FB8_Msk

#define CAN_F7R2_FB8

#define CAN_F7R2_FB9_Pos

#define CAN_F7R2_FB9_Msk

#define CAN_F7R2_FB9

#define CAN_F7R2_FB10_Pos

#define CAN_F7R2_FB10_Msk

#define CAN_F7R2_FB10

#define CAN_F7R2_FB11_Pos

#define CAN_F7R2_FB11_Msk

#define CAN_F7R2_FB11

#define CAN_F7R2_FB12_Pos

#define CAN_F7R2_FB12_Msk

#define CAN_F7R2_FB12

#define CAN_F7R2_FB13_Pos

#define CAN_F7R2_FB13_Msk

#define CAN_F7R2_FB13

#define CAN_F7R2_FB14_Pos

#define CAN_F7R2_FB14_Msk

#define CAN_F7R2_FB14

#define CAN_F7R2_FB15_Pos

#define CAN_F7R2_FB15_Msk

#define CAN_F7R2_FB15

#define CAN_F7R2_FB16_Pos

#define CAN_F7R2_FB16_Msk

#define CAN_F7R2_FB16

#define CAN_F7R2_FB17_Pos

#define CAN_F7R2_FB17_Msk

#define CAN_F7R2_FB17

#define CAN_F7R2_FB18_Pos

#define CAN_F7R2_FB18_Msk

#define CAN_F7R2_FB18

#define CAN_F7R2_FB19_Pos

#define CAN_F7R2_FB19_Msk

#define CAN_F7R2_FB19

#define CAN_F7R2_FB20_Pos

#define CAN_F7R2_FB20_Msk

#define CAN_F7R2_FB20

#define CAN_F7R2_FB21_Pos

#define CAN_F7R2_FB21_Msk

#define CAN_F7R2_FB21

#define CAN_F7R2_FB22_Pos

#define CAN_F7R2_FB22_Msk

#define CAN_F7R2_FB22

#define CAN_F7R2_FB23_Pos

#define CAN_F7R2_FB23_Msk

#define CAN_F7R2_FB23

#define CAN_F7R2_FB24_Pos

#define CAN_F7R2_FB24_Msk

#define CAN_F7R2_FB24

#define CAN_F7R2_FB25_Pos

#define CAN_F7R2_FB25_Msk

#define CAN_F7R2_FB25

#define CAN_F7R2_FB26_Pos

#define CAN_F7R2_FB26_Msk

#define CAN_F7R2_FB26

#define CAN_F7R2_FB27_Pos

#define CAN_F7R2_FB27_Msk

#define CAN_F7R2_FB27

#define CAN_F7R2_FB28_Pos

#define CAN_F7R2_FB28_Msk

#define CAN_F7R2_FB28

#define CAN_F7R2_FB29_Pos

#define CAN_F7R2_FB29_Msk

#define CAN_F7R2_FB29

#define CAN_F7R2_FB30_Pos

#define CAN_F7R2_FB30_Msk

#define CAN_F7R2_FB30

#define CAN_F7R2_FB31_Pos

#define CAN_F7R2_FB31_Msk

#define CAN_F7R2_FB31

Bit definition for CAN_F8R2 register

#define CAN_F8R2_FB0_Pos

#define CAN_F8R2_FB0_Msk

#define CAN_F8R2_FB0

#define CAN_F8R2_FB1_Pos

#define CAN_F8R2_FB1_Msk

#define CAN_F8R2_FB1

#define CAN_F8R2_FB2_Pos

#define CAN_F8R2_FB2_Msk

#define CAN_F8R2_FB2

#define CAN_F8R2_FB3_Pos

#define CAN_F8R2_FB3_Msk

#define CAN_F8R2_FB3

#define CAN_F8R2_FB4_Pos

#define CAN_F8R2_FB4_Msk

#define CAN_F8R2_FB4

#define CAN_F8R2_FB5_Pos

#define CAN_F8R2_FB5_Msk

#define CAN_F8R2_FB5

#define CAN_F8R2_FB6_Pos

#define CAN_F8R2_FB6_Msk

#define CAN_F8R2_FB6

#define CAN_F8R2_FB7_Pos

#define CAN_F8R2_FB7_Msk

#define CAN_F8R2_FB7

#define CAN_F8R2_FB8_Pos

#define CAN_F8R2_FB8_Msk

#define CAN_F8R2_FB8

#define CAN_F8R2_FB9_Pos

#define CAN_F8R2_FB9_Msk

#define CAN_F8R2_FB9

#define CAN_F8R2_FB10_Pos

#define CAN_F8R2_FB10_Msk

#define CAN_F8R2_FB10

#define CAN_F8R2_FB11_Pos

#define CAN_F8R2_FB11_Msk

#define CAN_F8R2_FB11

#define CAN_F8R2_FB12_Pos

#define CAN_F8R2_FB12_Msk

#define CAN_F8R2_FB12

#define CAN_F8R2_FB13_Pos

#define CAN_F8R2_FB13_Msk

#define CAN_F8R2_FB13

#define CAN_F8R2_FB14_Pos

#define CAN_F8R2_FB14_Msk

#define CAN_F8R2_FB14

#define CAN_F8R2_FB15_Pos

#define CAN_F8R2_FB15_Msk

#define CAN_F8R2_FB15

#define CAN_F8R2_FB16_Pos

#define CAN_F8R2_FB16_Msk

#define CAN_F8R2_FB16

#define CAN_F8R2_FB17_Pos

#define CAN_F8R2_FB17_Msk

#define CAN_F8R2_FB17

#define CAN_F8R2_FB18_Pos

#define CAN_F8R2_FB18_Msk

#define CAN_F8R2_FB18

#define CAN_F8R2_FB19_Pos

#define CAN_F8R2_FB19_Msk

#define CAN_F8R2_FB19

#define CAN_F8R2_FB20_Pos

#define CAN_F8R2_FB20_Msk

#define CAN_F8R2_FB20

#define CAN_F8R2_FB21_Pos

#define CAN_F8R2_FB21_Msk

#define CAN_F8R2_FB21

#define CAN_F8R2_FB22_Pos

#define CAN_F8R2_FB22_Msk

#define CAN_F8R2_FB22

#define CAN_F8R2_FB23_Pos

#define CAN_F8R2_FB23_Msk

#define CAN_F8R2_FB23

#define CAN_F8R2_FB24_Pos

#define CAN_F8R2_FB24_Msk

#define CAN_F8R2_FB24

#define CAN_F8R2_FB25_Pos

#define CAN_F8R2_FB25_Msk

#define CAN_F8R2_FB25

#define CAN_F8R2_FB26_Pos

#define CAN_F8R2_FB26_Msk

#define CAN_F8R2_FB26

#define CAN_F8R2_FB27_Pos

#define CAN_F8R2_FB27_Msk

#define CAN_F8R2_FB27

#define CAN_F8R2_FB28_Pos

#define CAN_F8R2_FB28_Msk

#define CAN_F8R2_FB28

#define CAN_F8R2_FB29_Pos

#define CAN_F8R2_FB29_Msk

#define CAN_F8R2_FB29

#define CAN_F8R2_FB30_Pos

#define CAN_F8R2_FB30_Msk

#define CAN_F8R2_FB30

#define CAN_F8R2_FB31_Pos

#define CAN_F8R2_FB31_Msk

#define CAN_F8R2_FB31

Bit definition for CAN_F9R2 register

#define CAN_F9R2_FB0_Pos

#define CAN_F9R2_FB0_Msk

#define CAN_F9R2_FB0

#define CAN_F9R2_FB1_Pos

#define CAN_F9R2_FB1_Msk

#define CAN_F9R2_FB1

#define CAN_F9R2_FB2_Pos

#define CAN_F9R2_FB2_Msk

#define CAN_F9R2_FB2

#define CAN_F9R2_FB3_Pos

#define CAN_F9R2_FB3_Msk

#define CAN_F9R2_FB3

#define CAN_F9R2_FB4_Pos

#define CAN_F9R2_FB4_Msk

#define CAN_F9R2_FB4

#define CAN_F9R2_FB5_Pos

#define CAN_F9R2_FB5_Msk

#define CAN_F9R2_FB5

#define CAN_F9R2_FB6_Pos

#define CAN_F9R2_FB6_Msk

#define CAN_F9R2_FB6

#define CAN_F9R2_FB7_Pos

#define CAN_F9R2_FB7_Msk

#define CAN_F9R2_FB7

#define CAN_F9R2_FB8_Pos

#define CAN_F9R2_FB8_Msk

#define CAN_F9R2_FB8

#define CAN_F9R2_FB9_Pos

#define CAN_F9R2_FB9_Msk

#define CAN_F9R2_FB9

#define CAN_F9R2_FB10_Pos

#define CAN_F9R2_FB10_Msk

#define CAN_F9R2_FB10

#define CAN_F9R2_FB11_Pos

#define CAN_F9R2_FB11_Msk

#define CAN_F9R2_FB11

#define CAN_F9R2_FB12_Pos

#define CAN_F9R2_FB12_Msk

#define CAN_F9R2_FB12

#define CAN_F9R2_FB13_Pos

#define CAN_F9R2_FB13_Msk

#define CAN_F9R2_FB13

#define CAN_F9R2_FB14_Pos

#define CAN_F9R2_FB14_Msk

#define CAN_F9R2_FB14

#define CAN_F9R2_FB15_Pos

#define CAN_F9R2_FB15_Msk

#define CAN_F9R2_FB15

#define CAN_F9R2_FB16_Pos

#define CAN_F9R2_FB16_Msk

#define CAN_F9R2_FB16

#define CAN_F9R2_FB17_Pos

#define CAN_F9R2_FB17_Msk

#define CAN_F9R2_FB17

#define CAN_F9R2_FB18_Pos

#define CAN_F9R2_FB18_Msk

#define CAN_F9R2_FB18

#define CAN_F9R2_FB19_Pos

#define CAN_F9R2_FB19_Msk

#define CAN_F9R2_FB19

#define CAN_F9R2_FB20_Pos

#define CAN_F9R2_FB20_Msk

#define CAN_F9R2_FB20

#define CAN_F9R2_FB21_Pos

#define CAN_F9R2_FB21_Msk

#define CAN_F9R2_FB21

#define CAN_F9R2_FB22_Pos

#define CAN_F9R2_FB22_Msk

#define CAN_F9R2_FB22

#define CAN_F9R2_FB23_Pos

#define CAN_F9R2_FB23_Msk

#define CAN_F9R2_FB23

#define CAN_F9R2_FB24_Pos

#define CAN_F9R2_FB24_Msk

#define CAN_F9R2_FB24

#define CAN_F9R2_FB25_Pos

#define CAN_F9R2_FB25_Msk

#define CAN_F9R2_FB25

#define CAN_F9R2_FB26_Pos

#define CAN_F9R2_FB26_Msk

#define CAN_F9R2_FB26

#define CAN_F9R2_FB27_Pos

#define CAN_F9R2_FB27_Msk

#define CAN_F9R2_FB27

#define CAN_F9R2_FB28_Pos

#define CAN_F9R2_FB28_Msk

#define CAN_F9R2_FB28

#define CAN_F9R2_FB29_Pos

#define CAN_F9R2_FB29_Msk

#define CAN_F9R2_FB29

#define CAN_F9R2_FB30_Pos

#define CAN_F9R2_FB30_Msk

#define CAN_F9R2_FB30

#define CAN_F9R2_FB31_Pos

#define CAN_F9R2_FB31_Msk

#define CAN_F9R2_FB31

Bit definition for CAN_F10R2 register

#define CAN_F10R2_FB0_Pos

#define CAN_F10R2_FB0_Msk

#define CAN_F10R2_FB0

#define CAN_F10R2_FB1_Pos

#define CAN_F10R2_FB1_Msk

#define CAN_F10R2_FB1

#define CAN_F10R2_FB2_Pos

#define CAN_F10R2_FB2_Msk

#define CAN_F10R2_FB2

#define CAN_F10R2_FB3_Pos

#define CAN_F10R2_FB3_Msk

#define CAN_F10R2_FB3

#define CAN_F10R2_FB4_Pos

#define CAN_F10R2_FB4_Msk

#define CAN_F10R2_FB4

#define CAN_F10R2_FB5_Pos

#define CAN_F10R2_FB5_Msk

#define CAN_F10R2_FB5

#define CAN_F10R2_FB6_Pos

#define CAN_F10R2_FB6_Msk

#define CAN_F10R2_FB6

#define CAN_F10R2_FB7_Pos

#define CAN_F10R2_FB7_Msk

#define CAN_F10R2_FB7

#define CAN_F10R2_FB8_Pos

#define CAN_F10R2_FB8_Msk

#define CAN_F10R2_FB8

#define CAN_F10R2_FB9_Pos

#define CAN_F10R2_FB9_Msk

#define CAN_F10R2_FB9

#define CAN_F10R2_FB10_Pos

#define CAN_F10R2_FB10_Msk

#define CAN_F10R2_FB10

#define CAN_F10R2_FB11_Pos

#define CAN_F10R2_FB11_Msk

#define CAN_F10R2_FB11

#define CAN_F10R2_FB12_Pos

#define CAN_F10R2_FB12_Msk

#define CAN_F10R2_FB12

#define CAN_F10R2_FB13_Pos

#define CAN_F10R2_FB13_Msk

#define CAN_F10R2_FB13

#define CAN_F10R2_FB14_Pos

#define CAN_F10R2_FB14_Msk

#define CAN_F10R2_FB14

#define CAN_F10R2_FB15_Pos

#define CAN_F10R2_FB15_Msk

#define CAN_F10R2_FB15

#define CAN_F10R2_FB16_Pos

#define CAN_F10R2_FB16_Msk

#define CAN_F10R2_FB16

#define CAN_F10R2_FB17_Pos

#define CAN_F10R2_FB17_Msk

#define CAN_F10R2_FB17

#define CAN_F10R2_FB18_Pos

#define CAN_F10R2_FB18_Msk

#define CAN_F10R2_FB18

#define CAN_F10R2_FB19_Pos

#define CAN_F10R2_FB19_Msk

#define CAN_F10R2_FB19

#define CAN_F10R2_FB20_Pos

#define CAN_F10R2_FB20_Msk

#define CAN_F10R2_FB20

#define CAN_F10R2_FB21_Pos

#define CAN_F10R2_FB21_Msk

#define CAN_F10R2_FB21

#define CAN_F10R2_FB22_Pos

#define CAN_F10R2_FB22_Msk

#define CAN_F10R2_FB22

#define CAN_F10R2_FB23_Pos

#define CAN_F10R2_FB23_Msk

#define CAN_F10R2_FB23

#define CAN_F10R2_FB24_Pos

#define CAN_F10R2_FB24_Msk

#define CAN_F10R2_FB24

#define CAN_F10R2_FB25_Pos

#define CAN_F10R2_FB25_Msk

#define CAN_F10R2_FB25

#define CAN_F10R2_FB26_Pos

#define CAN_F10R2_FB26_Msk

#define CAN_F10R2_FB26

#define CAN_F10R2_FB27_Pos

#define CAN_F10R2_FB27_Msk

#define CAN_F10R2_FB27

#define CAN_F10R2_FB28_Pos

#define CAN_F10R2_FB28_Msk

#define CAN_F10R2_FB28

#define CAN_F10R2_FB29_Pos

#define CAN_F10R2_FB29_Msk

#define CAN_F10R2_FB29

#define CAN_F10R2_FB30_Pos

#define CAN_F10R2_FB30_Msk

#define CAN_F10R2_FB30

#define CAN_F10R2_FB31_Pos

#define CAN_F10R2_FB31_Msk

#define CAN_F10R2_FB31

Bit definition for CAN_F11R2 register

#define CAN_F11R2_FB0_Pos

#define CAN_F11R2_FB0_Msk

#define CAN_F11R2_FB0

#define CAN_F11R2_FB1_Pos

#define CAN_F11R2_FB1_Msk

#define CAN_F11R2_FB1

#define CAN_F11R2_FB2_Pos

#define CAN_F11R2_FB2_Msk

#define CAN_F11R2_FB2

#define CAN_F11R2_FB3_Pos

#define CAN_F11R2_FB3_Msk

#define CAN_F11R2_FB3

#define CAN_F11R2_FB4_Pos

#define CAN_F11R2_FB4_Msk

#define CAN_F11R2_FB4

#define CAN_F11R2_FB5_Pos

#define CAN_F11R2_FB5_Msk

#define CAN_F11R2_FB5

#define CAN_F11R2_FB6_Pos

#define CAN_F11R2_FB6_Msk

#define CAN_F11R2_FB6

#define CAN_F11R2_FB7_Pos

#define CAN_F11R2_FB7_Msk

#define CAN_F11R2_FB7

#define CAN_F11R2_FB8_Pos

#define CAN_F11R2_FB8_Msk

#define CAN_F11R2_FB8

#define CAN_F11R2_FB9_Pos

#define CAN_F11R2_FB9_Msk

#define CAN_F11R2_FB9

#define CAN_F11R2_FB10_Pos

#define CAN_F11R2_FB10_Msk

#define CAN_F11R2_FB10

#define CAN_F11R2_FB11_Pos

#define CAN_F11R2_FB11_Msk

#define CAN_F11R2_FB11

#define CAN_F11R2_FB12_Pos

#define CAN_F11R2_FB12_Msk

#define CAN_F11R2_FB12

#define CAN_F11R2_FB13_Pos

#define CAN_F11R2_FB13_Msk

#define CAN_F11R2_FB13

#define CAN_F11R2_FB14_Pos

#define CAN_F11R2_FB14_Msk

#define CAN_F11R2_FB14

#define CAN_F11R2_FB15_Pos

#define CAN_F11R2_FB15_Msk

#define CAN_F11R2_FB15

#define CAN_F11R2_FB16_Pos

#define CAN_F11R2_FB16_Msk

#define CAN_F11R2_FB16

#define CAN_F11R2_FB17_Pos

#define CAN_F11R2_FB17_Msk

#define CAN_F11R2_FB17

#define CAN_F11R2_FB18_Pos

#define CAN_F11R2_FB18_Msk

#define CAN_F11R2_FB18

#define CAN_F11R2_FB19_Pos

#define CAN_F11R2_FB19_Msk

#define CAN_F11R2_FB19

#define CAN_F11R2_FB20_Pos

#define CAN_F11R2_FB20_Msk

#define CAN_F11R2_FB20

#define CAN_F11R2_FB21_Pos

#define CAN_F11R2_FB21_Msk

#define CAN_F11R2_FB21

#define CAN_F11R2_FB22_Pos

#define CAN_F11R2_FB22_Msk

#define CAN_F11R2_FB22

#define CAN_F11R2_FB23_Pos

#define CAN_F11R2_FB23_Msk

#define CAN_F11R2_FB23

#define CAN_F11R2_FB24_Pos

#define CAN_F11R2_FB24_Msk

#define CAN_F11R2_FB24

#define CAN_F11R2_FB25_Pos

#define CAN_F11R2_FB25_Msk

#define CAN_F11R2_FB25

#define CAN_F11R2_FB26_Pos

#define CAN_F11R2_FB26_Msk

#define CAN_F11R2_FB26

#define CAN_F11R2_FB27_Pos

#define CAN_F11R2_FB27_Msk

#define CAN_F11R2_FB27

#define CAN_F11R2_FB28_Pos

#define CAN_F11R2_FB28_Msk

#define CAN_F11R2_FB28

#define CAN_F11R2_FB29_Pos

#define CAN_F11R2_FB29_Msk

#define CAN_F11R2_FB29

#define CAN_F11R2_FB30_Pos

#define CAN_F11R2_FB30_Msk

#define CAN_F11R2_FB30

#define CAN_F11R2_FB31_Pos

#define CAN_F11R2_FB31_Msk

#define CAN_F11R2_FB31

Bit definition for CAN_F12R2 register

#define CAN_F12R2_FB0_Pos

#define CAN_F12R2_FB0_Msk

#define CAN_F12R2_FB0

#define CAN_F12R2_FB1_Pos

#define CAN_F12R2_FB1_Msk

#define CAN_F12R2_FB1

#define CAN_F12R2_FB2_Pos

#define CAN_F12R2_FB2_Msk

#define CAN_F12R2_FB2

#define CAN_F12R2_FB3_Pos

#define CAN_F12R2_FB3_Msk

#define CAN_F12R2_FB3

#define CAN_F12R2_FB4_Pos

#define CAN_F12R2_FB4_Msk

#define CAN_F12R2_FB4

#define CAN_F12R2_FB5_Pos

#define CAN_F12R2_FB5_Msk

#define CAN_F12R2_FB5

#define CAN_F12R2_FB6_Pos

#define CAN_F12R2_FB6_Msk

#define CAN_F12R2_FB6

#define CAN_F12R2_FB7_Pos

#define CAN_F12R2_FB7_Msk

#define CAN_F12R2_FB7

#define CAN_F12R2_FB8_Pos

#define CAN_F12R2_FB8_Msk

#define CAN_F12R2_FB8

#define CAN_F12R2_FB9_Pos

#define CAN_F12R2_FB9_Msk

#define CAN_F12R2_FB9

#define CAN_F12R2_FB10_Pos

#define CAN_F12R2_FB10_Msk

#define CAN_F12R2_FB10

#define CAN_F12R2_FB11_Pos

#define CAN_F12R2_FB11_Msk

#define CAN_F12R2_FB11

#define CAN_F12R2_FB12_Pos

#define CAN_F12R2_FB12_Msk

#define CAN_F12R2_FB12

#define CAN_F12R2_FB13_Pos

#define CAN_F12R2_FB13_Msk

#define CAN_F12R2_FB13

#define CAN_F12R2_FB14_Pos

#define CAN_F12R2_FB14_Msk

#define CAN_F12R2_FB14

#define CAN_F12R2_FB15_Pos

#define CAN_F12R2_FB15_Msk

#define CAN_F12R2_FB15

#define CAN_F12R2_FB16_Pos

#define CAN_F12R2_FB16_Msk

#define CAN_F12R2_FB16

#define CAN_F12R2_FB17_Pos

#define CAN_F12R2_FB17_Msk

#define CAN_F12R2_FB17

#define CAN_F12R2_FB18_Pos

#define CAN_F12R2_FB18_Msk

#define CAN_F12R2_FB18

#define CAN_F12R2_FB19_Pos

#define CAN_F12R2_FB19_Msk

#define CAN_F12R2_FB19

#define CAN_F12R2_FB20_Pos

#define CAN_F12R2_FB20_Msk

#define CAN_F12R2_FB20

#define CAN_F12R2_FB21_Pos

#define CAN_F12R2_FB21_Msk

#define CAN_F12R2_FB21

#define CAN_F12R2_FB22_Pos

#define CAN_F12R2_FB22_Msk

#define CAN_F12R2_FB22

#define CAN_F12R2_FB23_Pos

#define CAN_F12R2_FB23_Msk

#define CAN_F12R2_FB23

#define CAN_F12R2_FB24_Pos

#define CAN_F12R2_FB24_Msk

#define CAN_F12R2_FB24

#define CAN_F12R2_FB25_Pos

#define CAN_F12R2_FB25_Msk

#define CAN_F12R2_FB25

#define CAN_F12R2_FB26_Pos

#define CAN_F12R2_FB26_Msk

#define CAN_F12R2_FB26

#define CAN_F12R2_FB27_Pos

#define CAN_F12R2_FB27_Msk

#define CAN_F12R2_FB27

#define CAN_F12R2_FB28_Pos

#define CAN_F12R2_FB28_Msk

#define CAN_F12R2_FB28

#define CAN_F12R2_FB29_Pos

#define CAN_F12R2_FB29_Msk

#define CAN_F12R2_FB29

#define CAN_F12R2_FB30_Pos

#define CAN_F12R2_FB30_Msk

#define CAN_F12R2_FB30

#define CAN_F12R2_FB31_Pos

#define CAN_F12R2_FB31_Msk

#define CAN_F12R2_FB31

Bit definition for CAN_F13R2 register

#define CAN_F13R2_FB0_Pos

#define CAN_F13R2_FB0_Msk

#define CAN_F13R2_FB0

#define CAN_F13R2_FB1_Pos

#define CAN_F13R2_FB1_Msk

#define CAN_F13R2_FB1

#define CAN_F13R2_FB2_Pos

#define CAN_F13R2_FB2_Msk

#define CAN_F13R2_FB2

#define CAN_F13R2_FB3_Pos

#define CAN_F13R2_FB3_Msk

#define CAN_F13R2_FB3

#define CAN_F13R2_FB4_Pos

#define CAN_F13R2_FB4_Msk

#define CAN_F13R2_FB4

#define CAN_F13R2_FB5_Pos

#define CAN_F13R2_FB5_Msk

#define CAN_F13R2_FB5

#define CAN_F13R2_FB6_Pos

#define CAN_F13R2_FB6_Msk

#define CAN_F13R2_FB6

#define CAN_F13R2_FB7_Pos

#define CAN_F13R2_FB7_Msk

#define CAN_F13R2_FB7

#define CAN_F13R2_FB8_Pos

#define CAN_F13R2_FB8_Msk

#define CAN_F13R2_FB8

#define CAN_F13R2_FB9_Pos

#define CAN_F13R2_FB9_Msk

#define CAN_F13R2_FB9

#define CAN_F13R2_FB10_Pos

#define CAN_F13R2_FB10_Msk

#define CAN_F13R2_FB10

#define CAN_F13R2_FB11_Pos

#define CAN_F13R2_FB11_Msk

#define CAN_F13R2_FB11

#define CAN_F13R2_FB12_Pos

#define CAN_F13R2_FB12_Msk

#define CAN_F13R2_FB12

#define CAN_F13R2_FB13_Pos

#define CAN_F13R2_FB13_Msk

#define CAN_F13R2_FB13

#define CAN_F13R2_FB14_Pos

#define CAN_F13R2_FB14_Msk

#define CAN_F13R2_FB14

#define CAN_F13R2_FB15_Pos

#define CAN_F13R2_FB15_Msk

#define CAN_F13R2_FB15

#define CAN_F13R2_FB16_Pos

#define CAN_F13R2_FB16_Msk

#define CAN_F13R2_FB16

#define CAN_F13R2_FB17_Pos

#define CAN_F13R2_FB17_Msk

#define CAN_F13R2_FB17

#define CAN_F13R2_FB18_Pos

#define CAN_F13R2_FB18_Msk

#define CAN_F13R2_FB18

#define CAN_F13R2_FB19_Pos

#define CAN_F13R2_FB19_Msk

#define CAN_F13R2_FB19

#define CAN_F13R2_FB20_Pos

#define CAN_F13R2_FB20_Msk

#define CAN_F13R2_FB20

#define CAN_F13R2_FB21_Pos

#define CAN_F13R2_FB21_Msk

#define CAN_F13R2_FB21

#define CAN_F13R2_FB22_Pos

#define CAN_F13R2_FB22_Msk

#define CAN_F13R2_FB22

#define CAN_F13R2_FB23_Pos

#define CAN_F13R2_FB23_Msk

#define CAN_F13R2_FB23

#define CAN_F13R2_FB24_Pos

#define CAN_F13R2_FB24_Msk

#define CAN_F13R2_FB24

#define CAN_F13R2_FB25_Pos

#define CAN_F13R2_FB25_Msk

#define CAN_F13R2_FB25

#define CAN_F13R2_FB26_Pos

#define CAN_F13R2_FB26_Msk

#define CAN_F13R2_FB26

#define CAN_F13R2_FB27_Pos

#define CAN_F13R2_FB27_Msk

#define CAN_F13R2_FB27

#define CAN_F13R2_FB28_Pos

#define CAN_F13R2_FB28_Msk

#define CAN_F13R2_FB28

#define CAN_F13R2_FB29_Pos

#define CAN_F13R2_FB29_Msk

#define CAN_F13R2_FB29

#define CAN_F13R2_FB30_Pos

#define CAN_F13R2_FB30_Msk

#define CAN_F13R2_FB30

#define CAN_F13R2_FB31_Pos

#define CAN_F13R2_FB31_Msk

#define CAN_F13R2_FB31

...

Bit definition for CRC_DR register

#define CRC_DR_DR_Pos

#define CRC_DR_DR_Msk

#define CRC_DR_DR

Bit definition for CRC_IDR register

#define CRC_IDR_IDR_Pos

#define CRC_IDR_IDR_Msk

#define CRC_IDR_IDR

Bit definition for CRC_CR register

#define CRC_CR_RESET_Pos

#define CRC_CR_RESET_Msk

#define CRC_CR_RESET

...

#define DAC_CHANNEL2_SUPPORT

Bit definition for DAC_CR register

#define DAC_CR_EN1_Pos

#define DAC_CR_EN1_Msk

#define DAC_CR_EN1

#define DAC_CR_BOFF1_Pos

#define DAC_CR_BOFF1_Msk

#define DAC_CR_BOFF1

#define DAC_CR_TEN1_Pos

#define DAC_CR_TEN1_Msk

#define DAC_CR_TEN1

#define DAC_CR_TSEL1_Pos

#define DAC_CR_TSEL1_Msk

#define DAC_CR_TSEL1

#define DAC_CR_TSEL1_0

#define DAC_CR_TSEL1_1

#define DAC_CR_TSEL1_2

#define DAC_CR_WAVE1_Pos

#define DAC_CR_WAVE1_Msk

#define DAC_CR_WAVE1

#define DAC_CR_WAVE1_0

#define DAC_CR_WAVE1_1

#define DAC_CR_MAMP1_Pos

#define DAC_CR_MAMP1_Msk

#define DAC_CR_MAMP1

#define DAC_CR_MAMP1_0

#define DAC_CR_MAMP1_1

#define DAC_CR_MAMP1_2

#define DAC_CR_MAMP1_3

#define DAC_CR_DMAEN1_Pos

#define DAC_CR_DMAEN1_Msk

#define DAC_CR_DMAEN1

#define DAC_CR_DMAUDRIE1_Pos

#define DAC_CR_DMAUDRIE1_Msk

#define DAC_CR_DMAUDRIE1

#define DAC_CR_EN2_Pos

#define DAC_CR_EN2_Msk

#define DAC_CR_EN2

#define DAC_CR_BOFF2_Pos

#define DAC_CR_BOFF2_Msk

#define DAC_CR_BOFF2

#define DAC_CR_TEN2_Pos

#define DAC_CR_TEN2_Msk

#define DAC_CR_TEN2

#define DAC_CR_TSEL2_Pos

#define DAC_CR_TSEL2_Msk

#define DAC_CR_TSEL2

#define DAC_CR_TSEL2_0

#define DAC_CR_TSEL2_1

#define DAC_CR_TSEL2_2

#define DAC_CR_WAVE2_Pos

#define DAC_CR_WAVE2_Msk

#define DAC_CR_WAVE2

#define DAC_CR_WAVE2_0

#define DAC_CR_WAVE2_1

#define DAC_CR_MAMP2_Pos

#define DAC_CR_MAMP2_Msk

#define DAC_CR_MAMP2

#define DAC_CR_MAMP2_0

#define DAC_CR_MAMP2_1

#define DAC_CR_MAMP2_2

#define DAC_CR_MAMP2_3

#define DAC_CR_DMAEN2_Pos

#define DAC_CR_DMAEN2_Msk

#define DAC_CR_DMAEN2

#define DAC_CR_DMAUDRIE2_Pos

#define DAC_CR_DMAUDRIE2_Msk

#define DAC_CR_DMAUDRIE2

Bit definition for DAC_SWTRIGR register

#define DAC_SWTRIGR_SWTRIG1_Pos

#define DAC_SWTRIGR_SWTRIG1_Msk

#define DAC_SWTRIGR_SWTRIG1

#define DAC_SWTRIGR_SWTRIG2_Pos

#define DAC_SWTRIGR_SWTRIG2_Msk

#define DAC_SWTRIGR_SWTRIG2

Bit definition for DAC_DHR12R1 register

#define DAC_DHR12R1_DACC1DHR_Pos

#define DAC_DHR12R1_DACC1DHR_Msk

#define DAC_DHR12R1_DACC1DHR

Bit definition for DAC_DHR12L1 register

#define DAC_DHR12L1_DACC1DHR_Pos

#define DAC_DHR12L1_DACC1DHR_Msk

#define DAC_DHR12L1_DACC1DHR

Bit definition for DAC_DHR8R1 register

#define DAC_DHR8R1_DACC1DHR_Pos

#define DAC_DHR8R1_DACC1DHR_Msk

#define DAC_DHR8R1_DACC1DHR

Bit definition for DAC_DHR12R2 register

#define DAC_DHR12R2_DACC2DHR_Pos

#define DAC_DHR12R2_DACC2DHR_Msk

#define DAC_DHR12R2_DACC2DHR

Bit definition for DAC_DHR12L2 register

#define DAC_DHR12L2_DACC2DHR_Pos

#define DAC_DHR12L2_DACC2DHR_Msk

#define DAC_DHR12L2_DACC2DHR

Bit definition for DAC_DHR8R2 register

#define DAC_DHR8R2_DACC2DHR_Pos

#define DAC_DHR8R2_DACC2DHR_Msk

#define DAC_DHR8R2_DACC2DHR

Bit definition for DAC_DHR12RD register

#define DAC_DHR12RD_DACC1DHR_Pos

#define DAC_DHR12RD_DACC1DHR_Msk

#define DAC_DHR12RD_DACC1DHR

#define DAC_DHR12RD_DACC2DHR_Pos

#define DAC_DHR12RD_DACC2DHR_Msk

#define DAC_DHR12RD_DACC2DHR

Bit definition for DAC_DHR12LD register

#define DAC_DHR12LD_DACC1DHR_Pos

#define DAC_DHR12LD_DACC1DHR_Msk

#define DAC_DHR12LD_DACC1DHR

#define DAC_DHR12LD_DACC2DHR_Pos

#define DAC_DHR12LD_DACC2DHR_Msk

#define DAC_DHR12LD_DACC2DHR

Bit definition for DAC_DHR8RD register

#define DAC_DHR8RD_DACC1DHR_Pos

#define DAC_DHR8RD_DACC1DHR_Msk

#define DAC_DHR8RD_DACC1DHR

#define DAC_DHR8RD_DACC2DHR_Pos

#define DAC_DHR8RD_DACC2DHR_Msk

#define DAC_DHR8RD_DACC2DHR

Bit definition for DAC_DOR1 register

#define DAC_DOR1_DACC1DOR_Pos

#define DAC_DOR1_DACC1DOR_Msk

#define DAC_DOR1_DACC1DOR

Bit definition for DAC_DOR2 register

#define DAC_DOR2_DACC2DOR_Pos

#define DAC_DOR2_DACC2DOR_Msk

#define DAC_DOR2_DACC2DOR

Bit definition for DAC_SR register

#define DAC_SR_DMAUDR1_Pos

#define DAC_SR_DMAUDR1_Msk

#define DAC_SR_DMAUDR1

#define DAC_SR_DMAUDR2_Pos

#define DAC_SR_DMAUDR2_Msk

#define DAC_SR_DMAUDR2

...

Bits definition for DCMI_CR register

#define DCMI_CR_CAPTURE_Pos

#define DCMI_CR_CAPTURE_Msk

#define DCMI_CR_CAPTURE

#define DCMI_CR_CM_Pos

#define DCMI_CR_CM_Msk

#define DCMI_CR_CM

#define DCMI_CR_CROP_Pos

#define DCMI_CR_CROP_Msk

#define DCMI_CR_CROP

#define DCMI_CR_JPEG_Pos

#define DCMI_CR_JPEG_Msk

#define DCMI_CR_JPEG

#define DCMI_CR_ESS_Pos

#define DCMI_CR_ESS_Msk

#define DCMI_CR_ESS

#define DCMI_CR_PCKPOL_Pos

#define DCMI_CR_PCKPOL_Msk

#define DCMI_CR_PCKPOL

#define DCMI_CR_HSPOL_Pos

#define DCMI_CR_HSPOL_Msk

#define DCMI_CR_HSPOL

#define DCMI_CR_VSPOL_Pos

#define DCMI_CR_VSPOL_Msk

#define DCMI_CR_VSPOL

#define DCMI_CR_FCRC_0

#define DCMI_CR_FCRC_1

#define DCMI_CR_EDM_0

#define DCMI_CR_EDM_1

#define DCMI_CR_CRE_Pos

#define DCMI_CR_CRE_Msk

#define DCMI_CR_CRE

#define DCMI_CR_ENABLE_Pos

#define DCMI_CR_ENABLE_Msk

#define DCMI_CR_ENABLE

Bits definition for DCMI_SR register

#define DCMI_SR_HSYNC_Pos

#define DCMI_SR_HSYNC_Msk

#define DCMI_SR_HSYNC

#define DCMI_SR_VSYNC_Pos

#define DCMI_SR_VSYNC_Msk

#define DCMI_SR_VSYNC

#define DCMI_SR_FNE_Pos

#define DCMI_SR_FNE_Msk

#define DCMI_SR_FNE

Bits definition for DCMI_RIS register

#define DCMI_RIS_FRAME_RIS_Pos

#define DCMI_RIS_FRAME_RIS_Msk

#define DCMI_RIS_FRAME_RIS

#define DCMI_RIS_OVR_RIS_Pos

#define DCMI_RIS_OVR_RIS_Msk

#define DCMI_RIS_OVR_RIS

#define DCMI_RIS_ERR_RIS_Pos

#define DCMI_RIS_ERR_RIS_Msk

#define DCMI_RIS_ERR_RIS

#define DCMI_RIS_VSYNC_RIS_Pos

#define DCMI_RIS_VSYNC_RIS_Msk

#define DCMI_RIS_VSYNC_RIS

#define DCMI_RIS_LINE_RIS_Pos

#define DCMI_RIS_LINE_RIS_Msk

#define DCMI_RIS_LINE_RIS

#define DCMI_RISR_FRAME_RIS

#define DCMI_RISR_OVR_RIS

#define DCMI_RISR_ERR_RIS

#define DCMI_RISR_VSYNC_RIS

#define DCMI_RISR_LINE_RIS

#define DCMI_RISR_OVF_RIS

Bits definition for DCMI_IER register

#define DCMI_IER_FRAME_IE_Pos

#define DCMI_IER_FRAME_IE_Msk

#define DCMI_IER_FRAME_IE

#define DCMI_IER_OVR_IE_Pos

#define DCMI_IER_OVR_IE_Msk

#define DCMI_IER_OVR_IE

#define DCMI_IER_ERR_IE_Pos

#define DCMI_IER_ERR_IE_Msk

#define DCMI_IER_ERR_IE

#define DCMI_IER_VSYNC_IE_Pos

#define DCMI_IER_VSYNC_IE_Msk

#define DCMI_IER_VSYNC_IE

#define DCMI_IER_LINE_IE_Pos

#define DCMI_IER_LINE_IE_Msk

#define DCMI_IER_LINE_IE

#define DCMI_IER_OVF_IE

Bits definition for DCMI_MIS register

#define DCMI_MIS_FRAME_MIS_Pos

#define DCMI_MIS_FRAME_MIS_Msk

#define DCMI_MIS_FRAME_MIS

#define DCMI_MIS_OVR_MIS_Pos

#define DCMI_MIS_OVR_MIS_Msk

#define DCMI_MIS_OVR_MIS

#define DCMI_MIS_ERR_MIS_Pos

#define DCMI_MIS_ERR_MIS_Msk

#define DCMI_MIS_ERR_MIS

#define DCMI_MIS_VSYNC_MIS_Pos

#define DCMI_MIS_VSYNC_MIS_Msk

#define DCMI_MIS_VSYNC_MIS

#define DCMI_MIS_LINE_MIS_Pos

#define DCMI_MIS_LINE_MIS_Msk

#define DCMI_MIS_LINE_MIS

#define DCMI_MISR_FRAME_MIS

#define DCMI_MISR_OVF_MIS

#define DCMI_MISR_ERR_MIS

#define DCMI_MISR_VSYNC_MIS

#define DCMI_MISR_LINE_MIS

Bits definition for DCMI_ICR register

#define DCMI_ICR_FRAME_ISC_Pos

#define DCMI_ICR_FRAME_ISC_Msk

#define DCMI_ICR_FRAME_ISC

#define DCMI_ICR_OVR_ISC_Pos

#define DCMI_ICR_OVR_ISC_Msk

#define DCMI_ICR_OVR_ISC

#define DCMI_ICR_ERR_ISC_Pos

#define DCMI_ICR_ERR_ISC_Msk

#define DCMI_ICR_ERR_ISC

#define DCMI_ICR_VSYNC_ISC_Pos

#define DCMI_ICR_VSYNC_ISC_Msk

#define DCMI_ICR_VSYNC_ISC

#define DCMI_ICR_LINE_ISC_Pos

#define DCMI_ICR_LINE_ISC_Msk

#define DCMI_ICR_LINE_ISC

#define DCMI_ICR_OVF_ISC

Bits definition for DCMI_ESCR register

#define DCMI_ESCR_FSC_Pos

#define DCMI_ESCR_FSC_Msk

#define DCMI_ESCR_FSC

#define DCMI_ESCR_LSC_Pos

#define DCMI_ESCR_LSC_Msk

#define DCMI_ESCR_LSC

#define DCMI_ESCR_LEC_Pos

#define DCMI_ESCR_LEC_Msk

#define DCMI_ESCR_LEC

#define DCMI_ESCR_FEC_Pos

#define DCMI_ESCR_FEC_Msk

#define DCMI_ESCR_FEC

Bits definition for DCMI_ESUR register

#define DCMI_ESUR_FSU_Pos

#define DCMI_ESUR_FSU_Msk

#define DCMI_ESUR_FSU

#define DCMI_ESUR_LSU_Pos

#define DCMI_ESUR_LSU_Msk

#define DCMI_ESUR_LSU

#define DCMI_ESUR_LEU_Pos

#define DCMI_ESUR_LEU_Msk

#define DCMI_ESUR_LEU

#define DCMI_ESUR_FEU_Pos

#define DCMI_ESUR_FEU_Msk

#define DCMI_ESUR_FEU

Bits definition for DCMI_CWSTRT register

#define DCMI_CWSTRT_HOFFCNT_Pos

#define DCMI_CWSTRT_HOFFCNT_Msk

#define DCMI_CWSTRT_HOFFCNT

#define DCMI_CWSTRT_VST_Pos

#define DCMI_CWSTRT_VST_Msk

#define DCMI_CWSTRT_VST

Bits definition for DCMI_CWSIZE register

#define DCMI_CWSIZE_CAPCNT_Pos

#define DCMI_CWSIZE_CAPCNT_Msk

#define DCMI_CWSIZE_CAPCNT

#define DCMI_CWSIZE_VLINE_Pos

#define DCMI_CWSIZE_VLINE_Msk

#define DCMI_CWSIZE_VLINE

Bits definition for DCMI_DR register

#define DCMI_DR_BYTE0_Pos

#define DCMI_DR_BYTE0_Msk

#define DCMI_DR_BYTE0

#define DCMI_DR_BYTE1_Pos

#define DCMI_DR_BYTE1_Msk

#define DCMI_DR_BYTE1

#define DCMI_DR_BYTE2_Pos

#define DCMI_DR_BYTE2_Msk

#define DCMI_DR_BYTE2

#define DCMI_DR_BYTE3_Pos

#define DCMI_DR_BYTE3_Msk

#define DCMI_DR_BYTE3

...

Bits definition for DMA_SxCR register

#define DMA_SxCR_CHSEL_Pos

#define DMA_SxCR_CHSEL_Msk

#define DMA_SxCR_CHSEL

#define DMA_SxCR_CHSEL_0

#define DMA_SxCR_CHSEL_1

#define DMA_SxCR_CHSEL_2

#define DMA_SxCR_MBURST_Pos

#define DMA_SxCR_MBURST_Msk

#define DMA_SxCR_MBURST

#define DMA_SxCR_MBURST_0

#define DMA_SxCR_MBURST_1

#define DMA_SxCR_PBURST_Pos

#define DMA_SxCR_PBURST_Msk

#define DMA_SxCR_PBURST

#define DMA_SxCR_PBURST_0

#define DMA_SxCR_PBURST_1

#define DMA_SxCR_CT_Pos

#define DMA_SxCR_CT_Msk

#define DMA_SxCR_CT

#define DMA_SxCR_DBM_Pos

#define DMA_SxCR_DBM_Msk

#define DMA_SxCR_DBM

#define DMA_SxCR_PL_Pos

#define DMA_SxCR_PL_Msk

#define DMA_SxCR_PL

#define DMA_SxCR_PL_0

#define DMA_SxCR_PL_1

#define DMA_SxCR_PINCOS_Pos

#define DMA_SxCR_PINCOS_Msk

#define DMA_SxCR_PINCOS

#define DMA_SxCR_MSIZE_Pos

#define DMA_SxCR_MSIZE_Msk

#define DMA_SxCR_MSIZE

#define DMA_SxCR_MSIZE_0

#define DMA_SxCR_MSIZE_1

#define DMA_SxCR_PSIZE_Pos

#define DMA_SxCR_PSIZE_Msk

#define DMA_SxCR_PSIZE

#define DMA_SxCR_PSIZE_0

#define DMA_SxCR_PSIZE_1

#define DMA_SxCR_MINC_Pos

#define DMA_SxCR_MINC_Msk

#define DMA_SxCR_MINC

#define DMA_SxCR_PINC_Pos

#define DMA_SxCR_PINC_Msk

#define DMA_SxCR_PINC

#define DMA_SxCR_CIRC_Pos

#define DMA_SxCR_CIRC_Msk

#define DMA_SxCR_CIRC

#define DMA_SxCR_DIR_Pos

#define DMA_SxCR_DIR_Msk

#define DMA_SxCR_DIR

#define DMA_SxCR_DIR_0

#define DMA_SxCR_DIR_1

#define DMA_SxCR_PFCTRL_Pos

#define DMA_SxCR_PFCTRL_Msk

#define DMA_SxCR_PFCTRL

#define DMA_SxCR_TCIE_Pos

#define DMA_SxCR_TCIE_Msk

#define DMA_SxCR_TCIE

#define DMA_SxCR_HTIE_Pos

#define DMA_SxCR_HTIE_Msk

#define DMA_SxCR_HTIE

#define DMA_SxCR_TEIE_Pos

#define DMA_SxCR_TEIE_Msk

#define DMA_SxCR_TEIE

#define DMA_SxCR_DMEIE_Pos

#define DMA_SxCR_DMEIE_Msk

#define DMA_SxCR_DMEIE

#define DMA_SxCR_EN_Pos

#define DMA_SxCR_EN_Msk

#define DMA_SxCR_EN

#define DMA_SxCR_ACK_Pos

#define DMA_SxCR_ACK_Msk

#define DMA_SxCR_ACK

Bits definition for DMA_SxCNDTR register

#define DMA_SxNDT_Pos

#define DMA_SxNDT_Msk

#define DMA_SxNDT

#define DMA_SxNDT_0

#define DMA_SxNDT_1

#define DMA_SxNDT_2

#define DMA_SxNDT_3

#define DMA_SxNDT_4

#define DMA_SxNDT_5

#define DMA_SxNDT_6

#define DMA_SxNDT_7

#define DMA_SxNDT_8

#define DMA_SxNDT_9

#define DMA_SxNDT_10

#define DMA_SxNDT_11

#define DMA_SxNDT_12

#define DMA_SxNDT_13

#define DMA_SxNDT_14

#define DMA_SxNDT_15

Bits definition for DMA_SxFCR register

#define DMA_SxFCR_FEIE_Pos

#define DMA_SxFCR_FEIE_Msk

#define DMA_SxFCR_FEIE

#define DMA_SxFCR_FS_Pos

#define DMA_SxFCR_FS_Msk

#define DMA_SxFCR_FS

#define DMA_SxFCR_FS_0

#define DMA_SxFCR_FS_1

#define DMA_SxFCR_FS_2

#define DMA_SxFCR_DMDIS_Pos

#define DMA_SxFCR_DMDIS_Msk

#define DMA_SxFCR_DMDIS

#define DMA_SxFCR_FTH_Pos

#define DMA_SxFCR_FTH_Msk

#define DMA_SxFCR_FTH

#define DMA_SxFCR_FTH_0

#define DMA_SxFCR_FTH_1

Bits definition for DMA_LISR register

#define DMA_LISR_TCIF3_Pos

#define DMA_LISR_TCIF3_Msk

#define DMA_LISR_TCIF3

#define DMA_LISR_HTIF3_Pos

#define DMA_LISR_HTIF3_Msk

#define DMA_LISR_HTIF3

#define DMA_LISR_TEIF3_Pos

#define DMA_LISR_TEIF3_Msk

#define DMA_LISR_TEIF3

#define DMA_LISR_DMEIF3_Pos

#define DMA_LISR_DMEIF3_Msk

#define DMA_LISR_DMEIF3

#define DMA_LISR_FEIF3_Pos

#define DMA_LISR_FEIF3_Msk

#define DMA_LISR_FEIF3

#define DMA_LISR_TCIF2_Pos

#define DMA_LISR_TCIF2_Msk

#define DMA_LISR_TCIF2

#define DMA_LISR_HTIF2_Pos

#define DMA_LISR_HTIF2_Msk

#define DMA_LISR_HTIF2

#define DMA_LISR_TEIF2_Pos

#define DMA_LISR_TEIF2_Msk

#define DMA_LISR_TEIF2

#define DMA_LISR_DMEIF2_Pos

#define DMA_LISR_DMEIF2_Msk

#define DMA_LISR_DMEIF2

#define DMA_LISR_FEIF2_Pos

#define DMA_LISR_FEIF2_Msk

#define DMA_LISR_FEIF2

#define DMA_LISR_TCIF1_Pos

#define DMA_LISR_TCIF1_Msk

#define DMA_LISR_TCIF1

#define DMA_LISR_HTIF1_Pos

#define DMA_LISR_HTIF1_Msk

#define DMA_LISR_HTIF1

#define DMA_LISR_TEIF1_Pos

#define DMA_LISR_TEIF1_Msk

#define DMA_LISR_TEIF1

#define DMA_LISR_DMEIF1_Pos

#define DMA_LISR_DMEIF1_Msk

#define DMA_LISR_DMEIF1

#define DMA_LISR_FEIF1_Pos

#define DMA_LISR_FEIF1_Msk

#define DMA_LISR_FEIF1

#define DMA_LISR_TCIF0_Pos

#define DMA_LISR_TCIF0_Msk

#define DMA_LISR_TCIF0

#define DMA_LISR_HTIF0_Pos

#define DMA_LISR_HTIF0_Msk

#define DMA_LISR_HTIF0

#define DMA_LISR_TEIF0_Pos

#define DMA_LISR_TEIF0_Msk

#define DMA_LISR_TEIF0

#define DMA_LISR_DMEIF0_Pos

#define DMA_LISR_DMEIF0_Msk

#define DMA_LISR_DMEIF0

#define DMA_LISR_FEIF0_Pos

#define DMA_LISR_FEIF0_Msk

#define DMA_LISR_FEIF0

Bits definition for DMA_HISR register

#define DMA_HISR_TCIF7_Pos

#define DMA_HISR_TCIF7_Msk

#define DMA_HISR_TCIF7

#define DMA_HISR_HTIF7_Pos

#define DMA_HISR_HTIF7_Msk

#define DMA_HISR_HTIF7

#define DMA_HISR_TEIF7_Pos

#define DMA_HISR_TEIF7_Msk

#define DMA_HISR_TEIF7

#define DMA_HISR_DMEIF7_Pos

#define DMA_HISR_DMEIF7_Msk

#define DMA_HISR_DMEIF7

#define DMA_HISR_FEIF7_Pos

#define DMA_HISR_FEIF7_Msk

#define DMA_HISR_FEIF7

#define DMA_HISR_TCIF6_Pos

#define DMA_HISR_TCIF6_Msk

#define DMA_HISR_TCIF6

#define DMA_HISR_HTIF6_Pos

#define DMA_HISR_HTIF6_Msk

#define DMA_HISR_HTIF6

#define DMA_HISR_TEIF6_Pos

#define DMA_HISR_TEIF6_Msk

#define DMA_HISR_TEIF6

#define DMA_HISR_DMEIF6_Pos

#define DMA_HISR_DMEIF6_Msk

#define DMA_HISR_DMEIF6

#define DMA_HISR_FEIF6_Pos

#define DMA_HISR_FEIF6_Msk

#define DMA_HISR_FEIF6

#define DMA_HISR_TCIF5_Pos

#define DMA_HISR_TCIF5_Msk

#define DMA_HISR_TCIF5

#define DMA_HISR_HTIF5_Pos

#define DMA_HISR_HTIF5_Msk

#define DMA_HISR_HTIF5

#define DMA_HISR_TEIF5_Pos

#define DMA_HISR_TEIF5_Msk

#define DMA_HISR_TEIF5

#define DMA_HISR_DMEIF5_Pos

#define DMA_HISR_DMEIF5_Msk

#define DMA_HISR_DMEIF5

#define DMA_HISR_FEIF5_Pos

#define DMA_HISR_FEIF5_Msk

#define DMA_HISR_FEIF5

#define DMA_HISR_TCIF4_Pos

#define DMA_HISR_TCIF4_Msk

#define DMA_HISR_TCIF4

#define DMA_HISR_HTIF4_Pos

#define DMA_HISR_HTIF4_Msk

#define DMA_HISR_HTIF4

#define DMA_HISR_TEIF4_Pos

#define DMA_HISR_TEIF4_Msk

#define DMA_HISR_TEIF4

#define DMA_HISR_DMEIF4_Pos

#define DMA_HISR_DMEIF4_Msk

#define DMA_HISR_DMEIF4

#define DMA_HISR_FEIF4_Pos

#define DMA_HISR_FEIF4_Msk

#define DMA_HISR_FEIF4

Bits definition for DMA_LIFCR register

#define DMA_LIFCR_CTCIF3_Pos

#define DMA_LIFCR_CTCIF3_Msk

#define DMA_LIFCR_CTCIF3

#define DMA_LIFCR_CHTIF3_Pos

#define DMA_LIFCR_CHTIF3_Msk

#define DMA_LIFCR_CHTIF3

#define DMA_LIFCR_CTEIF3_Pos

#define DMA_LIFCR_CTEIF3_Msk

#define DMA_LIFCR_CTEIF3

#define DMA_LIFCR_CDMEIF3_Pos

#define DMA_LIFCR_CDMEIF3_Msk

#define DMA_LIFCR_CDMEIF3

#define DMA_LIFCR_CFEIF3_Pos

#define DMA_LIFCR_CFEIF3_Msk

#define DMA_LIFCR_CFEIF3

#define DMA_LIFCR_CTCIF2_Pos

#define DMA_LIFCR_CTCIF2_Msk

#define DMA_LIFCR_CTCIF2

#define DMA_LIFCR_CHTIF2_Pos

#define DMA_LIFCR_CHTIF2_Msk

#define DMA_LIFCR_CHTIF2

#define DMA_LIFCR_CTEIF2_Pos

#define DMA_LIFCR_CTEIF2_Msk

#define DMA_LIFCR_CTEIF2

#define DMA_LIFCR_CDMEIF2_Pos

#define DMA_LIFCR_CDMEIF2_Msk

#define DMA_LIFCR_CDMEIF2

#define DMA_LIFCR_CFEIF2_Pos

#define DMA_LIFCR_CFEIF2_Msk

#define DMA_LIFCR_CFEIF2

#define DMA_LIFCR_CTCIF1_Pos

#define DMA_LIFCR_CTCIF1_Msk

#define DMA_LIFCR_CTCIF1

#define DMA_LIFCR_CHTIF1_Pos

#define DMA_LIFCR_CHTIF1_Msk

#define DMA_LIFCR_CHTIF1

#define DMA_LIFCR_CTEIF1_Pos

#define DMA_LIFCR_CTEIF1_Msk

#define DMA_LIFCR_CTEIF1

#define DMA_LIFCR_CDMEIF1_Pos

#define DMA_LIFCR_CDMEIF1_Msk

#define DMA_LIFCR_CDMEIF1

#define DMA_LIFCR_CFEIF1_Pos

#define DMA_LIFCR_CFEIF1_Msk

#define DMA_LIFCR_CFEIF1

#define DMA_LIFCR_CTCIF0_Pos

#define DMA_LIFCR_CTCIF0_Msk

#define DMA_LIFCR_CTCIF0

#define DMA_LIFCR_CHTIF0_Pos

#define DMA_LIFCR_CHTIF0_Msk

#define DMA_LIFCR_CHTIF0

#define DMA_LIFCR_CTEIF0_Pos

#define DMA_LIFCR_CTEIF0_Msk

#define DMA_LIFCR_CTEIF0

#define DMA_LIFCR_CDMEIF0_Pos

#define DMA_LIFCR_CDMEIF0_Msk

#define DMA_LIFCR_CDMEIF0

#define DMA_LIFCR_CFEIF0_Pos

#define DMA_LIFCR_CFEIF0_Msk

#define DMA_LIFCR_CFEIF0

Bits definition for DMA_HIFCR register

#define DMA_HIFCR_CTCIF7_Pos

#define DMA_HIFCR_CTCIF7_Msk

#define DMA_HIFCR_CTCIF7

#define DMA_HIFCR_CHTIF7_Pos

#define DMA_HIFCR_CHTIF7_Msk

#define DMA_HIFCR_CHTIF7

#define DMA_HIFCR_CTEIF7_Pos

#define DMA_HIFCR_CTEIF7_Msk

#define DMA_HIFCR_CTEIF7

#define DMA_HIFCR_CDMEIF7_Pos

#define DMA_HIFCR_CDMEIF7_Msk

#define DMA_HIFCR_CDMEIF7

#define DMA_HIFCR_CFEIF7_Pos

#define DMA_HIFCR_CFEIF7_Msk

#define DMA_HIFCR_CFEIF7

#define DMA_HIFCR_CTCIF6_Pos

#define DMA_HIFCR_CTCIF6_Msk

#define DMA_HIFCR_CTCIF6

#define DMA_HIFCR_CHTIF6_Pos

#define DMA_HIFCR_CHTIF6_Msk

#define DMA_HIFCR_CHTIF6

#define DMA_HIFCR_CTEIF6_Pos

#define DMA_HIFCR_CTEIF6_Msk

#define DMA_HIFCR_CTEIF6

#define DMA_HIFCR_CDMEIF6_Pos

#define DMA_HIFCR_CDMEIF6_Msk

#define DMA_HIFCR_CDMEIF6

#define DMA_HIFCR_CFEIF6_Pos

#define DMA_HIFCR_CFEIF6_Msk

#define DMA_HIFCR_CFEIF6

#define DMA_HIFCR_CTCIF5_Pos

#define DMA_HIFCR_CTCIF5_Msk

#define DMA_HIFCR_CTCIF5

#define DMA_HIFCR_CHTIF5_Pos

#define DMA_HIFCR_CHTIF5_Msk

#define DMA_HIFCR_CHTIF5

#define DMA_HIFCR_CTEIF5_Pos

#define DMA_HIFCR_CTEIF5_Msk

#define DMA_HIFCR_CTEIF5

#define DMA_HIFCR_CDMEIF5_Pos

#define DMA_HIFCR_CDMEIF5_Msk

#define DMA_HIFCR_CDMEIF5

#define DMA_HIFCR_CFEIF5_Pos

#define DMA_HIFCR_CFEIF5_Msk

#define DMA_HIFCR_CFEIF5

#define DMA_HIFCR_CTCIF4_Pos

#define DMA_HIFCR_CTCIF4_Msk

#define DMA_HIFCR_CTCIF4

#define DMA_HIFCR_CHTIF4_Pos

#define DMA_HIFCR_CHTIF4_Msk

#define DMA_HIFCR_CHTIF4

#define DMA_HIFCR_CTEIF4_Pos

#define DMA_HIFCR_CTEIF4_Msk

#define DMA_HIFCR_CTEIF4

#define DMA_HIFCR_CDMEIF4_Pos

#define DMA_HIFCR_CDMEIF4_Msk

#define DMA_HIFCR_CDMEIF4

#define DMA_HIFCR_CFEIF4_Pos

#define DMA_HIFCR_CFEIF4_Msk

#define DMA_HIFCR_CFEIF4

Bit definition for DMA_SxPAR register

#define DMA_SxPAR_PA_Pos

#define DMA_SxPAR_PA_Msk

#define DMA_SxPAR_PA

Bit definition for DMA_SxM0AR register

#define DMA_SxM0AR_M0A_Pos

#define DMA_SxM0AR_M0A_Msk

#define DMA_SxM0AR_M0A

Bit definition for DMA_SxM1AR register

#define DMA_SxM1AR_M1A_Pos

#define DMA_SxM1AR_M1A_Msk

#define DMA_SxM1AR_M1A

...

Bit definition for DMA2D_CR register

#define DMA2D_CR_START_Pos

#define DMA2D_CR_START_Msk

#define DMA2D_CR_START

#define DMA2D_CR_SUSP_Pos

#define DMA2D_CR_SUSP_Msk

#define DMA2D_CR_SUSP

#define DMA2D_CR_ABORT_Pos

#define DMA2D_CR_ABORT_Msk

#define DMA2D_CR_ABORT

#define DMA2D_CR_TEIE_Pos

#define DMA2D_CR_TEIE_Msk

#define DMA2D_CR_TEIE

#define DMA2D_CR_TCIE_Pos

#define DMA2D_CR_TCIE_Msk

#define DMA2D_CR_TCIE

#define DMA2D_CR_TWIE_Pos

#define DMA2D_CR_TWIE_Msk

#define DMA2D_CR_TWIE

#define DMA2D_CR_CAEIE_Pos

#define DMA2D_CR_CAEIE_Msk

#define DMA2D_CR_CAEIE

#define DMA2D_CR_CTCIE_Pos

#define DMA2D_CR_CTCIE_Msk

#define DMA2D_CR_CTCIE

#define DMA2D_CR_CEIE_Pos

#define DMA2D_CR_CEIE_Msk

#define DMA2D_CR_CEIE

#define DMA2D_CR_MODE_Pos

#define DMA2D_CR_MODE_Msk

#define DMA2D_CR_MODE

#define DMA2D_CR_MODE_0

#define DMA2D_CR_MODE_1

Bit definition for DMA2D_ISR register

#define DMA2D_ISR_TEIF_Pos

#define DMA2D_ISR_TEIF_Msk

#define DMA2D_ISR_TEIF

#define DMA2D_ISR_TCIF_Pos

#define DMA2D_ISR_TCIF_Msk

#define DMA2D_ISR_TCIF

#define DMA2D_ISR_TWIF_Pos

#define DMA2D_ISR_TWIF_Msk

#define DMA2D_ISR_TWIF

#define DMA2D_ISR_CAEIF_Pos

#define DMA2D_ISR_CAEIF_Msk

#define DMA2D_ISR_CAEIF

#define DMA2D_ISR_CTCIF_Pos

#define DMA2D_ISR_CTCIF_Msk

#define DMA2D_ISR_CTCIF

#define DMA2D_ISR_CEIF_Pos

#define DMA2D_ISR_CEIF_Msk

#define DMA2D_ISR_CEIF

Bit definition for DMA2D_IFCR register

#define DMA2D_IFCR_CTEIF_Pos

#define DMA2D_IFCR_CTEIF_Msk

#define DMA2D_IFCR_CTEIF

#define DMA2D_IFCR_CTCIF_Pos

#define DMA2D_IFCR_CTCIF_Msk

#define DMA2D_IFCR_CTCIF

#define DMA2D_IFCR_CTWIF_Pos

#define DMA2D_IFCR_CTWIF_Msk

#define DMA2D_IFCR_CTWIF

#define DMA2D_IFCR_CAECIF_Pos

#define DMA2D_IFCR_CAECIF_Msk

#define DMA2D_IFCR_CAECIF

#define DMA2D_IFCR_CCTCIF_Pos

#define DMA2D_IFCR_CCTCIF_Msk

#define DMA2D_IFCR_CCTCIF

#define DMA2D_IFCR_CCEIF_Pos

#define DMA2D_IFCR_CCEIF_Msk

#define DMA2D_IFCR_CCEIF

#define DMA2D_IFSR_CTEIF

#define DMA2D_IFSR_CTCIF

#define DMA2D_IFSR_CTWIF

#define DMA2D_IFSR_CCAEIF

#define DMA2D_IFSR_CCTCIF

#define DMA2D_IFSR_CCEIF

Bit definition for DMA2D_FGMAR register

#define DMA2D_FGMAR_MA_Pos

#define DMA2D_FGMAR_MA_Msk

#define DMA2D_FGMAR_MA

Bit definition for DMA2D_FGOR register

#define DMA2D_FGOR_LO_Pos

#define DMA2D_FGOR_LO_Msk

#define DMA2D_FGOR_LO

Bit definition for DMA2D_BGMAR register

#define DMA2D_BGMAR_MA_Pos

#define DMA2D_BGMAR_MA_Msk

#define DMA2D_BGMAR_MA

Bit definition for DMA2D_BGOR register

#define DMA2D_BGOR_LO_Pos

#define DMA2D_BGOR_LO_Msk

#define DMA2D_BGOR_LO

Bit definition for DMA2D_FGPFCCR register

#define DMA2D_FGPFCCR_CM_Pos

#define DMA2D_FGPFCCR_CM_Msk

#define DMA2D_FGPFCCR_CM

#define DMA2D_FGPFCCR_CM_0

#define DMA2D_FGPFCCR_CM_1

#define DMA2D_FGPFCCR_CM_2

#define DMA2D_FGPFCCR_CM_3

#define DMA2D_FGPFCCR_CCM_Pos

#define DMA2D_FGPFCCR_CCM_Msk

#define DMA2D_FGPFCCR_CCM

#define DMA2D_FGPFCCR_START_Pos

#define DMA2D_FGPFCCR_START_Msk

#define DMA2D_FGPFCCR_START

#define DMA2D_FGPFCCR_CS_Pos

#define DMA2D_FGPFCCR_CS_Msk

#define DMA2D_FGPFCCR_CS

#define DMA2D_FGPFCCR_AM_Pos

#define DMA2D_FGPFCCR_AM_Msk

#define DMA2D_FGPFCCR_AM

#define DMA2D_FGPFCCR_AM_0

#define DMA2D_FGPFCCR_AM_1

#define DMA2D_FGPFCCR_ALPHA_Pos

#define DMA2D_FGPFCCR_ALPHA_Msk

#define DMA2D_FGPFCCR_ALPHA

Bit definition for DMA2D_FGCOLR register

#define DMA2D_FGCOLR_BLUE_Pos

#define DMA2D_FGCOLR_BLUE_Msk

#define DMA2D_FGCOLR_BLUE

#define DMA2D_FGCOLR_GREEN_Pos

#define DMA2D_FGCOLR_GREEN_Msk

#define DMA2D_FGCOLR_GREEN

#define DMA2D_FGCOLR_RED_Pos

#define DMA2D_FGCOLR_RED_Msk

#define DMA2D_FGCOLR_RED

Bit definition for DMA2D_BGPFCCR register

#define DMA2D_BGPFCCR_CM_Pos

#define DMA2D_BGPFCCR_CM_Msk

#define DMA2D_BGPFCCR_CM

#define DMA2D_BGPFCCR_CM_0

#define DMA2D_BGPFCCR_CM_1

#define DMA2D_BGPFCCR_CM_2

#define DMA2D_BGPFCCR_CM_3

#define DMA2D_BGPFCCR_CCM_Pos

#define DMA2D_BGPFCCR_CCM_Msk

#define DMA2D_BGPFCCR_CCM

#define DMA2D_BGPFCCR_START_Pos

#define DMA2D_BGPFCCR_START_Msk

#define DMA2D_BGPFCCR_START

#define DMA2D_BGPFCCR_CS_Pos

#define DMA2D_BGPFCCR_CS_Msk

#define DMA2D_BGPFCCR_CS

#define DMA2D_BGPFCCR_AM_Pos

#define DMA2D_BGPFCCR_AM_Msk

#define DMA2D_BGPFCCR_AM

#define DMA2D_BGPFCCR_AM_0

#define DMA2D_BGPFCCR_AM_1

#define DMA2D_BGPFCCR_ALPHA_Pos

#define DMA2D_BGPFCCR_ALPHA_Msk

#define DMA2D_BGPFCCR_ALPHA

Bit definition for DMA2D_BGCOLR register

#define DMA2D_BGCOLR_BLUE_Pos

#define DMA2D_BGCOLR_BLUE_Msk

#define DMA2D_BGCOLR_BLUE

#define DMA2D_BGCOLR_GREEN_Pos

#define DMA2D_BGCOLR_GREEN_Msk

#define DMA2D_BGCOLR_GREEN

#define DMA2D_BGCOLR_RED_Pos

#define DMA2D_BGCOLR_RED_Msk

#define DMA2D_BGCOLR_RED

Bit definition for DMA2D_FGCMAR register

#define DMA2D_FGCMAR_MA_Pos

#define DMA2D_FGCMAR_MA_Msk

#define DMA2D_FGCMAR_MA

Bit definition for DMA2D_BGCMAR register

#define DMA2D_BGCMAR_MA_Pos

#define DMA2D_BGCMAR_MA_Msk

#define DMA2D_BGCMAR_MA

Bit definition for DMA2D_OPFCCR register

#define DMA2D_OPFCCR_CM_Pos

#define DMA2D_OPFCCR_CM_Msk

#define DMA2D_OPFCCR_CM

#define DMA2D_OPFCCR_CM_0

#define DMA2D_OPFCCR_CM_1

#define DMA2D_OPFCCR_CM_2

Bit definition for DMA2D_OCOLR register

#define DMA2D_OCOLR_BLUE_1

#define DMA2D_OCOLR_GREEN_1

#define DMA2D_OCOLR_RED_1

#define DMA2D_OCOLR_ALPHA_1

#define DMA2D_OCOLR_BLUE_2

#define DMA2D_OCOLR_GREEN_2

#define DMA2D_OCOLR_RED_2

#define DMA2D_OCOLR_BLUE_3

#define DMA2D_OCOLR_GREEN_3

#define DMA2D_OCOLR_RED_3

#define DMA2D_OCOLR_ALPHA_3

#define DMA2D_OCOLR_BLUE_4

#define DMA2D_OCOLR_GREEN_4

#define DMA2D_OCOLR_RED_4

#define DMA2D_OCOLR_ALPHA_4

Bit definition for DMA2D_OMAR register

#define DMA2D_OMAR_MA_Pos

#define DMA2D_OMAR_MA_Msk

#define DMA2D_OMAR_MA

Bit definition for DMA2D_OOR register

#define DMA2D_OOR_LO_Pos

#define DMA2D_OOR_LO_Msk

#define DMA2D_OOR_LO

Bit definition for DMA2D_NLR register

#define DMA2D_NLR_NL_Pos

#define DMA2D_NLR_NL_Msk

#define DMA2D_NLR_NL

#define DMA2D_NLR_PL_Pos

#define DMA2D_NLR_PL_Msk

#define DMA2D_NLR_PL

Bit definition for DMA2D_LWR register

#define DMA2D_LWR_LW_Pos

#define DMA2D_LWR_LW_Msk

#define DMA2D_LWR_LW

Bit definition for DMA2D_AMTCR register

#define DMA2D_AMTCR_EN_Pos

#define DMA2D_AMTCR_EN_Msk

#define DMA2D_AMTCR_EN

#define DMA2D_AMTCR_DT_Pos

#define DMA2D_AMTCR_DT_Msk

#define DMA2D_AMTCR_DT

Bit definition for DMA2D_BGCLUT register

...

Bit definition for EXTI_IMR register

#define EXTI_IMR_MR0_Pos

#define EXTI_IMR_MR0_Msk

#define EXTI_IMR_MR0

#define EXTI_IMR_MR1_Pos

#define EXTI_IMR_MR1_Msk

#define EXTI_IMR_MR1

#define EXTI_IMR_MR2_Pos

#define EXTI_IMR_MR2_Msk

#define EXTI_IMR_MR2

#define EXTI_IMR_MR3_Pos

#define EXTI_IMR_MR3_Msk

#define EXTI_IMR_MR3

#define EXTI_IMR_MR4_Pos

#define EXTI_IMR_MR4_Msk

#define EXTI_IMR_MR4

#define EXTI_IMR_MR5_Pos

#define EXTI_IMR_MR5_Msk

#define EXTI_IMR_MR5

#define EXTI_IMR_MR6_Pos

#define EXTI_IMR_MR6_Msk

#define EXTI_IMR_MR6

#define EXTI_IMR_MR7_Pos

#define EXTI_IMR_MR7_Msk

#define EXTI_IMR_MR7

#define EXTI_IMR_MR8_Pos

#define EXTI_IMR_MR8_Msk

#define EXTI_IMR_MR8

#define EXTI_IMR_MR9_Pos

#define EXTI_IMR_MR9_Msk

#define EXTI_IMR_MR9

#define EXTI_IMR_MR10_Pos

#define EXTI_IMR_MR10_Msk

#define EXTI_IMR_MR10

#define EXTI_IMR_MR11_Pos

#define EXTI_IMR_MR11_Msk

#define EXTI_IMR_MR11

#define EXTI_IMR_MR12_Pos

#define EXTI_IMR_MR12_Msk

#define EXTI_IMR_MR12

#define EXTI_IMR_MR13_Pos

#define EXTI_IMR_MR13_Msk

#define EXTI_IMR_MR13

#define EXTI_IMR_MR14_Pos

#define EXTI_IMR_MR14_Msk

#define EXTI_IMR_MR14

#define EXTI_IMR_MR15_Pos

#define EXTI_IMR_MR15_Msk

#define EXTI_IMR_MR15

#define EXTI_IMR_MR16_Pos

#define EXTI_IMR_MR16_Msk

#define EXTI_IMR_MR16

#define EXTI_IMR_MR17_Pos

#define EXTI_IMR_MR17_Msk

#define EXTI_IMR_MR17

#define EXTI_IMR_MR18_Pos

#define EXTI_IMR_MR18_Msk

#define EXTI_IMR_MR18

#define EXTI_IMR_MR19_Pos

#define EXTI_IMR_MR19_Msk

#define EXTI_IMR_MR19

#define EXTI_IMR_MR20_Pos

#define EXTI_IMR_MR20_Msk

#define EXTI_IMR_MR20

#define EXTI_IMR_MR21_Pos

#define EXTI_IMR_MR21_Msk

#define EXTI_IMR_MR21

#define EXTI_IMR_MR22_Pos

#define EXTI_IMR_MR22_Msk

#define EXTI_IMR_MR22

#define EXTI_IMR_IM0

#define EXTI_IMR_IM1

#define EXTI_IMR_IM2

#define EXTI_IMR_IM3

#define EXTI_IMR_IM4

#define EXTI_IMR_IM5

#define EXTI_IMR_IM6

#define EXTI_IMR_IM7

#define EXTI_IMR_IM8

#define EXTI_IMR_IM9

#define EXTI_IMR_IM10

#define EXTI_IMR_IM11

#define EXTI_IMR_IM12

#define EXTI_IMR_IM13

#define EXTI_IMR_IM14

#define EXTI_IMR_IM15

#define EXTI_IMR_IM16

#define EXTI_IMR_IM17

#define EXTI_IMR_IM18

#define EXTI_IMR_IM19

#define EXTI_IMR_IM20

#define EXTI_IMR_IM21

#define EXTI_IMR_IM22

#define EXTI_IMR_IM_Pos

#define EXTI_IMR_IM_Msk

#define EXTI_IMR_IM

Bit definition for EXTI_EMR register

#define EXTI_EMR_MR0_Pos

#define EXTI_EMR_MR0_Msk

#define EXTI_EMR_MR0

#define EXTI_EMR_MR1_Pos

#define EXTI_EMR_MR1_Msk

#define EXTI_EMR_MR1

#define EXTI_EMR_MR2_Pos

#define EXTI_EMR_MR2_Msk

#define EXTI_EMR_MR2

#define EXTI_EMR_MR3_Pos

#define EXTI_EMR_MR3_Msk

#define EXTI_EMR_MR3

#define EXTI_EMR_MR4_Pos

#define EXTI_EMR_MR4_Msk

#define EXTI_EMR_MR4

#define EXTI_EMR_MR5_Pos

#define EXTI_EMR_MR5_Msk

#define EXTI_EMR_MR5

#define EXTI_EMR_MR6_Pos

#define EXTI_EMR_MR6_Msk

#define EXTI_EMR_MR6

#define EXTI_EMR_MR7_Pos

#define EXTI_EMR_MR7_Msk

#define EXTI_EMR_MR7

#define EXTI_EMR_MR8_Pos

#define EXTI_EMR_MR8_Msk

#define EXTI_EMR_MR8

#define EXTI_EMR_MR9_Pos

#define EXTI_EMR_MR9_Msk

#define EXTI_EMR_MR9

#define EXTI_EMR_MR10_Pos

#define EXTI_EMR_MR10_Msk

#define EXTI_EMR_MR10

#define EXTI_EMR_MR11_Pos

#define EXTI_EMR_MR11_Msk

#define EXTI_EMR_MR11

#define EXTI_EMR_MR12_Pos

#define EXTI_EMR_MR12_Msk

#define EXTI_EMR_MR12

#define EXTI_EMR_MR13_Pos

#define EXTI_EMR_MR13_Msk

#define EXTI_EMR_MR13

#define EXTI_EMR_MR14_Pos

#define EXTI_EMR_MR14_Msk

#define EXTI_EMR_MR14

#define EXTI_EMR_MR15_Pos

#define EXTI_EMR_MR15_Msk

#define EXTI_EMR_MR15

#define EXTI_EMR_MR16_Pos

#define EXTI_EMR_MR16_Msk

#define EXTI_EMR_MR16

#define EXTI_EMR_MR17_Pos

#define EXTI_EMR_MR17_Msk

#define EXTI_EMR_MR17

#define EXTI_EMR_MR18_Pos

#define EXTI_EMR_MR18_Msk

#define EXTI_EMR_MR18

#define EXTI_EMR_MR19_Pos

#define EXTI_EMR_MR19_Msk

#define EXTI_EMR_MR19

#define EXTI_EMR_MR20_Pos

#define EXTI_EMR_MR20_Msk

#define EXTI_EMR_MR20

#define EXTI_EMR_MR21_Pos

#define EXTI_EMR_MR21_Msk

#define EXTI_EMR_MR21

#define EXTI_EMR_MR22_Pos

#define EXTI_EMR_MR22_Msk

#define EXTI_EMR_MR22

#define EXTI_EMR_EM0

#define EXTI_EMR_EM1

#define EXTI_EMR_EM2

#define EXTI_EMR_EM3

#define EXTI_EMR_EM4

#define EXTI_EMR_EM5

#define EXTI_EMR_EM6

#define EXTI_EMR_EM7

#define EXTI_EMR_EM8

#define EXTI_EMR_EM9

#define EXTI_EMR_EM10

#define EXTI_EMR_EM11

#define EXTI_EMR_EM12

#define EXTI_EMR_EM13

#define EXTI_EMR_EM14

#define EXTI_EMR_EM15

#define EXTI_EMR_EM16

#define EXTI_EMR_EM17

#define EXTI_EMR_EM18

#define EXTI_EMR_EM19

#define EXTI_EMR_EM20

#define EXTI_EMR_EM21

#define EXTI_EMR_EM22

Bit definition for EXTI_RTSR register

#define EXTI_RTSR_TR0_Pos

#define EXTI_RTSR_TR0_Msk

#define EXTI_RTSR_TR0

#define EXTI_RTSR_TR1_Pos

#define EXTI_RTSR_TR1_Msk

#define EXTI_RTSR_TR1

#define EXTI_RTSR_TR2_Pos

#define EXTI_RTSR_TR2_Msk

#define EXTI_RTSR_TR2

#define EXTI_RTSR_TR3_Pos

#define EXTI_RTSR_TR3_Msk

#define EXTI_RTSR_TR3

#define EXTI_RTSR_TR4_Pos

#define EXTI_RTSR_TR4_Msk

#define EXTI_RTSR_TR4

#define EXTI_RTSR_TR5_Pos

#define EXTI_RTSR_TR5_Msk

#define EXTI_RTSR_TR5

#define EXTI_RTSR_TR6_Pos

#define EXTI_RTSR_TR6_Msk

#define EXTI_RTSR_TR6

#define EXTI_RTSR_TR7_Pos

#define EXTI_RTSR_TR7_Msk

#define EXTI_RTSR_TR7

#define EXTI_RTSR_TR8_Pos

#define EXTI_RTSR_TR8_Msk

#define EXTI_RTSR_TR8

#define EXTI_RTSR_TR9_Pos

#define EXTI_RTSR_TR9_Msk

#define EXTI_RTSR_TR9

#define EXTI_RTSR_TR10_Pos

#define EXTI_RTSR_TR10_Msk

#define EXTI_RTSR_TR10

#define EXTI_RTSR_TR11_Pos

#define EXTI_RTSR_TR11_Msk

#define EXTI_RTSR_TR11

#define EXTI_RTSR_TR12_Pos

#define EXTI_RTSR_TR12_Msk

#define EXTI_RTSR_TR12

#define EXTI_RTSR_TR13_Pos

#define EXTI_RTSR_TR13_Msk

#define EXTI_RTSR_TR13

#define EXTI_RTSR_TR14_Pos

#define EXTI_RTSR_TR14_Msk

#define EXTI_RTSR_TR14

#define EXTI_RTSR_TR15_Pos

#define EXTI_RTSR_TR15_Msk

#define EXTI_RTSR_TR15

#define EXTI_RTSR_TR16_Pos

#define EXTI_RTSR_TR16_Msk

#define EXTI_RTSR_TR16

#define EXTI_RTSR_TR17_Pos

#define EXTI_RTSR_TR17_Msk

#define EXTI_RTSR_TR17

#define EXTI_RTSR_TR18_Pos

#define EXTI_RTSR_TR18_Msk

#define EXTI_RTSR_TR18

#define EXTI_RTSR_TR19_Pos

#define EXTI_RTSR_TR19_Msk

#define EXTI_RTSR_TR19

#define EXTI_RTSR_TR20_Pos

#define EXTI_RTSR_TR20_Msk

#define EXTI_RTSR_TR20

#define EXTI_RTSR_TR21_Pos

#define EXTI_RTSR_TR21_Msk

#define EXTI_RTSR_TR21

#define EXTI_RTSR_TR22_Pos

#define EXTI_RTSR_TR22_Msk

#define EXTI_RTSR_TR22

Bit definition for EXTI_FTSR register

#define EXTI_FTSR_TR0_Pos

#define EXTI_FTSR_TR0_Msk

#define EXTI_FTSR_TR0

#define EXTI_FTSR_TR1_Pos

#define EXTI_FTSR_TR1_Msk

#define EXTI_FTSR_TR1

#define EXTI_FTSR_TR2_Pos

#define EXTI_FTSR_TR2_Msk

#define EXTI_FTSR_TR2

#define EXTI_FTSR_TR3_Pos

#define EXTI_FTSR_TR3_Msk

#define EXTI_FTSR_TR3

#define EXTI_FTSR_TR4_Pos

#define EXTI_FTSR_TR4_Msk

#define EXTI_FTSR_TR4

#define EXTI_FTSR_TR5_Pos

#define EXTI_FTSR_TR5_Msk

#define EXTI_FTSR_TR5

#define EXTI_FTSR_TR6_Pos

#define EXTI_FTSR_TR6_Msk

#define EXTI_FTSR_TR6

#define EXTI_FTSR_TR7_Pos

#define EXTI_FTSR_TR7_Msk

#define EXTI_FTSR_TR7

#define EXTI_FTSR_TR8_Pos

#define EXTI_FTSR_TR8_Msk

#define EXTI_FTSR_TR8

#define EXTI_FTSR_TR9_Pos

#define EXTI_FTSR_TR9_Msk

#define EXTI_FTSR_TR9

#define EXTI_FTSR_TR10_Pos

#define EXTI_FTSR_TR10_Msk

#define EXTI_FTSR_TR10

#define EXTI_FTSR_TR11_Pos

#define EXTI_FTSR_TR11_Msk

#define EXTI_FTSR_TR11

#define EXTI_FTSR_TR12_Pos

#define EXTI_FTSR_TR12_Msk

#define EXTI_FTSR_TR12

#define EXTI_FTSR_TR13_Pos

#define EXTI_FTSR_TR13_Msk

#define EXTI_FTSR_TR13

#define EXTI_FTSR_TR14_Pos

#define EXTI_FTSR_TR14_Msk

#define EXTI_FTSR_TR14

#define EXTI_FTSR_TR15_Pos

#define EXTI_FTSR_TR15_Msk

#define EXTI_FTSR_TR15

#define EXTI_FTSR_TR16_Pos

#define EXTI_FTSR_TR16_Msk

#define EXTI_FTSR_TR16

#define EXTI_FTSR_TR17_Pos

#define EXTI_FTSR_TR17_Msk

#define EXTI_FTSR_TR17

#define EXTI_FTSR_TR18_Pos

#define EXTI_FTSR_TR18_Msk

#define EXTI_FTSR_TR18

#define EXTI_FTSR_TR19_Pos

#define EXTI_FTSR_TR19_Msk

#define EXTI_FTSR_TR19

#define EXTI_FTSR_TR20_Pos

#define EXTI_FTSR_TR20_Msk

#define EXTI_FTSR_TR20

#define EXTI_FTSR_TR21_Pos

#define EXTI_FTSR_TR21_Msk

#define EXTI_FTSR_TR21

#define EXTI_FTSR_TR22_Pos

#define EXTI_FTSR_TR22_Msk

#define EXTI_FTSR_TR22

Bit definition for EXTI_SWIER register

#define EXTI_SWIER_SWIER0_Pos

#define EXTI_SWIER_SWIER0_Msk

#define EXTI_SWIER_SWIER0

#define EXTI_SWIER_SWIER1_Pos

#define EXTI_SWIER_SWIER1_Msk

#define EXTI_SWIER_SWIER1

#define EXTI_SWIER_SWIER2_Pos

#define EXTI_SWIER_SWIER2_Msk

#define EXTI_SWIER_SWIER2

#define EXTI_SWIER_SWIER3_Pos

#define EXTI_SWIER_SWIER3_Msk

#define EXTI_SWIER_SWIER3

#define EXTI_SWIER_SWIER4_Pos

#define EXTI_SWIER_SWIER4_Msk

#define EXTI_SWIER_SWIER4

#define EXTI_SWIER_SWIER5_Pos

#define EXTI_SWIER_SWIER5_Msk

#define EXTI_SWIER_SWIER5

#define EXTI_SWIER_SWIER6_Pos

#define EXTI_SWIER_SWIER6_Msk

#define EXTI_SWIER_SWIER6

#define EXTI_SWIER_SWIER7_Pos

#define EXTI_SWIER_SWIER7_Msk

#define EXTI_SWIER_SWIER7

#define EXTI_SWIER_SWIER8_Pos

#define EXTI_SWIER_SWIER8_Msk

#define EXTI_SWIER_SWIER8

#define EXTI_SWIER_SWIER9_Pos

#define EXTI_SWIER_SWIER9_Msk

#define EXTI_SWIER_SWIER9

#define EXTI_SWIER_SWIER10_Pos

#define EXTI_SWIER_SWIER10_Msk

#define EXTI_SWIER_SWIER10

#define EXTI_SWIER_SWIER11_Pos

#define EXTI_SWIER_SWIER11_Msk

#define EXTI_SWIER_SWIER11

#define EXTI_SWIER_SWIER12_Pos

#define EXTI_SWIER_SWIER12_Msk

#define EXTI_SWIER_SWIER12

#define EXTI_SWIER_SWIER13_Pos

#define EXTI_SWIER_SWIER13_Msk

#define EXTI_SWIER_SWIER13

#define EXTI_SWIER_SWIER14_Pos

#define EXTI_SWIER_SWIER14_Msk

#define EXTI_SWIER_SWIER14

#define EXTI_SWIER_SWIER15_Pos

#define EXTI_SWIER_SWIER15_Msk

#define EXTI_SWIER_SWIER15

#define EXTI_SWIER_SWIER16_Pos

#define EXTI_SWIER_SWIER16_Msk

#define EXTI_SWIER_SWIER16

#define EXTI_SWIER_SWIER17_Pos

#define EXTI_SWIER_SWIER17_Msk

#define EXTI_SWIER_SWIER17

#define EXTI_SWIER_SWIER18_Pos

#define EXTI_SWIER_SWIER18_Msk

#define EXTI_SWIER_SWIER18

#define EXTI_SWIER_SWIER19_Pos

#define EXTI_SWIER_SWIER19_Msk

#define EXTI_SWIER_SWIER19

#define EXTI_SWIER_SWIER20_Pos

#define EXTI_SWIER_SWIER20_Msk

#define EXTI_SWIER_SWIER20

#define EXTI_SWIER_SWIER21_Pos

#define EXTI_SWIER_SWIER21_Msk

#define EXTI_SWIER_SWIER21

#define EXTI_SWIER_SWIER22_Pos

#define EXTI_SWIER_SWIER22_Msk

#define EXTI_SWIER_SWIER22

Bit definition for EXTI_PR register

#define EXTI_PR_PR0_Pos

#define EXTI_PR_PR0_Msk

#define EXTI_PR_PR0

#define EXTI_PR_PR1_Pos

#define EXTI_PR_PR1_Msk

#define EXTI_PR_PR1

#define EXTI_PR_PR2_Pos

#define EXTI_PR_PR2_Msk

#define EXTI_PR_PR2

#define EXTI_PR_PR3_Pos

#define EXTI_PR_PR3_Msk

#define EXTI_PR_PR3

#define EXTI_PR_PR4_Pos

#define EXTI_PR_PR4_Msk

#define EXTI_PR_PR4

#define EXTI_PR_PR5_Pos

#define EXTI_PR_PR5_Msk

#define EXTI_PR_PR5

#define EXTI_PR_PR6_Pos

#define EXTI_PR_PR6_Msk

#define EXTI_PR_PR6

#define EXTI_PR_PR7_Pos

#define EXTI_PR_PR7_Msk

#define EXTI_PR_PR7

#define EXTI_PR_PR8_Pos

#define EXTI_PR_PR8_Msk

#define EXTI_PR_PR8

#define EXTI_PR_PR9_Pos

#define EXTI_PR_PR9_Msk

#define EXTI_PR_PR9

#define EXTI_PR_PR10_Pos

#define EXTI_PR_PR10_Msk

#define EXTI_PR_PR10

#define EXTI_PR_PR11_Pos

#define EXTI_PR_PR11_Msk

#define EXTI_PR_PR11

#define EXTI_PR_PR12_Pos

#define EXTI_PR_PR12_Msk

#define EXTI_PR_PR12

#define EXTI_PR_PR13_Pos

#define EXTI_PR_PR13_Msk

#define EXTI_PR_PR13

#define EXTI_PR_PR14_Pos

#define EXTI_PR_PR14_Msk

#define EXTI_PR_PR14

#define EXTI_PR_PR15_Pos

#define EXTI_PR_PR15_Msk

#define EXTI_PR_PR15

#define EXTI_PR_PR16_Pos

#define EXTI_PR_PR16_Msk

#define EXTI_PR_PR16

#define EXTI_PR_PR17_Pos

#define EXTI_PR_PR17_Msk

#define EXTI_PR_PR17

#define EXTI_PR_PR18_Pos

#define EXTI_PR_PR18_Msk

#define EXTI_PR_PR18

#define EXTI_PR_PR19_Pos

#define EXTI_PR_PR19_Msk

#define EXTI_PR_PR19

#define EXTI_PR_PR20_Pos

#define EXTI_PR_PR20_Msk

#define EXTI_PR_PR20

#define EXTI_PR_PR21_Pos

#define EXTI_PR_PR21_Msk

#define EXTI_PR_PR21

#define EXTI_PR_PR22_Pos

#define EXTI_PR_PR22_Msk

#define EXTI_PR_PR22

...

Bits definition for FLASH_ACR register

#define FLASH_ACR_LATENCY_Pos

#define FLASH_ACR_LATENCY_Msk

#define FLASH_ACR_LATENCY

#define FLASH_ACR_LATENCY_0WS

#define FLASH_ACR_LATENCY_1WS

#define FLASH_ACR_LATENCY_2WS

#define FLASH_ACR_LATENCY_3WS

#define FLASH_ACR_LATENCY_4WS

#define FLASH_ACR_LATENCY_5WS

#define FLASH_ACR_LATENCY_6WS

#define FLASH_ACR_LATENCY_7WS

#define FLASH_ACR_LATENCY_8WS

#define FLASH_ACR_LATENCY_9WS

#define FLASH_ACR_LATENCY_10WS

#define FLASH_ACR_LATENCY_11WS

#define FLASH_ACR_LATENCY_12WS

#define FLASH_ACR_LATENCY_13WS

#define FLASH_ACR_LATENCY_14WS

#define FLASH_ACR_LATENCY_15WS

#define FLASH_ACR_PRFTEN_Pos

#define FLASH_ACR_PRFTEN_Msk

#define FLASH_ACR_PRFTEN

#define FLASH_ACR_ICEN_Pos

#define FLASH_ACR_ICEN_Msk

#define FLASH_ACR_ICEN

#define FLASH_ACR_DCEN_Pos

#define FLASH_ACR_DCEN_Msk

#define FLASH_ACR_DCEN

#define FLASH_ACR_ICRST_Pos

#define FLASH_ACR_ICRST_Msk

#define FLASH_ACR_ICRST

#define FLASH_ACR_DCRST_Pos

#define FLASH_ACR_DCRST_Msk

#define FLASH_ACR_DCRST

#define FLASH_ACR_BYTE0_ADDRESS_Pos

#define FLASH_ACR_BYTE0_ADDRESS_Msk

#define FLASH_ACR_BYTE0_ADDRESS

#define FLASH_ACR_BYTE2_ADDRESS_Pos

#define FLASH_ACR_BYTE2_ADDRESS_Msk

#define FLASH_ACR_BYTE2_ADDRESS

Bits definition for FLASH_SR register

#define FLASH_SR_EOP_Pos

#define FLASH_SR_EOP_Msk

#define FLASH_SR_EOP

#define FLASH_SR_SOP_Pos

#define FLASH_SR_SOP_Msk

#define FLASH_SR_SOP

#define FLASH_SR_WRPERR_Pos

#define FLASH_SR_WRPERR_Msk

#define FLASH_SR_WRPERR

#define FLASH_SR_PGAERR_Pos

#define FLASH_SR_PGAERR_Msk

#define FLASH_SR_PGAERR

#define FLASH_SR_PGPERR_Pos

#define FLASH_SR_PGPERR_Msk

#define FLASH_SR_PGPERR

#define FLASH_SR_PGSERR_Pos

#define FLASH_SR_PGSERR_Msk

#define FLASH_SR_PGSERR

#define FLASH_SR_RDERR_Pos

#define FLASH_SR_RDERR_Msk

#define FLASH_SR_RDERR

#define FLASH_SR_BSY_Pos

#define FLASH_SR_BSY_Msk

#define FLASH_SR_BSY

Bits definition for FLASH_CR register

#define FLASH_CR_PG_Pos

#define FLASH_CR_PG_Msk

#define FLASH_CR_PG

#define FLASH_CR_SER_Pos

#define FLASH_CR_SER_Msk

#define FLASH_CR_SER

#define FLASH_CR_MER_Pos

#define FLASH_CR_MER_Msk

#define FLASH_CR_MER

#define FLASH_CR_MER1

#define FLASH_CR_SNB_Pos

#define FLASH_CR_SNB_Msk

#define FLASH_CR_SNB

#define FLASH_CR_SNB_0

#define FLASH_CR_SNB_1

#define FLASH_CR_SNB_2

#define FLASH_CR_SNB_3

#define FLASH_CR_SNB_4

#define FLASH_CR_PSIZE_Pos

#define FLASH_CR_PSIZE_Msk

#define FLASH_CR_PSIZE

#define FLASH_CR_PSIZE_0

#define FLASH_CR_PSIZE_1

#define FLASH_CR_MER2_Pos

#define FLASH_CR_MER2_Msk

#define FLASH_CR_MER2

#define FLASH_CR_STRT_Pos

#define FLASH_CR_STRT_Msk

#define FLASH_CR_STRT

#define FLASH_CR_EOPIE_Pos

#define FLASH_CR_EOPIE_Msk

#define FLASH_CR_EOPIE

#define FLASH_CR_ERRIE_Pos

#define FLASH_CR_ERRIE_Msk

#define FLASH_CR_ERRIE

#define FLASH_CR_LOCK_Pos

#define FLASH_CR_LOCK_Msk

#define FLASH_CR_LOCK

Bits definition for FLASH_OPTCR register

#define FLASH_OPTCR_OPTLOCK_Pos

#define FLASH_OPTCR_OPTLOCK_Msk

#define FLASH_OPTCR_OPTLOCK

#define FLASH_OPTCR_OPTSTRT_Pos

#define FLASH_OPTCR_OPTSTRT_Msk

#define FLASH_OPTCR_OPTSTRT

#define FLASH_OPTCR_BOR_LEV_0

#define FLASH_OPTCR_BOR_LEV_1

#define FLASH_OPTCR_BOR_LEV_Pos

#define FLASH_OPTCR_BOR_LEV_Msk

#define FLASH_OPTCR_BOR_LEV

#define FLASH_OPTCR_BFB2_Pos

#define FLASH_OPTCR_BFB2_Msk

#define FLASH_OPTCR_BFB2

#define FLASH_OPTCR_WDG_SW_Pos

#define FLASH_OPTCR_WDG_SW_Msk

#define FLASH_OPTCR_WDG_SW

#define FLASH_OPTCR_nRST_STOP_Pos

#define FLASH_OPTCR_nRST_STOP_Msk

#define FLASH_OPTCR_nRST_STOP

#define FLASH_OPTCR_nRST_STDBY_Pos

#define FLASH_OPTCR_nRST_STDBY_Msk

#define FLASH_OPTCR_nRST_STDBY

#define FLASH_OPTCR_RDP_Pos

#define FLASH_OPTCR_RDP_Msk

#define FLASH_OPTCR_RDP

#define FLASH_OPTCR_RDP_0

#define FLASH_OPTCR_RDP_1

#define FLASH_OPTCR_RDP_2

#define FLASH_OPTCR_RDP_3

#define FLASH_OPTCR_RDP_4

#define FLASH_OPTCR_RDP_5

#define FLASH_OPTCR_RDP_6

#define FLASH_OPTCR_RDP_7

#define FLASH_OPTCR_nWRP_Pos

#define FLASH_OPTCR_nWRP_Msk

#define FLASH_OPTCR_nWRP

#define FLASH_OPTCR_nWRP_0

#define FLASH_OPTCR_nWRP_1

#define FLASH_OPTCR_nWRP_2

#define FLASH_OPTCR_nWRP_3

#define FLASH_OPTCR_nWRP_4

#define FLASH_OPTCR_nWRP_5

#define FLASH_OPTCR_nWRP_6

#define FLASH_OPTCR_nWRP_7

#define FLASH_OPTCR_nWRP_8

#define FLASH_OPTCR_nWRP_9

#define FLASH_OPTCR_nWRP_10

#define FLASH_OPTCR_nWRP_11

#define FLASH_OPTCR_DB1M_Pos

#define FLASH_OPTCR_DB1M_Msk

#define FLASH_OPTCR_DB1M

#define FLASH_OPTCR_SPRMOD_Pos

#define FLASH_OPTCR_SPRMOD_Msk

#define FLASH_OPTCR_SPRMOD

Bits definition for FLASH_OPTCR1 register

#define FLASH_OPTCR1_nWRP_Pos

#define FLASH_OPTCR1_nWRP_Msk

#define FLASH_OPTCR1_nWRP

#define FLASH_OPTCR1_nWRP_0

#define FLASH_OPTCR1_nWRP_1

#define FLASH_OPTCR1_nWRP_2

#define FLASH_OPTCR1_nWRP_3

#define FLASH_OPTCR1_nWRP_4

#define FLASH_OPTCR1_nWRP_5

#define FLASH_OPTCR1_nWRP_6

#define FLASH_OPTCR1_nWRP_7

#define FLASH_OPTCR1_nWRP_8

#define FLASH_OPTCR1_nWRP_9

#define FLASH_OPTCR1_nWRP_10

#define FLASH_OPTCR1_nWRP_11

...

Bit definition for FMC_BCR1 register

#define FMC_BCR1_MBKEN_Pos

#define FMC_BCR1_MBKEN_Msk

#define FMC_BCR1_MBKEN

#define FMC_BCR1_MUXEN_Pos

#define FMC_BCR1_MUXEN_Msk

#define FMC_BCR1_MUXEN

#define FMC_BCR1_MTYP_Pos

#define FMC_BCR1_MTYP_Msk

#define FMC_BCR1_MTYP

#define FMC_BCR1_MTYP_0

#define FMC_BCR1_MTYP_1

#define FMC_BCR1_MWID_Pos

#define FMC_BCR1_MWID_Msk

#define FMC_BCR1_MWID

#define FMC_BCR1_MWID_0

#define FMC_BCR1_MWID_1

#define FMC_BCR1_FACCEN_Pos

#define FMC_BCR1_FACCEN_Msk

#define FMC_BCR1_FACCEN

#define FMC_BCR1_BURSTEN_Pos

#define FMC_BCR1_BURSTEN_Msk

#define FMC_BCR1_BURSTEN

#define FMC_BCR1_WAITPOL_Pos

#define FMC_BCR1_WAITPOL_Msk

#define FMC_BCR1_WAITPOL

#define FMC_BCR1_WRAPMOD_Pos

#define FMC_BCR1_WRAPMOD_Msk

#define FMC_BCR1_WRAPMOD

#define FMC_BCR1_WAITCFG_Pos

#define FMC_BCR1_WAITCFG_Msk

#define FMC_BCR1_WAITCFG

#define FMC_BCR1_WREN_Pos

#define FMC_BCR1_WREN_Msk

#define FMC_BCR1_WREN

#define FMC_BCR1_WAITEN_Pos

#define FMC_BCR1_WAITEN_Msk

#define FMC_BCR1_WAITEN

#define FMC_BCR1_EXTMOD_Pos

#define FMC_BCR1_EXTMOD_Msk

#define FMC_BCR1_EXTMOD

#define FMC_BCR1_ASYNCWAIT_Pos

#define FMC_BCR1_ASYNCWAIT_Msk

#define FMC_BCR1_ASYNCWAIT

#define FMC_BCR1_CPSIZE_Pos

#define FMC_BCR1_CPSIZE_Msk

#define FMC_BCR1_CPSIZE

#define FMC_BCR1_CPSIZE_0

#define FMC_BCR1_CPSIZE_1

#define FMC_BCR1_CPSIZE_2

#define FMC_BCR1_CBURSTRW_Pos

#define FMC_BCR1_CBURSTRW_Msk

#define FMC_BCR1_CBURSTRW

#define FMC_BCR1_CCLKEN_Pos

#define FMC_BCR1_CCLKEN_Msk

#define FMC_BCR1_CCLKEN

Bit definition for FMC_BCR2 register

#define FMC_BCR2_MBKEN_Pos

#define FMC_BCR2_MBKEN_Msk

#define FMC_BCR2_MBKEN

#define FMC_BCR2_MUXEN_Pos

#define FMC_BCR2_MUXEN_Msk

#define FMC_BCR2_MUXEN

#define FMC_BCR2_MTYP_Pos

#define FMC_BCR2_MTYP_Msk

#define FMC_BCR2_MTYP

#define FMC_BCR2_MTYP_0

#define FMC_BCR2_MTYP_1

#define FMC_BCR2_MWID_Pos

#define FMC_BCR2_MWID_Msk

#define FMC_BCR2_MWID

#define FMC_BCR2_MWID_0

#define FMC_BCR2_MWID_1

#define FMC_BCR2_FACCEN_Pos

#define FMC_BCR2_FACCEN_Msk

#define FMC_BCR2_FACCEN

#define FMC_BCR2_BURSTEN_Pos

#define FMC_BCR2_BURSTEN_Msk

#define FMC_BCR2_BURSTEN

#define FMC_BCR2_WAITPOL_Pos

#define FMC_BCR2_WAITPOL_Msk

#define FMC_BCR2_WAITPOL

#define FMC_BCR2_WRAPMOD_Pos

#define FMC_BCR2_WRAPMOD_Msk

#define FMC_BCR2_WRAPMOD

#define FMC_BCR2_WAITCFG_Pos

#define FMC_BCR2_WAITCFG_Msk

#define FMC_BCR2_WAITCFG

#define FMC_BCR2_WREN_Pos

#define FMC_BCR2_WREN_Msk

#define FMC_BCR2_WREN

#define FMC_BCR2_WAITEN_Pos

#define FMC_BCR2_WAITEN_Msk

#define FMC_BCR2_WAITEN

#define FMC_BCR2_EXTMOD_Pos

#define FMC_BCR2_EXTMOD_Msk

#define FMC_BCR2_EXTMOD

#define FMC_BCR2_ASYNCWAIT_Pos

#define FMC_BCR2_ASYNCWAIT_Msk

#define FMC_BCR2_ASYNCWAIT

#define FMC_BCR2_CPSIZE_Pos

#define FMC_BCR2_CPSIZE_Msk

#define FMC_BCR2_CPSIZE

#define FMC_BCR2_CPSIZE_0

#define FMC_BCR2_CPSIZE_1

#define FMC_BCR2_CPSIZE_2

#define FMC_BCR2_CBURSTRW_Pos

#define FMC_BCR2_CBURSTRW_Msk

#define FMC_BCR2_CBURSTRW

Bit definition for FMC_BCR3 register

#define FMC_BCR3_MBKEN_Pos

#define FMC_BCR3_MBKEN_Msk

#define FMC_BCR3_MBKEN

#define FMC_BCR3_MUXEN_Pos

#define FMC_BCR3_MUXEN_Msk

#define FMC_BCR3_MUXEN

#define FMC_BCR3_MTYP_Pos

#define FMC_BCR3_MTYP_Msk

#define FMC_BCR3_MTYP

#define FMC_BCR3_MTYP_0

#define FMC_BCR3_MTYP_1

#define FMC_BCR3_MWID_Pos

#define FMC_BCR3_MWID_Msk

#define FMC_BCR3_MWID

#define FMC_BCR3_MWID_0

#define FMC_BCR3_MWID_1

#define FMC_BCR3_FACCEN_Pos

#define FMC_BCR3_FACCEN_Msk

#define FMC_BCR3_FACCEN

#define FMC_BCR3_BURSTEN_Pos

#define FMC_BCR3_BURSTEN_Msk

#define FMC_BCR3_BURSTEN

#define FMC_BCR3_WAITPOL_Pos

#define FMC_BCR3_WAITPOL_Msk

#define FMC_BCR3_WAITPOL

#define FMC_BCR3_WRAPMOD_Pos

#define FMC_BCR3_WRAPMOD_Msk

#define FMC_BCR3_WRAPMOD

#define FMC_BCR3_WAITCFG_Pos

#define FMC_BCR3_WAITCFG_Msk

#define FMC_BCR3_WAITCFG

#define FMC_BCR3_WREN_Pos

#define FMC_BCR3_WREN_Msk

#define FMC_BCR3_WREN

#define FMC_BCR3_WAITEN_Pos

#define FMC_BCR3_WAITEN_Msk

#define FMC_BCR3_WAITEN

#define FMC_BCR3_EXTMOD_Pos

#define FMC_BCR3_EXTMOD_Msk

#define FMC_BCR3_EXTMOD

#define FMC_BCR3_ASYNCWAIT_Pos

#define FMC_BCR3_ASYNCWAIT_Msk

#define FMC_BCR3_ASYNCWAIT

#define FMC_BCR3_CPSIZE_Pos

#define FMC_BCR3_CPSIZE_Msk

#define FMC_BCR3_CPSIZE

#define FMC_BCR3_CPSIZE_0

#define FMC_BCR3_CPSIZE_1

#define FMC_BCR3_CPSIZE_2

#define FMC_BCR3_CBURSTRW_Pos

#define FMC_BCR3_CBURSTRW_Msk

#define FMC_BCR3_CBURSTRW

Bit definition for FMC_BCR4 register

#define FMC_BCR4_MBKEN_Pos

#define FMC_BCR4_MBKEN_Msk

#define FMC_BCR4_MBKEN

#define FMC_BCR4_MUXEN_Pos

#define FMC_BCR4_MUXEN_Msk

#define FMC_BCR4_MUXEN

#define FMC_BCR4_MTYP_Pos

#define FMC_BCR4_MTYP_Msk

#define FMC_BCR4_MTYP

#define FMC_BCR4_MTYP_0

#define FMC_BCR4_MTYP_1

#define FMC_BCR4_MWID_Pos

#define FMC_BCR4_MWID_Msk

#define FMC_BCR4_MWID

#define FMC_BCR4_MWID_0

#define FMC_BCR4_MWID_1

#define FMC_BCR4_FACCEN_Pos

#define FMC_BCR4_FACCEN_Msk

#define FMC_BCR4_FACCEN

#define FMC_BCR4_BURSTEN_Pos

#define FMC_BCR4_BURSTEN_Msk

#define FMC_BCR4_BURSTEN

#define FMC_BCR4_WAITPOL_Pos

#define FMC_BCR4_WAITPOL_Msk

#define FMC_BCR4_WAITPOL

#define FMC_BCR4_WRAPMOD_Pos

#define FMC_BCR4_WRAPMOD_Msk

#define FMC_BCR4_WRAPMOD

#define FMC_BCR4_WAITCFG_Pos

#define FMC_BCR4_WAITCFG_Msk

#define FMC_BCR4_WAITCFG

#define FMC_BCR4_WREN_Pos

#define FMC_BCR4_WREN_Msk

#define FMC_BCR4_WREN

#define FMC_BCR4_WAITEN_Pos

#define FMC_BCR4_WAITEN_Msk

#define FMC_BCR4_WAITEN

#define FMC_BCR4_EXTMOD_Pos

#define FMC_BCR4_EXTMOD_Msk

#define FMC_BCR4_EXTMOD

#define FMC_BCR4_ASYNCWAIT_Pos

#define FMC_BCR4_ASYNCWAIT_Msk

#define FMC_BCR4_ASYNCWAIT

#define FMC_BCR4_CPSIZE_Pos

#define FMC_BCR4_CPSIZE_Msk

#define FMC_BCR4_CPSIZE

#define FMC_BCR4_CPSIZE_0

#define FMC_BCR4_CPSIZE_1

#define FMC_BCR4_CPSIZE_2

#define FMC_BCR4_CBURSTRW_Pos

#define FMC_BCR4_CBURSTRW_Msk

#define FMC_BCR4_CBURSTRW

Bit definition for FMC_BTR1 register

#define FMC_BTR1_ADDSET_Pos

#define FMC_BTR1_ADDSET_Msk

#define FMC_BTR1_ADDSET

#define FMC_BTR1_ADDSET_0

#define FMC_BTR1_ADDSET_1

#define FMC_BTR1_ADDSET_2

#define FMC_BTR1_ADDSET_3

#define FMC_BTR1_ADDHLD_Pos

#define FMC_BTR1_ADDHLD_Msk

#define FMC_BTR1_ADDHLD

#define FMC_BTR1_ADDHLD_0

#define FMC_BTR1_ADDHLD_1

#define FMC_BTR1_ADDHLD_2

#define FMC_BTR1_ADDHLD_3

#define FMC_BTR1_DATAST_Pos

#define FMC_BTR1_DATAST_Msk

#define FMC_BTR1_DATAST

#define FMC_BTR1_DATAST_0

#define FMC_BTR1_DATAST_1

#define FMC_BTR1_DATAST_2

#define FMC_BTR1_DATAST_3

#define FMC_BTR1_DATAST_4

#define FMC_BTR1_DATAST_5

#define FMC_BTR1_DATAST_6

#define FMC_BTR1_DATAST_7

#define FMC_BTR1_BUSTURN_Pos

#define FMC_BTR1_BUSTURN_Msk

#define FMC_BTR1_BUSTURN

#define FMC_BTR1_BUSTURN_0

#define FMC_BTR1_BUSTURN_1

#define FMC_BTR1_BUSTURN_2

#define FMC_BTR1_BUSTURN_3

#define FMC_BTR1_CLKDIV_Pos

#define FMC_BTR1_CLKDIV_Msk

#define FMC_BTR1_CLKDIV

#define FMC_BTR1_CLKDIV_0

#define FMC_BTR1_CLKDIV_1

#define FMC_BTR1_CLKDIV_2

#define FMC_BTR1_CLKDIV_3

#define FMC_BTR1_DATLAT_Pos

#define FMC_BTR1_DATLAT_Msk

#define FMC_BTR1_DATLAT

#define FMC_BTR1_DATLAT_0

#define FMC_BTR1_DATLAT_1

#define FMC_BTR1_DATLAT_2

#define FMC_BTR1_DATLAT_3

#define FMC_BTR1_ACCMOD_Pos

#define FMC_BTR1_ACCMOD_Msk

#define FMC_BTR1_ACCMOD

#define FMC_BTR1_ACCMOD_0

#define FMC_BTR1_ACCMOD_1

Bit definition for FMC_BTR2 register

#define FMC_BTR2_ADDSET_Pos

#define FMC_BTR2_ADDSET_Msk

#define FMC_BTR2_ADDSET

#define FMC_BTR2_ADDSET_0

#define FMC_BTR2_ADDSET_1

#define FMC_BTR2_ADDSET_2

#define FMC_BTR2_ADDSET_3

#define FMC_BTR2_ADDHLD_Pos

#define FMC_BTR2_ADDHLD_Msk

#define FMC_BTR2_ADDHLD

#define FMC_BTR2_ADDHLD_0

#define FMC_BTR2_ADDHLD_1

#define FMC_BTR2_ADDHLD_2

#define FMC_BTR2_ADDHLD_3

#define FMC_BTR2_DATAST_Pos

#define FMC_BTR2_DATAST_Msk

#define FMC_BTR2_DATAST

#define FMC_BTR2_DATAST_0

#define FMC_BTR2_DATAST_1

#define FMC_BTR2_DATAST_2

#define FMC_BTR2_DATAST_3

#define FMC_BTR2_DATAST_4

#define FMC_BTR2_DATAST_5

#define FMC_BTR2_DATAST_6

#define FMC_BTR2_DATAST_7

#define FMC_BTR2_BUSTURN_Pos

#define FMC_BTR2_BUSTURN_Msk

#define FMC_BTR2_BUSTURN

#define FMC_BTR2_BUSTURN_0

#define FMC_BTR2_BUSTURN_1

#define FMC_BTR2_BUSTURN_2

#define FMC_BTR2_BUSTURN_3

#define FMC_BTR2_CLKDIV_Pos

#define FMC_BTR2_CLKDIV_Msk

#define FMC_BTR2_CLKDIV

#define FMC_BTR2_CLKDIV_0

#define FMC_BTR2_CLKDIV_1

#define FMC_BTR2_CLKDIV_2

#define FMC_BTR2_CLKDIV_3

#define FMC_BTR2_DATLAT_Pos

#define FMC_BTR2_DATLAT_Msk

#define FMC_BTR2_DATLAT

#define FMC_BTR2_DATLAT_0

#define FMC_BTR2_DATLAT_1

#define FMC_BTR2_DATLAT_2

#define FMC_BTR2_DATLAT_3

#define FMC_BTR2_ACCMOD_Pos

#define FMC_BTR2_ACCMOD_Msk

#define FMC_BTR2_ACCMOD

#define FMC_BTR2_ACCMOD_0

#define FMC_BTR2_ACCMOD_1

Bit definition for FMC_BTR3 register

#define FMC_BTR3_ADDSET_Pos

#define FMC_BTR3_ADDSET_Msk

#define FMC_BTR3_ADDSET

#define FMC_BTR3_ADDSET_0

#define FMC_BTR3_ADDSET_1

#define FMC_BTR3_ADDSET_2

#define FMC_BTR3_ADDSET_3

#define FMC_BTR3_ADDHLD_Pos

#define FMC_BTR3_ADDHLD_Msk

#define FMC_BTR3_ADDHLD

#define FMC_BTR3_ADDHLD_0

#define FMC_BTR3_ADDHLD_1

#define FMC_BTR3_ADDHLD_2

#define FMC_BTR3_ADDHLD_3

#define FMC_BTR3_DATAST_Pos

#define FMC_BTR3_DATAST_Msk

#define FMC_BTR3_DATAST

#define FMC_BTR3_DATAST_0

#define FMC_BTR3_DATAST_1

#define FMC_BTR3_DATAST_2

#define FMC_BTR3_DATAST_3

#define FMC_BTR3_DATAST_4

#define FMC_BTR3_DATAST_5

#define FMC_BTR3_DATAST_6

#define FMC_BTR3_DATAST_7

#define FMC_BTR3_BUSTURN_Pos

#define FMC_BTR3_BUSTURN_Msk

#define FMC_BTR3_BUSTURN

#define FMC_BTR3_BUSTURN_0

#define FMC_BTR3_BUSTURN_1

#define FMC_BTR3_BUSTURN_2

#define FMC_BTR3_BUSTURN_3

#define FMC_BTR3_CLKDIV_Pos

#define FMC_BTR3_CLKDIV_Msk

#define FMC_BTR3_CLKDIV

#define FMC_BTR3_CLKDIV_0

#define FMC_BTR3_CLKDIV_1

#define FMC_BTR3_CLKDIV_2

#define FMC_BTR3_CLKDIV_3

#define FMC_BTR3_DATLAT_Pos

#define FMC_BTR3_DATLAT_Msk

#define FMC_BTR3_DATLAT

#define FMC_BTR3_DATLAT_0

#define FMC_BTR3_DATLAT_1

#define FMC_BTR3_DATLAT_2

#define FMC_BTR3_DATLAT_3

#define FMC_BTR3_ACCMOD_Pos

#define FMC_BTR3_ACCMOD_Msk

#define FMC_BTR3_ACCMOD

#define FMC_BTR3_ACCMOD_0

#define FMC_BTR3_ACCMOD_1

Bit definition for FMC_BTR4 register

#define FMC_BTR4_ADDSET_Pos

#define FMC_BTR4_ADDSET_Msk

#define FMC_BTR4_ADDSET

#define FMC_BTR4_ADDSET_0

#define FMC_BTR4_ADDSET_1

#define FMC_BTR4_ADDSET_2

#define FMC_BTR4_ADDSET_3

#define FMC_BTR4_ADDHLD_Pos

#define FMC_BTR4_ADDHLD_Msk

#define FMC_BTR4_ADDHLD

#define FMC_BTR4_ADDHLD_0

#define FMC_BTR4_ADDHLD_1

#define FMC_BTR4_ADDHLD_2

#define FMC_BTR4_ADDHLD_3

#define FMC_BTR4_DATAST_Pos

#define FMC_BTR4_DATAST_Msk

#define FMC_BTR4_DATAST

#define FMC_BTR4_DATAST_0

#define FMC_BTR4_DATAST_1

#define FMC_BTR4_DATAST_2

#define FMC_BTR4_DATAST_3

#define FMC_BTR4_DATAST_4

#define FMC_BTR4_DATAST_5

#define FMC_BTR4_DATAST_6

#define FMC_BTR4_DATAST_7

#define FMC_BTR4_BUSTURN_Pos

#define FMC_BTR4_BUSTURN_Msk

#define FMC_BTR4_BUSTURN

#define FMC_BTR4_BUSTURN_0

#define FMC_BTR4_BUSTURN_1

#define FMC_BTR4_BUSTURN_2

#define FMC_BTR4_BUSTURN_3

#define FMC_BTR4_CLKDIV_Pos

#define FMC_BTR4_CLKDIV_Msk

#define FMC_BTR4_CLKDIV

#define FMC_BTR4_CLKDIV_0

#define FMC_BTR4_CLKDIV_1

#define FMC_BTR4_CLKDIV_2

#define FMC_BTR4_CLKDIV_3

#define FMC_BTR4_DATLAT_Pos

#define FMC_BTR4_DATLAT_Msk

#define FMC_BTR4_DATLAT

#define FMC_BTR4_DATLAT_0

#define FMC_BTR4_DATLAT_1

#define FMC_BTR4_DATLAT_2

#define FMC_BTR4_DATLAT_3

#define FMC_BTR4_ACCMOD_Pos

#define FMC_BTR4_ACCMOD_Msk

#define FMC_BTR4_ACCMOD

#define FMC_BTR4_ACCMOD_0

#define FMC_BTR4_ACCMOD_1

Bit definition for FMC_BWTR1 register

#define FMC_BWTR1_ADDSET_Pos

#define FMC_BWTR1_ADDSET_Msk

#define FMC_BWTR1_ADDSET

#define FMC_BWTR1_ADDSET_0

#define FMC_BWTR1_ADDSET_1

#define FMC_BWTR1_ADDSET_2

#define FMC_BWTR1_ADDSET_3

#define FMC_BWTR1_ADDHLD_Pos

#define FMC_BWTR1_ADDHLD_Msk

#define FMC_BWTR1_ADDHLD

#define FMC_BWTR1_ADDHLD_0

#define FMC_BWTR1_ADDHLD_1

#define FMC_BWTR1_ADDHLD_2

#define FMC_BWTR1_ADDHLD_3

#define FMC_BWTR1_DATAST_Pos

#define FMC_BWTR1_DATAST_Msk

#define FMC_BWTR1_DATAST

#define FMC_BWTR1_DATAST_0

#define FMC_BWTR1_DATAST_1

#define FMC_BWTR1_DATAST_2

#define FMC_BWTR1_DATAST_3

#define FMC_BWTR1_DATAST_4

#define FMC_BWTR1_DATAST_5

#define FMC_BWTR1_DATAST_6

#define FMC_BWTR1_DATAST_7

#define FMC_BWTR1_BUSTURN_Pos

#define FMC_BWTR1_BUSTURN_Msk

#define FMC_BWTR1_BUSTURN

#define FMC_BWTR1_BUSTURN_0

#define FMC_BWTR1_BUSTURN_1

#define FMC_BWTR1_BUSTURN_2

#define FMC_BWTR1_BUSTURN_3

#define FMC_BWTR1_ACCMOD_Pos

#define FMC_BWTR1_ACCMOD_Msk

#define FMC_BWTR1_ACCMOD

#define FMC_BWTR1_ACCMOD_0

#define FMC_BWTR1_ACCMOD_1

Bit definition for FMC_BWTR2 register

#define FMC_BWTR2_ADDSET_Pos

#define FMC_BWTR2_ADDSET_Msk

#define FMC_BWTR2_ADDSET

#define FMC_BWTR2_ADDSET_0

#define FMC_BWTR2_ADDSET_1

#define FMC_BWTR2_ADDSET_2

#define FMC_BWTR2_ADDSET_3

#define FMC_BWTR2_ADDHLD_Pos

#define FMC_BWTR2_ADDHLD_Msk

#define FMC_BWTR2_ADDHLD

#define FMC_BWTR2_ADDHLD_0

#define FMC_BWTR2_ADDHLD_1

#define FMC_BWTR2_ADDHLD_2

#define FMC_BWTR2_ADDHLD_3

#define FMC_BWTR2_DATAST_Pos

#define FMC_BWTR2_DATAST_Msk

#define FMC_BWTR2_DATAST

#define FMC_BWTR2_DATAST_0

#define FMC_BWTR2_DATAST_1

#define FMC_BWTR2_DATAST_2

#define FMC_BWTR2_DATAST_3

#define FMC_BWTR2_DATAST_4

#define FMC_BWTR2_DATAST_5

#define FMC_BWTR2_DATAST_6

#define FMC_BWTR2_DATAST_7

#define FMC_BWTR2_BUSTURN_Pos

#define FMC_BWTR2_BUSTURN_Msk

#define FMC_BWTR2_BUSTURN

#define FMC_BWTR2_BUSTURN_0

#define FMC_BWTR2_BUSTURN_1

#define FMC_BWTR2_BUSTURN_2

#define FMC_BWTR2_BUSTURN_3

#define FMC_BWTR2_ACCMOD_Pos

#define FMC_BWTR2_ACCMOD_Msk

#define FMC_BWTR2_ACCMOD

#define FMC_BWTR2_ACCMOD_0

#define FMC_BWTR2_ACCMOD_1

Bit definition for FMC_BWTR3 register

#define FMC_BWTR3_ADDSET_Pos

#define FMC_BWTR3_ADDSET_Msk

#define FMC_BWTR3_ADDSET

#define FMC_BWTR3_ADDSET_0

#define FMC_BWTR3_ADDSET_1

#define FMC_BWTR3_ADDSET_2

#define FMC_BWTR3_ADDSET_3

#define FMC_BWTR3_ADDHLD_Pos

#define FMC_BWTR3_ADDHLD_Msk

#define FMC_BWTR3_ADDHLD

#define FMC_BWTR3_ADDHLD_0

#define FMC_BWTR3_ADDHLD_1

#define FMC_BWTR3_ADDHLD_2

#define FMC_BWTR3_ADDHLD_3

#define FMC_BWTR3_DATAST_Pos

#define FMC_BWTR3_DATAST_Msk

#define FMC_BWTR3_DATAST

#define FMC_BWTR3_DATAST_0

#define FMC_BWTR3_DATAST_1

#define FMC_BWTR3_DATAST_2

#define FMC_BWTR3_DATAST_3

#define FMC_BWTR3_DATAST_4

#define FMC_BWTR3_DATAST_5

#define FMC_BWTR3_DATAST_6

#define FMC_BWTR3_DATAST_7

#define FMC_BWTR3_BUSTURN_Pos

#define FMC_BWTR3_BUSTURN_Msk

#define FMC_BWTR3_BUSTURN

#define FMC_BWTR3_BUSTURN_0

#define FMC_BWTR3_BUSTURN_1

#define FMC_BWTR3_BUSTURN_2

#define FMC_BWTR3_BUSTURN_3

#define FMC_BWTR3_ACCMOD_Pos

#define FMC_BWTR3_ACCMOD_Msk

#define FMC_BWTR3_ACCMOD

#define FMC_BWTR3_ACCMOD_0

#define FMC_BWTR3_ACCMOD_1

Bit definition for FMC_BWTR4 register

#define FMC_BWTR4_ADDSET_Pos

#define FMC_BWTR4_ADDSET_Msk

#define FMC_BWTR4_ADDSET

#define FMC_BWTR4_ADDSET_0

#define FMC_BWTR4_ADDSET_1

#define FMC_BWTR4_ADDSET_2

#define FMC_BWTR4_ADDSET_3

#define FMC_BWTR4_ADDHLD_Pos

#define FMC_BWTR4_ADDHLD_Msk

#define FMC_BWTR4_ADDHLD

#define FMC_BWTR4_ADDHLD_0

#define FMC_BWTR4_ADDHLD_1

#define FMC_BWTR4_ADDHLD_2

#define FMC_BWTR4_ADDHLD_3

#define FMC_BWTR4_DATAST_Pos

#define FMC_BWTR4_DATAST_Msk

#define FMC_BWTR4_DATAST

#define FMC_BWTR4_DATAST_0

#define FMC_BWTR4_DATAST_1

#define FMC_BWTR4_DATAST_2

#define FMC_BWTR4_DATAST_3

#define FMC_BWTR4_DATAST_4

#define FMC_BWTR4_DATAST_5

#define FMC_BWTR4_DATAST_6

#define FMC_BWTR4_DATAST_7

#define FMC_BWTR4_BUSTURN_Pos

#define FMC_BWTR4_BUSTURN_Msk

#define FMC_BWTR4_BUSTURN

#define FMC_BWTR4_BUSTURN_0

#define FMC_BWTR4_BUSTURN_1

#define FMC_BWTR4_BUSTURN_2

#define FMC_BWTR4_BUSTURN_3

#define FMC_BWTR4_ACCMOD_Pos

#define FMC_BWTR4_ACCMOD_Msk

#define FMC_BWTR4_ACCMOD

#define FMC_BWTR4_ACCMOD_0

#define FMC_BWTR4_ACCMOD_1

Bit definition for FMC_PCR2 register

#define FMC_PCR2_PWAITEN_Pos

#define FMC_PCR2_PWAITEN_Msk

#define FMC_PCR2_PWAITEN

#define FMC_PCR2_PBKEN_Pos

#define FMC_PCR2_PBKEN_Msk

#define FMC_PCR2_PBKEN

#define FMC_PCR2_PTYP_Pos

#define FMC_PCR2_PTYP_Msk

#define FMC_PCR2_PTYP

#define FMC_PCR2_PWID_Pos

#define FMC_PCR2_PWID_Msk

#define FMC_PCR2_PWID

#define FMC_PCR2_PWID_0

#define FMC_PCR2_PWID_1

#define FMC_PCR2_ECCEN_Pos

#define FMC_PCR2_ECCEN_Msk

#define FMC_PCR2_ECCEN

#define FMC_PCR2_TCLR_Pos

#define FMC_PCR2_TCLR_Msk

#define FMC_PCR2_TCLR

#define FMC_PCR2_TCLR_0

#define FMC_PCR2_TCLR_1

#define FMC_PCR2_TCLR_2

#define FMC_PCR2_TCLR_3

#define FMC_PCR2_TAR_Pos

#define FMC_PCR2_TAR_Msk

#define FMC_PCR2_TAR

#define FMC_PCR2_TAR_0

#define FMC_PCR2_TAR_1

#define FMC_PCR2_TAR_2

#define FMC_PCR2_TAR_3

#define FMC_PCR2_ECCPS_Pos

#define FMC_PCR2_ECCPS_Msk

#define FMC_PCR2_ECCPS

#define FMC_PCR2_ECCPS_0

#define FMC_PCR2_ECCPS_1

#define FMC_PCR2_ECCPS_2

Bit definition for FMC_PCR3 register

#define FMC_PCR3_PWAITEN_Pos

#define FMC_PCR3_PWAITEN_Msk

#define FMC_PCR3_PWAITEN

#define FMC_PCR3_PBKEN_Pos

#define FMC_PCR3_PBKEN_Msk

#define FMC_PCR3_PBKEN

#define FMC_PCR3_PTYP_Pos

#define FMC_PCR3_PTYP_Msk

#define FMC_PCR3_PTYP

#define FMC_PCR3_PWID_Pos

#define FMC_PCR3_PWID_Msk

#define FMC_PCR3_PWID

#define FMC_PCR3_PWID_0

#define FMC_PCR3_PWID_1

#define FMC_PCR3_ECCEN_Pos

#define FMC_PCR3_ECCEN_Msk

#define FMC_PCR3_ECCEN

#define FMC_PCR3_TCLR_Pos

#define FMC_PCR3_TCLR_Msk

#define FMC_PCR3_TCLR

#define FMC_PCR3_TCLR_0

#define FMC_PCR3_TCLR_1

#define FMC_PCR3_TCLR_2

#define FMC_PCR3_TCLR_3

#define FMC_PCR3_TAR_Pos

#define FMC_PCR3_TAR_Msk

#define FMC_PCR3_TAR

#define FMC_PCR3_TAR_0

#define FMC_PCR3_TAR_1

#define FMC_PCR3_TAR_2

#define FMC_PCR3_TAR_3

#define FMC_PCR3_ECCPS_Pos

#define FMC_PCR3_ECCPS_Msk

#define FMC_PCR3_ECCPS

#define FMC_PCR3_ECCPS_0

#define FMC_PCR3_ECCPS_1

#define FMC_PCR3_ECCPS_2

Bit definition for FMC_PCR4 register

#define FMC_PCR4_PWAITEN_Pos

#define FMC_PCR4_PWAITEN_Msk

#define FMC_PCR4_PWAITEN

#define FMC_PCR4_PBKEN_Pos

#define FMC_PCR4_PBKEN_Msk

#define FMC_PCR4_PBKEN

#define FMC_PCR4_PTYP_Pos

#define FMC_PCR4_PTYP_Msk

#define FMC_PCR4_PTYP

#define FMC_PCR4_PWID_Pos

#define FMC_PCR4_PWID_Msk

#define FMC_PCR4_PWID

#define FMC_PCR4_PWID_0

#define FMC_PCR4_PWID_1

#define FMC_PCR4_ECCEN_Pos

#define FMC_PCR4_ECCEN_Msk

#define FMC_PCR4_ECCEN

#define FMC_PCR4_TCLR_Pos

#define FMC_PCR4_TCLR_Msk

#define FMC_PCR4_TCLR

#define FMC_PCR4_TCLR_0

#define FMC_PCR4_TCLR_1

#define FMC_PCR4_TCLR_2

#define FMC_PCR4_TCLR_3

#define FMC_PCR4_TAR_Pos

#define FMC_PCR4_TAR_Msk

#define FMC_PCR4_TAR

#define FMC_PCR4_TAR_0

#define FMC_PCR4_TAR_1

#define FMC_PCR4_TAR_2

#define FMC_PCR4_TAR_3

#define FMC_PCR4_ECCPS_Pos

#define FMC_PCR4_ECCPS_Msk

#define FMC_PCR4_ECCPS

#define FMC_PCR4_ECCPS_0

#define FMC_PCR4_ECCPS_1

#define FMC_PCR4_ECCPS_2

Bit definition for FMC_SR2 register

#define FMC_SR2_IRS_Pos

#define FMC_SR2_IRS_Msk

#define FMC_SR2_IRS

#define FMC_SR2_ILS_Pos

#define FMC_SR2_ILS_Msk

#define FMC_SR2_ILS

#define FMC_SR2_IFS_Pos

#define FMC_SR2_IFS_Msk

#define FMC_SR2_IFS

#define FMC_SR2_IREN_Pos

#define FMC_SR2_IREN_Msk

#define FMC_SR2_IREN

#define FMC_SR2_ILEN_Pos

#define FMC_SR2_ILEN_Msk

#define FMC_SR2_ILEN

#define FMC_SR2_IFEN_Pos

#define FMC_SR2_IFEN_Msk

#define FMC_SR2_IFEN

#define FMC_SR2_FEMPT_Pos

#define FMC_SR2_FEMPT_Msk

#define FMC_SR2_FEMPT

Bit definition for FMC_SR3 register

#define FMC_SR3_IRS_Pos

#define FMC_SR3_IRS_Msk

#define FMC_SR3_IRS

#define FMC_SR3_ILS_Pos

#define FMC_SR3_ILS_Msk

#define FMC_SR3_ILS

#define FMC_SR3_IFS_Pos

#define FMC_SR3_IFS_Msk

#define FMC_SR3_IFS

#define FMC_SR3_IREN_Pos

#define FMC_SR3_IREN_Msk

#define FMC_SR3_IREN

#define FMC_SR3_ILEN_Pos

#define FMC_SR3_ILEN_Msk

#define FMC_SR3_ILEN

#define FMC_SR3_IFEN_Pos

#define FMC_SR3_IFEN_Msk

#define FMC_SR3_IFEN

#define FMC_SR3_FEMPT_Pos

#define FMC_SR3_FEMPT_Msk

#define FMC_SR3_FEMPT

Bit definition for FMC_SR4 register

#define FMC_SR4_IRS_Pos

#define FMC_SR4_IRS_Msk

#define FMC_SR4_IRS

#define FMC_SR4_ILS_Pos

#define FMC_SR4_ILS_Msk

#define FMC_SR4_ILS

#define FMC_SR4_IFS_Pos

#define FMC_SR4_IFS_Msk

#define FMC_SR4_IFS

#define FMC_SR4_IREN_Pos

#define FMC_SR4_IREN_Msk

#define FMC_SR4_IREN

#define FMC_SR4_ILEN_Pos

#define FMC_SR4_ILEN_Msk

#define FMC_SR4_ILEN

#define FMC_SR4_IFEN_Pos

#define FMC_SR4_IFEN_Msk

#define FMC_SR4_IFEN

#define FMC_SR4_FEMPT_Pos

#define FMC_SR4_FEMPT_Msk

#define FMC_SR4_FEMPT

Bit definition for FMC_PMEM2 register

#define FMC_PMEM2_MEMSET2_Pos

#define FMC_PMEM2_MEMSET2_Msk

#define FMC_PMEM2_MEMSET2

#define FMC_PMEM2_MEMSET2_0

#define FMC_PMEM2_MEMSET2_1

#define FMC_PMEM2_MEMSET2_2

#define FMC_PMEM2_MEMSET2_3

#define FMC_PMEM2_MEMSET2_4

#define FMC_PMEM2_MEMSET2_5

#define FMC_PMEM2_MEMSET2_6

#define FMC_PMEM2_MEMSET2_7

#define FMC_PMEM2_MEMWAIT2_Pos

#define FMC_PMEM2_MEMWAIT2_Msk

#define FMC_PMEM2_MEMWAIT2

#define FMC_PMEM2_MEMWAIT2_0

#define FMC_PMEM2_MEMWAIT2_1

#define FMC_PMEM2_MEMWAIT2_2

#define FMC_PMEM2_MEMWAIT2_3

#define FMC_PMEM2_MEMWAIT2_4

#define FMC_PMEM2_MEMWAIT2_5

#define FMC_PMEM2_MEMWAIT2_6

#define FMC_PMEM2_MEMWAIT2_7

#define FMC_PMEM2_MEMHOLD2_Pos

#define FMC_PMEM2_MEMHOLD2_Msk

#define FMC_PMEM2_MEMHOLD2

#define FMC_PMEM2_MEMHOLD2_0

#define FMC_PMEM2_MEMHOLD2_1

#define FMC_PMEM2_MEMHOLD2_2

#define FMC_PMEM2_MEMHOLD2_3

#define FMC_PMEM2_MEMHOLD2_4

#define FMC_PMEM2_MEMHOLD2_5

#define FMC_PMEM2_MEMHOLD2_6

#define FMC_PMEM2_MEMHOLD2_7

#define FMC_PMEM2_MEMHIZ2_Pos

#define FMC_PMEM2_MEMHIZ2_Msk

#define FMC_PMEM2_MEMHIZ2

#define FMC_PMEM2_MEMHIZ2_0

#define FMC_PMEM2_MEMHIZ2_1

#define FMC_PMEM2_MEMHIZ2_2

#define FMC_PMEM2_MEMHIZ2_3

#define FMC_PMEM2_MEMHIZ2_4

#define FMC_PMEM2_MEMHIZ2_5

#define FMC_PMEM2_MEMHIZ2_6

#define FMC_PMEM2_MEMHIZ2_7

Bit definition for FMC_PMEM3 register

#define FMC_PMEM3_MEMSET3_Pos

#define FMC_PMEM3_MEMSET3_Msk

#define FMC_PMEM3_MEMSET3

#define FMC_PMEM3_MEMSET3_0

#define FMC_PMEM3_MEMSET3_1

#define FMC_PMEM3_MEMSET3_2

#define FMC_PMEM3_MEMSET3_3

#define FMC_PMEM3_MEMSET3_4

#define FMC_PMEM3_MEMSET3_5

#define FMC_PMEM3_MEMSET3_6

#define FMC_PMEM3_MEMSET3_7

#define FMC_PMEM3_MEMWAIT3_Pos

#define FMC_PMEM3_MEMWAIT3_Msk

#define FMC_PMEM3_MEMWAIT3

#define FMC_PMEM3_MEMWAIT3_0

#define FMC_PMEM3_MEMWAIT3_1

#define FMC_PMEM3_MEMWAIT3_2

#define FMC_PMEM3_MEMWAIT3_3

#define FMC_PMEM3_MEMWAIT3_4

#define FMC_PMEM3_MEMWAIT3_5

#define FMC_PMEM3_MEMWAIT3_6

#define FMC_PMEM3_MEMWAIT3_7

#define FMC_PMEM3_MEMHOLD3_Pos

#define FMC_PMEM3_MEMHOLD3_Msk

#define FMC_PMEM3_MEMHOLD3

#define FMC_PMEM3_MEMHOLD3_0

#define FMC_PMEM3_MEMHOLD3_1

#define FMC_PMEM3_MEMHOLD3_2

#define FMC_PMEM3_MEMHOLD3_3

#define FMC_PMEM3_MEMHOLD3_4

#define FMC_PMEM3_MEMHOLD3_5

#define FMC_PMEM3_MEMHOLD3_6

#define FMC_PMEM3_MEMHOLD3_7

#define FMC_PMEM3_MEMHIZ3_Pos

#define FMC_PMEM3_MEMHIZ3_Msk

#define FMC_PMEM3_MEMHIZ3

#define FMC_PMEM3_MEMHIZ3_0

#define FMC_PMEM3_MEMHIZ3_1

#define FMC_PMEM3_MEMHIZ3_2

#define FMC_PMEM3_MEMHIZ3_3

#define FMC_PMEM3_MEMHIZ3_4

#define FMC_PMEM3_MEMHIZ3_5

#define FMC_PMEM3_MEMHIZ3_6

#define FMC_PMEM3_MEMHIZ3_7

Bit definition for FMC_PMEM4 register

#define FMC_PMEM4_MEMSET4_Pos

#define FMC_PMEM4_MEMSET4_Msk

#define FMC_PMEM4_MEMSET4

#define FMC_PMEM4_MEMSET4_0

#define FMC_PMEM4_MEMSET4_1

#define FMC_PMEM4_MEMSET4_2

#define FMC_PMEM4_MEMSET4_3

#define FMC_PMEM4_MEMSET4_4

#define FMC_PMEM4_MEMSET4_5

#define FMC_PMEM4_MEMSET4_6

#define FMC_PMEM4_MEMSET4_7

#define FMC_PMEM4_MEMWAIT4_Pos

#define FMC_PMEM4_MEMWAIT4_Msk

#define FMC_PMEM4_MEMWAIT4

#define FMC_PMEM4_MEMWAIT4_0

#define FMC_PMEM4_MEMWAIT4_1

#define FMC_PMEM4_MEMWAIT4_2

#define FMC_PMEM4_MEMWAIT4_3

#define FMC_PMEM4_MEMWAIT4_4

#define FMC_PMEM4_MEMWAIT4_5

#define FMC_PMEM4_MEMWAIT4_6

#define FMC_PMEM4_MEMWAIT4_7

#define FMC_PMEM4_MEMHOLD4_Pos

#define FMC_PMEM4_MEMHOLD4_Msk

#define FMC_PMEM4_MEMHOLD4

#define FMC_PMEM4_MEMHOLD4_0

#define FMC_PMEM4_MEMHOLD4_1

#define FMC_PMEM4_MEMHOLD4_2

#define FMC_PMEM4_MEMHOLD4_3

#define FMC_PMEM4_MEMHOLD4_4

#define FMC_PMEM4_MEMHOLD4_5

#define FMC_PMEM4_MEMHOLD4_6

#define FMC_PMEM4_MEMHOLD4_7

#define FMC_PMEM4_MEMHIZ4_Pos

#define FMC_PMEM4_MEMHIZ4_Msk

#define FMC_PMEM4_MEMHIZ4

#define FMC_PMEM4_MEMHIZ4_0

#define FMC_PMEM4_MEMHIZ4_1

#define FMC_PMEM4_MEMHIZ4_2

#define FMC_PMEM4_MEMHIZ4_3

#define FMC_PMEM4_MEMHIZ4_4

#define FMC_PMEM4_MEMHIZ4_5

#define FMC_PMEM4_MEMHIZ4_6

#define FMC_PMEM4_MEMHIZ4_7

Bit definition for FMC_PATT2 register

#define FMC_PATT2_ATTSET2_Pos

#define FMC_PATT2_ATTSET2_Msk

#define FMC_PATT2_ATTSET2

#define FMC_PATT2_ATTSET2_0

#define FMC_PATT2_ATTSET2_1

#define FMC_PATT2_ATTSET2_2

#define FMC_PATT2_ATTSET2_3

#define FMC_PATT2_ATTSET2_4

#define FMC_PATT2_ATTSET2_5

#define FMC_PATT2_ATTSET2_6

#define FMC_PATT2_ATTSET2_7

#define FMC_PATT2_ATTWAIT2_Pos

#define FMC_PATT2_ATTWAIT2_Msk

#define FMC_PATT2_ATTWAIT2

#define FMC_PATT2_ATTWAIT2_0

#define FMC_PATT2_ATTWAIT2_1

#define FMC_PATT2_ATTWAIT2_2

#define FMC_PATT2_ATTWAIT2_3

#define FMC_PATT2_ATTWAIT2_4

#define FMC_PATT2_ATTWAIT2_5

#define FMC_PATT2_ATTWAIT2_6

#define FMC_PATT2_ATTWAIT2_7

#define FMC_PATT2_ATTHOLD2_Pos

#define FMC_PATT2_ATTHOLD2_Msk

#define FMC_PATT2_ATTHOLD2

#define FMC_PATT2_ATTHOLD2_0

#define FMC_PATT2_ATTHOLD2_1

#define FMC_PATT2_ATTHOLD2_2

#define FMC_PATT2_ATTHOLD2_3

#define FMC_PATT2_ATTHOLD2_4

#define FMC_PATT2_ATTHOLD2_5

#define FMC_PATT2_ATTHOLD2_6

#define FMC_PATT2_ATTHOLD2_7

#define FMC_PATT2_ATTHIZ2_Pos

#define FMC_PATT2_ATTHIZ2_Msk

#define FMC_PATT2_ATTHIZ2

#define FMC_PATT2_ATTHIZ2_0

#define FMC_PATT2_ATTHIZ2_1

#define FMC_PATT2_ATTHIZ2_2

#define FMC_PATT2_ATTHIZ2_3

#define FMC_PATT2_ATTHIZ2_4

#define FMC_PATT2_ATTHIZ2_5

#define FMC_PATT2_ATTHIZ2_6

#define FMC_PATT2_ATTHIZ2_7

Bit definition for FMC_PATT3 register

#define FMC_PATT3_ATTSET3_Pos

#define FMC_PATT3_ATTSET3_Msk

#define FMC_PATT3_ATTSET3

#define FMC_PATT3_ATTSET3_0

#define FMC_PATT3_ATTSET3_1

#define FMC_PATT3_ATTSET3_2

#define FMC_PATT3_ATTSET3_3

#define FMC_PATT3_ATTSET3_4

#define FMC_PATT3_ATTSET3_5

#define FMC_PATT3_ATTSET3_6

#define FMC_PATT3_ATTSET3_7

#define FMC_PATT3_ATTWAIT3_Pos

#define FMC_PATT3_ATTWAIT3_Msk

#define FMC_PATT3_ATTWAIT3

#define FMC_PATT3_ATTWAIT3_0

#define FMC_PATT3_ATTWAIT3_1

#define FMC_PATT3_ATTWAIT3_2

#define FMC_PATT3_ATTWAIT3_3

#define FMC_PATT3_ATTWAIT3_4

#define FMC_PATT3_ATTWAIT3_5

#define FMC_PATT3_ATTWAIT3_6

#define FMC_PATT3_ATTWAIT3_7

#define FMC_PATT3_ATTHOLD3_Pos

#define FMC_PATT3_ATTHOLD3_Msk

#define FMC_PATT3_ATTHOLD3

#define FMC_PATT3_ATTHOLD3_0

#define FMC_PATT3_ATTHOLD3_1

#define FMC_PATT3_ATTHOLD3_2

#define FMC_PATT3_ATTHOLD3_3

#define FMC_PATT3_ATTHOLD3_4

#define FMC_PATT3_ATTHOLD3_5

#define FMC_PATT3_ATTHOLD3_6

#define FMC_PATT3_ATTHOLD3_7

#define FMC_PATT3_ATTHIZ3_Pos

#define FMC_PATT3_ATTHIZ3_Msk

#define FMC_PATT3_ATTHIZ3

#define FMC_PATT3_ATTHIZ3_0

#define FMC_PATT3_ATTHIZ3_1

#define FMC_PATT3_ATTHIZ3_2

#define FMC_PATT3_ATTHIZ3_3

#define FMC_PATT3_ATTHIZ3_4

#define FMC_PATT3_ATTHIZ3_5

#define FMC_PATT3_ATTHIZ3_6

#define FMC_PATT3_ATTHIZ3_7

Bit definition for FMC_PATT4 register

#define FMC_PATT4_ATTSET4_Pos

#define FMC_PATT4_ATTSET4_Msk

#define FMC_PATT4_ATTSET4

#define FMC_PATT4_ATTSET4_0

#define FMC_PATT4_ATTSET4_1

#define FMC_PATT4_ATTSET4_2

#define FMC_PATT4_ATTSET4_3

#define FMC_PATT4_ATTSET4_4

#define FMC_PATT4_ATTSET4_5

#define FMC_PATT4_ATTSET4_6

#define FMC_PATT4_ATTSET4_7

#define FMC_PATT4_ATTWAIT4_Pos

#define FMC_PATT4_ATTWAIT4_Msk

#define FMC_PATT4_ATTWAIT4

#define FMC_PATT4_ATTWAIT4_0

#define FMC_PATT4_ATTWAIT4_1

#define FMC_PATT4_ATTWAIT4_2

#define FMC_PATT4_ATTWAIT4_3

#define FMC_PATT4_ATTWAIT4_4

#define FMC_PATT4_ATTWAIT4_5

#define FMC_PATT4_ATTWAIT4_6

#define FMC_PATT4_ATTWAIT4_7

#define FMC_PATT4_ATTHOLD4_Pos

#define FMC_PATT4_ATTHOLD4_Msk

#define FMC_PATT4_ATTHOLD4

#define FMC_PATT4_ATTHOLD4_0

#define FMC_PATT4_ATTHOLD4_1

#define FMC_PATT4_ATTHOLD4_2

#define FMC_PATT4_ATTHOLD4_3

#define FMC_PATT4_ATTHOLD4_4

#define FMC_PATT4_ATTHOLD4_5

#define FMC_PATT4_ATTHOLD4_6

#define FMC_PATT4_ATTHOLD4_7

#define FMC_PATT4_ATTHIZ4_Pos

#define FMC_PATT4_ATTHIZ4_Msk

#define FMC_PATT4_ATTHIZ4

#define FMC_PATT4_ATTHIZ4_0

#define FMC_PATT4_ATTHIZ4_1

#define FMC_PATT4_ATTHIZ4_2

#define FMC_PATT4_ATTHIZ4_3

#define FMC_PATT4_ATTHIZ4_4

#define FMC_PATT4_ATTHIZ4_5

#define FMC_PATT4_ATTHIZ4_6

#define FMC_PATT4_ATTHIZ4_7

Bit definition for FMC_PIO4 register

#define FMC_PIO4_IOSET4_Pos

#define FMC_PIO4_IOSET4_Msk

#define FMC_PIO4_IOSET4

#define FMC_PIO4_IOSET4_0

#define FMC_PIO4_IOSET4_1

#define FMC_PIO4_IOSET4_2

#define FMC_PIO4_IOSET4_3

#define FMC_PIO4_IOSET4_4

#define FMC_PIO4_IOSET4_5

#define FMC_PIO4_IOSET4_6

#define FMC_PIO4_IOSET4_7

#define FMC_PIO4_IOWAIT4_Pos

#define FMC_PIO4_IOWAIT4_Msk

#define FMC_PIO4_IOWAIT4

#define FMC_PIO4_IOWAIT4_0

#define FMC_PIO4_IOWAIT4_1

#define FMC_PIO4_IOWAIT4_2

#define FMC_PIO4_IOWAIT4_3

#define FMC_PIO4_IOWAIT4_4

#define FMC_PIO4_IOWAIT4_5

#define FMC_PIO4_IOWAIT4_6

#define FMC_PIO4_IOWAIT4_7

#define FMC_PIO4_IOHOLD4_Pos

#define FMC_PIO4_IOHOLD4_Msk

#define FMC_PIO4_IOHOLD4

#define FMC_PIO4_IOHOLD4_0

#define FMC_PIO4_IOHOLD4_1

#define FMC_PIO4_IOHOLD4_2

#define FMC_PIO4_IOHOLD4_3

#define FMC_PIO4_IOHOLD4_4

#define FMC_PIO4_IOHOLD4_5

#define FMC_PIO4_IOHOLD4_6

#define FMC_PIO4_IOHOLD4_7

#define FMC_PIO4_IOHIZ4_Pos

#define FMC_PIO4_IOHIZ4_Msk

#define FMC_PIO4_IOHIZ4

#define FMC_PIO4_IOHIZ4_0

#define FMC_PIO4_IOHIZ4_1

#define FMC_PIO4_IOHIZ4_2

#define FMC_PIO4_IOHIZ4_3

#define FMC_PIO4_IOHIZ4_4

#define FMC_PIO4_IOHIZ4_5

#define FMC_PIO4_IOHIZ4_6

#define FMC_PIO4_IOHIZ4_7

Bit definition for FMC_ECCR2 register

#define FMC_ECCR2_ECC2_Pos

#define FMC_ECCR2_ECC2_Msk

#define FMC_ECCR2_ECC2

Bit definition for FMC_ECCR3 register

#define FMC_ECCR3_ECC3_Pos

#define FMC_ECCR3_ECC3_Msk

#define FMC_ECCR3_ECC3

Bit definition for FMC_SDCR1 register

#define FMC_SDCR1_NC_Pos

#define FMC_SDCR1_NC_Msk

#define FMC_SDCR1_NC

#define FMC_SDCR1_NC_0

#define FMC_SDCR1_NC_1

#define FMC_SDCR1_NR_Pos

#define FMC_SDCR1_NR_Msk

#define FMC_SDCR1_NR

#define FMC_SDCR1_NR_0

#define FMC_SDCR1_NR_1

#define FMC_SDCR1_MWID_Pos

#define FMC_SDCR1_MWID_Msk

#define FMC_SDCR1_MWID

#define FMC_SDCR1_MWID_0

#define FMC_SDCR1_MWID_1

#define FMC_SDCR1_NB_Pos

#define FMC_SDCR1_NB_Msk

#define FMC_SDCR1_NB

#define FMC_SDCR1_CAS_Pos

#define FMC_SDCR1_CAS_Msk

#define FMC_SDCR1_CAS

#define FMC_SDCR1_CAS_0

#define FMC_SDCR1_CAS_1

#define FMC_SDCR1_WP_Pos

#define FMC_SDCR1_WP_Msk

#define FMC_SDCR1_WP

#define FMC_SDCR1_SDCLK_Pos

#define FMC_SDCR1_SDCLK_Msk

#define FMC_SDCR1_SDCLK

#define FMC_SDCR1_SDCLK_0

#define FMC_SDCR1_SDCLK_1

#define FMC_SDCR1_RBURST_Pos

#define FMC_SDCR1_RBURST_Msk

#define FMC_SDCR1_RBURST

#define FMC_SDCR1_RPIPE_Pos

#define FMC_SDCR1_RPIPE_Msk

#define FMC_SDCR1_RPIPE

#define FMC_SDCR1_RPIPE_0

#define FMC_SDCR1_RPIPE_1

Bit definition for FMC_SDCR2 register

#define FMC_SDCR2_NC_Pos

#define FMC_SDCR2_NC_Msk

#define FMC_SDCR2_NC

#define FMC_SDCR2_NC_0

#define FMC_SDCR2_NC_1

#define FMC_SDCR2_NR_Pos

#define FMC_SDCR2_NR_Msk

#define FMC_SDCR2_NR

#define FMC_SDCR2_NR_0

#define FMC_SDCR2_NR_1

#define FMC_SDCR2_MWID_Pos

#define FMC_SDCR2_MWID_Msk

#define FMC_SDCR2_MWID

#define FMC_SDCR2_MWID_0

#define FMC_SDCR2_MWID_1

#define FMC_SDCR2_NB_Pos

#define FMC_SDCR2_NB_Msk

#define FMC_SDCR2_NB

#define FMC_SDCR2_CAS_Pos

#define FMC_SDCR2_CAS_Msk

#define FMC_SDCR2_CAS

#define FMC_SDCR2_CAS_0

#define FMC_SDCR2_CAS_1

#define FMC_SDCR2_WP_Pos

#define FMC_SDCR2_WP_Msk

#define FMC_SDCR2_WP

#define FMC_SDCR2_SDCLK_Pos

#define FMC_SDCR2_SDCLK_Msk

#define FMC_SDCR2_SDCLK

#define FMC_SDCR2_SDCLK_0

#define FMC_SDCR2_SDCLK_1

#define FMC_SDCR2_RBURST_Pos

#define FMC_SDCR2_RBURST_Msk

#define FMC_SDCR2_RBURST

#define FMC_SDCR2_RPIPE_Pos

#define FMC_SDCR2_RPIPE_Msk

#define FMC_SDCR2_RPIPE

#define FMC_SDCR2_RPIPE_0

#define FMC_SDCR2_RPIPE_1

Bit definition for FMC_SDTR1 register

#define FMC_SDTR1_TMRD_Pos

#define FMC_SDTR1_TMRD_Msk

#define FMC_SDTR1_TMRD

#define FMC_SDTR1_TMRD_0

#define FMC_SDTR1_TMRD_1

#define FMC_SDTR1_TMRD_2

#define FMC_SDTR1_TMRD_3

#define FMC_SDTR1_TXSR_Pos

#define FMC_SDTR1_TXSR_Msk

#define FMC_SDTR1_TXSR

#define FMC_SDTR1_TXSR_0

#define FMC_SDTR1_TXSR_1

#define FMC_SDTR1_TXSR_2

#define FMC_SDTR1_TXSR_3

#define FMC_SDTR1_TRAS_Pos

#define FMC_SDTR1_TRAS_Msk

#define FMC_SDTR1_TRAS

#define FMC_SDTR1_TRAS_0

#define FMC_SDTR1_TRAS_1

#define FMC_SDTR1_TRAS_2

#define FMC_SDTR1_TRAS_3

#define FMC_SDTR1_TRC_Pos

#define FMC_SDTR1_TRC_Msk

#define FMC_SDTR1_TRC

#define FMC_SDTR1_TRC_0

#define FMC_SDTR1_TRC_1

#define FMC_SDTR1_TRC_2

#define FMC_SDTR1_TWR_Pos

#define FMC_SDTR1_TWR_Msk

#define FMC_SDTR1_TWR

#define FMC_SDTR1_TWR_0

#define FMC_SDTR1_TWR_1

#define FMC_SDTR1_TWR_2

#define FMC_SDTR1_TRP_Pos

#define FMC_SDTR1_TRP_Msk

#define FMC_SDTR1_TRP

#define FMC_SDTR1_TRP_0

#define FMC_SDTR1_TRP_1

#define FMC_SDTR1_TRP_2

#define FMC_SDTR1_TRCD_Pos

#define FMC_SDTR1_TRCD_Msk

#define FMC_SDTR1_TRCD

#define FMC_SDTR1_TRCD_0

#define FMC_SDTR1_TRCD_1

#define FMC_SDTR1_TRCD_2

Bit definition for FMC_SDTR2 register

#define FMC_SDTR2_TMRD_Pos

#define FMC_SDTR2_TMRD_Msk

#define FMC_SDTR2_TMRD

#define FMC_SDTR2_TMRD_0

#define FMC_SDTR2_TMRD_1

#define FMC_SDTR2_TMRD_2

#define FMC_SDTR2_TMRD_3

#define FMC_SDTR2_TXSR_Pos

#define FMC_SDTR2_TXSR_Msk

#define FMC_SDTR2_TXSR

#define FMC_SDTR2_TXSR_0

#define FMC_SDTR2_TXSR_1

#define FMC_SDTR2_TXSR_2

#define FMC_SDTR2_TXSR_3

#define FMC_SDTR2_TRAS_Pos

#define FMC_SDTR2_TRAS_Msk

#define FMC_SDTR2_TRAS

#define FMC_SDTR2_TRAS_0

#define FMC_SDTR2_TRAS_1

#define FMC_SDTR2_TRAS_2

#define FMC_SDTR2_TRAS_3

#define FMC_SDTR2_TRC_Pos

#define FMC_SDTR2_TRC_Msk

#define FMC_SDTR2_TRC

#define FMC_SDTR2_TRC_0

#define FMC_SDTR2_TRC_1

#define FMC_SDTR2_TRC_2

#define FMC_SDTR2_TWR_Pos

#define FMC_SDTR2_TWR_Msk

#define FMC_SDTR2_TWR

#define FMC_SDTR2_TWR_0

#define FMC_SDTR2_TWR_1

#define FMC_SDTR2_TWR_2

#define FMC_SDTR2_TRP_Pos

#define FMC_SDTR2_TRP_Msk

#define FMC_SDTR2_TRP

#define FMC_SDTR2_TRP_0

#define FMC_SDTR2_TRP_1

#define FMC_SDTR2_TRP_2

#define FMC_SDTR2_TRCD_Pos

#define FMC_SDTR2_TRCD_Msk

#define FMC_SDTR2_TRCD

#define FMC_SDTR2_TRCD_0

#define FMC_SDTR2_TRCD_1

#define FMC_SDTR2_TRCD_2

Bit definition for FMC_SDCMR register

#define FMC_SDCMR_MODE_Pos

#define FMC_SDCMR_MODE_Msk

#define FMC_SDCMR_MODE

#define FMC_SDCMR_MODE_0

#define FMC_SDCMR_MODE_1

#define FMC_SDCMR_MODE_2

#define FMC_SDCMR_CTB2_Pos

#define FMC_SDCMR_CTB2_Msk

#define FMC_SDCMR_CTB2

#define FMC_SDCMR_CTB1_Pos

#define FMC_SDCMR_CTB1_Msk

#define FMC_SDCMR_CTB1

#define FMC_SDCMR_NRFS_Pos

#define FMC_SDCMR_NRFS_Msk

#define FMC_SDCMR_NRFS

#define FMC_SDCMR_NRFS_0

#define FMC_SDCMR_NRFS_1

#define FMC_SDCMR_NRFS_2

#define FMC_SDCMR_NRFS_3

#define FMC_SDCMR_MRD_Pos

#define FMC_SDCMR_MRD_Msk

#define FMC_SDCMR_MRD

Bit definition for FMC_SDRTR register

#define FMC_SDRTR_CRE_Pos

#define FMC_SDRTR_CRE_Msk

#define FMC_SDRTR_CRE

#define FMC_SDRTR_COUNT_Pos

#define FMC_SDRTR_COUNT_Msk

#define FMC_SDRTR_COUNT

#define FMC_SDRTR_REIE_Pos

#define FMC_SDRTR_REIE_Msk

#define FMC_SDRTR_REIE

Bit definition for FMC_SDSR register

#define FMC_SDSR_RE_Pos

#define FMC_SDSR_RE_Msk

#define FMC_SDSR_RE

#define FMC_SDSR_MODES1_Pos

#define FMC_SDSR_MODES1_Msk

#define FMC_SDSR_MODES1

#define FMC_SDSR_MODES1_0

#define FMC_SDSR_MODES1_1

#define FMC_SDSR_MODES2_Pos

#define FMC_SDSR_MODES2_Msk

#define FMC_SDSR_MODES2

#define FMC_SDSR_MODES2_0

#define FMC_SDSR_MODES2_1

#define FMC_SDSR_BUSY_Pos

#define FMC_SDSR_BUSY_Msk

#define FMC_SDSR_BUSY

...

Bits definition for GPIO_MODER register

#define GPIO_MODER_MODER0_Pos

#define GPIO_MODER_MODER0_Msk

#define GPIO_MODER_MODER0

#define GPIO_MODER_MODER0_0

#define GPIO_MODER_MODER0_1

#define GPIO_MODER_MODER1_Pos

#define GPIO_MODER_MODER1_Msk

#define GPIO_MODER_MODER1

#define GPIO_MODER_MODER1_0

#define GPIO_MODER_MODER1_1

#define GPIO_MODER_MODER2_Pos

#define GPIO_MODER_MODER2_Msk

#define GPIO_MODER_MODER2

#define GPIO_MODER_MODER2_0

#define GPIO_MODER_MODER2_1

#define GPIO_MODER_MODER3_Pos

#define GPIO_MODER_MODER3_Msk

#define GPIO_MODER_MODER3

#define GPIO_MODER_MODER3_0

#define GPIO_MODER_MODER3_1

#define GPIO_MODER_MODER4_Pos

#define GPIO_MODER_MODER4_Msk

#define GPIO_MODER_MODER4

#define GPIO_MODER_MODER4_0

#define GPIO_MODER_MODER4_1

#define GPIO_MODER_MODER5_Pos

#define GPIO_MODER_MODER5_Msk

#define GPIO_MODER_MODER5

#define GPIO_MODER_MODER5_0

#define GPIO_MODER_MODER5_1

#define GPIO_MODER_MODER6_Pos

#define GPIO_MODER_MODER6_Msk

#define GPIO_MODER_MODER6

#define GPIO_MODER_MODER6_0

#define GPIO_MODER_MODER6_1

#define GPIO_MODER_MODER7_Pos

#define GPIO_MODER_MODER7_Msk

#define GPIO_MODER_MODER7

#define GPIO_MODER_MODER7_0

#define GPIO_MODER_MODER7_1

#define GPIO_MODER_MODER8_Pos

#define GPIO_MODER_MODER8_Msk

#define GPIO_MODER_MODER8

#define GPIO_MODER_MODER8_0

#define GPIO_MODER_MODER8_1

#define GPIO_MODER_MODER9_Pos

#define GPIO_MODER_MODER9_Msk

#define GPIO_MODER_MODER9

#define GPIO_MODER_MODER9_0

#define GPIO_MODER_MODER9_1

#define GPIO_MODER_MODER10_Pos

#define GPIO_MODER_MODER10_Msk

#define GPIO_MODER_MODER10

#define GPIO_MODER_MODER10_0

#define GPIO_MODER_MODER10_1

#define GPIO_MODER_MODER11_Pos

#define GPIO_MODER_MODER11_Msk

#define GPIO_MODER_MODER11

#define GPIO_MODER_MODER11_0

#define GPIO_MODER_MODER11_1

#define GPIO_MODER_MODER12_Pos

#define GPIO_MODER_MODER12_Msk

#define GPIO_MODER_MODER12

#define GPIO_MODER_MODER12_0

#define GPIO_MODER_MODER12_1

#define GPIO_MODER_MODER13_Pos

#define GPIO_MODER_MODER13_Msk

#define GPIO_MODER_MODER13

#define GPIO_MODER_MODER13_0

#define GPIO_MODER_MODER13_1

#define GPIO_MODER_MODER14_Pos

#define GPIO_MODER_MODER14_Msk

#define GPIO_MODER_MODER14

#define GPIO_MODER_MODER14_0

#define GPIO_MODER_MODER14_1

#define GPIO_MODER_MODER15_Pos

#define GPIO_MODER_MODER15_Msk

#define GPIO_MODER_MODER15

#define GPIO_MODER_MODER15_0

#define GPIO_MODER_MODER15_1

#define GPIO_MODER_MODE0_Pos

#define GPIO_MODER_MODE0_Msk

#define GPIO_MODER_MODE0

#define GPIO_MODER_MODE0_0

#define GPIO_MODER_MODE0_1

#define GPIO_MODER_MODE1_Pos

#define GPIO_MODER_MODE1_Msk

#define GPIO_MODER_MODE1

#define GPIO_MODER_MODE1_0

#define GPIO_MODER_MODE1_1

#define GPIO_MODER_MODE2_Pos

#define GPIO_MODER_MODE2_Msk

#define GPIO_MODER_MODE2

#define GPIO_MODER_MODE2_0

#define GPIO_MODER_MODE2_1

#define GPIO_MODER_MODE3_Pos

#define GPIO_MODER_MODE3_Msk

#define GPIO_MODER_MODE3

#define GPIO_MODER_MODE3_0

#define GPIO_MODER_MODE3_1

#define GPIO_MODER_MODE4_Pos

#define GPIO_MODER_MODE4_Msk

#define GPIO_MODER_MODE4

#define GPIO_MODER_MODE4_0

#define GPIO_MODER_MODE4_1

#define GPIO_MODER_MODE5_Pos

#define GPIO_MODER_MODE5_Msk

#define GPIO_MODER_MODE5

#define GPIO_MODER_MODE5_0

#define GPIO_MODER_MODE5_1

#define GPIO_MODER_MODE6_Pos

#define GPIO_MODER_MODE6_Msk

#define GPIO_MODER_MODE6

#define GPIO_MODER_MODE6_0

#define GPIO_MODER_MODE6_1

#define GPIO_MODER_MODE7_Pos

#define GPIO_MODER_MODE7_Msk

#define GPIO_MODER_MODE7

#define GPIO_MODER_MODE7_0

#define GPIO_MODER_MODE7_1

#define GPIO_MODER_MODE8_Pos

#define GPIO_MODER_MODE8_Msk

#define GPIO_MODER_MODE8

#define GPIO_MODER_MODE8_0

#define GPIO_MODER_MODE8_1

#define GPIO_MODER_MODE9_Pos

#define GPIO_MODER_MODE9_Msk

#define GPIO_MODER_MODE9

#define GPIO_MODER_MODE9_0

#define GPIO_MODER_MODE9_1

#define GPIO_MODER_MODE10_Pos

#define GPIO_MODER_MODE10_Msk

#define GPIO_MODER_MODE10

#define GPIO_MODER_MODE10_0

#define GPIO_MODER_MODE10_1

#define GPIO_MODER_MODE11_Pos

#define GPIO_MODER_MODE11_Msk

#define GPIO_MODER_MODE11

#define GPIO_MODER_MODE11_0

#define GPIO_MODER_MODE11_1

#define GPIO_MODER_MODE12_Pos

#define GPIO_MODER_MODE12_Msk

#define GPIO_MODER_MODE12

#define GPIO_MODER_MODE12_0

#define GPIO_MODER_MODE12_1

#define GPIO_MODER_MODE13_Pos

#define GPIO_MODER_MODE13_Msk

#define GPIO_MODER_MODE13

#define GPIO_MODER_MODE13_0

#define GPIO_MODER_MODE13_1

#define GPIO_MODER_MODE14_Pos

#define GPIO_MODER_MODE14_Msk

#define GPIO_MODER_MODE14

#define GPIO_MODER_MODE14_0

#define GPIO_MODER_MODE14_1

#define GPIO_MODER_MODE15_Pos

#define GPIO_MODER_MODE15_Msk

#define GPIO_MODER_MODE15

#define GPIO_MODER_MODE15_0

#define GPIO_MODER_MODE15_1

Bits definition for GPIO_OTYPER register

#define GPIO_OTYPER_OT0_Pos

#define GPIO_OTYPER_OT0_Msk

#define GPIO_OTYPER_OT0

#define GPIO_OTYPER_OT1_Pos

#define GPIO_OTYPER_OT1_Msk

#define GPIO_OTYPER_OT1

#define GPIO_OTYPER_OT2_Pos

#define GPIO_OTYPER_OT2_Msk

#define GPIO_OTYPER_OT2

#define GPIO_OTYPER_OT3_Pos

#define GPIO_OTYPER_OT3_Msk

#define GPIO_OTYPER_OT3

#define GPIO_OTYPER_OT4_Pos

#define GPIO_OTYPER_OT4_Msk

#define GPIO_OTYPER_OT4

#define GPIO_OTYPER_OT5_Pos

#define GPIO_OTYPER_OT5_Msk

#define GPIO_OTYPER_OT5

#define GPIO_OTYPER_OT6_Pos

#define GPIO_OTYPER_OT6_Msk

#define GPIO_OTYPER_OT6

#define GPIO_OTYPER_OT7_Pos

#define GPIO_OTYPER_OT7_Msk

#define GPIO_OTYPER_OT7

#define GPIO_OTYPER_OT8_Pos

#define GPIO_OTYPER_OT8_Msk

#define GPIO_OTYPER_OT8

#define GPIO_OTYPER_OT9_Pos

#define GPIO_OTYPER_OT9_Msk

#define GPIO_OTYPER_OT9

#define GPIO_OTYPER_OT10_Pos

#define GPIO_OTYPER_OT10_Msk

#define GPIO_OTYPER_OT10

#define GPIO_OTYPER_OT11_Pos

#define GPIO_OTYPER_OT11_Msk

#define GPIO_OTYPER_OT11

#define GPIO_OTYPER_OT12_Pos

#define GPIO_OTYPER_OT12_Msk

#define GPIO_OTYPER_OT12

#define GPIO_OTYPER_OT13_Pos

#define GPIO_OTYPER_OT13_Msk

#define GPIO_OTYPER_OT13

#define GPIO_OTYPER_OT14_Pos

#define GPIO_OTYPER_OT14_Msk

#define GPIO_OTYPER_OT14

#define GPIO_OTYPER_OT15_Pos

#define GPIO_OTYPER_OT15_Msk

#define GPIO_OTYPER_OT15

#define GPIO_OTYPER_OT_0

#define GPIO_OTYPER_OT_1

#define GPIO_OTYPER_OT_2

#define GPIO_OTYPER_OT_3

#define GPIO_OTYPER_OT_4

#define GPIO_OTYPER_OT_5

#define GPIO_OTYPER_OT_6

#define GPIO_OTYPER_OT_7

#define GPIO_OTYPER_OT_8

#define GPIO_OTYPER_OT_9

#define GPIO_OTYPER_OT_10

#define GPIO_OTYPER_OT_11

#define GPIO_OTYPER_OT_12

#define GPIO_OTYPER_OT_13

#define GPIO_OTYPER_OT_14

#define GPIO_OTYPER_OT_15

Bits definition for GPIO_OSPEEDR register

#define GPIO_OSPEEDR_OSPEED0_Pos

#define GPIO_OSPEEDR_OSPEED0_Msk

#define GPIO_OSPEEDR_OSPEED0

#define GPIO_OSPEEDR_OSPEED0_0

#define GPIO_OSPEEDR_OSPEED0_1

#define GPIO_OSPEEDR_OSPEED1_Pos

#define GPIO_OSPEEDR_OSPEED1_Msk

#define GPIO_OSPEEDR_OSPEED1

#define GPIO_OSPEEDR_OSPEED1_0

#define GPIO_OSPEEDR_OSPEED1_1

#define GPIO_OSPEEDR_OSPEED2_Pos

#define GPIO_OSPEEDR_OSPEED2_Msk

#define GPIO_OSPEEDR_OSPEED2

#define GPIO_OSPEEDR_OSPEED2_0

#define GPIO_OSPEEDR_OSPEED2_1

#define GPIO_OSPEEDR_OSPEED3_Pos

#define GPIO_OSPEEDR_OSPEED3_Msk

#define GPIO_OSPEEDR_OSPEED3

#define GPIO_OSPEEDR_OSPEED3_0

#define GPIO_OSPEEDR_OSPEED3_1

#define GPIO_OSPEEDR_OSPEED4_Pos

#define GPIO_OSPEEDR_OSPEED4_Msk

#define GPIO_OSPEEDR_OSPEED4

#define GPIO_OSPEEDR_OSPEED4_0

#define GPIO_OSPEEDR_OSPEED4_1

#define GPIO_OSPEEDR_OSPEED5_Pos

#define GPIO_OSPEEDR_OSPEED5_Msk

#define GPIO_OSPEEDR_OSPEED5

#define GPIO_OSPEEDR_OSPEED5_0

#define GPIO_OSPEEDR_OSPEED5_1

#define GPIO_OSPEEDR_OSPEED6_Pos

#define GPIO_OSPEEDR_OSPEED6_Msk

#define GPIO_OSPEEDR_OSPEED6

#define GPIO_OSPEEDR_OSPEED6_0

#define GPIO_OSPEEDR_OSPEED6_1

#define GPIO_OSPEEDR_OSPEED7_Pos

#define GPIO_OSPEEDR_OSPEED7_Msk

#define GPIO_OSPEEDR_OSPEED7

#define GPIO_OSPEEDR_OSPEED7_0

#define GPIO_OSPEEDR_OSPEED7_1

#define GPIO_OSPEEDR_OSPEED8_Pos

#define GPIO_OSPEEDR_OSPEED8_Msk

#define GPIO_OSPEEDR_OSPEED8

#define GPIO_OSPEEDR_OSPEED8_0

#define GPIO_OSPEEDR_OSPEED8_1

#define GPIO_OSPEEDR_OSPEED9_Pos

#define GPIO_OSPEEDR_OSPEED9_Msk

#define GPIO_OSPEEDR_OSPEED9

#define GPIO_OSPEEDR_OSPEED9_0

#define GPIO_OSPEEDR_OSPEED9_1

#define GPIO_OSPEEDR_OSPEED10_Pos

#define GPIO_OSPEEDR_OSPEED10_Msk

#define GPIO_OSPEEDR_OSPEED10

#define GPIO_OSPEEDR_OSPEED10_0

#define GPIO_OSPEEDR_OSPEED10_1

#define GPIO_OSPEEDR_OSPEED11_Pos

#define GPIO_OSPEEDR_OSPEED11_Msk

#define GPIO_OSPEEDR_OSPEED11

#define GPIO_OSPEEDR_OSPEED11_0

#define GPIO_OSPEEDR_OSPEED11_1

#define GPIO_OSPEEDR_OSPEED12_Pos

#define GPIO_OSPEEDR_OSPEED12_Msk

#define GPIO_OSPEEDR_OSPEED12

#define GPIO_OSPEEDR_OSPEED12_0

#define GPIO_OSPEEDR_OSPEED12_1

#define GPIO_OSPEEDR_OSPEED13_Pos

#define GPIO_OSPEEDR_OSPEED13_Msk

#define GPIO_OSPEEDR_OSPEED13

#define GPIO_OSPEEDR_OSPEED13_0

#define GPIO_OSPEEDR_OSPEED13_1

#define GPIO_OSPEEDR_OSPEED14_Pos

#define GPIO_OSPEEDR_OSPEED14_Msk

#define GPIO_OSPEEDR_OSPEED14

#define GPIO_OSPEEDR_OSPEED14_0

#define GPIO_OSPEEDR_OSPEED14_1

#define GPIO_OSPEEDR_OSPEED15_Pos

#define GPIO_OSPEEDR_OSPEED15_Msk

#define GPIO_OSPEEDR_OSPEED15

#define GPIO_OSPEEDR_OSPEED15_0

#define GPIO_OSPEEDR_OSPEED15_1

#define GPIO_OSPEEDER_OSPEEDR0

#define GPIO_OSPEEDER_OSPEEDR0_0

#define GPIO_OSPEEDER_OSPEEDR0_1

#define GPIO_OSPEEDER_OSPEEDR1

#define GPIO_OSPEEDER_OSPEEDR1_0

#define GPIO_OSPEEDER_OSPEEDR1_1

#define GPIO_OSPEEDER_OSPEEDR2

#define GPIO_OSPEEDER_OSPEEDR2_0

#define GPIO_OSPEEDER_OSPEEDR2_1

#define GPIO_OSPEEDER_OSPEEDR3

#define GPIO_OSPEEDER_OSPEEDR3_0

#define GPIO_OSPEEDER_OSPEEDR3_1

#define GPIO_OSPEEDER_OSPEEDR4

#define GPIO_OSPEEDER_OSPEEDR4_0

#define GPIO_OSPEEDER_OSPEEDR4_1

#define GPIO_OSPEEDER_OSPEEDR5

#define GPIO_OSPEEDER_OSPEEDR5_0

#define GPIO_OSPEEDER_OSPEEDR5_1

#define GPIO_OSPEEDER_OSPEEDR6

#define GPIO_OSPEEDER_OSPEEDR6_0

#define GPIO_OSPEEDER_OSPEEDR6_1

#define GPIO_OSPEEDER_OSPEEDR7

#define GPIO_OSPEEDER_OSPEEDR7_0

#define GPIO_OSPEEDER_OSPEEDR7_1

#define GPIO_OSPEEDER_OSPEEDR8

#define GPIO_OSPEEDER_OSPEEDR8_0

#define GPIO_OSPEEDER_OSPEEDR8_1

#define GPIO_OSPEEDER_OSPEEDR9

#define GPIO_OSPEEDER_OSPEEDR9_0

#define GPIO_OSPEEDER_OSPEEDR9_1

#define GPIO_OSPEEDER_OSPEEDR10

#define GPIO_OSPEEDER_OSPEEDR10_0

#define GPIO_OSPEEDER_OSPEEDR10_1

#define GPIO_OSPEEDER_OSPEEDR11

#define GPIO_OSPEEDER_OSPEEDR11_0

#define GPIO_OSPEEDER_OSPEEDR11_1

#define GPIO_OSPEEDER_OSPEEDR12

#define GPIO_OSPEEDER_OSPEEDR12_0

#define GPIO_OSPEEDER_OSPEEDR12_1

#define GPIO_OSPEEDER_OSPEEDR13

#define GPIO_OSPEEDER_OSPEEDR13_0

#define GPIO_OSPEEDER_OSPEEDR13_1

#define GPIO_OSPEEDER_OSPEEDR14

#define GPIO_OSPEEDER_OSPEEDR14_0

#define GPIO_OSPEEDER_OSPEEDR14_1

#define GPIO_OSPEEDER_OSPEEDR15

#define GPIO_OSPEEDER_OSPEEDR15_0

#define GPIO_OSPEEDER_OSPEEDR15_1

Bits definition for GPIO_PUPDR register

#define GPIO_PUPDR_PUPD0_Pos

#define GPIO_PUPDR_PUPD0_Msk

#define GPIO_PUPDR_PUPD0

#define GPIO_PUPDR_PUPD0_0

#define GPIO_PUPDR_PUPD0_1

#define GPIO_PUPDR_PUPD1_Pos

#define GPIO_PUPDR_PUPD1_Msk

#define GPIO_PUPDR_PUPD1

#define GPIO_PUPDR_PUPD1_0

#define GPIO_PUPDR_PUPD1_1

#define GPIO_PUPDR_PUPD2_Pos

#define GPIO_PUPDR_PUPD2_Msk

#define GPIO_PUPDR_PUPD2

#define GPIO_PUPDR_PUPD2_0

#define GPIO_PUPDR_PUPD2_1

#define GPIO_PUPDR_PUPD3_Pos

#define GPIO_PUPDR_PUPD3_Msk

#define GPIO_PUPDR_PUPD3

#define GPIO_PUPDR_PUPD3_0

#define GPIO_PUPDR_PUPD3_1

#define GPIO_PUPDR_PUPD4_Pos

#define GPIO_PUPDR_PUPD4_Msk

#define GPIO_PUPDR_PUPD4

#define GPIO_PUPDR_PUPD4_0

#define GPIO_PUPDR_PUPD4_1

#define GPIO_PUPDR_PUPD5_Pos

#define GPIO_PUPDR_PUPD5_Msk

#define GPIO_PUPDR_PUPD5

#define GPIO_PUPDR_PUPD5_0

#define GPIO_PUPDR_PUPD5_1

#define GPIO_PUPDR_PUPD6_Pos

#define GPIO_PUPDR_PUPD6_Msk

#define GPIO_PUPDR_PUPD6

#define GPIO_PUPDR_PUPD6_0

#define GPIO_PUPDR_PUPD6_1

#define GPIO_PUPDR_PUPD7_Pos

#define GPIO_PUPDR_PUPD7_Msk

#define GPIO_PUPDR_PUPD7

#define GPIO_PUPDR_PUPD7_0

#define GPIO_PUPDR_PUPD7_1

#define GPIO_PUPDR_PUPD8_Pos

#define GPIO_PUPDR_PUPD8_Msk

#define GPIO_PUPDR_PUPD8

#define GPIO_PUPDR_PUPD8_0

#define GPIO_PUPDR_PUPD8_1

#define GPIO_PUPDR_PUPD9_Pos

#define GPIO_PUPDR_PUPD9_Msk

#define GPIO_PUPDR_PUPD9

#define GPIO_PUPDR_PUPD9_0

#define GPIO_PUPDR_PUPD9_1

#define GPIO_PUPDR_PUPD10_Pos

#define GPIO_PUPDR_PUPD10_Msk

#define GPIO_PUPDR_PUPD10

#define GPIO_PUPDR_PUPD10_0

#define GPIO_PUPDR_PUPD10_1

#define GPIO_PUPDR_PUPD11_Pos

#define GPIO_PUPDR_PUPD11_Msk

#define GPIO_PUPDR_PUPD11

#define GPIO_PUPDR_PUPD11_0

#define GPIO_PUPDR_PUPD11_1

#define GPIO_PUPDR_PUPD12_Pos

#define GPIO_PUPDR_PUPD12_Msk

#define GPIO_PUPDR_PUPD12

#define GPIO_PUPDR_PUPD12_0

#define GPIO_PUPDR_PUPD12_1

#define GPIO_PUPDR_PUPD13_Pos

#define GPIO_PUPDR_PUPD13_Msk

#define GPIO_PUPDR_PUPD13

#define GPIO_PUPDR_PUPD13_0

#define GPIO_PUPDR_PUPD13_1

#define GPIO_PUPDR_PUPD14_Pos

#define GPIO_PUPDR_PUPD14_Msk

#define GPIO_PUPDR_PUPD14

#define GPIO_PUPDR_PUPD14_0

#define GPIO_PUPDR_PUPD14_1

#define GPIO_PUPDR_PUPD15_Pos

#define GPIO_PUPDR_PUPD15_Msk

#define GPIO_PUPDR_PUPD15

#define GPIO_PUPDR_PUPD15_0

#define GPIO_PUPDR_PUPD15_1

#define GPIO_PUPDR_PUPDR0

#define GPIO_PUPDR_PUPDR0_0

#define GPIO_PUPDR_PUPDR0_1

#define GPIO_PUPDR_PUPDR1

#define GPIO_PUPDR_PUPDR1_0

#define GPIO_PUPDR_PUPDR1_1

#define GPIO_PUPDR_PUPDR2

#define GPIO_PUPDR_PUPDR2_0

#define GPIO_PUPDR_PUPDR2_1

#define GPIO_PUPDR_PUPDR3

#define GPIO_PUPDR_PUPDR3_0

#define GPIO_PUPDR_PUPDR3_1

#define GPIO_PUPDR_PUPDR4

#define GPIO_PUPDR_PUPDR4_0

#define GPIO_PUPDR_PUPDR4_1

#define GPIO_PUPDR_PUPDR5

#define GPIO_PUPDR_PUPDR5_0

#define GPIO_PUPDR_PUPDR5_1

#define GPIO_PUPDR_PUPDR6

#define GPIO_PUPDR_PUPDR6_0

#define GPIO_PUPDR_PUPDR6_1

#define GPIO_PUPDR_PUPDR7

#define GPIO_PUPDR_PUPDR7_0

#define GPIO_PUPDR_PUPDR7_1

#define GPIO_PUPDR_PUPDR8

#define GPIO_PUPDR_PUPDR8_0

#define GPIO_PUPDR_PUPDR8_1

#define GPIO_PUPDR_PUPDR9

#define GPIO_PUPDR_PUPDR9_0

#define GPIO_PUPDR_PUPDR9_1

#define GPIO_PUPDR_PUPDR10

#define GPIO_PUPDR_PUPDR10_0

#define GPIO_PUPDR_PUPDR10_1

#define GPIO_PUPDR_PUPDR11

#define GPIO_PUPDR_PUPDR11_0

#define GPIO_PUPDR_PUPDR11_1

#define GPIO_PUPDR_PUPDR12

#define GPIO_PUPDR_PUPDR12_0

#define GPIO_PUPDR_PUPDR12_1

#define GPIO_PUPDR_PUPDR13

#define GPIO_PUPDR_PUPDR13_0

#define GPIO_PUPDR_PUPDR13_1

#define GPIO_PUPDR_PUPDR14

#define GPIO_PUPDR_PUPDR14_0

#define GPIO_PUPDR_PUPDR14_1

#define GPIO_PUPDR_PUPDR15

#define GPIO_PUPDR_PUPDR15_0

#define GPIO_PUPDR_PUPDR15_1

Bits definition for GPIO_IDR register

#define GPIO_IDR_ID0_Pos

#define GPIO_IDR_ID0_Msk

#define GPIO_IDR_ID0

#define GPIO_IDR_ID1_Pos

#define GPIO_IDR_ID1_Msk

#define GPIO_IDR_ID1

#define GPIO_IDR_ID2_Pos

#define GPIO_IDR_ID2_Msk

#define GPIO_IDR_ID2

#define GPIO_IDR_ID3_Pos

#define GPIO_IDR_ID3_Msk

#define GPIO_IDR_ID3

#define GPIO_IDR_ID4_Pos

#define GPIO_IDR_ID4_Msk

#define GPIO_IDR_ID4

#define GPIO_IDR_ID5_Pos

#define GPIO_IDR_ID5_Msk

#define GPIO_IDR_ID5

#define GPIO_IDR_ID6_Pos

#define GPIO_IDR_ID6_Msk

#define GPIO_IDR_ID6

#define GPIO_IDR_ID7_Pos

#define GPIO_IDR_ID7_Msk

#define GPIO_IDR_ID7

#define GPIO_IDR_ID8_Pos

#define GPIO_IDR_ID8_Msk

#define GPIO_IDR_ID8

#define GPIO_IDR_ID9_Pos

#define GPIO_IDR_ID9_Msk

#define GPIO_IDR_ID9

#define GPIO_IDR_ID10_Pos

#define GPIO_IDR_ID10_Msk

#define GPIO_IDR_ID10

#define GPIO_IDR_ID11_Pos

#define GPIO_IDR_ID11_Msk

#define GPIO_IDR_ID11

#define GPIO_IDR_ID12_Pos

#define GPIO_IDR_ID12_Msk

#define GPIO_IDR_ID12

#define GPIO_IDR_ID13_Pos

#define GPIO_IDR_ID13_Msk

#define GPIO_IDR_ID13

#define GPIO_IDR_ID14_Pos

#define GPIO_IDR_ID14_Msk

#define GPIO_IDR_ID14

#define GPIO_IDR_ID15_Pos

#define GPIO_IDR_ID15_Msk

#define GPIO_IDR_ID15

#define GPIO_IDR_IDR_0

#define GPIO_IDR_IDR_1

#define GPIO_IDR_IDR_2

#define GPIO_IDR_IDR_3

#define GPIO_IDR_IDR_4

#define GPIO_IDR_IDR_5

#define GPIO_IDR_IDR_6

#define GPIO_IDR_IDR_7

#define GPIO_IDR_IDR_8

#define GPIO_IDR_IDR_9

#define GPIO_IDR_IDR_10

#define GPIO_IDR_IDR_11

#define GPIO_IDR_IDR_12

#define GPIO_IDR_IDR_13

#define GPIO_IDR_IDR_14

#define GPIO_IDR_IDR_15

Bits definition for GPIO_ODR register

#define GPIO_ODR_OD0_Pos

#define GPIO_ODR_OD0_Msk

#define GPIO_ODR_OD0

#define GPIO_ODR_OD1_Pos

#define GPIO_ODR_OD1_Msk

#define GPIO_ODR_OD1

#define GPIO_ODR_OD2_Pos

#define GPIO_ODR_OD2_Msk

#define GPIO_ODR_OD2

#define GPIO_ODR_OD3_Pos

#define GPIO_ODR_OD3_Msk

#define GPIO_ODR_OD3

#define GPIO_ODR_OD4_Pos

#define GPIO_ODR_OD4_Msk

#define GPIO_ODR_OD4

#define GPIO_ODR_OD5_Pos

#define GPIO_ODR_OD5_Msk

#define GPIO_ODR_OD5

#define GPIO_ODR_OD6_Pos

#define GPIO_ODR_OD6_Msk

#define GPIO_ODR_OD6

#define GPIO_ODR_OD7_Pos

#define GPIO_ODR_OD7_Msk

#define GPIO_ODR_OD7

#define GPIO_ODR_OD8_Pos

#define GPIO_ODR_OD8_Msk

#define GPIO_ODR_OD8

#define GPIO_ODR_OD9_Pos

#define GPIO_ODR_OD9_Msk

#define GPIO_ODR_OD9

#define GPIO_ODR_OD10_Pos

#define GPIO_ODR_OD10_Msk

#define GPIO_ODR_OD10

#define GPIO_ODR_OD11_Pos

#define GPIO_ODR_OD11_Msk

#define GPIO_ODR_OD11

#define GPIO_ODR_OD12_Pos

#define GPIO_ODR_OD12_Msk

#define GPIO_ODR_OD12

#define GPIO_ODR_OD13_Pos

#define GPIO_ODR_OD13_Msk

#define GPIO_ODR_OD13

#define GPIO_ODR_OD14_Pos

#define GPIO_ODR_OD14_Msk

#define GPIO_ODR_OD14

#define GPIO_ODR_OD15_Pos

#define GPIO_ODR_OD15_Msk

#define GPIO_ODR_OD15

#define GPIO_ODR_ODR_0

#define GPIO_ODR_ODR_1

#define GPIO_ODR_ODR_2

#define GPIO_ODR_ODR_3

#define GPIO_ODR_ODR_4

#define GPIO_ODR_ODR_5

#define GPIO_ODR_ODR_6

#define GPIO_ODR_ODR_7

#define GPIO_ODR_ODR_8

#define GPIO_ODR_ODR_9

#define GPIO_ODR_ODR_10

#define GPIO_ODR_ODR_11

#define GPIO_ODR_ODR_12

#define GPIO_ODR_ODR_13

#define GPIO_ODR_ODR_14

#define GPIO_ODR_ODR_15

Bits definition for GPIO_BSRR register

#define GPIO_BSRR_BS0_Pos

#define GPIO_BSRR_BS0_Msk

#define GPIO_BSRR_BS0

#define GPIO_BSRR_BS1_Pos

#define GPIO_BSRR_BS1_Msk

#define GPIO_BSRR_BS1

#define GPIO_BSRR_BS2_Pos

#define GPIO_BSRR_BS2_Msk

#define GPIO_BSRR_BS2

#define GPIO_BSRR_BS3_Pos

#define GPIO_BSRR_BS3_Msk

#define GPIO_BSRR_BS3

#define GPIO_BSRR_BS4_Pos

#define GPIO_BSRR_BS4_Msk

#define GPIO_BSRR_BS4

#define GPIO_BSRR_BS5_Pos

#define GPIO_BSRR_BS5_Msk

#define GPIO_BSRR_BS5

#define GPIO_BSRR_BS6_Pos

#define GPIO_BSRR_BS6_Msk

#define GPIO_BSRR_BS6

#define GPIO_BSRR_BS7_Pos

#define GPIO_BSRR_BS7_Msk

#define GPIO_BSRR_BS7

#define GPIO_BSRR_BS8_Pos

#define GPIO_BSRR_BS8_Msk

#define GPIO_BSRR_BS8

#define GPIO_BSRR_BS9_Pos

#define GPIO_BSRR_BS9_Msk

#define GPIO_BSRR_BS9

#define GPIO_BSRR_BS10_Pos

#define GPIO_BSRR_BS10_Msk

#define GPIO_BSRR_BS10

#define GPIO_BSRR_BS11_Pos

#define GPIO_BSRR_BS11_Msk

#define GPIO_BSRR_BS11

#define GPIO_BSRR_BS12_Pos

#define GPIO_BSRR_BS12_Msk

#define GPIO_BSRR_BS12

#define GPIO_BSRR_BS13_Pos

#define GPIO_BSRR_BS13_Msk

#define GPIO_BSRR_BS13

#define GPIO_BSRR_BS14_Pos

#define GPIO_BSRR_BS14_Msk

#define GPIO_BSRR_BS14

#define GPIO_BSRR_BS15_Pos

#define GPIO_BSRR_BS15_Msk

#define GPIO_BSRR_BS15

#define GPIO_BSRR_BR0_Pos

#define GPIO_BSRR_BR0_Msk

#define GPIO_BSRR_BR0

#define GPIO_BSRR_BR1_Pos

#define GPIO_BSRR_BR1_Msk

#define GPIO_BSRR_BR1

#define GPIO_BSRR_BR2_Pos

#define GPIO_BSRR_BR2_Msk

#define GPIO_BSRR_BR2

#define GPIO_BSRR_BR3_Pos

#define GPIO_BSRR_BR3_Msk

#define GPIO_BSRR_BR3

#define GPIO_BSRR_BR4_Pos

#define GPIO_BSRR_BR4_Msk

#define GPIO_BSRR_BR4

#define GPIO_BSRR_BR5_Pos

#define GPIO_BSRR_BR5_Msk

#define GPIO_BSRR_BR5

#define GPIO_BSRR_BR6_Pos

#define GPIO_BSRR_BR6_Msk

#define GPIO_BSRR_BR6

#define GPIO_BSRR_BR7_Pos

#define GPIO_BSRR_BR7_Msk

#define GPIO_BSRR_BR7

#define GPIO_BSRR_BR8_Pos

#define GPIO_BSRR_BR8_Msk

#define GPIO_BSRR_BR8

#define GPIO_BSRR_BR9_Pos

#define GPIO_BSRR_BR9_Msk

#define GPIO_BSRR_BR9

#define GPIO_BSRR_BR10_Pos

#define GPIO_BSRR_BR10_Msk

#define GPIO_BSRR_BR10

#define GPIO_BSRR_BR11_Pos

#define GPIO_BSRR_BR11_Msk

#define GPIO_BSRR_BR11

#define GPIO_BSRR_BR12_Pos

#define GPIO_BSRR_BR12_Msk

#define GPIO_BSRR_BR12

#define GPIO_BSRR_BR13_Pos

#define GPIO_BSRR_BR13_Msk

#define GPIO_BSRR_BR13

#define GPIO_BSRR_BR14_Pos

#define GPIO_BSRR_BR14_Msk

#define GPIO_BSRR_BR14

#define GPIO_BSRR_BR15_Pos

#define GPIO_BSRR_BR15_Msk

#define GPIO_BSRR_BR15

#define GPIO_BSRR_BS_0

#define GPIO_BSRR_BS_1

#define GPIO_BSRR_BS_2

#define GPIO_BSRR_BS_3

#define GPIO_BSRR_BS_4

#define GPIO_BSRR_BS_5

#define GPIO_BSRR_BS_6

#define GPIO_BSRR_BS_7

#define GPIO_BSRR_BS_8

#define GPIO_BSRR_BS_9

#define GPIO_BSRR_BS_10

#define GPIO_BSRR_BS_11

#define GPIO_BSRR_BS_12

#define GPIO_BSRR_BS_13

#define GPIO_BSRR_BS_14

#define GPIO_BSRR_BS_15

#define GPIO_BSRR_BR_0

#define GPIO_BSRR_BR_1

#define GPIO_BSRR_BR_2

#define GPIO_BSRR_BR_3

#define GPIO_BSRR_BR_4

#define GPIO_BSRR_BR_5

#define GPIO_BSRR_BR_6

#define GPIO_BSRR_BR_7

#define GPIO_BSRR_BR_8

#define GPIO_BSRR_BR_9

#define GPIO_BSRR_BR_10

#define GPIO_BSRR_BR_11

#define GPIO_BSRR_BR_12

#define GPIO_BSRR_BR_13

#define GPIO_BSRR_BR_14

#define GPIO_BSRR_BR_15

#define GPIO_BRR_BR0

#define GPIO_BRR_BR0_Pos

#define GPIO_BRR_BR0_Msk

#define GPIO_BRR_BR1

#define GPIO_BRR_BR1_Pos

#define GPIO_BRR_BR1_Msk

#define GPIO_BRR_BR2

#define GPIO_BRR_BR2_Pos

#define GPIO_BRR_BR2_Msk

#define GPIO_BRR_BR3

#define GPIO_BRR_BR3_Pos

#define GPIO_BRR_BR3_Msk

#define GPIO_BRR_BR4

#define GPIO_BRR_BR4_Pos

#define GPIO_BRR_BR4_Msk

#define GPIO_BRR_BR5

#define GPIO_BRR_BR5_Pos

#define GPIO_BRR_BR5_Msk

#define GPIO_BRR_BR6

#define GPIO_BRR_BR6_Pos

#define GPIO_BRR_BR6_Msk

#define GPIO_BRR_BR7

#define GPIO_BRR_BR7_Pos

#define GPIO_BRR_BR7_Msk

#define GPIO_BRR_BR8

#define GPIO_BRR_BR8_Pos

#define GPIO_BRR_BR8_Msk

#define GPIO_BRR_BR9

#define GPIO_BRR_BR9_Pos

#define GPIO_BRR_BR9_Msk

#define GPIO_BRR_BR10

#define GPIO_BRR_BR10_Pos

#define GPIO_BRR_BR10_Msk

#define GPIO_BRR_BR11

#define GPIO_BRR_BR11_Pos

#define GPIO_BRR_BR11_Msk

#define GPIO_BRR_BR12

#define GPIO_BRR_BR12_Pos

#define GPIO_BRR_BR12_Msk

#define GPIO_BRR_BR13

#define GPIO_BRR_BR13_Pos

#define GPIO_BRR_BR13_Msk

#define GPIO_BRR_BR14

#define GPIO_BRR_BR14_Pos

#define GPIO_BRR_BR14_Msk

#define GPIO_BRR_BR15

#define GPIO_BRR_BR15_Pos

#define GPIO_BRR_BR15_Msk

Bit definition for GPIO_LCKR register

#define GPIO_LCKR_LCK0_Pos

#define GPIO_LCKR_LCK0_Msk

#define GPIO_LCKR_LCK0

#define GPIO_LCKR_LCK1_Pos

#define GPIO_LCKR_LCK1_Msk

#define GPIO_LCKR_LCK1

#define GPIO_LCKR_LCK2_Pos

#define GPIO_LCKR_LCK2_Msk

#define GPIO_LCKR_LCK2

#define GPIO_LCKR_LCK3_Pos

#define GPIO_LCKR_LCK3_Msk

#define GPIO_LCKR_LCK3

#define GPIO_LCKR_LCK4_Pos

#define GPIO_LCKR_LCK4_Msk

#define GPIO_LCKR_LCK4

#define GPIO_LCKR_LCK5_Pos

#define GPIO_LCKR_LCK5_Msk

#define GPIO_LCKR_LCK5

#define GPIO_LCKR_LCK6_Pos

#define GPIO_LCKR_LCK6_Msk

#define GPIO_LCKR_LCK6

#define GPIO_LCKR_LCK7_Pos

#define GPIO_LCKR_LCK7_Msk

#define GPIO_LCKR_LCK7

#define GPIO_LCKR_LCK8_Pos

#define GPIO_LCKR_LCK8_Msk

#define GPIO_LCKR_LCK8

#define GPIO_LCKR_LCK9_Pos

#define GPIO_LCKR_LCK9_Msk

#define GPIO_LCKR_LCK9

#define GPIO_LCKR_LCK10_Pos

#define GPIO_LCKR_LCK10_Msk

#define GPIO_LCKR_LCK10

#define GPIO_LCKR_LCK11_Pos

#define GPIO_LCKR_LCK11_Msk

#define GPIO_LCKR_LCK11

#define GPIO_LCKR_LCK12_Pos

#define GPIO_LCKR_LCK12_Msk

#define GPIO_LCKR_LCK12

#define GPIO_LCKR_LCK13_Pos

#define GPIO_LCKR_LCK13_Msk

#define GPIO_LCKR_LCK13

#define GPIO_LCKR_LCK14_Pos

#define GPIO_LCKR_LCK14_Msk

#define GPIO_LCKR_LCK14

#define GPIO_LCKR_LCK15_Pos

#define GPIO_LCKR_LCK15_Msk

#define GPIO_LCKR_LCK15

#define GPIO_LCKR_LCKK_Pos

#define GPIO_LCKR_LCKK_Msk

#define GPIO_LCKR_LCKK

Bit definition for GPIO_AFRL register

#define GPIO_AFRL_AFSEL0_Pos

#define GPIO_AFRL_AFSEL0_Msk

#define GPIO_AFRL_AFSEL0

#define GPIO_AFRL_AFSEL0_0

#define GPIO_AFRL_AFSEL0_1

#define GPIO_AFRL_AFSEL0_2

#define GPIO_AFRL_AFSEL0_3

#define GPIO_AFRL_AFSEL1_Pos

#define GPIO_AFRL_AFSEL1_Msk

#define GPIO_AFRL_AFSEL1

#define GPIO_AFRL_AFSEL1_0

#define GPIO_AFRL_AFSEL1_1

#define GPIO_AFRL_AFSEL1_2

#define GPIO_AFRL_AFSEL1_3

#define GPIO_AFRL_AFSEL2_Pos

#define GPIO_AFRL_AFSEL2_Msk

#define GPIO_AFRL_AFSEL2

#define GPIO_AFRL_AFSEL2_0

#define GPIO_AFRL_AFSEL2_1

#define GPIO_AFRL_AFSEL2_2

#define GPIO_AFRL_AFSEL2_3

#define GPIO_AFRL_AFSEL3_Pos

#define GPIO_AFRL_AFSEL3_Msk

#define GPIO_AFRL_AFSEL3

#define GPIO_AFRL_AFSEL3_0

#define GPIO_AFRL_AFSEL3_1

#define GPIO_AFRL_AFSEL3_2

#define GPIO_AFRL_AFSEL3_3

#define GPIO_AFRL_AFSEL4_Pos

#define GPIO_AFRL_AFSEL4_Msk

#define GPIO_AFRL_AFSEL4

#define GPIO_AFRL_AFSEL4_0

#define GPIO_AFRL_AFSEL4_1

#define GPIO_AFRL_AFSEL4_2

#define GPIO_AFRL_AFSEL4_3

#define GPIO_AFRL_AFSEL5_Pos

#define GPIO_AFRL_AFSEL5_Msk

#define GPIO_AFRL_AFSEL5

#define GPIO_AFRL_AFSEL5_0

#define GPIO_AFRL_AFSEL5_1

#define GPIO_AFRL_AFSEL5_2

#define GPIO_AFRL_AFSEL5_3

#define GPIO_AFRL_AFSEL6_Pos

#define GPIO_AFRL_AFSEL6_Msk

#define GPIO_AFRL_AFSEL6

#define GPIO_AFRL_AFSEL6_0

#define GPIO_AFRL_AFSEL6_1

#define GPIO_AFRL_AFSEL6_2

#define GPIO_AFRL_AFSEL6_3

#define GPIO_AFRL_AFSEL7_Pos

#define GPIO_AFRL_AFSEL7_Msk

#define GPIO_AFRL_AFSEL7

#define GPIO_AFRL_AFSEL7_0

#define GPIO_AFRL_AFSEL7_1

#define GPIO_AFRL_AFSEL7_2

#define GPIO_AFRL_AFSEL7_3

#define GPIO_AFRL_AFRL0

#define GPIO_AFRL_AFRL0_0

#define GPIO_AFRL_AFRL0_1

#define GPIO_AFRL_AFRL0_2

#define GPIO_AFRL_AFRL0_3

#define GPIO_AFRL_AFRL1

#define GPIO_AFRL_AFRL1_0

#define GPIO_AFRL_AFRL1_1

#define GPIO_AFRL_AFRL1_2

#define GPIO_AFRL_AFRL1_3

#define GPIO_AFRL_AFRL2

#define GPIO_AFRL_AFRL2_0

#define GPIO_AFRL_AFRL2_1

#define GPIO_AFRL_AFRL2_2

#define GPIO_AFRL_AFRL2_3

#define GPIO_AFRL_AFRL3

#define GPIO_AFRL_AFRL3_0

#define GPIO_AFRL_AFRL3_1

#define GPIO_AFRL_AFRL3_2

#define GPIO_AFRL_AFRL3_3

#define GPIO_AFRL_AFRL4

#define GPIO_AFRL_AFRL4_0

#define GPIO_AFRL_AFRL4_1

#define GPIO_AFRL_AFRL4_2

#define GPIO_AFRL_AFRL4_3

#define GPIO_AFRL_AFRL5

#define GPIO_AFRL_AFRL5_0

#define GPIO_AFRL_AFRL5_1

#define GPIO_AFRL_AFRL5_2

#define GPIO_AFRL_AFRL5_3

#define GPIO_AFRL_AFRL6

#define GPIO_AFRL_AFRL6_0

#define GPIO_AFRL_AFRL6_1

#define GPIO_AFRL_AFRL6_2

#define GPIO_AFRL_AFRL6_3

#define GPIO_AFRL_AFRL7

#define GPIO_AFRL_AFRL7_0

#define GPIO_AFRL_AFRL7_1

#define GPIO_AFRL_AFRL7_2

#define GPIO_AFRL_AFRL7_3

Bit definition for GPIO_AFRH register

#define GPIO_AFRH_AFSEL8_Pos

#define GPIO_AFRH_AFSEL8_Msk

#define GPIO_AFRH_AFSEL8

#define GPIO_AFRH_AFSEL8_0

#define GPIO_AFRH_AFSEL8_1

#define GPIO_AFRH_AFSEL8_2

#define GPIO_AFRH_AFSEL8_3

#define GPIO_AFRH_AFSEL9_Pos

#define GPIO_AFRH_AFSEL9_Msk

#define GPIO_AFRH_AFSEL9

#define GPIO_AFRH_AFSEL9_0

#define GPIO_AFRH_AFSEL9_1

#define GPIO_AFRH_AFSEL9_2

#define GPIO_AFRH_AFSEL9_3

#define GPIO_AFRH_AFSEL10_Pos

#define GPIO_AFRH_AFSEL10_Msk

#define GPIO_AFRH_AFSEL10

#define GPIO_AFRH_AFSEL10_0

#define GPIO_AFRH_AFSEL10_1

#define GPIO_AFRH_AFSEL10_2

#define GPIO_AFRH_AFSEL10_3

#define GPIO_AFRH_AFSEL11_Pos

#define GPIO_AFRH_AFSEL11_Msk

#define GPIO_AFRH_AFSEL11

#define GPIO_AFRH_AFSEL11_0

#define GPIO_AFRH_AFSEL11_1

#define GPIO_AFRH_AFSEL11_2

#define GPIO_AFRH_AFSEL11_3

#define GPIO_AFRH_AFSEL12_Pos

#define GPIO_AFRH_AFSEL12_Msk

#define GPIO_AFRH_AFSEL12

#define GPIO_AFRH_AFSEL12_0

#define GPIO_AFRH_AFSEL12_1

#define GPIO_AFRH_AFSEL12_2

#define GPIO_AFRH_AFSEL12_3

#define GPIO_AFRH_AFSEL13_Pos

#define GPIO_AFRH_AFSEL13_Msk

#define GPIO_AFRH_AFSEL13

#define GPIO_AFRH_AFSEL13_0

#define GPIO_AFRH_AFSEL13_1

#define GPIO_AFRH_AFSEL13_2

#define GPIO_AFRH_AFSEL13_3

#define GPIO_AFRH_AFSEL14_Pos

#define GPIO_AFRH_AFSEL14_Msk

#define GPIO_AFRH_AFSEL14

#define GPIO_AFRH_AFSEL14_0

#define GPIO_AFRH_AFSEL14_1

#define GPIO_AFRH_AFSEL14_2

#define GPIO_AFRH_AFSEL14_3

#define GPIO_AFRH_AFSEL15_Pos

#define GPIO_AFRH_AFSEL15_Msk

#define GPIO_AFRH_AFSEL15

#define GPIO_AFRH_AFSEL15_0

#define GPIO_AFRH_AFSEL15_1

#define GPIO_AFRH_AFSEL15_2

#define GPIO_AFRH_AFSEL15_3

#define GPIO_AFRH_AFRH0

#define GPIO_AFRH_AFRH0_0

#define GPIO_AFRH_AFRH0_1

#define GPIO_AFRH_AFRH0_2

#define GPIO_AFRH_AFRH0_3

#define GPIO_AFRH_AFRH1

#define GPIO_AFRH_AFRH1_0

#define GPIO_AFRH_AFRH1_1

#define GPIO_AFRH_AFRH1_2

#define GPIO_AFRH_AFRH1_3

#define GPIO_AFRH_AFRH2

#define GPIO_AFRH_AFRH2_0

#define GPIO_AFRH_AFRH2_1

#define GPIO_AFRH_AFRH2_2

#define GPIO_AFRH_AFRH2_3

#define GPIO_AFRH_AFRH3

#define GPIO_AFRH_AFRH3_0

#define GPIO_AFRH_AFRH3_1

#define GPIO_AFRH_AFRH3_2

#define GPIO_AFRH_AFRH3_3

#define GPIO_AFRH_AFRH4

#define GPIO_AFRH_AFRH4_0

#define GPIO_AFRH_AFRH4_1

#define GPIO_AFRH_AFRH4_2

#define GPIO_AFRH_AFRH4_3

#define GPIO_AFRH_AFRH5

#define GPIO_AFRH_AFRH5_0

#define GPIO_AFRH_AFRH5_1

#define GPIO_AFRH_AFRH5_2

#define GPIO_AFRH_AFRH5_3

#define GPIO_AFRH_AFRH6

#define GPIO_AFRH_AFRH6_0

#define GPIO_AFRH_AFRH6_1

#define GPIO_AFRH_AFRH6_2

#define GPIO_AFRH_AFRH6_3

#define GPIO_AFRH_AFRH7

#define GPIO_AFRH_AFRH7_0

#define GPIO_AFRH_AFRH7_1

#define GPIO_AFRH_AFRH7_2

#define GPIO_AFRH_AFRH7_3

...

Bit definition for I2C_CR1 register

#define I2C_CR1_PE_Pos

#define I2C_CR1_PE_Msk

#define I2C_CR1_PE

#define I2C_CR1_SMBUS_Pos

#define I2C_CR1_SMBUS_Msk

#define I2C_CR1_SMBUS

#define I2C_CR1_SMBTYPE_Pos

#define I2C_CR1_SMBTYPE_Msk

#define I2C_CR1_SMBTYPE

#define I2C_CR1_ENARP_Pos

#define I2C_CR1_ENARP_Msk

#define I2C_CR1_ENARP

#define I2C_CR1_ENPEC_Pos

#define I2C_CR1_ENPEC_Msk

#define I2C_CR1_ENPEC

#define I2C_CR1_ENGC_Pos

#define I2C_CR1_ENGC_Msk

#define I2C_CR1_ENGC

#define I2C_CR1_NOSTRETCH_Pos

#define I2C_CR1_NOSTRETCH_Msk

#define I2C_CR1_NOSTRETCH

#define I2C_CR1_START_Pos

#define I2C_CR1_START_Msk

#define I2C_CR1_START

#define I2C_CR1_STOP_Pos

#define I2C_CR1_STOP_Msk

#define I2C_CR1_STOP

#define I2C_CR1_ACK_Pos

#define I2C_CR1_ACK_Msk

#define I2C_CR1_ACK

#define I2C_CR1_POS_Pos

#define I2C_CR1_POS_Msk

#define I2C_CR1_POS

#define I2C_CR1_PEC_Pos

#define I2C_CR1_PEC_Msk

#define I2C_CR1_PEC

#define I2C_CR1_ALERT_Pos

#define I2C_CR1_ALERT_Msk

#define I2C_CR1_ALERT

#define I2C_CR1_SWRST_Pos

#define I2C_CR1_SWRST_Msk

#define I2C_CR1_SWRST

Bit definition for I2C_CR2 register

#define I2C_CR2_FREQ_Pos

#define I2C_CR2_FREQ_Msk

#define I2C_CR2_FREQ

#define I2C_CR2_FREQ_0

#define I2C_CR2_FREQ_1

#define I2C_CR2_FREQ_2

#define I2C_CR2_FREQ_3

#define I2C_CR2_FREQ_4

#define I2C_CR2_FREQ_5

#define I2C_CR2_ITERREN_Pos

#define I2C_CR2_ITERREN_Msk

#define I2C_CR2_ITERREN

#define I2C_CR2_ITEVTEN_Pos

#define I2C_CR2_ITEVTEN_Msk

#define I2C_CR2_ITEVTEN

#define I2C_CR2_ITBUFEN_Pos

#define I2C_CR2_ITBUFEN_Msk

#define I2C_CR2_ITBUFEN

#define I2C_CR2_DMAEN_Pos

#define I2C_CR2_DMAEN_Msk

#define I2C_CR2_DMAEN

#define I2C_CR2_LAST_Pos

#define I2C_CR2_LAST_Msk

#define I2C_CR2_LAST

Bit definition for I2C_OAR1 register

#define I2C_OAR1_ADD1_7

#define I2C_OAR1_ADD8_9

#define I2C_OAR1_ADD0_Pos

#define I2C_OAR1_ADD0_Msk

#define I2C_OAR1_ADD0

#define I2C_OAR1_ADD1_Pos

#define I2C_OAR1_ADD1_Msk

#define I2C_OAR1_ADD1

#define I2C_OAR1_ADD2_Pos

#define I2C_OAR1_ADD2_Msk

#define I2C_OAR1_ADD2

#define I2C_OAR1_ADD3_Pos

#define I2C_OAR1_ADD3_Msk

#define I2C_OAR1_ADD3

#define I2C_OAR1_ADD4_Pos

#define I2C_OAR1_ADD4_Msk

#define I2C_OAR1_ADD4

#define I2C_OAR1_ADD5_Pos

#define I2C_OAR1_ADD5_Msk

#define I2C_OAR1_ADD5

#define I2C_OAR1_ADD6_Pos

#define I2C_OAR1_ADD6_Msk

#define I2C_OAR1_ADD6

#define I2C_OAR1_ADD7_Pos

#define I2C_OAR1_ADD7_Msk

#define I2C_OAR1_ADD7

#define I2C_OAR1_ADD8_Pos

#define I2C_OAR1_ADD8_Msk

#define I2C_OAR1_ADD8

#define I2C_OAR1_ADD9_Pos

#define I2C_OAR1_ADD9_Msk

#define I2C_OAR1_ADD9

#define I2C_OAR1_ADDMODE_Pos

#define I2C_OAR1_ADDMODE_Msk

#define I2C_OAR1_ADDMODE

Bit definition for I2C_OAR2 register

#define I2C_OAR2_ENDUAL_Pos

#define I2C_OAR2_ENDUAL_Msk

#define I2C_OAR2_ENDUAL

#define I2C_OAR2_ADD2_Pos

#define I2C_OAR2_ADD2_Msk

#define I2C_OAR2_ADD2

Bit definition for I2C_DR register

#define I2C_DR_DR_Pos

#define I2C_DR_DR_Msk

#define I2C_DR_DR

Bit definition for I2C_SR1 register

#define I2C_SR1_SB_Pos

#define I2C_SR1_SB_Msk

#define I2C_SR1_SB

#define I2C_SR1_ADDR_Pos

#define I2C_SR1_ADDR_Msk

#define I2C_SR1_ADDR

#define I2C_SR1_BTF_Pos

#define I2C_SR1_BTF_Msk

#define I2C_SR1_BTF

#define I2C_SR1_ADD10_Pos

#define I2C_SR1_ADD10_Msk

#define I2C_SR1_ADD10

#define I2C_SR1_STOPF_Pos

#define I2C_SR1_STOPF_Msk

#define I2C_SR1_STOPF

#define I2C_SR1_RXNE_Pos

#define I2C_SR1_RXNE_Msk

#define I2C_SR1_RXNE

#define I2C_SR1_TXE_Pos

#define I2C_SR1_TXE_Msk

#define I2C_SR1_TXE

#define I2C_SR1_BERR_Pos

#define I2C_SR1_BERR_Msk

#define I2C_SR1_BERR

#define I2C_SR1_ARLO_Pos

#define I2C_SR1_ARLO_Msk

#define I2C_SR1_ARLO

#define I2C_SR1_AF_Pos

#define I2C_SR1_AF_Msk

#define I2C_SR1_AF

#define I2C_SR1_OVR_Pos

#define I2C_SR1_OVR_Msk

#define I2C_SR1_OVR

#define I2C_SR1_PECERR_Pos

#define I2C_SR1_PECERR_Msk

#define I2C_SR1_PECERR

#define I2C_SR1_TIMEOUT_Pos

#define I2C_SR1_TIMEOUT_Msk

#define I2C_SR1_TIMEOUT

#define I2C_SR1_SMBALERT_Pos

#define I2C_SR1_SMBALERT_Msk

#define I2C_SR1_SMBALERT

Bit definition for I2C_SR2 register

#define I2C_SR2_MSL_Pos

#define I2C_SR2_MSL_Msk

#define I2C_SR2_MSL

#define I2C_SR2_BUSY_Pos

#define I2C_SR2_BUSY_Msk

#define I2C_SR2_BUSY

#define I2C_SR2_TRA_Pos

#define I2C_SR2_TRA_Msk

#define I2C_SR2_TRA

#define I2C_SR2_GENCALL_Pos

#define I2C_SR2_GENCALL_Msk

#define I2C_SR2_GENCALL

#define I2C_SR2_SMBDEFAULT_Pos

#define I2C_SR2_SMBDEFAULT_Msk

#define I2C_SR2_SMBDEFAULT

#define I2C_SR2_SMBHOST_Pos

#define I2C_SR2_SMBHOST_Msk

#define I2C_SR2_SMBHOST

#define I2C_SR2_DUALF_Pos

#define I2C_SR2_DUALF_Msk

#define I2C_SR2_DUALF

#define I2C_SR2_PEC_Pos

#define I2C_SR2_PEC_Msk

#define I2C_SR2_PEC

Bit definition for I2C_CCR register

#define I2C_CCR_CCR_Pos

#define I2C_CCR_CCR_Msk

#define I2C_CCR_CCR

#define I2C_CCR_DUTY_Pos

#define I2C_CCR_DUTY_Msk

#define I2C_CCR_DUTY

#define I2C_CCR_FS_Pos

#define I2C_CCR_FS_Msk

#define I2C_CCR_FS

Bit definition for I2C_TRISE register

#define I2C_TRISE_TRISE_Pos

#define I2C_TRISE_TRISE_Msk

#define I2C_TRISE_TRISE

Bit definition for I2C_FLTR register

#define I2C_FLTR_DNF_Pos

#define I2C_FLTR_DNF_Msk

#define I2C_FLTR_DNF

#define I2C_FLTR_ANOFF_Pos

#define I2C_FLTR_ANOFF_Msk

#define I2C_FLTR_ANOFF

...

Bit definition for IWDG_KR register

#define IWDG_KR_KEY_Pos

#define IWDG_KR_KEY_Msk

#define IWDG_KR_KEY

Bit definition for IWDG_PR register

#define IWDG_PR_PR_Pos

#define IWDG_PR_PR_Msk

#define IWDG_PR_PR

#define IWDG_PR_PR_0

#define IWDG_PR_PR_1

#define IWDG_PR_PR_2

Bit definition for IWDG_RLR register

#define IWDG_RLR_RL_Pos

#define IWDG_RLR_RL_Msk

#define IWDG_RLR_RL

Bit definition for IWDG_SR register

#define IWDG_SR_PVU_Pos

#define IWDG_SR_PVU_Msk

#define IWDG_SR_PVU

#define IWDG_SR_RVU_Pos

#define IWDG_SR_RVU_Msk

#define IWDG_SR_RVU

...

Bit definition for LTDC_SSCR register

#define LTDC_SSCR_VSH_Pos

#define LTDC_SSCR_VSH_Msk

#define LTDC_SSCR_VSH

#define LTDC_SSCR_HSW_Pos

#define LTDC_SSCR_HSW_Msk

#define LTDC_SSCR_HSW

Bit definition for LTDC_BPCR register

#define LTDC_BPCR_AVBP_Pos

#define LTDC_BPCR_AVBP_Msk

#define LTDC_BPCR_AVBP

#define LTDC_BPCR_AHBP_Pos

#define LTDC_BPCR_AHBP_Msk

#define LTDC_BPCR_AHBP

Bit definition for LTDC_AWCR register

#define LTDC_AWCR_AAH_Pos

#define LTDC_AWCR_AAH_Msk

#define LTDC_AWCR_AAH

#define LTDC_AWCR_AAW_Pos

#define LTDC_AWCR_AAW_Msk

#define LTDC_AWCR_AAW

Bit definition for LTDC_TWCR register

#define LTDC_TWCR_TOTALH_Pos

#define LTDC_TWCR_TOTALH_Msk

#define LTDC_TWCR_TOTALH

#define LTDC_TWCR_TOTALW_Pos

#define LTDC_TWCR_TOTALW_Msk

#define LTDC_TWCR_TOTALW

Bit definition for LTDC_GCR register

#define LTDC_GCR_LTDCEN_Pos

#define LTDC_GCR_LTDCEN_Msk

#define LTDC_GCR_LTDCEN

#define LTDC_GCR_DBW_Pos

#define LTDC_GCR_DBW_Msk

#define LTDC_GCR_DBW

#define LTDC_GCR_DGW_Pos

#define LTDC_GCR_DGW_Msk

#define LTDC_GCR_DGW

#define LTDC_GCR_DRW_Pos

#define LTDC_GCR_DRW_Msk

#define LTDC_GCR_DRW

#define LTDC_GCR_DEN_Pos

#define LTDC_GCR_DEN_Msk

#define LTDC_GCR_DEN

#define LTDC_GCR_PCPOL_Pos

#define LTDC_GCR_PCPOL_Msk

#define LTDC_GCR_PCPOL

#define LTDC_GCR_DEPOL_Pos

#define LTDC_GCR_DEPOL_Msk

#define LTDC_GCR_DEPOL

#define LTDC_GCR_VSPOL_Pos

#define LTDC_GCR_VSPOL_Msk

#define LTDC_GCR_VSPOL

#define LTDC_GCR_HSPOL_Pos

#define LTDC_GCR_HSPOL_Msk

#define LTDC_GCR_HSPOL

#define LTDC_GCR_DTEN

Bit definition for LTDC_SRCR register

#define LTDC_SRCR_IMR_Pos

#define LTDC_SRCR_IMR_Msk

#define LTDC_SRCR_IMR

#define LTDC_SRCR_VBR_Pos

#define LTDC_SRCR_VBR_Msk

#define LTDC_SRCR_VBR

Bit definition for LTDC_BCCR register

#define LTDC_BCCR_BCBLUE_Pos

#define LTDC_BCCR_BCBLUE_Msk

#define LTDC_BCCR_BCBLUE

#define LTDC_BCCR_BCGREEN_Pos

#define LTDC_BCCR_BCGREEN_Msk

#define LTDC_BCCR_BCGREEN

#define LTDC_BCCR_BCRED_Pos

#define LTDC_BCCR_BCRED_Msk

#define LTDC_BCCR_BCRED

Bit definition for LTDC_IER register

#define LTDC_IER_LIE_Pos

#define LTDC_IER_LIE_Msk

#define LTDC_IER_LIE

#define LTDC_IER_FUIE_Pos

#define LTDC_IER_FUIE_Msk

#define LTDC_IER_FUIE

#define LTDC_IER_TERRIE_Pos

#define LTDC_IER_TERRIE_Msk

#define LTDC_IER_TERRIE

#define LTDC_IER_RRIE_Pos

#define LTDC_IER_RRIE_Msk

#define LTDC_IER_RRIE

Bit definition for LTDC_ISR register

#define LTDC_ISR_LIF_Pos

#define LTDC_ISR_LIF_Msk

#define LTDC_ISR_LIF

#define LTDC_ISR_FUIF_Pos

#define LTDC_ISR_FUIF_Msk

#define LTDC_ISR_FUIF

#define LTDC_ISR_TERRIF_Pos

#define LTDC_ISR_TERRIF_Msk

#define LTDC_ISR_TERRIF

#define LTDC_ISR_RRIF_Pos

#define LTDC_ISR_RRIF_Msk

#define LTDC_ISR_RRIF

Bit definition for LTDC_ICR register

#define LTDC_ICR_CLIF_Pos

#define LTDC_ICR_CLIF_Msk

#define LTDC_ICR_CLIF

#define LTDC_ICR_CFUIF_Pos

#define LTDC_ICR_CFUIF_Msk

#define LTDC_ICR_CFUIF

#define LTDC_ICR_CTERRIF_Pos

#define LTDC_ICR_CTERRIF_Msk

#define LTDC_ICR_CTERRIF

#define LTDC_ICR_CRRIF_Pos

#define LTDC_ICR_CRRIF_Msk

#define LTDC_ICR_CRRIF

Bit definition for LTDC_LIPCR register

#define LTDC_LIPCR_LIPOS_Pos

#define LTDC_LIPCR_LIPOS_Msk

#define LTDC_LIPCR_LIPOS

Bit definition for LTDC_CPSR register

#define LTDC_CPSR_CYPOS_Pos

#define LTDC_CPSR_CYPOS_Msk

#define LTDC_CPSR_CYPOS

#define LTDC_CPSR_CXPOS_Pos

#define LTDC_CPSR_CXPOS_Msk

#define LTDC_CPSR_CXPOS

Bit definition for LTDC_CDSR register

#define LTDC_CDSR_VDES_Pos

#define LTDC_CDSR_VDES_Msk

#define LTDC_CDSR_VDES

#define LTDC_CDSR_HDES_Pos

#define LTDC_CDSR_HDES_Msk

#define LTDC_CDSR_HDES

#define LTDC_CDSR_VSYNCS_Pos

#define LTDC_CDSR_VSYNCS_Msk

#define LTDC_CDSR_VSYNCS

#define LTDC_CDSR_HSYNCS_Pos

#define LTDC_CDSR_HSYNCS_Msk

#define LTDC_CDSR_HSYNCS

Bit definition for LTDC_LxCR register

#define LTDC_LxCR_LEN_Pos

#define LTDC_LxCR_LEN_Msk

#define LTDC_LxCR_LEN

#define LTDC_LxCR_COLKEN_Pos

#define LTDC_LxCR_COLKEN_Msk

#define LTDC_LxCR_COLKEN

#define LTDC_LxCR_CLUTEN_Pos

#define LTDC_LxCR_CLUTEN_Msk

#define LTDC_LxCR_CLUTEN

Bit definition for LTDC_LxWHPCR register

#define LTDC_LxWHPCR_WHSTPOS_Pos

#define LTDC_LxWHPCR_WHSTPOS_Msk

#define LTDC_LxWHPCR_WHSTPOS

#define LTDC_LxWHPCR_WHSPPOS_Pos

#define LTDC_LxWHPCR_WHSPPOS_Msk

#define LTDC_LxWHPCR_WHSPPOS

Bit definition for LTDC_LxWVPCR register

#define LTDC_LxWVPCR_WVSTPOS_Pos

#define LTDC_LxWVPCR_WVSTPOS_Msk

#define LTDC_LxWVPCR_WVSTPOS

#define LTDC_LxWVPCR_WVSPPOS_Pos

#define LTDC_LxWVPCR_WVSPPOS_Msk

#define LTDC_LxWVPCR_WVSPPOS

Bit definition for LTDC_LxCKCR register

#define LTDC_LxCKCR_CKBLUE_Pos

#define LTDC_LxCKCR_CKBLUE_Msk

#define LTDC_LxCKCR_CKBLUE

#define LTDC_LxCKCR_CKGREEN_Pos

#define LTDC_LxCKCR_CKGREEN_Msk

#define LTDC_LxCKCR_CKGREEN

#define LTDC_LxCKCR_CKRED_Pos

#define LTDC_LxCKCR_CKRED_Msk

#define LTDC_LxCKCR_CKRED

Bit definition for LTDC_LxPFCR register

#define LTDC_LxPFCR_PF_Pos

#define LTDC_LxPFCR_PF_Msk

#define LTDC_LxPFCR_PF

Bit definition for LTDC_LxCACR register

#define LTDC_LxCACR_CONSTA_Pos

#define LTDC_LxCACR_CONSTA_Msk

#define LTDC_LxCACR_CONSTA

Bit definition for LTDC_LxDCCR register

#define LTDC_LxDCCR_DCBLUE_Pos

#define LTDC_LxDCCR_DCBLUE_Msk

#define LTDC_LxDCCR_DCBLUE

#define LTDC_LxDCCR_DCGREEN_Pos

#define LTDC_LxDCCR_DCGREEN_Msk

#define LTDC_LxDCCR_DCGREEN

#define LTDC_LxDCCR_DCRED_Pos

#define LTDC_LxDCCR_DCRED_Msk

#define LTDC_LxDCCR_DCRED

#define LTDC_LxDCCR_DCALPHA_Pos

#define LTDC_LxDCCR_DCALPHA_Msk

#define LTDC_LxDCCR_DCALPHA

Bit definition for LTDC_LxBFCR register

#define LTDC_LxBFCR_BF2_Pos

#define LTDC_LxBFCR_BF2_Msk

#define LTDC_LxBFCR_BF2

#define LTDC_LxBFCR_BF1_Pos

#define LTDC_LxBFCR_BF1_Msk

#define LTDC_LxBFCR_BF1

Bit definition for LTDC_LxCFBAR register

#define LTDC_LxCFBAR_CFBADD_Pos

#define LTDC_LxCFBAR_CFBADD_Msk

#define LTDC_LxCFBAR_CFBADD

Bit definition for LTDC_LxCFBLR register

#define LTDC_LxCFBLR_CFBLL_Pos

#define LTDC_LxCFBLR_CFBLL_Msk

#define LTDC_LxCFBLR_CFBLL

#define LTDC_LxCFBLR_CFBP_Pos

#define LTDC_LxCFBLR_CFBP_Msk

#define LTDC_LxCFBLR_CFBP

Bit definition for LTDC_LxCFBLNR register

#define LTDC_LxCFBLNR_CFBLNBR_Pos

#define LTDC_LxCFBLNR_CFBLNBR_Msk

#define LTDC_LxCFBLNR_CFBLNBR

Bit definition for LTDC_LxCLUTWR register

#define LTDC_LxCLUTWR_BLUE_Pos

#define LTDC_LxCLUTWR_BLUE_Msk

#define LTDC_LxCLUTWR_BLUE

#define LTDC_LxCLUTWR_GREEN_Pos

#define LTDC_LxCLUTWR_GREEN_Msk

#define LTDC_LxCLUTWR_GREEN

#define LTDC_LxCLUTWR_RED_Pos

#define LTDC_LxCLUTWR_RED_Msk

#define LTDC_LxCLUTWR_RED

#define LTDC_LxCLUTWR_CLUTADD_Pos

#define LTDC_LxCLUTWR_CLUTADD_Msk

#define LTDC_LxCLUTWR_CLUTADD

...

Bit definition for PWR_CR register

#define PWR_CR_LPDS_Pos

#define PWR_CR_LPDS_Msk

#define PWR_CR_LPDS

#define PWR_CR_PDDS_Pos

#define PWR_CR_PDDS_Msk

#define PWR_CR_PDDS

#define PWR_CR_CWUF_Pos

#define PWR_CR_CWUF_Msk

#define PWR_CR_CWUF

#define PWR_CR_CSBF_Pos

#define PWR_CR_CSBF_Msk

#define PWR_CR_CSBF

#define PWR_CR_PVDE_Pos

#define PWR_CR_PVDE_Msk

#define PWR_CR_PVDE

#define PWR_CR_PLS_Pos

#define PWR_CR_PLS_Msk

#define PWR_CR_PLS

#define PWR_CR_PLS_0

#define PWR_CR_PLS_1

#define PWR_CR_PLS_2

#define PWR_CR_PLS_LEV0

#define PWR_CR_PLS_LEV1

#define PWR_CR_PLS_LEV2

#define PWR_CR_PLS_LEV3

#define PWR_CR_PLS_LEV4

#define PWR_CR_PLS_LEV5

#define PWR_CR_PLS_LEV6

#define PWR_CR_PLS_LEV7

#define PWR_CR_DBP_Pos

#define PWR_CR_DBP_Msk

#define PWR_CR_DBP

#define PWR_CR_FPDS_Pos

#define PWR_CR_FPDS_Msk

#define PWR_CR_FPDS

#define PWR_CR_LPLVDS_Pos

#define PWR_CR_LPLVDS_Msk

#define PWR_CR_LPLVDS

#define PWR_CR_MRLVDS_Pos

#define PWR_CR_MRLVDS_Msk

#define PWR_CR_MRLVDS

#define PWR_CR_ADCDC1_Pos

#define PWR_CR_ADCDC1_Msk

#define PWR_CR_ADCDC1

#define PWR_CR_VOS_Pos

#define PWR_CR_VOS_Msk

#define PWR_CR_VOS

#define PWR_CR_VOS_0

#define PWR_CR_VOS_1

#define PWR_CR_ODEN_Pos

#define PWR_CR_ODEN_Msk

#define PWR_CR_ODEN

#define PWR_CR_ODSWEN_Pos

#define PWR_CR_ODSWEN_Msk

#define PWR_CR_ODSWEN

#define PWR_CR_UDEN_Pos

#define PWR_CR_UDEN_Msk

#define PWR_CR_UDEN

#define PWR_CR_UDEN_0

#define PWR_CR_UDEN_1

#define PWR_CR_PMODE

#define PWR_CR_LPUDS

#define PWR_CR_MRUDS

Bit definition for PWR_CSR register

#define PWR_CSR_WUF_Pos

#define PWR_CSR_WUF_Msk

#define PWR_CSR_WUF

#define PWR_CSR_SBF_Pos

#define PWR_CSR_SBF_Msk

#define PWR_CSR_SBF

#define PWR_CSR_PVDO_Pos

#define PWR_CSR_PVDO_Msk

#define PWR_CSR_PVDO

#define PWR_CSR_BRR_Pos

#define PWR_CSR_BRR_Msk

#define PWR_CSR_BRR

#define PWR_CSR_EWUP_Pos

#define PWR_CSR_EWUP_Msk

#define PWR_CSR_EWUP

#define PWR_CSR_BRE_Pos

#define PWR_CSR_BRE_Msk

#define PWR_CSR_BRE

#define PWR_CSR_VOSRDY_Pos

#define PWR_CSR_VOSRDY_Msk

#define PWR_CSR_VOSRDY

#define PWR_CSR_ODRDY_Pos

#define PWR_CSR_ODRDY_Msk

#define PWR_CSR_ODRDY

#define PWR_CSR_ODSWRDY_Pos

#define PWR_CSR_ODSWRDY_Msk

#define PWR_CSR_ODSWRDY

#define PWR_CSR_UDRDY_Pos

#define PWR_CSR_UDRDY_Msk

#define PWR_CSR_UDRDY

#define PWR_CSR_UDSWRDY

#define PWR_CSR_REGRDY

...

Bit definition for RCC_CR register

#define RCC_CR_HSION_Pos

#define RCC_CR_HSION_Msk

#define RCC_CR_HSION

#define RCC_CR_HSIRDY_Pos

#define RCC_CR_HSIRDY_Msk

#define RCC_CR_HSIRDY

#define RCC_CR_HSITRIM_Pos

#define RCC_CR_HSITRIM_Msk

#define RCC_CR_HSITRIM

#define RCC_CR_HSITRIM_0

#define RCC_CR_HSITRIM_1

#define RCC_CR_HSITRIM_2

#define RCC_CR_HSITRIM_3

#define RCC_CR_HSITRIM_4

#define RCC_CR_HSICAL_Pos

#define RCC_CR_HSICAL_Msk

#define RCC_CR_HSICAL

#define RCC_CR_HSICAL_0

#define RCC_CR_HSICAL_1

#define RCC_CR_HSICAL_2

#define RCC_CR_HSICAL_3

#define RCC_CR_HSICAL_4

#define RCC_CR_HSICAL_5

#define RCC_CR_HSICAL_6

#define RCC_CR_HSICAL_7

#define RCC_CR_HSEON_Pos

#define RCC_CR_HSEON_Msk

#define RCC_CR_HSEON

#define RCC_CR_HSERDY_Pos

#define RCC_CR_HSERDY_Msk

#define RCC_CR_HSERDY

#define RCC_CR_HSEBYP_Pos

#define RCC_CR_HSEBYP_Msk

#define RCC_CR_HSEBYP

#define RCC_CR_CSSON_Pos

#define RCC_CR_CSSON_Msk

#define RCC_CR_CSSON

#define RCC_CR_PLLON_Pos

#define RCC_CR_PLLON_Msk

#define RCC_CR_PLLON

#define RCC_CR_PLLRDY_Pos

#define RCC_CR_PLLRDY_Msk

#define RCC_CR_PLLRDY

#define RCC_PLLI2S_SUPPORT

#define RCC_CR_PLLI2SON_Pos

#define RCC_CR_PLLI2SON_Msk

#define RCC_CR_PLLI2SON

#define RCC_CR_PLLI2SRDY_Pos

#define RCC_CR_PLLI2SRDY_Msk

#define RCC_CR_PLLI2SRDY

#define RCC_PLLSAI_SUPPORT

#define RCC_CR_PLLSAION_Pos

#define RCC_CR_PLLSAION_Msk

#define RCC_CR_PLLSAION

#define RCC_CR_PLLSAIRDY_Pos

#define RCC_CR_PLLSAIRDY_Msk

#define RCC_CR_PLLSAIRDY

Bit definition for RCC_PLLCFGR register

#define RCC_PLLCFGR_PLLM_Pos

#define RCC_PLLCFGR_PLLM_Msk

#define RCC_PLLCFGR_PLLM

#define RCC_PLLCFGR_PLLM_0

#define RCC_PLLCFGR_PLLM_1

#define RCC_PLLCFGR_PLLM_2

#define RCC_PLLCFGR_PLLM_3

#define RCC_PLLCFGR_PLLM_4

#define RCC_PLLCFGR_PLLM_5

#define RCC_PLLCFGR_PLLN_Pos

#define RCC_PLLCFGR_PLLN_Msk

#define RCC_PLLCFGR_PLLN

#define RCC_PLLCFGR_PLLN_0

#define RCC_PLLCFGR_PLLN_1

#define RCC_PLLCFGR_PLLN_2

#define RCC_PLLCFGR_PLLN_3

#define RCC_PLLCFGR_PLLN_4

#define RCC_PLLCFGR_PLLN_5

#define RCC_PLLCFGR_PLLN_6

#define RCC_PLLCFGR_PLLN_7

#define RCC_PLLCFGR_PLLN_8

#define RCC_PLLCFGR_PLLP_Pos

#define RCC_PLLCFGR_PLLP_Msk

#define RCC_PLLCFGR_PLLP

#define RCC_PLLCFGR_PLLP_0

#define RCC_PLLCFGR_PLLP_1

#define RCC_PLLCFGR_PLLSRC_Pos

#define RCC_PLLCFGR_PLLSRC_Msk

#define RCC_PLLCFGR_PLLSRC

#define RCC_PLLCFGR_PLLSRC_HSE_Pos

#define RCC_PLLCFGR_PLLSRC_HSE_Msk

#define RCC_PLLCFGR_PLLSRC_HSE

#define RCC_PLLCFGR_PLLSRC_HSI

#define RCC_PLLCFGR_PLLQ_Pos

#define RCC_PLLCFGR_PLLQ_Msk

#define RCC_PLLCFGR_PLLQ

#define RCC_PLLCFGR_PLLQ_0

#define RCC_PLLCFGR_PLLQ_1

#define RCC_PLLCFGR_PLLQ_2

#define RCC_PLLCFGR_PLLQ_3

Bit definition for RCC_CFGR register

#define RCC_CFGR_SW_Pos

#define RCC_CFGR_SW_Msk

#define RCC_CFGR_SW

#define RCC_CFGR_SW_0

#define RCC_CFGR_SW_1

#define RCC_CFGR_SW_HSI

#define RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_PLL

#define RCC_CFGR_SWS_Pos

#define RCC_CFGR_SWS_Msk

#define RCC_CFGR_SWS

#define RCC_CFGR_SWS_0

#define RCC_CFGR_SWS_1

#define RCC_CFGR_SWS_HSI

#define RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_PLL

#define RCC_CFGR_HPRE_Pos

#define RCC_CFGR_HPRE_Msk

#define RCC_CFGR_HPRE

#define RCC_CFGR_HPRE_0

#define RCC_CFGR_HPRE_1

#define RCC_CFGR_HPRE_2

#define RCC_CFGR_HPRE_3

#define RCC_CFGR_HPRE_DIV1

#define RCC_CFGR_HPRE_DIV2

#define RCC_CFGR_HPRE_DIV4

#define RCC_CFGR_HPRE_DIV8

#define RCC_CFGR_HPRE_DIV16

#define RCC_CFGR_HPRE_DIV64

#define RCC_CFGR_HPRE_DIV128

#define RCC_CFGR_HPRE_DIV256

#define RCC_CFGR_HPRE_DIV512

#define RCC_CFGR_PPRE1_Pos

#define RCC_CFGR_PPRE1_Msk

#define RCC_CFGR_PPRE1

#define RCC_CFGR_PPRE1_0

#define RCC_CFGR_PPRE1_1

#define RCC_CFGR_PPRE1_2

#define RCC_CFGR_PPRE1_DIV1

#define RCC_CFGR_PPRE1_DIV2

#define RCC_CFGR_PPRE1_DIV4

#define RCC_CFGR_PPRE1_DIV8

#define RCC_CFGR_PPRE1_DIV16

#define RCC_CFGR_PPRE2_Pos

#define RCC_CFGR_PPRE2_Msk

#define RCC_CFGR_PPRE2

#define RCC_CFGR_PPRE2_0

#define RCC_CFGR_PPRE2_1

#define RCC_CFGR_PPRE2_2

#define RCC_CFGR_PPRE2_DIV1

#define RCC_CFGR_PPRE2_DIV2

#define RCC_CFGR_PPRE2_DIV4

#define RCC_CFGR_PPRE2_DIV8

#define RCC_CFGR_PPRE2_DIV16

#define RCC_CFGR_RTCPRE_Pos

#define RCC_CFGR_RTCPRE_Msk

#define RCC_CFGR_RTCPRE

#define RCC_CFGR_RTCPRE_0

#define RCC_CFGR_RTCPRE_1

#define RCC_CFGR_RTCPRE_2

#define RCC_CFGR_RTCPRE_3

#define RCC_CFGR_RTCPRE_4

#define RCC_CFGR_MCO1_Pos

#define RCC_CFGR_MCO1_Msk

#define RCC_CFGR_MCO1

#define RCC_CFGR_MCO1_0

#define RCC_CFGR_MCO1_1

#define RCC_CFGR_I2SSRC_Pos

#define RCC_CFGR_I2SSRC_Msk

#define RCC_CFGR_I2SSRC

#define RCC_CFGR_MCO1PRE_Pos

#define RCC_CFGR_MCO1PRE_Msk

#define RCC_CFGR_MCO1PRE

#define RCC_CFGR_MCO1PRE_0

#define RCC_CFGR_MCO1PRE_1

#define RCC_CFGR_MCO1PRE_2

#define RCC_CFGR_MCO2PRE_Pos

#define RCC_CFGR_MCO2PRE_Msk

#define RCC_CFGR_MCO2PRE

#define RCC_CFGR_MCO2PRE_0

#define RCC_CFGR_MCO2PRE_1

#define RCC_CFGR_MCO2PRE_2

#define RCC_CFGR_MCO2_Pos

#define RCC_CFGR_MCO2_Msk

#define RCC_CFGR_MCO2

#define RCC_CFGR_MCO2_0

#define RCC_CFGR_MCO2_1

Bit definition for RCC_CIR register

#define RCC_CIR_LSIRDYF_Pos

#define RCC_CIR_LSIRDYF_Msk

#define RCC_CIR_LSIRDYF

#define RCC_CIR_LSERDYF_Pos

#define RCC_CIR_LSERDYF_Msk

#define RCC_CIR_LSERDYF

#define RCC_CIR_HSIRDYF_Pos

#define RCC_CIR_HSIRDYF_Msk

#define RCC_CIR_HSIRDYF

#define RCC_CIR_HSERDYF_Pos

#define RCC_CIR_HSERDYF_Msk

#define RCC_CIR_HSERDYF

#define RCC_CIR_PLLRDYF_Pos

#define RCC_CIR_PLLRDYF_Msk

#define RCC_CIR_PLLRDYF

#define RCC_CIR_PLLI2SRDYF_Pos

#define RCC_CIR_PLLI2SRDYF_Msk

#define RCC_CIR_PLLI2SRDYF

#define RCC_CIR_PLLSAIRDYF_Pos

#define RCC_CIR_PLLSAIRDYF_Msk

#define RCC_CIR_PLLSAIRDYF

#define RCC_CIR_CSSF_Pos

#define RCC_CIR_CSSF_Msk

#define RCC_CIR_CSSF

#define RCC_CIR_LSIRDYIE_Pos

#define RCC_CIR_LSIRDYIE_Msk

#define RCC_CIR_LSIRDYIE

#define RCC_CIR_LSERDYIE_Pos

#define RCC_CIR_LSERDYIE_Msk

#define RCC_CIR_LSERDYIE

#define RCC_CIR_HSIRDYIE_Pos

#define RCC_CIR_HSIRDYIE_Msk

#define RCC_CIR_HSIRDYIE

#define RCC_CIR_HSERDYIE_Pos

#define RCC_CIR_HSERDYIE_Msk

#define RCC_CIR_HSERDYIE

#define RCC_CIR_PLLRDYIE_Pos

#define RCC_CIR_PLLRDYIE_Msk

#define RCC_CIR_PLLRDYIE

#define RCC_CIR_PLLI2SRDYIE_Pos

#define RCC_CIR_PLLI2SRDYIE_Msk

#define RCC_CIR_PLLI2SRDYIE

#define RCC_CIR_PLLSAIRDYIE_Pos

#define RCC_CIR_PLLSAIRDYIE_Msk

#define RCC_CIR_PLLSAIRDYIE

#define RCC_CIR_LSIRDYC_Pos

#define RCC_CIR_LSIRDYC_Msk

#define RCC_CIR_LSIRDYC

#define RCC_CIR_LSERDYC_Pos

#define RCC_CIR_LSERDYC_Msk

#define RCC_CIR_LSERDYC

#define RCC_CIR_HSIRDYC_Pos

#define RCC_CIR_HSIRDYC_Msk

#define RCC_CIR_HSIRDYC

#define RCC_CIR_HSERDYC_Pos

#define RCC_CIR_HSERDYC_Msk

#define RCC_CIR_HSERDYC

#define RCC_CIR_PLLRDYC_Pos

#define RCC_CIR_PLLRDYC_Msk

#define RCC_CIR_PLLRDYC

#define RCC_CIR_PLLI2SRDYC_Pos

#define RCC_CIR_PLLI2SRDYC_Msk

#define RCC_CIR_PLLI2SRDYC

#define RCC_CIR_PLLSAIRDYC_Pos

#define RCC_CIR_PLLSAIRDYC_Msk

#define RCC_CIR_PLLSAIRDYC

#define RCC_CIR_CSSC_Pos

#define RCC_CIR_CSSC_Msk

#define RCC_CIR_CSSC

Bit definition for RCC_AHB1RSTR register

#define RCC_AHB1RSTR_GPIOARST_Pos

#define RCC_AHB1RSTR_GPIOARST_Msk

#define RCC_AHB1RSTR_GPIOARST

#define RCC_AHB1RSTR_GPIOBRST_Pos

#define RCC_AHB1RSTR_GPIOBRST_Msk

#define RCC_AHB1RSTR_GPIOBRST

#define RCC_AHB1RSTR_GPIOCRST_Pos

#define RCC_AHB1RSTR_GPIOCRST_Msk

#define RCC_AHB1RSTR_GPIOCRST

#define RCC_AHB1RSTR_GPIODRST_Pos

#define RCC_AHB1RSTR_GPIODRST_Msk

#define RCC_AHB1RSTR_GPIODRST

#define RCC_AHB1RSTR_GPIOERST_Pos

#define RCC_AHB1RSTR_GPIOERST_Msk

#define RCC_AHB1RSTR_GPIOERST

#define RCC_AHB1RSTR_GPIOFRST_Pos

#define RCC_AHB1RSTR_GPIOFRST_Msk

#define RCC_AHB1RSTR_GPIOFRST

#define RCC_AHB1RSTR_GPIOGRST_Pos

#define RCC_AHB1RSTR_GPIOGRST_Msk

#define RCC_AHB1RSTR_GPIOGRST

#define RCC_AHB1RSTR_GPIOHRST_Pos

#define RCC_AHB1RSTR_GPIOHRST_Msk

#define RCC_AHB1RSTR_GPIOHRST

#define RCC_AHB1RSTR_GPIOIRST_Pos

#define RCC_AHB1RSTR_GPIOIRST_Msk

#define RCC_AHB1RSTR_GPIOIRST

#define RCC_AHB1RSTR_GPIOJRST_Pos

#define RCC_AHB1RSTR_GPIOJRST_Msk

#define RCC_AHB1RSTR_GPIOJRST

#define RCC_AHB1RSTR_GPIOKRST_Pos

#define RCC_AHB1RSTR_GPIOKRST_Msk

#define RCC_AHB1RSTR_GPIOKRST

#define RCC_AHB1RSTR_CRCRST_Pos

#define RCC_AHB1RSTR_CRCRST_Msk

#define RCC_AHB1RSTR_CRCRST

#define RCC_AHB1RSTR_DMA1RST_Pos

#define RCC_AHB1RSTR_DMA1RST_Msk

#define RCC_AHB1RSTR_DMA1RST

#define RCC_AHB1RSTR_DMA2RST_Pos

#define RCC_AHB1RSTR_DMA2RST_Msk

#define RCC_AHB1RSTR_DMA2RST

#define RCC_AHB1RSTR_DMA2DRST_Pos

#define RCC_AHB1RSTR_DMA2DRST_Msk

#define RCC_AHB1RSTR_DMA2DRST

#define RCC_AHB1RSTR_ETHMACRST_Pos

#define RCC_AHB1RSTR_ETHMACRST_Msk

#define RCC_AHB1RSTR_ETHMACRST

#define RCC_AHB1RSTR_OTGHRST_Pos

#define RCC_AHB1RSTR_OTGHRST_Msk

#define RCC_AHB1RSTR_OTGHRST

Bit definition for RCC_AHB2RSTR register

#define RCC_AHB2RSTR_DCMIRST_Pos

#define RCC_AHB2RSTR_DCMIRST_Msk

#define RCC_AHB2RSTR_DCMIRST

#define RCC_AHB2RSTR_RNGRST_Pos

#define RCC_AHB2RSTR_RNGRST_Msk

#define RCC_AHB2RSTR_RNGRST

#define RCC_AHB2RSTR_OTGFSRST_Pos

#define RCC_AHB2RSTR_OTGFSRST_Msk

#define RCC_AHB2RSTR_OTGFSRST

Bit definition for RCC_AHB3RSTR register

#define RCC_AHB3RSTR_FMCRST_Pos

#define RCC_AHB3RSTR_FMCRST_Msk

#define RCC_AHB3RSTR_FMCRST

Bit definition for RCC_APB1RSTR register

#define RCC_APB1RSTR_TIM2RST_Pos

#define RCC_APB1RSTR_TIM2RST_Msk

#define RCC_APB1RSTR_TIM2RST

#define RCC_APB1RSTR_TIM3RST_Pos

#define RCC_APB1RSTR_TIM3RST_Msk

#define RCC_APB1RSTR_TIM3RST

#define RCC_APB1RSTR_TIM4RST_Pos

#define RCC_APB1RSTR_TIM4RST_Msk

#define RCC_APB1RSTR_TIM4RST

#define RCC_APB1RSTR_TIM5RST_Pos

#define RCC_APB1RSTR_TIM5RST_Msk

#define RCC_APB1RSTR_TIM5RST

#define RCC_APB1RSTR_TIM6RST_Pos

#define RCC_APB1RSTR_TIM6RST_Msk

#define RCC_APB1RSTR_TIM6RST

#define RCC_APB1RSTR_TIM7RST_Pos

#define RCC_APB1RSTR_TIM7RST_Msk

#define RCC_APB1RSTR_TIM7RST

#define RCC_APB1RSTR_TIM12RST_Pos

#define RCC_APB1RSTR_TIM12RST_Msk

#define RCC_APB1RSTR_TIM12RST

#define RCC_APB1RSTR_TIM13RST_Pos

#define RCC_APB1RSTR_TIM13RST_Msk

#define RCC_APB1RSTR_TIM13RST

#define RCC_APB1RSTR_TIM14RST_Pos

#define RCC_APB1RSTR_TIM14RST_Msk

#define RCC_APB1RSTR_TIM14RST

#define RCC_APB1RSTR_WWDGRST_Pos

#define RCC_APB1RSTR_WWDGRST_Msk

#define RCC_APB1RSTR_WWDGRST

#define RCC_APB1RSTR_SPI2RST_Pos

#define RCC_APB1RSTR_SPI2RST_Msk

#define RCC_APB1RSTR_SPI2RST

#define RCC_APB1RSTR_SPI3RST_Pos

#define RCC_APB1RSTR_SPI3RST_Msk

#define RCC_APB1RSTR_SPI3RST

#define RCC_APB1RSTR_USART2RST_Pos

#define RCC_APB1RSTR_USART2RST_Msk

#define RCC_APB1RSTR_USART2RST

#define RCC_APB1RSTR_USART3RST_Pos

#define RCC_APB1RSTR_USART3RST_Msk

#define RCC_APB1RSTR_USART3RST

#define RCC_APB1RSTR_UART4RST_Pos

#define RCC_APB1RSTR_UART4RST_Msk

#define RCC_APB1RSTR_UART4RST

#define RCC_APB1RSTR_UART5RST_Pos

#define RCC_APB1RSTR_UART5RST_Msk

#define RCC_APB1RSTR_UART5RST

#define RCC_APB1RSTR_I2C1RST_Pos

#define RCC_APB1RSTR_I2C1RST_Msk

#define RCC_APB1RSTR_I2C1RST

#define RCC_APB1RSTR_I2C2RST_Pos

#define RCC_APB1RSTR_I2C2RST_Msk

#define RCC_APB1RSTR_I2C2RST

#define RCC_APB1RSTR_I2C3RST_Pos

#define RCC_APB1RSTR_I2C3RST_Msk

#define RCC_APB1RSTR_I2C3RST

#define RCC_APB1RSTR_CAN1RST_Pos

#define RCC_APB1RSTR_CAN1RST_Msk

#define RCC_APB1RSTR_CAN1RST

#define RCC_APB1RSTR_CAN2RST_Pos

#define RCC_APB1RSTR_CAN2RST_Msk

#define RCC_APB1RSTR_CAN2RST

#define RCC_APB1RSTR_PWRRST_Pos

#define RCC_APB1RSTR_PWRRST_Msk

#define RCC_APB1RSTR_PWRRST

#define RCC_APB1RSTR_DACRST_Pos

#define RCC_APB1RSTR_DACRST_Msk

#define RCC_APB1RSTR_DACRST

#define RCC_APB1RSTR_UART7RST_Pos

#define RCC_APB1RSTR_UART7RST_Msk

#define RCC_APB1RSTR_UART7RST

#define RCC_APB1RSTR_UART8RST_Pos

#define RCC_APB1RSTR_UART8RST_Msk

#define RCC_APB1RSTR_UART8RST

Bit definition for RCC_APB2RSTR register

#define RCC_APB2RSTR_TIM1RST_Pos

#define RCC_APB2RSTR_TIM1RST_Msk

#define RCC_APB2RSTR_TIM1RST

#define RCC_APB2RSTR_TIM8RST_Pos

#define RCC_APB2RSTR_TIM8RST_Msk

#define RCC_APB2RSTR_TIM8RST

#define RCC_APB2RSTR_USART1RST_Pos

#define RCC_APB2RSTR_USART1RST_Msk

#define RCC_APB2RSTR_USART1RST

#define RCC_APB2RSTR_USART6RST_Pos

#define RCC_APB2RSTR_USART6RST_Msk

#define RCC_APB2RSTR_USART6RST

#define RCC_APB2RSTR_ADCRST_Pos

#define RCC_APB2RSTR_ADCRST_Msk

#define RCC_APB2RSTR_ADCRST

#define RCC_APB2RSTR_SDIORST_Pos

#define RCC_APB2RSTR_SDIORST_Msk

#define RCC_APB2RSTR_SDIORST

#define RCC_APB2RSTR_SPI1RST_Pos

#define RCC_APB2RSTR_SPI1RST_Msk

#define RCC_APB2RSTR_SPI1RST

#define RCC_APB2RSTR_SPI4RST_Pos

#define RCC_APB2RSTR_SPI4RST_Msk

#define RCC_APB2RSTR_SPI4RST

#define RCC_APB2RSTR_SYSCFGRST_Pos

#define RCC_APB2RSTR_SYSCFGRST_Msk

#define RCC_APB2RSTR_SYSCFGRST

#define RCC_APB2RSTR_TIM9RST_Pos

#define RCC_APB2RSTR_TIM9RST_Msk

#define RCC_APB2RSTR_TIM9RST

#define RCC_APB2RSTR_TIM10RST_Pos

#define RCC_APB2RSTR_TIM10RST_Msk

#define RCC_APB2RSTR_TIM10RST

#define RCC_APB2RSTR_TIM11RST_Pos

#define RCC_APB2RSTR_TIM11RST_Msk

#define RCC_APB2RSTR_TIM11RST

#define RCC_APB2RSTR_SPI5RST_Pos

#define RCC_APB2RSTR_SPI5RST_Msk

#define RCC_APB2RSTR_SPI5RST

#define RCC_APB2RSTR_SPI6RST_Pos

#define RCC_APB2RSTR_SPI6RST_Msk

#define RCC_APB2RSTR_SPI6RST

#define RCC_APB2RSTR_SAI1RST_Pos

#define RCC_APB2RSTR_SAI1RST_Msk

#define RCC_APB2RSTR_SAI1RST

#define RCC_APB2RSTR_LTDCRST_Pos

#define RCC_APB2RSTR_LTDCRST_Msk

#define RCC_APB2RSTR_LTDCRST

#define RCC_APB2RSTR_SPI1

Bit definition for RCC_AHB1ENR register

#define RCC_AHB1ENR_GPIOAEN_Pos

#define RCC_AHB1ENR_GPIOAEN_Msk

#define RCC_AHB1ENR_GPIOAEN

#define RCC_AHB1ENR_GPIOBEN_Pos

#define RCC_AHB1ENR_GPIOBEN_Msk

#define RCC_AHB1ENR_GPIOBEN

#define RCC_AHB1ENR_GPIOCEN_Pos

#define RCC_AHB1ENR_GPIOCEN_Msk

#define RCC_AHB1ENR_GPIOCEN

#define RCC_AHB1ENR_GPIODEN_Pos

#define RCC_AHB1ENR_GPIODEN_Msk

#define RCC_AHB1ENR_GPIODEN

#define RCC_AHB1ENR_GPIOEEN_Pos

#define RCC_AHB1ENR_GPIOEEN_Msk

#define RCC_AHB1ENR_GPIOEEN

#define RCC_AHB1ENR_GPIOFEN_Pos

#define RCC_AHB1ENR_GPIOFEN_Msk

#define RCC_AHB1ENR_GPIOFEN

#define RCC_AHB1ENR_GPIOGEN_Pos

#define RCC_AHB1ENR_GPIOGEN_Msk

#define RCC_AHB1ENR_GPIOGEN

#define RCC_AHB1ENR_GPIOHEN_Pos

#define RCC_AHB1ENR_GPIOHEN_Msk

#define RCC_AHB1ENR_GPIOHEN

#define RCC_AHB1ENR_GPIOIEN_Pos

#define RCC_AHB1ENR_GPIOIEN_Msk

#define RCC_AHB1ENR_GPIOIEN

#define RCC_AHB1ENR_GPIOJEN_Pos

#define RCC_AHB1ENR_GPIOJEN_Msk

#define RCC_AHB1ENR_GPIOJEN

#define RCC_AHB1ENR_GPIOKEN_Pos

#define RCC_AHB1ENR_GPIOKEN_Msk

#define RCC_AHB1ENR_GPIOKEN

#define RCC_AHB1ENR_CRCEN_Pos

#define RCC_AHB1ENR_CRCEN_Msk

#define RCC_AHB1ENR_CRCEN

#define RCC_AHB1ENR_BKPSRAMEN_Pos

#define RCC_AHB1ENR_BKPSRAMEN_Msk

#define RCC_AHB1ENR_BKPSRAMEN

#define RCC_AHB1ENR_CCMDATARAMEN_Pos

#define RCC_AHB1ENR_CCMDATARAMEN_Msk

#define RCC_AHB1ENR_CCMDATARAMEN

#define RCC_AHB1ENR_DMA1EN_Pos

#define RCC_AHB1ENR_DMA1EN_Msk

#define RCC_AHB1ENR_DMA1EN

#define RCC_AHB1ENR_DMA2EN_Pos

#define RCC_AHB1ENR_DMA2EN_Msk

#define RCC_AHB1ENR_DMA2EN

#define RCC_AHB1ENR_DMA2DEN_Pos

#define RCC_AHB1ENR_DMA2DEN_Msk

#define RCC_AHB1ENR_DMA2DEN

#define RCC_AHB1ENR_ETHMACEN_Pos

#define RCC_AHB1ENR_ETHMACEN_Msk

#define RCC_AHB1ENR_ETHMACEN

#define RCC_AHB1ENR_ETHMACTXEN_Pos

#define RCC_AHB1ENR_ETHMACTXEN_Msk

#define RCC_AHB1ENR_ETHMACTXEN

#define RCC_AHB1ENR_ETHMACRXEN_Pos

#define RCC_AHB1ENR_ETHMACRXEN_Msk

#define RCC_AHB1ENR_ETHMACRXEN

#define RCC_AHB1ENR_ETHMACPTPEN_Pos

#define RCC_AHB1ENR_ETHMACPTPEN_Msk

#define RCC_AHB1ENR_ETHMACPTPEN

#define RCC_AHB1ENR_OTGHSEN_Pos

#define RCC_AHB1ENR_OTGHSEN_Msk

#define RCC_AHB1ENR_OTGHSEN

#define RCC_AHB1ENR_OTGHSULPIEN_Pos

#define RCC_AHB1ENR_OTGHSULPIEN_Msk

#define RCC_AHB1ENR_OTGHSULPIEN

Bit definition for RCC_AHB2ENR register

#define RCC_AHB2_SUPPORT

#define RCC_AHB2ENR_DCMIEN_Pos

#define RCC_AHB2ENR_DCMIEN_Msk

#define RCC_AHB2ENR_DCMIEN

#define RCC_AHB2ENR_RNGEN_Pos

#define RCC_AHB2ENR_RNGEN_Msk

#define RCC_AHB2ENR_RNGEN

#define RCC_AHB2ENR_OTGFSEN_Pos

#define RCC_AHB2ENR_OTGFSEN_Msk

#define RCC_AHB2ENR_OTGFSEN

Bit definition for RCC_AHB3ENR register

#define RCC_AHB3_SUPPORT

#define RCC_AHB3ENR_FMCEN_Pos

#define RCC_AHB3ENR_FMCEN_Msk

#define RCC_AHB3ENR_FMCEN

Bit definition for RCC_APB1ENR register

#define RCC_APB1ENR_TIM2EN_Pos

#define RCC_APB1ENR_TIM2EN_Msk

#define RCC_APB1ENR_TIM2EN

#define RCC_APB1ENR_TIM3EN_Pos

#define RCC_APB1ENR_TIM3EN_Msk

#define RCC_APB1ENR_TIM3EN

#define RCC_APB1ENR_TIM4EN_Pos

#define RCC_APB1ENR_TIM4EN_Msk

#define RCC_APB1ENR_TIM4EN

#define RCC_APB1ENR_TIM5EN_Pos

#define RCC_APB1ENR_TIM5EN_Msk

#define RCC_APB1ENR_TIM5EN

#define RCC_APB1ENR_TIM6EN_Pos

#define RCC_APB1ENR_TIM6EN_Msk

#define RCC_APB1ENR_TIM6EN

#define RCC_APB1ENR_TIM7EN_Pos

#define RCC_APB1ENR_TIM7EN_Msk

#define RCC_APB1ENR_TIM7EN

#define RCC_APB1ENR_TIM12EN_Pos

#define RCC_APB1ENR_TIM12EN_Msk

#define RCC_APB1ENR_TIM12EN

#define RCC_APB1ENR_TIM13EN_Pos

#define RCC_APB1ENR_TIM13EN_Msk

#define RCC_APB1ENR_TIM13EN

#define RCC_APB1ENR_TIM14EN_Pos

#define RCC_APB1ENR_TIM14EN_Msk

#define RCC_APB1ENR_TIM14EN

#define RCC_APB1ENR_WWDGEN_Pos

#define RCC_APB1ENR_WWDGEN_Msk

#define RCC_APB1ENR_WWDGEN

#define RCC_APB1ENR_SPI2EN_Pos

#define RCC_APB1ENR_SPI2EN_Msk

#define RCC_APB1ENR_SPI2EN

#define RCC_APB1ENR_SPI3EN_Pos

#define RCC_APB1ENR_SPI3EN_Msk

#define RCC_APB1ENR_SPI3EN

#define RCC_APB1ENR_USART2EN_Pos

#define RCC_APB1ENR_USART2EN_Msk

#define RCC_APB1ENR_USART2EN

#define RCC_APB1ENR_USART3EN_Pos

#define RCC_APB1ENR_USART3EN_Msk

#define RCC_APB1ENR_USART3EN

#define RCC_APB1ENR_UART4EN_Pos

#define RCC_APB1ENR_UART4EN_Msk

#define RCC_APB1ENR_UART4EN

#define RCC_APB1ENR_UART5EN_Pos

#define RCC_APB1ENR_UART5EN_Msk

#define RCC_APB1ENR_UART5EN

#define RCC_APB1ENR_I2C1EN_Pos

#define RCC_APB1ENR_I2C1EN_Msk

#define RCC_APB1ENR_I2C1EN

#define RCC_APB1ENR_I2C2EN_Pos

#define RCC_APB1ENR_I2C2EN_Msk

#define RCC_APB1ENR_I2C2EN

#define RCC_APB1ENR_I2C3EN_Pos

#define RCC_APB1ENR_I2C3EN_Msk

#define RCC_APB1ENR_I2C3EN

#define RCC_APB1ENR_CAN1EN_Pos

#define RCC_APB1ENR_CAN1EN_Msk

#define RCC_APB1ENR_CAN1EN

#define RCC_APB1ENR_CAN2EN_Pos

#define RCC_APB1ENR_CAN2EN_Msk

#define RCC_APB1ENR_CAN2EN

#define RCC_APB1ENR_PWREN_Pos

#define RCC_APB1ENR_PWREN_Msk

#define RCC_APB1ENR_PWREN

#define RCC_APB1ENR_DACEN_Pos

#define RCC_APB1ENR_DACEN_Msk

#define RCC_APB1ENR_DACEN

#define RCC_APB1ENR_UART7EN_Pos

#define RCC_APB1ENR_UART7EN_Msk

#define RCC_APB1ENR_UART7EN

#define RCC_APB1ENR_UART8EN_Pos

#define RCC_APB1ENR_UART8EN_Msk

#define RCC_APB1ENR_UART8EN

Bit definition for RCC_APB2ENR register

#define RCC_APB2ENR_TIM1EN_Pos

#define RCC_APB2ENR_TIM1EN_Msk

#define RCC_APB2ENR_TIM1EN

#define RCC_APB2ENR_TIM8EN_Pos

#define RCC_APB2ENR_TIM8EN_Msk

#define RCC_APB2ENR_TIM8EN

#define RCC_APB2ENR_USART1EN_Pos

#define RCC_APB2ENR_USART1EN_Msk

#define RCC_APB2ENR_USART1EN

#define RCC_APB2ENR_USART6EN_Pos

#define RCC_APB2ENR_USART6EN_Msk

#define RCC_APB2ENR_USART6EN

#define RCC_APB2ENR_ADC1EN_Pos

#define RCC_APB2ENR_ADC1EN_Msk

#define RCC_APB2ENR_ADC1EN

#define RCC_APB2ENR_ADC2EN_Pos

#define RCC_APB2ENR_ADC2EN_Msk

#define RCC_APB2ENR_ADC2EN

#define RCC_APB2ENR_ADC3EN_Pos

#define RCC_APB2ENR_ADC3EN_Msk

#define RCC_APB2ENR_ADC3EN

#define RCC_APB2ENR_SDIOEN_Pos

#define RCC_APB2ENR_SDIOEN_Msk

#define RCC_APB2ENR_SDIOEN

#define RCC_APB2ENR_SPI1EN_Pos

#define RCC_APB2ENR_SPI1EN_Msk

#define RCC_APB2ENR_SPI1EN

#define RCC_APB2ENR_SPI4EN_Pos

#define RCC_APB2ENR_SPI4EN_Msk

#define RCC_APB2ENR_SPI4EN

#define RCC_APB2ENR_SYSCFGEN_Pos

#define RCC_APB2ENR_SYSCFGEN_Msk

#define RCC_APB2ENR_SYSCFGEN

#define RCC_APB2ENR_TIM9EN_Pos

#define RCC_APB2ENR_TIM9EN_Msk

#define RCC_APB2ENR_TIM9EN

#define RCC_APB2ENR_TIM10EN_Pos

#define RCC_APB2ENR_TIM10EN_Msk

#define RCC_APB2ENR_TIM10EN

#define RCC_APB2ENR_TIM11EN_Pos

#define RCC_APB2ENR_TIM11EN_Msk

#define RCC_APB2ENR_TIM11EN

#define RCC_APB2ENR_SPI5EN_Pos

#define RCC_APB2ENR_SPI5EN_Msk

#define RCC_APB2ENR_SPI5EN

#define RCC_APB2ENR_SPI6EN_Pos

#define RCC_APB2ENR_SPI6EN_Msk

#define RCC_APB2ENR_SPI6EN

#define RCC_APB2ENR_SAI1EN_Pos

#define RCC_APB2ENR_SAI1EN_Msk

#define RCC_APB2ENR_SAI1EN

#define RCC_APB2ENR_LTDCEN_Pos

#define RCC_APB2ENR_LTDCEN_Msk

#define RCC_APB2ENR_LTDCEN

Bit definition for RCC_AHB1LPENR register

#define RCC_AHB1LPENR_GPIOALPEN_Pos

#define RCC_AHB1LPENR_GPIOALPEN_Msk

#define RCC_AHB1LPENR_GPIOALPEN

#define RCC_AHB1LPENR_GPIOBLPEN_Pos

#define RCC_AHB1LPENR_GPIOBLPEN_Msk

#define RCC_AHB1LPENR_GPIOBLPEN

#define RCC_AHB1LPENR_GPIOCLPEN_Pos

#define RCC_AHB1LPENR_GPIOCLPEN_Msk

#define RCC_AHB1LPENR_GPIOCLPEN

#define RCC_AHB1LPENR_GPIODLPEN_Pos

#define RCC_AHB1LPENR_GPIODLPEN_Msk

#define RCC_AHB1LPENR_GPIODLPEN

#define RCC_AHB1LPENR_GPIOELPEN_Pos

#define RCC_AHB1LPENR_GPIOELPEN_Msk

#define RCC_AHB1LPENR_GPIOELPEN

#define RCC_AHB1LPENR_GPIOFLPEN_Pos

#define RCC_AHB1LPENR_GPIOFLPEN_Msk

#define RCC_AHB1LPENR_GPIOFLPEN

#define RCC_AHB1LPENR_GPIOGLPEN_Pos

#define RCC_AHB1LPENR_GPIOGLPEN_Msk

#define RCC_AHB1LPENR_GPIOGLPEN

#define RCC_AHB1LPENR_GPIOHLPEN_Pos

#define RCC_AHB1LPENR_GPIOHLPEN_Msk

#define RCC_AHB1LPENR_GPIOHLPEN

#define RCC_AHB1LPENR_GPIOILPEN_Pos

#define RCC_AHB1LPENR_GPIOILPEN_Msk

#define RCC_AHB1LPENR_GPIOILPEN

#define RCC_AHB1LPENR_GPIOJLPEN_Pos

#define RCC_AHB1LPENR_GPIOJLPEN_Msk

#define RCC_AHB1LPENR_GPIOJLPEN

#define RCC_AHB1LPENR_GPIOKLPEN_Pos

#define RCC_AHB1LPENR_GPIOKLPEN_Msk

#define RCC_AHB1LPENR_GPIOKLPEN

#define RCC_AHB1LPENR_CRCLPEN_Pos

#define RCC_AHB1LPENR_CRCLPEN_Msk

#define RCC_AHB1LPENR_CRCLPEN

#define RCC_AHB1LPENR_FLITFLPEN_Pos

#define RCC_AHB1LPENR_FLITFLPEN_Msk

#define RCC_AHB1LPENR_FLITFLPEN

#define RCC_AHB1LPENR_SRAM1LPEN_Pos

#define RCC_AHB1LPENR_SRAM1LPEN_Msk

#define RCC_AHB1LPENR_SRAM1LPEN

#define RCC_AHB1LPENR_SRAM2LPEN_Pos

#define RCC_AHB1LPENR_SRAM2LPEN_Msk

#define RCC_AHB1LPENR_SRAM2LPEN

#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos

#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk

#define RCC_AHB1LPENR_BKPSRAMLPEN

#define RCC_AHB1LPENR_SRAM3LPEN_Pos

#define RCC_AHB1LPENR_SRAM3LPEN_Msk

#define RCC_AHB1LPENR_SRAM3LPEN

#define RCC_AHB1LPENR_DMA1LPEN_Pos

#define RCC_AHB1LPENR_DMA1LPEN_Msk

#define RCC_AHB1LPENR_DMA1LPEN

#define RCC_AHB1LPENR_DMA2LPEN_Pos

#define RCC_AHB1LPENR_DMA2LPEN_Msk

#define RCC_AHB1LPENR_DMA2LPEN

#define RCC_AHB1LPENR_DMA2DLPEN_Pos

#define RCC_AHB1LPENR_DMA2DLPEN_Msk

#define RCC_AHB1LPENR_DMA2DLPEN

#define RCC_AHB1LPENR_ETHMACLPEN_Pos

#define RCC_AHB1LPENR_ETHMACLPEN_Msk

#define RCC_AHB1LPENR_ETHMACLPEN

#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos

#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk

#define RCC_AHB1LPENR_ETHMACTXLPEN

#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos

#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk

#define RCC_AHB1LPENR_ETHMACRXLPEN

#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos

#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk

#define RCC_AHB1LPENR_ETHMACPTPLPEN

#define RCC_AHB1LPENR_OTGHSLPEN_Pos

#define RCC_AHB1LPENR_OTGHSLPEN_Msk

#define RCC_AHB1LPENR_OTGHSLPEN

#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos

#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk

#define RCC_AHB1LPENR_OTGHSULPILPEN

Bit definition for RCC_AHB2LPENR register

#define RCC_AHB2LPENR_DCMILPEN_Pos

#define RCC_AHB2LPENR_DCMILPEN_Msk

#define RCC_AHB2LPENR_DCMILPEN

#define RCC_AHB2LPENR_RNGLPEN_Pos

#define RCC_AHB2LPENR_RNGLPEN_Msk

#define RCC_AHB2LPENR_RNGLPEN

#define RCC_AHB2LPENR_OTGFSLPEN_Pos

#define RCC_AHB2LPENR_OTGFSLPEN_Msk

#define RCC_AHB2LPENR_OTGFSLPEN

Bit definition for RCC_AHB3LPENR register

#define RCC_AHB3LPENR_FMCLPEN_Pos

#define RCC_AHB3LPENR_FMCLPEN_Msk

#define RCC_AHB3LPENR_FMCLPEN

Bit definition for RCC_APB1LPENR register

#define RCC_APB1LPENR_TIM2LPEN_Pos

#define RCC_APB1LPENR_TIM2LPEN_Msk

#define RCC_APB1LPENR_TIM2LPEN

#define RCC_APB1LPENR_TIM3LPEN_Pos

#define RCC_APB1LPENR_TIM3LPEN_Msk

#define RCC_APB1LPENR_TIM3LPEN

#define RCC_APB1LPENR_TIM4LPEN_Pos

#define RCC_APB1LPENR_TIM4LPEN_Msk

#define RCC_APB1LPENR_TIM4LPEN

#define RCC_APB1LPENR_TIM5LPEN_Pos

#define RCC_APB1LPENR_TIM5LPEN_Msk

#define RCC_APB1LPENR_TIM5LPEN

#define RCC_APB1LPENR_TIM6LPEN_Pos

#define RCC_APB1LPENR_TIM6LPEN_Msk

#define RCC_APB1LPENR_TIM6LPEN

#define RCC_APB1LPENR_TIM7LPEN_Pos

#define RCC_APB1LPENR_TIM7LPEN_Msk

#define RCC_APB1LPENR_TIM7LPEN

#define RCC_APB1LPENR_TIM12LPEN_Pos

#define RCC_APB1LPENR_TIM12LPEN_Msk

#define RCC_APB1LPENR_TIM12LPEN

#define RCC_APB1LPENR_TIM13LPEN_Pos

#define RCC_APB1LPENR_TIM13LPEN_Msk

#define RCC_APB1LPENR_TIM13LPEN

#define RCC_APB1LPENR_TIM14LPEN_Pos

#define RCC_APB1LPENR_TIM14LPEN_Msk

#define RCC_APB1LPENR_TIM14LPEN

#define RCC_APB1LPENR_WWDGLPEN_Pos

#define RCC_APB1LPENR_WWDGLPEN_Msk

#define RCC_APB1LPENR_WWDGLPEN

#define RCC_APB1LPENR_SPI2LPEN_Pos

#define RCC_APB1LPENR_SPI2LPEN_Msk

#define RCC_APB1LPENR_SPI2LPEN

#define RCC_APB1LPENR_SPI3LPEN_Pos

#define RCC_APB1LPENR_SPI3LPEN_Msk

#define RCC_APB1LPENR_SPI3LPEN

#define RCC_APB1LPENR_USART2LPEN_Pos

#define RCC_APB1LPENR_USART2LPEN_Msk

#define RCC_APB1LPENR_USART2LPEN

#define RCC_APB1LPENR_USART3LPEN_Pos

#define RCC_APB1LPENR_USART3LPEN_Msk

#define RCC_APB1LPENR_USART3LPEN

#define RCC_APB1LPENR_UART4LPEN_Pos

#define RCC_APB1LPENR_UART4LPEN_Msk

#define RCC_APB1LPENR_UART4LPEN

#define RCC_APB1LPENR_UART5LPEN_Pos

#define RCC_APB1LPENR_UART5LPEN_Msk

#define RCC_APB1LPENR_UART5LPEN

#define RCC_APB1LPENR_I2C1LPEN_Pos

#define RCC_APB1LPENR_I2C1LPEN_Msk

#define RCC_APB1LPENR_I2C1LPEN

#define RCC_APB1LPENR_I2C2LPEN_Pos

#define RCC_APB1LPENR_I2C2LPEN_Msk

#define RCC_APB1LPENR_I2C2LPEN

#define RCC_APB1LPENR_I2C3LPEN_Pos

#define RCC_APB1LPENR_I2C3LPEN_Msk

#define RCC_APB1LPENR_I2C3LPEN

#define RCC_APB1LPENR_CAN1LPEN_Pos

#define RCC_APB1LPENR_CAN1LPEN_Msk

#define RCC_APB1LPENR_CAN1LPEN

#define RCC_APB1LPENR_CAN2LPEN_Pos

#define RCC_APB1LPENR_CAN2LPEN_Msk

#define RCC_APB1LPENR_CAN2LPEN

#define RCC_APB1LPENR_PWRLPEN_Pos

#define RCC_APB1LPENR_PWRLPEN_Msk

#define RCC_APB1LPENR_PWRLPEN

#define RCC_APB1LPENR_DACLPEN_Pos

#define RCC_APB1LPENR_DACLPEN_Msk

#define RCC_APB1LPENR_DACLPEN

#define RCC_APB1LPENR_UART7LPEN_Pos

#define RCC_APB1LPENR_UART7LPEN_Msk

#define RCC_APB1LPENR_UART7LPEN

#define RCC_APB1LPENR_UART8LPEN_Pos

#define RCC_APB1LPENR_UART8LPEN_Msk

#define RCC_APB1LPENR_UART8LPEN

Bit definition for RCC_APB2LPENR register

#define RCC_APB2LPENR_TIM1LPEN_Pos

#define RCC_APB2LPENR_TIM1LPEN_Msk

#define RCC_APB2LPENR_TIM1LPEN

#define RCC_APB2LPENR_TIM8LPEN_Pos

#define RCC_APB2LPENR_TIM8LPEN_Msk

#define RCC_APB2LPENR_TIM8LPEN

#define RCC_APB2LPENR_USART1LPEN_Pos

#define RCC_APB2LPENR_USART1LPEN_Msk

#define RCC_APB2LPENR_USART1LPEN

#define RCC_APB2LPENR_USART6LPEN_Pos

#define RCC_APB2LPENR_USART6LPEN_Msk

#define RCC_APB2LPENR_USART6LPEN

#define RCC_APB2LPENR_ADC1LPEN_Pos

#define RCC_APB2LPENR_ADC1LPEN_Msk

#define RCC_APB2LPENR_ADC1LPEN

#define RCC_APB2LPENR_ADC2LPEN_Pos

#define RCC_APB2LPENR_ADC2LPEN_Msk

#define RCC_APB2LPENR_ADC2LPEN

#define RCC_APB2LPENR_ADC3LPEN_Pos

#define RCC_APB2LPENR_ADC3LPEN_Msk

#define RCC_APB2LPENR_ADC3LPEN

#define RCC_APB2LPENR_SDIOLPEN_Pos

#define RCC_APB2LPENR_SDIOLPEN_Msk

#define RCC_APB2LPENR_SDIOLPEN

#define RCC_APB2LPENR_SPI1LPEN_Pos

#define RCC_APB2LPENR_SPI1LPEN_Msk

#define RCC_APB2LPENR_SPI1LPEN

#define RCC_APB2LPENR_SPI4LPEN_Pos

#define RCC_APB2LPENR_SPI4LPEN_Msk

#define RCC_APB2LPENR_SPI4LPEN

#define RCC_APB2LPENR_SYSCFGLPEN_Pos

#define RCC_APB2LPENR_SYSCFGLPEN_Msk

#define RCC_APB2LPENR_SYSCFGLPEN

#define RCC_APB2LPENR_TIM9LPEN_Pos

#define RCC_APB2LPENR_TIM9LPEN_Msk

#define RCC_APB2LPENR_TIM9LPEN

#define RCC_APB2LPENR_TIM10LPEN_Pos

#define RCC_APB2LPENR_TIM10LPEN_Msk

#define RCC_APB2LPENR_TIM10LPEN

#define RCC_APB2LPENR_TIM11LPEN_Pos

#define RCC_APB2LPENR_TIM11LPEN_Msk

#define RCC_APB2LPENR_TIM11LPEN

#define RCC_APB2LPENR_SPI5LPEN_Pos

#define RCC_APB2LPENR_SPI5LPEN_Msk

#define RCC_APB2LPENR_SPI5LPEN

#define RCC_APB2LPENR_SPI6LPEN_Pos

#define RCC_APB2LPENR_SPI6LPEN_Msk

#define RCC_APB2LPENR_SPI6LPEN

#define RCC_APB2LPENR_SAI1LPEN_Pos

#define RCC_APB2LPENR_SAI1LPEN_Msk

#define RCC_APB2LPENR_SAI1LPEN

#define RCC_APB2LPENR_LTDCLPEN_Pos

#define RCC_APB2LPENR_LTDCLPEN_Msk

#define RCC_APB2LPENR_LTDCLPEN

Bit definition for RCC_BDCR register

#define RCC_BDCR_LSEON_Pos

#define RCC_BDCR_LSEON_Msk

#define RCC_BDCR_LSEON

#define RCC_BDCR_LSERDY_Pos

#define RCC_BDCR_LSERDY_Msk

#define RCC_BDCR_LSERDY

#define RCC_BDCR_LSEBYP_Pos

#define RCC_BDCR_LSEBYP_Msk

#define RCC_BDCR_LSEBYP

#define RCC_BDCR_RTCSEL_Pos

#define RCC_BDCR_RTCSEL_Msk

#define RCC_BDCR_RTCSEL

#define RCC_BDCR_RTCSEL_0

#define RCC_BDCR_RTCSEL_1

#define RCC_BDCR_RTCEN_Pos

#define RCC_BDCR_RTCEN_Msk

#define RCC_BDCR_RTCEN

#define RCC_BDCR_BDRST_Pos

#define RCC_BDCR_BDRST_Msk

#define RCC_BDCR_BDRST

Bit definition for RCC_CSR register

#define RCC_CSR_LSION_Pos

#define RCC_CSR_LSION_Msk

#define RCC_CSR_LSION

#define RCC_CSR_LSIRDY_Pos

#define RCC_CSR_LSIRDY_Msk

#define RCC_CSR_LSIRDY

#define RCC_CSR_RMVF_Pos

#define RCC_CSR_RMVF_Msk

#define RCC_CSR_RMVF

#define RCC_CSR_BORRSTF_Pos

#define RCC_CSR_BORRSTF_Msk

#define RCC_CSR_BORRSTF

#define RCC_CSR_PINRSTF_Pos

#define RCC_CSR_PINRSTF_Msk

#define RCC_CSR_PINRSTF

#define RCC_CSR_PORRSTF_Pos

#define RCC_CSR_PORRSTF_Msk

#define RCC_CSR_PORRSTF

#define RCC_CSR_SFTRSTF_Pos

#define RCC_CSR_SFTRSTF_Msk

#define RCC_CSR_SFTRSTF

#define RCC_CSR_IWDGRSTF_Pos

#define RCC_CSR_IWDGRSTF_Msk

#define RCC_CSR_IWDGRSTF

#define RCC_CSR_WWDGRSTF_Pos

#define RCC_CSR_WWDGRSTF_Msk

#define RCC_CSR_WWDGRSTF

#define RCC_CSR_LPWRRSTF_Pos

#define RCC_CSR_LPWRRSTF_Msk

#define RCC_CSR_LPWRRSTF

#define RCC_CSR_PADRSTF

#define RCC_CSR_WDGRSTF

Bit definition for RCC_SSCGR register

#define RCC_SSCGR_MODPER_Pos

#define RCC_SSCGR_MODPER_Msk

#define RCC_SSCGR_MODPER

#define RCC_SSCGR_INCSTEP_Pos

#define RCC_SSCGR_INCSTEP_Msk

#define RCC_SSCGR_INCSTEP

#define RCC_SSCGR_SPREADSEL_Pos

#define RCC_SSCGR_SPREADSEL_Msk

#define RCC_SSCGR_SPREADSEL

#define RCC_SSCGR_SSCGEN_Pos

#define RCC_SSCGR_SSCGEN_Msk

#define RCC_SSCGR_SSCGEN

Bit definition for RCC_PLLI2SCFGR register

#define RCC_PLLI2SCFGR_PLLI2SN_Pos

#define RCC_PLLI2SCFGR_PLLI2SN_Msk

#define RCC_PLLI2SCFGR_PLLI2SN

#define RCC_PLLI2SCFGR_PLLI2SN_0

#define RCC_PLLI2SCFGR_PLLI2SN_1

#define RCC_PLLI2SCFGR_PLLI2SN_2

#define RCC_PLLI2SCFGR_PLLI2SN_3

#define RCC_PLLI2SCFGR_PLLI2SN_4

#define RCC_PLLI2SCFGR_PLLI2SN_5

#define RCC_PLLI2SCFGR_PLLI2SN_6

#define RCC_PLLI2SCFGR_PLLI2SN_7

#define RCC_PLLI2SCFGR_PLLI2SN_8

#define RCC_PLLI2SCFGR_PLLI2SQ_Pos

#define RCC_PLLI2SCFGR_PLLI2SQ_Msk

#define RCC_PLLI2SCFGR_PLLI2SQ

#define RCC_PLLI2SCFGR_PLLI2SQ_0

#define RCC_PLLI2SCFGR_PLLI2SQ_1

#define RCC_PLLI2SCFGR_PLLI2SQ_2

#define RCC_PLLI2SCFGR_PLLI2SQ_3

#define RCC_PLLI2SCFGR_PLLI2SR_Pos

#define RCC_PLLI2SCFGR_PLLI2SR_Msk

#define RCC_PLLI2SCFGR_PLLI2SR

#define RCC_PLLI2SCFGR_PLLI2SR_0

#define RCC_PLLI2SCFGR_PLLI2SR_1

#define RCC_PLLI2SCFGR_PLLI2SR_2

Bit definition for RCC_PLLSAICFGR register

#define RCC_PLLSAICFGR_PLLSAIN_Pos

#define RCC_PLLSAICFGR_PLLSAIN_Msk

#define RCC_PLLSAICFGR_PLLSAIN

#define RCC_PLLSAICFGR_PLLSAIN_0

#define RCC_PLLSAICFGR_PLLSAIN_1

#define RCC_PLLSAICFGR_PLLSAIN_2

#define RCC_PLLSAICFGR_PLLSAIN_3

#define RCC_PLLSAICFGR_PLLSAIN_4

#define RCC_PLLSAICFGR_PLLSAIN_5

#define RCC_PLLSAICFGR_PLLSAIN_6

#define RCC_PLLSAICFGR_PLLSAIN_7

#define RCC_PLLSAICFGR_PLLSAIN_8

#define RCC_PLLSAICFGR_PLLSAIQ_Pos

#define RCC_PLLSAICFGR_PLLSAIQ_Msk

#define RCC_PLLSAICFGR_PLLSAIQ

#define RCC_PLLSAICFGR_PLLSAIQ_0

#define RCC_PLLSAICFGR_PLLSAIQ_1

#define RCC_PLLSAICFGR_PLLSAIQ_2

#define RCC_PLLSAICFGR_PLLSAIQ_3

#define RCC_PLLSAICFGR_PLLSAIR_Pos

#define RCC_PLLSAICFGR_PLLSAIR_Msk

#define RCC_PLLSAICFGR_PLLSAIR

#define RCC_PLLSAICFGR_PLLSAIR_0

#define RCC_PLLSAICFGR_PLLSAIR_1

#define RCC_PLLSAICFGR_PLLSAIR_2

Bit definition for RCC_DCKCFGR register

#define RCC_DCKCFGR_PLLI2SDIVQ_Pos

#define RCC_DCKCFGR_PLLI2SDIVQ_Msk

#define RCC_DCKCFGR_PLLI2SDIVQ

#define RCC_DCKCFGR_PLLI2SDIVQ_0

#define RCC_DCKCFGR_PLLI2SDIVQ_1

#define RCC_DCKCFGR_PLLI2SDIVQ_2

#define RCC_DCKCFGR_PLLI2SDIVQ_3

#define RCC_DCKCFGR_PLLI2SDIVQ_4

#define RCC_DCKCFGR_PLLSAIDIVQ_Pos

#define RCC_DCKCFGR_PLLSAIDIVQ_Msk

#define RCC_DCKCFGR_PLLSAIDIVQ

#define RCC_DCKCFGR_PLLSAIDIVQ_0

#define RCC_DCKCFGR_PLLSAIDIVQ_1

#define RCC_DCKCFGR_PLLSAIDIVQ_2

#define RCC_DCKCFGR_PLLSAIDIVQ_3

#define RCC_DCKCFGR_PLLSAIDIVQ_4

#define RCC_DCKCFGR_PLLSAIDIVR_Pos

#define RCC_DCKCFGR_PLLSAIDIVR_Msk

#define RCC_DCKCFGR_PLLSAIDIVR

#define RCC_DCKCFGR_PLLSAIDIVR_0

#define RCC_DCKCFGR_PLLSAIDIVR_1

#define RCC_DCKCFGR_SAI1ASRC_Pos

#define RCC_DCKCFGR_SAI1ASRC_Msk

#define RCC_DCKCFGR_SAI1ASRC

#define RCC_DCKCFGR_SAI1ASRC_0

#define RCC_DCKCFGR_SAI1ASRC_1

#define RCC_DCKCFGR_SAI1BSRC_Pos

#define RCC_DCKCFGR_SAI1BSRC_Msk

#define RCC_DCKCFGR_SAI1BSRC

#define RCC_DCKCFGR_SAI1BSRC_0

#define RCC_DCKCFGR_SAI1BSRC_1

#define RCC_DCKCFGR_TIMPRE_Pos

#define RCC_DCKCFGR_TIMPRE_Msk

#define RCC_DCKCFGR_TIMPRE

...

Bits definition for RNG_CR register

#define RNG_CR_RNGEN_Pos

#define RNG_CR_RNGEN_Msk

#define RNG_CR_RNGEN

#define RNG_CR_IE_Pos

#define RNG_CR_IE_Msk

#define RNG_CR_IE

Bits definition for RNG_SR register

#define RNG_SR_DRDY_Pos

#define RNG_SR_DRDY_Msk

#define RNG_SR_DRDY

#define RNG_SR_CECS_Pos

#define RNG_SR_CECS_Msk

#define RNG_SR_CECS

#define RNG_SR_SECS_Pos

#define RNG_SR_SECS_Msk

#define RNG_SR_SECS

#define RNG_SR_CEIS_Pos

#define RNG_SR_CEIS_Msk

#define RNG_SR_CEIS

#define RNG_SR_SEIS_Pos

#define RNG_SR_SEIS_Msk

#define RNG_SR_SEIS

...

#define RTC_TAMPER2_SUPPORT

#define RTC_AF2_SUPPORT

Bits definition for RTC_TR register

#define RTC_TR_PM_Pos

#define RTC_TR_PM_Msk

#define RTC_TR_PM

#define RTC_TR_HT_Pos

#define RTC_TR_HT_Msk

#define RTC_TR_HT

#define RTC_TR_HT_0

#define RTC_TR_HT_1

#define RTC_TR_HU_Pos

#define RTC_TR_HU_Msk

#define RTC_TR_HU

#define RTC_TR_HU_0

#define RTC_TR_HU_1

#define RTC_TR_HU_2

#define RTC_TR_HU_3

#define RTC_TR_MNT_Pos

#define RTC_TR_MNT_Msk

#define RTC_TR_MNT

#define RTC_TR_MNT_0

#define RTC_TR_MNT_1

#define RTC_TR_MNT_2

#define RTC_TR_MNU_Pos

#define RTC_TR_MNU_Msk

#define RTC_TR_MNU

#define RTC_TR_MNU_0

#define RTC_TR_MNU_1

#define RTC_TR_MNU_2

#define RTC_TR_MNU_3

#define RTC_TR_ST_Pos

#define RTC_TR_ST_Msk

#define RTC_TR_ST

#define RTC_TR_ST_0

#define RTC_TR_ST_1

#define RTC_TR_ST_2

#define RTC_TR_SU_Pos

#define RTC_TR_SU_Msk

#define RTC_TR_SU

#define RTC_TR_SU_0

#define RTC_TR_SU_1

#define RTC_TR_SU_2

#define RTC_TR_SU_3

Bits definition for RTC_DR register

#define RTC_DR_YT_Pos

#define RTC_DR_YT_Msk

#define RTC_DR_YT

#define RTC_DR_YT_0

#define RTC_DR_YT_1

#define RTC_DR_YT_2

#define RTC_DR_YT_3

#define RTC_DR_YU_Pos

#define RTC_DR_YU_Msk

#define RTC_DR_YU

#define RTC_DR_YU_0

#define RTC_DR_YU_1

#define RTC_DR_YU_2

#define RTC_DR_YU_3

#define RTC_DR_WDU_Pos

#define RTC_DR_WDU_Msk

#define RTC_DR_WDU

#define RTC_DR_WDU_0

#define RTC_DR_WDU_1

#define RTC_DR_WDU_2

#define RTC_DR_MT_Pos

#define RTC_DR_MT_Msk

#define RTC_DR_MT

#define RTC_DR_MU_Pos

#define RTC_DR_MU_Msk

#define RTC_DR_MU

#define RTC_DR_MU_0

#define RTC_DR_MU_1

#define RTC_DR_MU_2

#define RTC_DR_MU_3

#define RTC_DR_DT_Pos

#define RTC_DR_DT_Msk

#define RTC_DR_DT

#define RTC_DR_DT_0

#define RTC_DR_DT_1

#define RTC_DR_DU_Pos

#define RTC_DR_DU_Msk

#define RTC_DR_DU

#define RTC_DR_DU_0

#define RTC_DR_DU_1

#define RTC_DR_DU_2

#define RTC_DR_DU_3

Bits definition for RTC_CR register

#define RTC_CR_COE_Pos

#define RTC_CR_COE_Msk

#define RTC_CR_COE

#define RTC_CR_OSEL_Pos

#define RTC_CR_OSEL_Msk

#define RTC_CR_OSEL

#define RTC_CR_OSEL_0

#define RTC_CR_OSEL_1

#define RTC_CR_POL_Pos

#define RTC_CR_POL_Msk

#define RTC_CR_POL

#define RTC_CR_COSEL_Pos

#define RTC_CR_COSEL_Msk

#define RTC_CR_COSEL

#define RTC_CR_BKP_Pos

#define RTC_CR_BKP_Msk

#define RTC_CR_BKP

#define RTC_CR_SUB1H_Pos

#define RTC_CR_SUB1H_Msk

#define RTC_CR_SUB1H

#define RTC_CR_ADD1H_Pos

#define RTC_CR_ADD1H_Msk

#define RTC_CR_ADD1H

#define RTC_CR_TSIE_Pos

#define RTC_CR_TSIE_Msk

#define RTC_CR_TSIE

#define RTC_CR_WUTIE_Pos

#define RTC_CR_WUTIE_Msk

#define RTC_CR_WUTIE

#define RTC_CR_ALRBIE_Pos

#define RTC_CR_ALRBIE_Msk

#define RTC_CR_ALRBIE

#define RTC_CR_ALRAIE_Pos

#define RTC_CR_ALRAIE_Msk

#define RTC_CR_ALRAIE

#define RTC_CR_TSE_Pos

#define RTC_CR_TSE_Msk

#define RTC_CR_TSE

#define RTC_CR_WUTE_Pos

#define RTC_CR_WUTE_Msk

#define RTC_CR_WUTE

#define RTC_CR_ALRBE_Pos

#define RTC_CR_ALRBE_Msk

#define RTC_CR_ALRBE

#define RTC_CR_ALRAE_Pos

#define RTC_CR_ALRAE_Msk

#define RTC_CR_ALRAE

#define RTC_CR_DCE_Pos

#define RTC_CR_DCE_Msk

#define RTC_CR_DCE

#define RTC_CR_FMT_Pos

#define RTC_CR_FMT_Msk

#define RTC_CR_FMT

#define RTC_CR_BYPSHAD_Pos

#define RTC_CR_BYPSHAD_Msk

#define RTC_CR_BYPSHAD

#define RTC_CR_REFCKON_Pos

#define RTC_CR_REFCKON_Msk

#define RTC_CR_REFCKON

#define RTC_CR_TSEDGE_Pos

#define RTC_CR_TSEDGE_Msk

#define RTC_CR_TSEDGE

#define RTC_CR_WUCKSEL_Pos

#define RTC_CR_WUCKSEL_Msk

#define RTC_CR_WUCKSEL

#define RTC_CR_WUCKSEL_0

#define RTC_CR_WUCKSEL_1

#define RTC_CR_WUCKSEL_2

#define RTC_CR_BCK

Bits definition for RTC_ISR register

#define RTC_ISR_RECALPF_Pos

#define RTC_ISR_RECALPF_Msk

#define RTC_ISR_RECALPF

#define RTC_ISR_TAMP1F_Pos

#define RTC_ISR_TAMP1F_Msk

#define RTC_ISR_TAMP1F

#define RTC_ISR_TAMP2F_Pos

#define RTC_ISR_TAMP2F_Msk

#define RTC_ISR_TAMP2F

#define RTC_ISR_TSOVF_Pos

#define RTC_ISR_TSOVF_Msk

#define RTC_ISR_TSOVF

#define RTC_ISR_TSF_Pos

#define RTC_ISR_TSF_Msk

#define RTC_ISR_TSF

#define RTC_ISR_WUTF_Pos

#define RTC_ISR_WUTF_Msk

#define RTC_ISR_WUTF

#define RTC_ISR_ALRBF_Pos

#define RTC_ISR_ALRBF_Msk

#define RTC_ISR_ALRBF

#define RTC_ISR_ALRAF_Pos

#define RTC_ISR_ALRAF_Msk

#define RTC_ISR_ALRAF

#define RTC_ISR_INIT_Pos

#define RTC_ISR_INIT_Msk

#define RTC_ISR_INIT

#define RTC_ISR_INITF_Pos

#define RTC_ISR_INITF_Msk

#define RTC_ISR_INITF

#define RTC_ISR_RSF_Pos

#define RTC_ISR_RSF_Msk

#define RTC_ISR_RSF

#define RTC_ISR_INITS_Pos

#define RTC_ISR_INITS_Msk

#define RTC_ISR_INITS

#define RTC_ISR_SHPF_Pos

#define RTC_ISR_SHPF_Msk

#define RTC_ISR_SHPF

#define RTC_ISR_WUTWF_Pos

#define RTC_ISR_WUTWF_Msk

#define RTC_ISR_WUTWF

#define RTC_ISR_ALRBWF_Pos

#define RTC_ISR_ALRBWF_Msk

#define RTC_ISR_ALRBWF

#define RTC_ISR_ALRAWF_Pos

#define RTC_ISR_ALRAWF_Msk

#define RTC_ISR_ALRAWF

Bits definition for RTC_PRER register

#define RTC_PRER_PREDIV_A_Pos

#define RTC_PRER_PREDIV_A_Msk

#define RTC_PRER_PREDIV_A

#define RTC_PRER_PREDIV_S_Pos

#define RTC_PRER_PREDIV_S_Msk

#define RTC_PRER_PREDIV_S

Bits definition for RTC_WUTR register

#define RTC_WUTR_WUT_Pos

#define RTC_WUTR_WUT_Msk

#define RTC_WUTR_WUT

Bits definition for RTC_CALIBR register

#define RTC_CALIBR_DCS_Pos

#define RTC_CALIBR_DCS_Msk

#define RTC_CALIBR_DCS

#define RTC_CALIBR_DC_Pos

#define RTC_CALIBR_DC_Msk

#define RTC_CALIBR_DC

Bits definition for RTC_ALRMAR register

#define RTC_ALRMAR_MSK4_Pos

#define RTC_ALRMAR_MSK4_Msk

#define RTC_ALRMAR_MSK4

#define RTC_ALRMAR_WDSEL_Pos

#define RTC_ALRMAR_WDSEL_Msk

#define RTC_ALRMAR_WDSEL

#define RTC_ALRMAR_DT_Pos

#define RTC_ALRMAR_DT_Msk

#define RTC_ALRMAR_DT

#define RTC_ALRMAR_DT_0

#define RTC_ALRMAR_DT_1

#define RTC_ALRMAR_DU_Pos

#define RTC_ALRMAR_DU_Msk

#define RTC_ALRMAR_DU

#define RTC_ALRMAR_DU_0

#define RTC_ALRMAR_DU_1

#define RTC_ALRMAR_DU_2

#define RTC_ALRMAR_DU_3

#define RTC_ALRMAR_MSK3_Pos

#define RTC_ALRMAR_MSK3_Msk

#define RTC_ALRMAR_MSK3

#define RTC_ALRMAR_PM_Pos

#define RTC_ALRMAR_PM_Msk

#define RTC_ALRMAR_PM

#define RTC_ALRMAR_HT_Pos

#define RTC_ALRMAR_HT_Msk

#define RTC_ALRMAR_HT

#define RTC_ALRMAR_HT_0

#define RTC_ALRMAR_HT_1

#define RTC_ALRMAR_HU_Pos

#define RTC_ALRMAR_HU_Msk

#define RTC_ALRMAR_HU

#define RTC_ALRMAR_HU_0

#define RTC_ALRMAR_HU_1

#define RTC_ALRMAR_HU_2

#define RTC_ALRMAR_HU_3

#define RTC_ALRMAR_MSK2_Pos

#define RTC_ALRMAR_MSK2_Msk

#define RTC_ALRMAR_MSK2

#define RTC_ALRMAR_MNT_Pos

#define RTC_ALRMAR_MNT_Msk

#define RTC_ALRMAR_MNT

#define RTC_ALRMAR_MNT_0

#define RTC_ALRMAR_MNT_1

#define RTC_ALRMAR_MNT_2

#define RTC_ALRMAR_MNU_Pos

#define RTC_ALRMAR_MNU_Msk

#define RTC_ALRMAR_MNU

#define RTC_ALRMAR_MNU_0

#define RTC_ALRMAR_MNU_1

#define RTC_ALRMAR_MNU_2

#define RTC_ALRMAR_MNU_3

#define RTC_ALRMAR_MSK1_Pos

#define RTC_ALRMAR_MSK1_Msk

#define RTC_ALRMAR_MSK1

#define RTC_ALRMAR_ST_Pos

#define RTC_ALRMAR_ST_Msk

#define RTC_ALRMAR_ST

#define RTC_ALRMAR_ST_0

#define RTC_ALRMAR_ST_1

#define RTC_ALRMAR_ST_2

#define RTC_ALRMAR_SU_Pos

#define RTC_ALRMAR_SU_Msk

#define RTC_ALRMAR_SU

#define RTC_ALRMAR_SU_0

#define RTC_ALRMAR_SU_1

#define RTC_ALRMAR_SU_2

#define RTC_ALRMAR_SU_3

Bits definition for RTC_ALRMBR register

#define RTC_ALRMBR_MSK4_Pos

#define RTC_ALRMBR_MSK4_Msk

#define RTC_ALRMBR_MSK4

#define RTC_ALRMBR_WDSEL_Pos

#define RTC_ALRMBR_WDSEL_Msk

#define RTC_ALRMBR_WDSEL

#define RTC_ALRMBR_DT_Pos

#define RTC_ALRMBR_DT_Msk

#define RTC_ALRMBR_DT

#define RTC_ALRMBR_DT_0

#define RTC_ALRMBR_DT_1

#define RTC_ALRMBR_DU_Pos

#define RTC_ALRMBR_DU_Msk

#define RTC_ALRMBR_DU

#define RTC_ALRMBR_DU_0

#define RTC_ALRMBR_DU_1

#define RTC_ALRMBR_DU_2

#define RTC_ALRMBR_DU_3

#define RTC_ALRMBR_MSK3_Pos

#define RTC_ALRMBR_MSK3_Msk

#define RTC_ALRMBR_MSK3

#define RTC_ALRMBR_PM_Pos

#define RTC_ALRMBR_PM_Msk

#define RTC_ALRMBR_PM

#define RTC_ALRMBR_HT_Pos

#define RTC_ALRMBR_HT_Msk

#define RTC_ALRMBR_HT

#define RTC_ALRMBR_HT_0

#define RTC_ALRMBR_HT_1

#define RTC_ALRMBR_HU_Pos

#define RTC_ALRMBR_HU_Msk

#define RTC_ALRMBR_HU

#define RTC_ALRMBR_HU_0

#define RTC_ALRMBR_HU_1

#define RTC_ALRMBR_HU_2

#define RTC_ALRMBR_HU_3

#define RTC_ALRMBR_MSK2_Pos

#define RTC_ALRMBR_MSK2_Msk

#define RTC_ALRMBR_MSK2

#define RTC_ALRMBR_MNT_Pos

#define RTC_ALRMBR_MNT_Msk

#define RTC_ALRMBR_MNT

#define RTC_ALRMBR_MNT_0

#define RTC_ALRMBR_MNT_1

#define RTC_ALRMBR_MNT_2

#define RTC_ALRMBR_MNU_Pos

#define RTC_ALRMBR_MNU_Msk

#define RTC_ALRMBR_MNU

#define RTC_ALRMBR_MNU_0

#define RTC_ALRMBR_MNU_1

#define RTC_ALRMBR_MNU_2

#define RTC_ALRMBR_MNU_3

#define RTC_ALRMBR_MSK1_Pos

#define RTC_ALRMBR_MSK1_Msk

#define RTC_ALRMBR_MSK1

#define RTC_ALRMBR_ST_Pos

#define RTC_ALRMBR_ST_Msk

#define RTC_ALRMBR_ST

#define RTC_ALRMBR_ST_0

#define RTC_ALRMBR_ST_1

#define RTC_ALRMBR_ST_2

#define RTC_ALRMBR_SU_Pos

#define RTC_ALRMBR_SU_Msk

#define RTC_ALRMBR_SU

#define RTC_ALRMBR_SU_0

#define RTC_ALRMBR_SU_1

#define RTC_ALRMBR_SU_2

#define RTC_ALRMBR_SU_3

Bits definition for RTC_WPR register

#define RTC_WPR_KEY_Pos

#define RTC_WPR_KEY_Msk

#define RTC_WPR_KEY

Bits definition for RTC_SSR register

#define RTC_SSR_SS_Pos

#define RTC_SSR_SS_Msk

#define RTC_SSR_SS

Bits definition for RTC_SHIFTR register

#define RTC_SHIFTR_SUBFS_Pos

#define RTC_SHIFTR_SUBFS_Msk

#define RTC_SHIFTR_SUBFS

#define RTC_SHIFTR_ADD1S_Pos

#define RTC_SHIFTR_ADD1S_Msk

#define RTC_SHIFTR_ADD1S

Bits definition for RTC_TSTR register

#define RTC_TSTR_PM_Pos

#define RTC_TSTR_PM_Msk

#define RTC_TSTR_PM

#define RTC_TSTR_HT_Pos

#define RTC_TSTR_HT_Msk

#define RTC_TSTR_HT

#define RTC_TSTR_HT_0

#define RTC_TSTR_HT_1

#define RTC_TSTR_HU_Pos

#define RTC_TSTR_HU_Msk

#define RTC_TSTR_HU

#define RTC_TSTR_HU_0

#define RTC_TSTR_HU_1

#define RTC_TSTR_HU_2

#define RTC_TSTR_HU_3

#define RTC_TSTR_MNT_Pos

#define RTC_TSTR_MNT_Msk

#define RTC_TSTR_MNT

#define RTC_TSTR_MNT_0

#define RTC_TSTR_MNT_1

#define RTC_TSTR_MNT_2

#define RTC_TSTR_MNU_Pos

#define RTC_TSTR_MNU_Msk

#define RTC_TSTR_MNU

#define RTC_TSTR_MNU_0

#define RTC_TSTR_MNU_1

#define RTC_TSTR_MNU_2

#define RTC_TSTR_MNU_3

#define RTC_TSTR_ST_Pos

#define RTC_TSTR_ST_Msk

#define RTC_TSTR_ST

#define RTC_TSTR_ST_0

#define RTC_TSTR_ST_1

#define RTC_TSTR_ST_2

#define RTC_TSTR_SU_Pos

#define RTC_TSTR_SU_Msk

#define RTC_TSTR_SU

#define RTC_TSTR_SU_0

#define RTC_TSTR_SU_1

#define RTC_TSTR_SU_2

#define RTC_TSTR_SU_3

Bits definition for RTC_TSDR register

#define RTC_TSDR_WDU_Pos

#define RTC_TSDR_WDU_Msk

#define RTC_TSDR_WDU

#define RTC_TSDR_WDU_0

#define RTC_TSDR_WDU_1

#define RTC_TSDR_WDU_2

#define RTC_TSDR_MT_Pos

#define RTC_TSDR_MT_Msk

#define RTC_TSDR_MT

#define RTC_TSDR_MU_Pos

#define RTC_TSDR_MU_Msk

#define RTC_TSDR_MU

#define RTC_TSDR_MU_0

#define RTC_TSDR_MU_1

#define RTC_TSDR_MU_2

#define RTC_TSDR_MU_3

#define RTC_TSDR_DT_Pos

#define RTC_TSDR_DT_Msk

#define RTC_TSDR_DT

#define RTC_TSDR_DT_0

#define RTC_TSDR_DT_1

#define RTC_TSDR_DU_Pos

#define RTC_TSDR_DU_Msk

#define RTC_TSDR_DU

#define RTC_TSDR_DU_0

#define RTC_TSDR_DU_1

#define RTC_TSDR_DU_2

#define RTC_TSDR_DU_3

Bits definition for RTC_TSSSR register

#define RTC_TSSSR_SS_Pos

#define RTC_TSSSR_SS_Msk

#define RTC_TSSSR_SS

Bits definition for RTC_CAL register

#define RTC_CALR_CALP_Pos

#define RTC_CALR_CALP_Msk

#define RTC_CALR_CALP

#define RTC_CALR_CALW8_Pos

#define RTC_CALR_CALW8_Msk

#define RTC_CALR_CALW8

#define RTC_CALR_CALW16_Pos

#define RTC_CALR_CALW16_Msk

#define RTC_CALR_CALW16

#define RTC_CALR_CALM_Pos

#define RTC_CALR_CALM_Msk

#define RTC_CALR_CALM

#define RTC_CALR_CALM_0

#define RTC_CALR_CALM_1

#define RTC_CALR_CALM_2

#define RTC_CALR_CALM_3

#define RTC_CALR_CALM_4

#define RTC_CALR_CALM_5

#define RTC_CALR_CALM_6

#define RTC_CALR_CALM_7

#define RTC_CALR_CALM_8

Bits definition for RTC_TAFCR register

#define RTC_TAFCR_ALARMOUTTYPE_Pos

#define RTC_TAFCR_ALARMOUTTYPE_Msk

#define RTC_TAFCR_ALARMOUTTYPE

#define RTC_TAFCR_TSINSEL_Pos

#define RTC_TAFCR_TSINSEL_Msk

#define RTC_TAFCR_TSINSEL

#define RTC_TAFCR_TAMP1INSEL_Pos

#define RTC_TAFCR_TAMP1INSEL_Msk

#define RTC_TAFCR_TAMP1INSEL

#define RTC_TAFCR_TAMPPUDIS_Pos

#define RTC_TAFCR_TAMPPUDIS_Msk

#define RTC_TAFCR_TAMPPUDIS

#define RTC_TAFCR_TAMPPRCH_Pos

#define RTC_TAFCR_TAMPPRCH_Msk

#define RTC_TAFCR_TAMPPRCH

#define RTC_TAFCR_TAMPPRCH_0

#define RTC_TAFCR_TAMPPRCH_1

#define RTC_TAFCR_TAMPFLT_Pos

#define RTC_TAFCR_TAMPFLT_Msk

#define RTC_TAFCR_TAMPFLT

#define RTC_TAFCR_TAMPFLT_0

#define RTC_TAFCR_TAMPFLT_1

#define RTC_TAFCR_TAMPFREQ_Pos

#define RTC_TAFCR_TAMPFREQ_Msk

#define RTC_TAFCR_TAMPFREQ

#define RTC_TAFCR_TAMPFREQ_0

#define RTC_TAFCR_TAMPFREQ_1

#define RTC_TAFCR_TAMPFREQ_2

#define RTC_TAFCR_TAMPTS_Pos

#define RTC_TAFCR_TAMPTS_Msk

#define RTC_TAFCR_TAMPTS

#define RTC_TAFCR_TAMP2TRG_Pos

#define RTC_TAFCR_TAMP2TRG_Msk

#define RTC_TAFCR_TAMP2TRG

#define RTC_TAFCR_TAMP2E_Pos

#define RTC_TAFCR_TAMP2E_Msk

#define RTC_TAFCR_TAMP2E

#define RTC_TAFCR_TAMPIE_Pos

#define RTC_TAFCR_TAMPIE_Msk

#define RTC_TAFCR_TAMPIE

#define RTC_TAFCR_TAMP1TRG_Pos

#define RTC_TAFCR_TAMP1TRG_Msk

#define RTC_TAFCR_TAMP1TRG

#define RTC_TAFCR_TAMP1E_Pos

#define RTC_TAFCR_TAMP1E_Msk

#define RTC_TAFCR_TAMP1E

#define RTC_TAFCR_TAMPINSEL

Bits definition for RTC_ALRMASSR register

#define RTC_ALRMASSR_MASKSS_Pos

#define RTC_ALRMASSR_MASKSS_Msk

#define RTC_ALRMASSR_MASKSS

#define RTC_ALRMASSR_MASKSS_0

#define RTC_ALRMASSR_MASKSS_1

#define RTC_ALRMASSR_MASKSS_2

#define RTC_ALRMASSR_MASKSS_3

#define RTC_ALRMASSR_SS_Pos

#define RTC_ALRMASSR_SS_Msk

#define RTC_ALRMASSR_SS

Bits definition for RTC_ALRMBSSR register

#define RTC_ALRMBSSR_MASKSS_Pos

#define RTC_ALRMBSSR_MASKSS_Msk

#define RTC_ALRMBSSR_MASKSS

#define RTC_ALRMBSSR_MASKSS_0

#define RTC_ALRMBSSR_MASKSS_1

#define RTC_ALRMBSSR_MASKSS_2

#define RTC_ALRMBSSR_MASKSS_3

#define RTC_ALRMBSSR_SS_Pos

#define RTC_ALRMBSSR_SS_Msk

#define RTC_ALRMBSSR_SS

Bits definition for RTC_BKP0R register

#define RTC_BKP0R_Pos

#define RTC_BKP0R_Msk

#define RTC_BKP0R

Bits definition for RTC_BKP1R register

#define RTC_BKP1R_Pos

#define RTC_BKP1R_Msk

#define RTC_BKP1R

Bits definition for RTC_BKP2R register

#define RTC_BKP2R_Pos

#define RTC_BKP2R_Msk

#define RTC_BKP2R

Bits definition for RTC_BKP3R register

#define RTC_BKP3R_Pos

#define RTC_BKP3R_Msk

#define RTC_BKP3R

Bits definition for RTC_BKP4R register

#define RTC_BKP4R_Pos

#define RTC_BKP4R_Msk

#define RTC_BKP4R

Bits definition for RTC_BKP5R register

#define RTC_BKP5R_Pos

#define RTC_BKP5R_Msk

#define RTC_BKP5R

Bits definition for RTC_BKP6R register

#define RTC_BKP6R_Pos

#define RTC_BKP6R_Msk

#define RTC_BKP6R

Bits definition for RTC_BKP7R register

#define RTC_BKP7R_Pos

#define RTC_BKP7R_Msk

#define RTC_BKP7R

Bits definition for RTC_BKP8R register

#define RTC_BKP8R_Pos

#define RTC_BKP8R_Msk

#define RTC_BKP8R

Bits definition for RTC_BKP9R register

#define RTC_BKP9R_Pos

#define RTC_BKP9R_Msk

#define RTC_BKP9R

Bits definition for RTC_BKP10R register

#define RTC_BKP10R_Pos

#define RTC_BKP10R_Msk

#define RTC_BKP10R

Bits definition for RTC_BKP11R register

#define RTC_BKP11R_Pos

#define RTC_BKP11R_Msk

#define RTC_BKP11R

Bits definition for RTC_BKP12R register

#define RTC_BKP12R_Pos

#define RTC_BKP12R_Msk

#define RTC_BKP12R

Bits definition for RTC_BKP13R register

#define RTC_BKP13R_Pos

#define RTC_BKP13R_Msk

#define RTC_BKP13R

Bits definition for RTC_BKP14R register

#define RTC_BKP14R_Pos

#define RTC_BKP14R_Msk

#define RTC_BKP14R

Bits definition for RTC_BKP15R register

#define RTC_BKP15R_Pos

#define RTC_BKP15R_Msk

#define RTC_BKP15R

Bits definition for RTC_BKP16R register

#define RTC_BKP16R_Pos

#define RTC_BKP16R_Msk

#define RTC_BKP16R

Bits definition for RTC_BKP17R register

#define RTC_BKP17R_Pos

#define RTC_BKP17R_Msk

#define RTC_BKP17R

Bits definition for RTC_BKP18R register

#define RTC_BKP18R_Pos

#define RTC_BKP18R_Msk

#define RTC_BKP18R

Bits definition for RTC_BKP19R register

#define RTC_BKP19R_Pos

#define RTC_BKP19R_Msk

#define RTC_BKP19R

Number of backup registers

#define RTC_BKP_NUMBER

...

Bit definition for SAI_GCR register

#define SAI_GCR_SYNCIN_Pos

#define SAI_GCR_SYNCIN_Msk

#define SAI_GCR_SYNCIN

#define SAI_GCR_SYNCIN_0

#define SAI_GCR_SYNCIN_1

#define SAI_GCR_SYNCOUT_Pos

#define SAI_GCR_SYNCOUT_Msk

#define SAI_GCR_SYNCOUT

#define SAI_GCR_SYNCOUT_0

#define SAI_GCR_SYNCOUT_1

Bit definition for SAI_xCR1 register

#define SAI_xCR1_MODE_Pos

#define SAI_xCR1_MODE_Msk

#define SAI_xCR1_MODE

#define SAI_xCR1_MODE_0

#define SAI_xCR1_MODE_1

#define SAI_xCR1_PRTCFG_Pos

#define SAI_xCR1_PRTCFG_Msk

#define SAI_xCR1_PRTCFG

#define SAI_xCR1_PRTCFG_0

#define SAI_xCR1_PRTCFG_1

#define SAI_xCR1_DS_Pos

#define SAI_xCR1_DS_Msk

#define SAI_xCR1_DS

#define SAI_xCR1_DS_0

#define SAI_xCR1_DS_1

#define SAI_xCR1_DS_2

#define SAI_xCR1_LSBFIRST_Pos

#define SAI_xCR1_LSBFIRST_Msk

#define SAI_xCR1_LSBFIRST

#define SAI_xCR1_CKSTR_Pos

#define SAI_xCR1_CKSTR_Msk

#define SAI_xCR1_CKSTR

#define SAI_xCR1_SYNCEN_Pos

#define SAI_xCR1_SYNCEN_Msk

#define SAI_xCR1_SYNCEN

#define SAI_xCR1_SYNCEN_0

#define SAI_xCR1_SYNCEN_1

#define SAI_xCR1_MONO_Pos

#define SAI_xCR1_MONO_Msk

#define SAI_xCR1_MONO

#define SAI_xCR1_OUTDRIV_Pos

#define SAI_xCR1_OUTDRIV_Msk

#define SAI_xCR1_OUTDRIV

#define SAI_xCR1_SAIEN_Pos

#define SAI_xCR1_SAIEN_Msk

#define SAI_xCR1_SAIEN

#define SAI_xCR1_DMAEN_Pos

#define SAI_xCR1_DMAEN_Msk

#define SAI_xCR1_DMAEN

#define SAI_xCR1_NODIV_Pos

#define SAI_xCR1_NODIV_Msk

#define SAI_xCR1_NODIV

#define SAI_xCR1_MCKDIV_Pos

#define SAI_xCR1_MCKDIV_Msk

#define SAI_xCR1_MCKDIV

#define SAI_xCR1_MCKDIV_0

#define SAI_xCR1_MCKDIV_1

#define SAI_xCR1_MCKDIV_2

#define SAI_xCR1_MCKDIV_3

Bit definition for SAI_xCR2 register

#define SAI_xCR2_FTH_Pos

#define SAI_xCR2_FTH_Msk

#define SAI_xCR2_FTH

#define SAI_xCR2_FTH_0

#define SAI_xCR2_FTH_1

#define SAI_xCR2_FTH_2

#define SAI_xCR2_FFLUSH_Pos

#define SAI_xCR2_FFLUSH_Msk

#define SAI_xCR2_FFLUSH

#define SAI_xCR2_TRIS_Pos

#define SAI_xCR2_TRIS_Msk

#define SAI_xCR2_TRIS

#define SAI_xCR2_MUTE_Pos

#define SAI_xCR2_MUTE_Msk

#define SAI_xCR2_MUTE

#define SAI_xCR2_MUTEVAL_Pos

#define SAI_xCR2_MUTEVAL_Msk

#define SAI_xCR2_MUTEVAL

#define SAI_xCR2_MUTECNT_Pos

#define SAI_xCR2_MUTECNT_Msk

#define SAI_xCR2_MUTECNT

#define SAI_xCR2_MUTECNT_0

#define SAI_xCR2_MUTECNT_1

#define SAI_xCR2_MUTECNT_2

#define SAI_xCR2_MUTECNT_3

#define SAI_xCR2_MUTECNT_4

#define SAI_xCR2_MUTECNT_5

#define SAI_xCR2_CPL_Pos

#define SAI_xCR2_CPL_Msk

#define SAI_xCR2_CPL

#define SAI_xCR2_COMP_Pos

#define SAI_xCR2_COMP_Msk

#define SAI_xCR2_COMP

#define SAI_xCR2_COMP_0

#define SAI_xCR2_COMP_1

Bit definition for SAI_xFRCR register

#define SAI_xFRCR_FRL_Pos

#define SAI_xFRCR_FRL_Msk

#define SAI_xFRCR_FRL

#define SAI_xFRCR_FRL_0

#define SAI_xFRCR_FRL_1

#define SAI_xFRCR_FRL_2

#define SAI_xFRCR_FRL_3

#define SAI_xFRCR_FRL_4

#define SAI_xFRCR_FRL_5

#define SAI_xFRCR_FRL_6

#define SAI_xFRCR_FRL_7

#define SAI_xFRCR_FSALL_Pos

#define SAI_xFRCR_FSALL_Msk

#define SAI_xFRCR_FSALL

#define SAI_xFRCR_FSALL_0

#define SAI_xFRCR_FSALL_1

#define SAI_xFRCR_FSALL_2

#define SAI_xFRCR_FSALL_3

#define SAI_xFRCR_FSALL_4

#define SAI_xFRCR_FSALL_5

#define SAI_xFRCR_FSALL_6

#define SAI_xFRCR_FSDEF_Pos

#define SAI_xFRCR_FSDEF_Msk

#define SAI_xFRCR_FSDEF

#define SAI_xFRCR_FSPOL_Pos

#define SAI_xFRCR_FSPOL_Msk

#define SAI_xFRCR_FSPOL

#define SAI_xFRCR_FSOFF_Pos

#define SAI_xFRCR_FSOFF_Msk

#define SAI_xFRCR_FSOFF

#define SAI_xFRCR_FSPO

Bit definition for SAI_xSLOTR register

#define SAI_xSLOTR_FBOFF_Pos

#define SAI_xSLOTR_FBOFF_Msk

#define SAI_xSLOTR_FBOFF

#define SAI_xSLOTR_FBOFF_0

#define SAI_xSLOTR_FBOFF_1

#define SAI_xSLOTR_FBOFF_2

#define SAI_xSLOTR_FBOFF_3

#define SAI_xSLOTR_FBOFF_4

#define SAI_xSLOTR_SLOTSZ_Pos

#define SAI_xSLOTR_SLOTSZ_Msk

#define SAI_xSLOTR_SLOTSZ

#define SAI_xSLOTR_SLOTSZ_0

#define SAI_xSLOTR_SLOTSZ_1

#define SAI_xSLOTR_NBSLOT_Pos

#define SAI_xSLOTR_NBSLOT_Msk

#define SAI_xSLOTR_NBSLOT

#define SAI_xSLOTR_NBSLOT_0

#define SAI_xSLOTR_NBSLOT_1

#define SAI_xSLOTR_NBSLOT_2

#define SAI_xSLOTR_NBSLOT_3

#define SAI_xSLOTR_SLOTEN_Pos

#define SAI_xSLOTR_SLOTEN_Msk

#define SAI_xSLOTR_SLOTEN

Bit definition for SAI_xIMR register

#define SAI_xIMR_OVRUDRIE_Pos

#define SAI_xIMR_OVRUDRIE_Msk

#define SAI_xIMR_OVRUDRIE

#define SAI_xIMR_MUTEDETIE_Pos

#define SAI_xIMR_MUTEDETIE_Msk

#define SAI_xIMR_MUTEDETIE

#define SAI_xIMR_WCKCFGIE_Pos

#define SAI_xIMR_WCKCFGIE_Msk

#define SAI_xIMR_WCKCFGIE

#define SAI_xIMR_FREQIE_Pos

#define SAI_xIMR_FREQIE_Msk

#define SAI_xIMR_FREQIE

#define SAI_xIMR_CNRDYIE_Pos

#define SAI_xIMR_CNRDYIE_Msk

#define SAI_xIMR_CNRDYIE

#define SAI_xIMR_AFSDETIE_Pos

#define SAI_xIMR_AFSDETIE_Msk

#define SAI_xIMR_AFSDETIE

#define SAI_xIMR_LFSDETIE_Pos

#define SAI_xIMR_LFSDETIE_Msk

#define SAI_xIMR_LFSDETIE

Bit definition for SAI_xSR register

#define SAI_xSR_OVRUDR_Pos

#define SAI_xSR_OVRUDR_Msk

#define SAI_xSR_OVRUDR

#define SAI_xSR_MUTEDET_Pos

#define SAI_xSR_MUTEDET_Msk

#define SAI_xSR_MUTEDET

#define SAI_xSR_WCKCFG_Pos

#define SAI_xSR_WCKCFG_Msk

#define SAI_xSR_WCKCFG

#define SAI_xSR_FREQ_Pos

#define SAI_xSR_FREQ_Msk

#define SAI_xSR_FREQ

#define SAI_xSR_CNRDY_Pos

#define SAI_xSR_CNRDY_Msk

#define SAI_xSR_CNRDY

#define SAI_xSR_AFSDET_Pos

#define SAI_xSR_AFSDET_Msk

#define SAI_xSR_AFSDET

#define SAI_xSR_LFSDET_Pos

#define SAI_xSR_LFSDET_Msk

#define SAI_xSR_LFSDET

#define SAI_xSR_FLVL_Pos

#define SAI_xSR_FLVL_Msk

#define SAI_xSR_FLVL

#define SAI_xSR_FLVL_0

#define SAI_xSR_FLVL_1

#define SAI_xSR_FLVL_2

Bit definition for SAI_xCLRFR register

#define SAI_xCLRFR_COVRUDR_Pos

#define SAI_xCLRFR_COVRUDR_Msk

#define SAI_xCLRFR_COVRUDR

#define SAI_xCLRFR_CMUTEDET_Pos

#define SAI_xCLRFR_CMUTEDET_Msk

#define SAI_xCLRFR_CMUTEDET

#define SAI_xCLRFR_CWCKCFG_Pos

#define SAI_xCLRFR_CWCKCFG_Msk

#define SAI_xCLRFR_CWCKCFG

#define SAI_xCLRFR_CFREQ_Pos

#define SAI_xCLRFR_CFREQ_Msk

#define SAI_xCLRFR_CFREQ

#define SAI_xCLRFR_CCNRDY_Pos

#define SAI_xCLRFR_CCNRDY_Msk

#define SAI_xCLRFR_CCNRDY

#define SAI_xCLRFR_CAFSDET_Pos

#define SAI_xCLRFR_CAFSDET_Msk

#define SAI_xCLRFR_CAFSDET

#define SAI_xCLRFR_CLFSDET_Pos

#define SAI_xCLRFR_CLFSDET_Msk

#define SAI_xCLRFR_CLFSDET

Bit definition for SAI_xDR register

#define SAI_xDR_DATA_Pos

#define SAI_xDR_DATA_Msk

#define SAI_xDR_DATA

...

Bit definition for SDIO_POWER register

#define SDIO_POWER_PWRCTRL_Pos

#define SDIO_POWER_PWRCTRL_Msk

#define SDIO_POWER_PWRCTRL

#define SDIO_POWER_PWRCTRL_0

#define SDIO_POWER_PWRCTRL_1

Bit definition for SDIO_CLKCR register

#define SDIO_CLKCR_CLKDIV_Pos

#define SDIO_CLKCR_CLKDIV_Msk

#define SDIO_CLKCR_CLKDIV

#define SDIO_CLKCR_CLKEN_Pos

#define SDIO_CLKCR_CLKEN_Msk

#define SDIO_CLKCR_CLKEN

#define SDIO_CLKCR_PWRSAV_Pos

#define SDIO_CLKCR_PWRSAV_Msk

#define SDIO_CLKCR_PWRSAV

#define SDIO_CLKCR_BYPASS_Pos

#define SDIO_CLKCR_BYPASS_Msk

#define SDIO_CLKCR_BYPASS

#define SDIO_CLKCR_WIDBUS_Pos

#define SDIO_CLKCR_WIDBUS_Msk

#define SDIO_CLKCR_WIDBUS

#define SDIO_CLKCR_WIDBUS_0

#define SDIO_CLKCR_WIDBUS_1

#define SDIO_CLKCR_NEGEDGE_Pos

#define SDIO_CLKCR_NEGEDGE_Msk

#define SDIO_CLKCR_NEGEDGE

#define SDIO_CLKCR_HWFC_EN_Pos

#define SDIO_CLKCR_HWFC_EN_Msk

#define SDIO_CLKCR_HWFC_EN

Bit definition for SDIO_ARG register

#define SDIO_ARG_CMDARG_Pos

#define SDIO_ARG_CMDARG_Msk

#define SDIO_ARG_CMDARG

Bit definition for SDIO_CMD register

#define SDIO_CMD_CMDINDEX_Pos

#define SDIO_CMD_CMDINDEX_Msk

#define SDIO_CMD_CMDINDEX

#define SDIO_CMD_WAITRESP_Pos

#define SDIO_CMD_WAITRESP_Msk

#define SDIO_CMD_WAITRESP

#define SDIO_CMD_WAITRESP_0

#define SDIO_CMD_WAITRESP_1

#define SDIO_CMD_WAITINT_Pos

#define SDIO_CMD_WAITINT_Msk

#define SDIO_CMD_WAITINT

#define SDIO_CMD_WAITPEND_Pos

#define SDIO_CMD_WAITPEND_Msk

#define SDIO_CMD_WAITPEND

#define SDIO_CMD_CPSMEN_Pos

#define SDIO_CMD_CPSMEN_Msk

#define SDIO_CMD_CPSMEN

#define SDIO_CMD_SDIOSUSPEND_Pos

#define SDIO_CMD_SDIOSUSPEND_Msk

#define SDIO_CMD_SDIOSUSPEND

#define SDIO_CMD_ENCMDCOMPL_Pos

#define SDIO_CMD_ENCMDCOMPL_Msk

#define SDIO_CMD_ENCMDCOMPL

#define SDIO_CMD_NIEN_Pos

#define SDIO_CMD_NIEN_Msk

#define SDIO_CMD_NIEN

#define SDIO_CMD_CEATACMD_Pos

#define SDIO_CMD_CEATACMD_Msk

#define SDIO_CMD_CEATACMD

Bit definition for SDIO_RESPCMD register

#define SDIO_RESPCMD_RESPCMD_Pos

#define SDIO_RESPCMD_RESPCMD_Msk

#define SDIO_RESPCMD_RESPCMD

Bit definition for SDIO_RESP0 register

#define SDIO_RESP0_CARDSTATUS0_Pos

#define SDIO_RESP0_CARDSTATUS0_Msk

#define SDIO_RESP0_CARDSTATUS0

Bit definition for SDIO_RESP1 register

#define SDIO_RESP1_CARDSTATUS1_Pos

#define SDIO_RESP1_CARDSTATUS1_Msk

#define SDIO_RESP1_CARDSTATUS1

Bit definition for SDIO_RESP2 register

#define SDIO_RESP2_CARDSTATUS2_Pos

#define SDIO_RESP2_CARDSTATUS2_Msk

#define SDIO_RESP2_CARDSTATUS2

Bit definition for SDIO_RESP3 register

#define SDIO_RESP3_CARDSTATUS3_Pos

#define SDIO_RESP3_CARDSTATUS3_Msk

#define SDIO_RESP3_CARDSTATUS3

Bit definition for SDIO_RESP4 register

#define SDIO_RESP4_CARDSTATUS4_Pos

#define SDIO_RESP4_CARDSTATUS4_Msk

#define SDIO_RESP4_CARDSTATUS4

Bit definition for SDIO_DTIMER register

#define SDIO_DTIMER_DATATIME_Pos

#define SDIO_DTIMER_DATATIME_Msk

#define SDIO_DTIMER_DATATIME

Bit definition for SDIO_DLEN register

#define SDIO_DLEN_DATALENGTH_Pos

#define SDIO_DLEN_DATALENGTH_Msk

#define SDIO_DLEN_DATALENGTH

Bit definition for SDIO_DCTRL register

#define SDIO_DCTRL_DTEN_Pos

#define SDIO_DCTRL_DTEN_Msk

#define SDIO_DCTRL_DTEN

#define SDIO_DCTRL_DTDIR_Pos

#define SDIO_DCTRL_DTDIR_Msk

#define SDIO_DCTRL_DTDIR

#define SDIO_DCTRL_DTMODE_Pos

#define SDIO_DCTRL_DTMODE_Msk

#define SDIO_DCTRL_DTMODE

#define SDIO_DCTRL_DMAEN_Pos

#define SDIO_DCTRL_DMAEN_Msk

#define SDIO_DCTRL_DMAEN

#define SDIO_DCTRL_DBLOCKSIZE_Pos

#define SDIO_DCTRL_DBLOCKSIZE_Msk

#define SDIO_DCTRL_DBLOCKSIZE

#define SDIO_DCTRL_DBLOCKSIZE_0

#define SDIO_DCTRL_DBLOCKSIZE_1

#define SDIO_DCTRL_DBLOCKSIZE_2

#define SDIO_DCTRL_DBLOCKSIZE_3

#define SDIO_DCTRL_RWSTART_Pos

#define SDIO_DCTRL_RWSTART_Msk

#define SDIO_DCTRL_RWSTART

#define SDIO_DCTRL_RWSTOP_Pos

#define SDIO_DCTRL_RWSTOP_Msk

#define SDIO_DCTRL_RWSTOP

#define SDIO_DCTRL_RWMOD_Pos

#define SDIO_DCTRL_RWMOD_Msk

#define SDIO_DCTRL_RWMOD

#define SDIO_DCTRL_SDIOEN_Pos

#define SDIO_DCTRL_SDIOEN_Msk

#define SDIO_DCTRL_SDIOEN

Bit definition for SDIO_DCOUNT register

#define SDIO_DCOUNT_DATACOUNT_Pos

#define SDIO_DCOUNT_DATACOUNT_Msk

#define SDIO_DCOUNT_DATACOUNT

Bit definition for SDIO_STA register

#define SDIO_STA_CCRCFAIL_Pos

#define SDIO_STA_CCRCFAIL_Msk

#define SDIO_STA_CCRCFAIL

#define SDIO_STA_DCRCFAIL_Pos

#define SDIO_STA_DCRCFAIL_Msk

#define SDIO_STA_DCRCFAIL

#define SDIO_STA_CTIMEOUT_Pos

#define SDIO_STA_CTIMEOUT_Msk

#define SDIO_STA_CTIMEOUT

#define SDIO_STA_DTIMEOUT_Pos

#define SDIO_STA_DTIMEOUT_Msk

#define SDIO_STA_DTIMEOUT

#define SDIO_STA_TXUNDERR_Pos

#define SDIO_STA_TXUNDERR_Msk

#define SDIO_STA_TXUNDERR

#define SDIO_STA_RXOVERR_Pos

#define SDIO_STA_RXOVERR_Msk

#define SDIO_STA_RXOVERR

#define SDIO_STA_CMDREND_Pos

#define SDIO_STA_CMDREND_Msk

#define SDIO_STA_CMDREND

#define SDIO_STA_CMDSENT_Pos

#define SDIO_STA_CMDSENT_Msk

#define SDIO_STA_CMDSENT

#define SDIO_STA_DATAEND_Pos

#define SDIO_STA_DATAEND_Msk

#define SDIO_STA_DATAEND

#define SDIO_STA_STBITERR_Pos

#define SDIO_STA_STBITERR_Msk

#define SDIO_STA_STBITERR

#define SDIO_STA_DBCKEND_Pos

#define SDIO_STA_DBCKEND_Msk

#define SDIO_STA_DBCKEND

#define SDIO_STA_CMDACT_Pos

#define SDIO_STA_CMDACT_Msk

#define SDIO_STA_CMDACT

#define SDIO_STA_TXACT_Pos

#define SDIO_STA_TXACT_Msk

#define SDIO_STA_TXACT

#define SDIO_STA_RXACT_Pos

#define SDIO_STA_RXACT_Msk

#define SDIO_STA_RXACT

#define SDIO_STA_TXFIFOHE_Pos

#define SDIO_STA_TXFIFOHE_Msk

#define SDIO_STA_TXFIFOHE

#define SDIO_STA_RXFIFOHF_Pos

#define SDIO_STA_RXFIFOHF_Msk

#define SDIO_STA_RXFIFOHF

#define SDIO_STA_TXFIFOF_Pos

#define SDIO_STA_TXFIFOF_Msk

#define SDIO_STA_TXFIFOF

#define SDIO_STA_RXFIFOF_Pos

#define SDIO_STA_RXFIFOF_Msk

#define SDIO_STA_RXFIFOF

#define SDIO_STA_TXFIFOE_Pos

#define SDIO_STA_TXFIFOE_Msk

#define SDIO_STA_TXFIFOE

#define SDIO_STA_RXFIFOE_Pos

#define SDIO_STA_RXFIFOE_Msk

#define SDIO_STA_RXFIFOE

#define SDIO_STA_TXDAVL_Pos

#define SDIO_STA_TXDAVL_Msk

#define SDIO_STA_TXDAVL

#define SDIO_STA_RXDAVL_Pos

#define SDIO_STA_RXDAVL_Msk

#define SDIO_STA_RXDAVL

#define SDIO_STA_SDIOIT_Pos

#define SDIO_STA_SDIOIT_Msk

#define SDIO_STA_SDIOIT

#define SDIO_STA_CEATAEND_Pos

#define SDIO_STA_CEATAEND_Msk

#define SDIO_STA_CEATAEND

Bit definition for SDIO_ICR register

#define SDIO_ICR_CCRCFAILC_Pos

#define SDIO_ICR_CCRCFAILC_Msk

#define SDIO_ICR_CCRCFAILC

#define SDIO_ICR_DCRCFAILC_Pos

#define SDIO_ICR_DCRCFAILC_Msk

#define SDIO_ICR_DCRCFAILC

#define SDIO_ICR_CTIMEOUTC_Pos

#define SDIO_ICR_CTIMEOUTC_Msk

#define SDIO_ICR_CTIMEOUTC

#define SDIO_ICR_DTIMEOUTC_Pos

#define SDIO_ICR_DTIMEOUTC_Msk

#define SDIO_ICR_DTIMEOUTC

#define SDIO_ICR_TXUNDERRC_Pos

#define SDIO_ICR_TXUNDERRC_Msk

#define SDIO_ICR_TXUNDERRC

#define SDIO_ICR_RXOVERRC_Pos

#define SDIO_ICR_RXOVERRC_Msk

#define SDIO_ICR_RXOVERRC

#define SDIO_ICR_CMDRENDC_Pos

#define SDIO_ICR_CMDRENDC_Msk

#define SDIO_ICR_CMDRENDC

#define SDIO_ICR_CMDSENTC_Pos

#define SDIO_ICR_CMDSENTC_Msk

#define SDIO_ICR_CMDSENTC

#define SDIO_ICR_DATAENDC_Pos

#define SDIO_ICR_DATAENDC_Msk

#define SDIO_ICR_DATAENDC

#define SDIO_ICR_STBITERRC_Pos

#define SDIO_ICR_STBITERRC_Msk

#define SDIO_ICR_STBITERRC

#define SDIO_ICR_DBCKENDC_Pos

#define SDIO_ICR_DBCKENDC_Msk

#define SDIO_ICR_DBCKENDC

#define SDIO_ICR_SDIOITC_Pos

#define SDIO_ICR_SDIOITC_Msk

#define SDIO_ICR_SDIOITC

#define SDIO_ICR_CEATAENDC_Pos

#define SDIO_ICR_CEATAENDC_Msk

#define SDIO_ICR_CEATAENDC

Bit definition for SDIO_MASK register

#define SDIO_MASK_CCRCFAILIE_Pos

#define SDIO_MASK_CCRCFAILIE_Msk

#define SDIO_MASK_CCRCFAILIE

#define SDIO_MASK_DCRCFAILIE_Pos

#define SDIO_MASK_DCRCFAILIE_Msk

#define SDIO_MASK_DCRCFAILIE

#define SDIO_MASK_CTIMEOUTIE_Pos

#define SDIO_MASK_CTIMEOUTIE_Msk

#define SDIO_MASK_CTIMEOUTIE

#define SDIO_MASK_DTIMEOUTIE_Pos

#define SDIO_MASK_DTIMEOUTIE_Msk

#define SDIO_MASK_DTIMEOUTIE

#define SDIO_MASK_TXUNDERRIE_Pos

#define SDIO_MASK_TXUNDERRIE_Msk

#define SDIO_MASK_TXUNDERRIE

#define SDIO_MASK_RXOVERRIE_Pos

#define SDIO_MASK_RXOVERRIE_Msk

#define SDIO_MASK_RXOVERRIE

#define SDIO_MASK_CMDRENDIE_Pos

#define SDIO_MASK_CMDRENDIE_Msk

#define SDIO_MASK_CMDRENDIE

#define SDIO_MASK_CMDSENTIE_Pos

#define SDIO_MASK_CMDSENTIE_Msk

#define SDIO_MASK_CMDSENTIE

#define SDIO_MASK_DATAENDIE_Pos

#define SDIO_MASK_DATAENDIE_Msk

#define SDIO_MASK_DATAENDIE

#define SDIO_MASK_STBITERRIE_Pos

#define SDIO_MASK_STBITERRIE_Msk

#define SDIO_MASK_STBITERRIE

#define SDIO_MASK_DBCKENDIE_Pos

#define SDIO_MASK_DBCKENDIE_Msk

#define SDIO_MASK_DBCKENDIE

#define SDIO_MASK_CMDACTIE_Pos

#define SDIO_MASK_CMDACTIE_Msk

#define SDIO_MASK_CMDACTIE

#define SDIO_MASK_TXACTIE_Pos

#define SDIO_MASK_TXACTIE_Msk

#define SDIO_MASK_TXACTIE

#define SDIO_MASK_RXACTIE_Pos

#define SDIO_MASK_RXACTIE_Msk

#define SDIO_MASK_RXACTIE

#define SDIO_MASK_TXFIFOHEIE_Pos

#define SDIO_MASK_TXFIFOHEIE_Msk

#define SDIO_MASK_TXFIFOHEIE

#define SDIO_MASK_RXFIFOHFIE_Pos

#define SDIO_MASK_RXFIFOHFIE_Msk

#define SDIO_MASK_RXFIFOHFIE

#define SDIO_MASK_TXFIFOFIE_Pos

#define SDIO_MASK_TXFIFOFIE_Msk

#define SDIO_MASK_TXFIFOFIE

#define SDIO_MASK_RXFIFOFIE_Pos

#define SDIO_MASK_RXFIFOFIE_Msk

#define SDIO_MASK_RXFIFOFIE

#define SDIO_MASK_TXFIFOEIE_Pos

#define SDIO_MASK_TXFIFOEIE_Msk

#define SDIO_MASK_TXFIFOEIE

#define SDIO_MASK_RXFIFOEIE_Pos

#define SDIO_MASK_RXFIFOEIE_Msk

#define SDIO_MASK_RXFIFOEIE

#define SDIO_MASK_TXDAVLIE_Pos

#define SDIO_MASK_TXDAVLIE_Msk

#define SDIO_MASK_TXDAVLIE

#define SDIO_MASK_RXDAVLIE_Pos

#define SDIO_MASK_RXDAVLIE_Msk

#define SDIO_MASK_RXDAVLIE

#define SDIO_MASK_SDIOITIE_Pos

#define SDIO_MASK_SDIOITIE_Msk

#define SDIO_MASK_SDIOITIE

#define SDIO_MASK_CEATAENDIE_Pos

#define SDIO_MASK_CEATAENDIE_Msk

#define SDIO_MASK_CEATAENDIE

Bit definition for SDIO_FIFOCNT register

#define SDIO_FIFOCNT_FIFOCOUNT_Pos

#define SDIO_FIFOCNT_FIFOCOUNT_Msk

#define SDIO_FIFOCNT_FIFOCOUNT

Bit definition for SDIO_FIFO register

#define SDIO_FIFO_FIFODATA_Pos

#define SDIO_FIFO_FIFODATA_Msk

#define SDIO_FIFO_FIFODATA

...

#define SPI_I2S_FULLDUPLEX_SUPPORT

Bit definition for SPI_CR1 register

#define SPI_CR1_CPHA_Pos

#define SPI_CR1_CPHA_Msk

#define SPI_CR1_CPHA

#define SPI_CR1_CPOL_Pos

#define SPI_CR1_CPOL_Msk

#define SPI_CR1_CPOL

#define SPI_CR1_MSTR_Pos

#define SPI_CR1_MSTR_Msk

#define SPI_CR1_MSTR

#define SPI_CR1_BR_Pos

#define SPI_CR1_BR_Msk

#define SPI_CR1_BR

#define SPI_CR1_BR_0

#define SPI_CR1_BR_1

#define SPI_CR1_BR_2

#define SPI_CR1_SPE_Pos

#define SPI_CR1_SPE_Msk

#define SPI_CR1_SPE

#define SPI_CR1_LSBFIRST_Pos

#define SPI_CR1_LSBFIRST_Msk

#define SPI_CR1_LSBFIRST

#define SPI_CR1_SSI_Pos

#define SPI_CR1_SSI_Msk

#define SPI_CR1_SSI

#define SPI_CR1_SSM_Pos

#define SPI_CR1_SSM_Msk

#define SPI_CR1_SSM

#define SPI_CR1_RXONLY_Pos

#define SPI_CR1_RXONLY_Msk

#define SPI_CR1_RXONLY

#define SPI_CR1_DFF_Pos

#define SPI_CR1_DFF_Msk

#define SPI_CR1_DFF

#define SPI_CR1_CRCNEXT_Pos

#define SPI_CR1_CRCNEXT_Msk

#define SPI_CR1_CRCNEXT

#define SPI_CR1_CRCEN_Pos

#define SPI_CR1_CRCEN_Msk

#define SPI_CR1_CRCEN

#define SPI_CR1_BIDIOE_Pos

#define SPI_CR1_BIDIOE_Msk

#define SPI_CR1_BIDIOE

#define SPI_CR1_BIDIMODE_Pos

#define SPI_CR1_BIDIMODE_Msk

#define SPI_CR1_BIDIMODE

Bit definition for SPI_CR2 register

#define SPI_CR2_RXDMAEN_Pos

#define SPI_CR2_RXDMAEN_Msk

#define SPI_CR2_RXDMAEN

#define SPI_CR2_TXDMAEN_Pos

#define SPI_CR2_TXDMAEN_Msk

#define SPI_CR2_TXDMAEN

#define SPI_CR2_SSOE_Pos

#define SPI_CR2_SSOE_Msk

#define SPI_CR2_SSOE

#define SPI_CR2_FRF_Pos

#define SPI_CR2_FRF_Msk

#define SPI_CR2_FRF

#define SPI_CR2_ERRIE_Pos

#define SPI_CR2_ERRIE_Msk

#define SPI_CR2_ERRIE

#define SPI_CR2_RXNEIE_Pos

#define SPI_CR2_RXNEIE_Msk

#define SPI_CR2_RXNEIE

#define SPI_CR2_TXEIE_Pos

#define SPI_CR2_TXEIE_Msk

#define SPI_CR2_TXEIE

Bit definition for SPI_SR register

#define SPI_SR_RXNE_Pos

#define SPI_SR_RXNE_Msk

#define SPI_SR_RXNE

#define SPI_SR_TXE_Pos

#define SPI_SR_TXE_Msk

#define SPI_SR_TXE

#define SPI_SR_CHSIDE_Pos

#define SPI_SR_CHSIDE_Msk

#define SPI_SR_CHSIDE

#define SPI_SR_UDR_Pos

#define SPI_SR_UDR_Msk

#define SPI_SR_UDR

#define SPI_SR_CRCERR_Pos

#define SPI_SR_CRCERR_Msk

#define SPI_SR_CRCERR

#define SPI_SR_MODF_Pos

#define SPI_SR_MODF_Msk

#define SPI_SR_MODF

#define SPI_SR_OVR_Pos

#define SPI_SR_OVR_Msk

#define SPI_SR_OVR

#define SPI_SR_BSY_Pos

#define SPI_SR_BSY_Msk

#define SPI_SR_BSY

#define SPI_SR_FRE_Pos

#define SPI_SR_FRE_Msk

#define SPI_SR_FRE

Bit definition for SPI_DR register

#define SPI_DR_DR_Pos

#define SPI_DR_DR_Msk

#define SPI_DR_DR

Bit definition for SPI_CRCPR register

#define SPI_CRCPR_CRCPOLY_Pos

#define SPI_CRCPR_CRCPOLY_Msk

#define SPI_CRCPR_CRCPOLY

Bit definition for SPI_RXCRCR register

#define SPI_RXCRCR_RXCRC_Pos

#define SPI_RXCRCR_RXCRC_Msk

#define SPI_RXCRCR_RXCRC

Bit definition for SPI_TXCRCR register

#define SPI_TXCRCR_TXCRC_Pos

#define SPI_TXCRCR_TXCRC_Msk

#define SPI_TXCRCR_TXCRC

Bit definition for SPI_I2SCFGR register

#define SPI_I2SCFGR_CHLEN_Pos

#define SPI_I2SCFGR_CHLEN_Msk

#define SPI_I2SCFGR_CHLEN

#define SPI_I2SCFGR_DATLEN_Pos

#define SPI_I2SCFGR_DATLEN_Msk

#define SPI_I2SCFGR_DATLEN

#define SPI_I2SCFGR_DATLEN_0

#define SPI_I2SCFGR_DATLEN_1

#define SPI_I2SCFGR_CKPOL_Pos

#define SPI_I2SCFGR_CKPOL_Msk

#define SPI_I2SCFGR_CKPOL

#define SPI_I2SCFGR_I2SSTD_Pos

#define SPI_I2SCFGR_I2SSTD_Msk

#define SPI_I2SCFGR_I2SSTD

#define SPI_I2SCFGR_I2SSTD_0

#define SPI_I2SCFGR_I2SSTD_1

#define SPI_I2SCFGR_PCMSYNC_Pos

#define SPI_I2SCFGR_PCMSYNC_Msk

#define SPI_I2SCFGR_PCMSYNC

#define SPI_I2SCFGR_I2SCFG_Pos

#define SPI_I2SCFGR_I2SCFG_Msk

#define SPI_I2SCFGR_I2SCFG

#define SPI_I2SCFGR_I2SCFG_0

#define SPI_I2SCFGR_I2SCFG_1

#define SPI_I2SCFGR_I2SE_Pos

#define SPI_I2SCFGR_I2SE_Msk

#define SPI_I2SCFGR_I2SE

#define SPI_I2SCFGR_I2SMOD_Pos

#define SPI_I2SCFGR_I2SMOD_Msk

#define SPI_I2SCFGR_I2SMOD

Bit definition for SPI_I2SPR register

#define SPI_I2SPR_I2SDIV_Pos

#define SPI_I2SPR_I2SDIV_Msk

#define SPI_I2SPR_I2SDIV

#define SPI_I2SPR_ODD_Pos

#define SPI_I2SPR_ODD_Msk

#define SPI_I2SPR_ODD

#define SPI_I2SPR_MCKOE_Pos

#define SPI_I2SPR_MCKOE_Msk

#define SPI_I2SPR_MCKOE

...

Bit definition for SYSCFG_MEMRMP register

#define SYSCFG_MEMRMP_MEM_MODE_Pos

#define SYSCFG_MEMRMP_MEM_MODE_Msk

#define SYSCFG_MEMRMP_MEM_MODE

#define SYSCFG_MEMRMP_MEM_MODE_0

#define SYSCFG_MEMRMP_MEM_MODE_1

#define SYSCFG_MEMRMP_MEM_MODE_2

#define SYSCFG_MEMRMP_UFB_MODE_Pos

#define SYSCFG_MEMRMP_UFB_MODE_Msk

#define SYSCFG_MEMRMP_UFB_MODE

#define SYSCFG_MEMRMP_SWP_FMC_Pos

#define SYSCFG_MEMRMP_SWP_FMC_Msk

#define SYSCFG_MEMRMP_SWP_FMC

#define SYSCFG_MEMRMP_SWP_FMC_0

#define SYSCFG_SWP_FMC

Bit definition for SYSCFG_PMC register

#define SYSCFG_PMC_ADCxDC2_Pos

#define SYSCFG_PMC_ADCxDC2_Msk

#define SYSCFG_PMC_ADCxDC2

#define SYSCFG_PMC_ADC1DC2_Pos

#define SYSCFG_PMC_ADC1DC2_Msk

#define SYSCFG_PMC_ADC1DC2

#define SYSCFG_PMC_ADC2DC2_Pos

#define SYSCFG_PMC_ADC2DC2_Msk

#define SYSCFG_PMC_ADC2DC2

#define SYSCFG_PMC_ADC3DC2_Pos

#define SYSCFG_PMC_ADC3DC2_Msk

#define SYSCFG_PMC_ADC3DC2

#define SYSCFG_PMC_MII_RMII_SEL_Pos

#define SYSCFG_PMC_MII_RMII_SEL_Msk

#define SYSCFG_PMC_MII_RMII_SEL

#define SYSCFG_PMC_MII_RMII

Bit definition for SYSCFG_EXTICR1 register

#define SYSCFG_EXTICR1_EXTI0_Pos

#define SYSCFG_EXTICR1_EXTI0_Msk

#define SYSCFG_EXTICR1_EXTI0

#define SYSCFG_EXTICR1_EXTI1_Pos

#define SYSCFG_EXTICR1_EXTI1_Msk

#define SYSCFG_EXTICR1_EXTI1

#define SYSCFG_EXTICR1_EXTI2_Pos

#define SYSCFG_EXTICR1_EXTI2_Msk

#define SYSCFG_EXTICR1_EXTI2

#define SYSCFG_EXTICR1_EXTI3_Pos

#define SYSCFG_EXTICR1_EXTI3_Msk

#define SYSCFG_EXTICR1_EXTI3

#define SYSCFG_EXTICR1_EXTI0_PA

#define SYSCFG_EXTICR1_EXTI0_PB

#define SYSCFG_EXTICR1_EXTI0_PC

#define SYSCFG_EXTICR1_EXTI0_PD

#define SYSCFG_EXTICR1_EXTI0_PE

#define SYSCFG_EXTICR1_EXTI0_PF

#define SYSCFG_EXTICR1_EXTI0_PG

#define SYSCFG_EXTICR1_EXTI0_PH

#define SYSCFG_EXTICR1_EXTI0_PI

#define SYSCFG_EXTICR1_EXTI0_PJ

#define SYSCFG_EXTICR1_EXTI0_PK

#define SYSCFG_EXTICR1_EXTI1_PA

#define SYSCFG_EXTICR1_EXTI1_PB

#define SYSCFG_EXTICR1_EXTI1_PC

#define SYSCFG_EXTICR1_EXTI1_PD

#define SYSCFG_EXTICR1_EXTI1_PE

#define SYSCFG_EXTICR1_EXTI1_PF

#define SYSCFG_EXTICR1_EXTI1_PG

#define SYSCFG_EXTICR1_EXTI1_PH

#define SYSCFG_EXTICR1_EXTI1_PI

#define SYSCFG_EXTICR1_EXTI1_PJ

#define SYSCFG_EXTICR1_EXTI1_PK

#define SYSCFG_EXTICR1_EXTI2_PA

#define SYSCFG_EXTICR1_EXTI2_PB

#define SYSCFG_EXTICR1_EXTI2_PC

#define SYSCFG_EXTICR1_EXTI2_PD

#define SYSCFG_EXTICR1_EXTI2_PE

#define SYSCFG_EXTICR1_EXTI2_PF

#define SYSCFG_EXTICR1_EXTI2_PG

#define SYSCFG_EXTICR1_EXTI2_PH

#define SYSCFG_EXTICR1_EXTI2_PI

#define SYSCFG_EXTICR1_EXTI2_PJ

#define SYSCFG_EXTICR1_EXTI2_PK

#define SYSCFG_EXTICR1_EXTI3_PA

#define SYSCFG_EXTICR1_EXTI3_PB

#define SYSCFG_EXTICR1_EXTI3_PC

#define SYSCFG_EXTICR1_EXTI3_PD

#define SYSCFG_EXTICR1_EXTI3_PE

#define SYSCFG_EXTICR1_EXTI3_PF

#define SYSCFG_EXTICR1_EXTI3_PG

#define SYSCFG_EXTICR1_EXTI3_PH

#define SYSCFG_EXTICR1_EXTI3_PI

#define SYSCFG_EXTICR1_EXTI3_PJ

#define SYSCFG_EXTICR1_EXTI3_PK

Bit definition for SYSCFG_EXTICR2 register

#define SYSCFG_EXTICR2_EXTI4_Pos

#define SYSCFG_EXTICR2_EXTI4_Msk

#define SYSCFG_EXTICR2_EXTI4

#define SYSCFG_EXTICR2_EXTI5_Pos

#define SYSCFG_EXTICR2_EXTI5_Msk

#define SYSCFG_EXTICR2_EXTI5

#define SYSCFG_EXTICR2_EXTI6_Pos

#define SYSCFG_EXTICR2_EXTI6_Msk

#define SYSCFG_EXTICR2_EXTI6

#define SYSCFG_EXTICR2_EXTI7_Pos

#define SYSCFG_EXTICR2_EXTI7_Msk

#define SYSCFG_EXTICR2_EXTI7

#define SYSCFG_EXTICR2_EXTI4_PA

#define SYSCFG_EXTICR2_EXTI4_PB

#define SYSCFG_EXTICR2_EXTI4_PC

#define SYSCFG_EXTICR2_EXTI4_PD

#define SYSCFG_EXTICR2_EXTI4_PE

#define SYSCFG_EXTICR2_EXTI4_PF

#define SYSCFG_EXTICR2_EXTI4_PG

#define SYSCFG_EXTICR2_EXTI4_PH

#define SYSCFG_EXTICR2_EXTI4_PI

#define SYSCFG_EXTICR2_EXTI4_PJ

#define SYSCFG_EXTICR2_EXTI4_PK

#define SYSCFG_EXTICR2_EXTI5_PA

#define SYSCFG_EXTICR2_EXTI5_PB

#define SYSCFG_EXTICR2_EXTI5_PC

#define SYSCFG_EXTICR2_EXTI5_PD

#define SYSCFG_EXTICR2_EXTI5_PE

#define SYSCFG_EXTICR2_EXTI5_PF

#define SYSCFG_EXTICR2_EXTI5_PG

#define SYSCFG_EXTICR2_EXTI5_PH

#define SYSCFG_EXTICR2_EXTI5_PI

#define SYSCFG_EXTICR2_EXTI5_PJ

#define SYSCFG_EXTICR2_EXTI5_PK

#define SYSCFG_EXTICR2_EXTI6_PA

#define SYSCFG_EXTICR2_EXTI6_PB

#define SYSCFG_EXTICR2_EXTI6_PC

#define SYSCFG_EXTICR2_EXTI6_PD

#define SYSCFG_EXTICR2_EXTI6_PE

#define SYSCFG_EXTICR2_EXTI6_PF

#define SYSCFG_EXTICR2_EXTI6_PG

#define SYSCFG_EXTICR2_EXTI6_PH

#define SYSCFG_EXTICR2_EXTI6_PI

#define SYSCFG_EXTICR2_EXTI6_PJ

#define SYSCFG_EXTICR2_EXTI6_PK

#define SYSCFG_EXTICR2_EXTI7_PA

#define SYSCFG_EXTICR2_EXTI7_PB

#define SYSCFG_EXTICR2_EXTI7_PC

#define SYSCFG_EXTICR2_EXTI7_PD

#define SYSCFG_EXTICR2_EXTI7_PE

#define SYSCFG_EXTICR2_EXTI7_PF

#define SYSCFG_EXTICR2_EXTI7_PG

#define SYSCFG_EXTICR2_EXTI7_PH

#define SYSCFG_EXTICR2_EXTI7_PI

#define SYSCFG_EXTICR2_EXTI7_PJ

#define SYSCFG_EXTICR2_EXTI7_PK

Bit definition for SYSCFG_EXTICR3 register

#define SYSCFG_EXTICR3_EXTI8_Pos

#define SYSCFG_EXTICR3_EXTI8_Msk

#define SYSCFG_EXTICR3_EXTI8

#define SYSCFG_EXTICR3_EXTI9_Pos

#define SYSCFG_EXTICR3_EXTI9_Msk

#define SYSCFG_EXTICR3_EXTI9

#define SYSCFG_EXTICR3_EXTI10_Pos

#define SYSCFG_EXTICR3_EXTI10_Msk

#define SYSCFG_EXTICR3_EXTI10

#define SYSCFG_EXTICR3_EXTI11_Pos

#define SYSCFG_EXTICR3_EXTI11_Msk

#define SYSCFG_EXTICR3_EXTI11

#define SYSCFG_EXTICR3_EXTI8_PA

#define SYSCFG_EXTICR3_EXTI8_PB

#define SYSCFG_EXTICR3_EXTI8_PC

#define SYSCFG_EXTICR3_EXTI8_PD

#define SYSCFG_EXTICR3_EXTI8_PE

#define SYSCFG_EXTICR3_EXTI8_PF

#define SYSCFG_EXTICR3_EXTI8_PG

#define SYSCFG_EXTICR3_EXTI8_PH

#define SYSCFG_EXTICR3_EXTI8_PI

#define SYSCFG_EXTICR3_EXTI8_PJ

#define SYSCFG_EXTICR3_EXTI9_PA

#define SYSCFG_EXTICR3_EXTI9_PB

#define SYSCFG_EXTICR3_EXTI9_PC

#define SYSCFG_EXTICR3_EXTI9_PD

#define SYSCFG_EXTICR3_EXTI9_PE

#define SYSCFG_EXTICR3_EXTI9_PF

#define SYSCFG_EXTICR3_EXTI9_PG

#define SYSCFG_EXTICR3_EXTI9_PH

#define SYSCFG_EXTICR3_EXTI9_PI

#define SYSCFG_EXTICR3_EXTI9_PJ

#define SYSCFG_EXTICR3_EXTI10_PA

#define SYSCFG_EXTICR3_EXTI10_PB

#define SYSCFG_EXTICR3_EXTI10_PC

#define SYSCFG_EXTICR3_EXTI10_PD

#define SYSCFG_EXTICR3_EXTI10_PE

#define SYSCFG_EXTICR3_EXTI10_PF

#define SYSCFG_EXTICR3_EXTI10_PG

#define SYSCFG_EXTICR3_EXTI10_PH

#define SYSCFG_EXTICR3_EXTI10_PI

#define SYSCFG_EXTICR3_EXTI10_PJ

#define SYSCFG_EXTICR3_EXTI11_PA

#define SYSCFG_EXTICR3_EXTI11_PB

#define SYSCFG_EXTICR3_EXTI11_PC

#define SYSCFG_EXTICR3_EXTI11_PD

#define SYSCFG_EXTICR3_EXTI11_PE

#define SYSCFG_EXTICR3_EXTI11_PF

#define SYSCFG_EXTICR3_EXTI11_PG

#define SYSCFG_EXTICR3_EXTI11_PH

#define SYSCFG_EXTICR3_EXTI11_PI

#define SYSCFG_EXTICR3_EXTI11_PJ

Bit definition for SYSCFG_EXTICR4 register

#define SYSCFG_EXTICR4_EXTI12_Pos

#define SYSCFG_EXTICR4_EXTI12_Msk

#define SYSCFG_EXTICR4_EXTI12

#define SYSCFG_EXTICR4_EXTI13_Pos

#define SYSCFG_EXTICR4_EXTI13_Msk

#define SYSCFG_EXTICR4_EXTI13

#define SYSCFG_EXTICR4_EXTI14_Pos

#define SYSCFG_EXTICR4_EXTI14_Msk

#define SYSCFG_EXTICR4_EXTI14

#define SYSCFG_EXTICR4_EXTI15_Pos

#define SYSCFG_EXTICR4_EXTI15_Msk

#define SYSCFG_EXTICR4_EXTI15

#define SYSCFG_EXTICR4_EXTI12_PA

#define SYSCFG_EXTICR4_EXTI12_PB

#define SYSCFG_EXTICR4_EXTI12_PC

#define SYSCFG_EXTICR4_EXTI12_PD

#define SYSCFG_EXTICR4_EXTI12_PE

#define SYSCFG_EXTICR4_EXTI12_PF

#define SYSCFG_EXTICR4_EXTI12_PG

#define SYSCFG_EXTICR4_EXTI12_PH

#define SYSCFG_EXTICR4_EXTI12_PI

#define SYSCFG_EXTICR4_EXTI12_PJ

#define SYSCFG_EXTICR4_EXTI13_PA

#define SYSCFG_EXTICR4_EXTI13_PB

#define SYSCFG_EXTICR4_EXTI13_PC

#define SYSCFG_EXTICR4_EXTI13_PD

#define SYSCFG_EXTICR4_EXTI13_PE

#define SYSCFG_EXTICR4_EXTI13_PF

#define SYSCFG_EXTICR4_EXTI13_PG

#define SYSCFG_EXTICR4_EXTI13_PH

#define SYSCFG_EXTICR4_EXTI13_PI

#define SYSCFG_EXTICR4_EXTI13_PJ

#define SYSCFG_EXTICR4_EXTI14_PA

#define SYSCFG_EXTICR4_EXTI14_PB

#define SYSCFG_EXTICR4_EXTI14_PC

#define SYSCFG_EXTICR4_EXTI14_PD

#define SYSCFG_EXTICR4_EXTI14_PE

#define SYSCFG_EXTICR4_EXTI14_PF

#define SYSCFG_EXTICR4_EXTI14_PG

#define SYSCFG_EXTICR4_EXTI14_PH

#define SYSCFG_EXTICR4_EXTI14_PI

#define SYSCFG_EXTICR4_EXTI14_PJ

#define SYSCFG_EXTICR4_EXTI15_PA

#define SYSCFG_EXTICR4_EXTI15_PB

#define SYSCFG_EXTICR4_EXTI15_PC

#define SYSCFG_EXTICR4_EXTI15_PD

#define SYSCFG_EXTICR4_EXTI15_PE

#define SYSCFG_EXTICR4_EXTI15_PF

#define SYSCFG_EXTICR4_EXTI15_PG

#define SYSCFG_EXTICR4_EXTI15_PH

#define SYSCFG_EXTICR4_EXTI15_PI

#define SYSCFG_EXTICR4_EXTI15_PJ

Bit definition for SYSCFG_CMPCR register

#define SYSCFG_CMPCR_CMP_PD_Pos

#define SYSCFG_CMPCR_CMP_PD_Msk

#define SYSCFG_CMPCR_CMP_PD

#define SYSCFG_CMPCR_READY_Pos

#define SYSCFG_CMPCR_READY_Msk

#define SYSCFG_CMPCR_READY

...

Bit definition for TIM_CR1 register

#define TIM_CR1_CEN_Pos

#define TIM_CR1_CEN_Msk

#define TIM_CR1_CEN

#define TIM_CR1_UDIS_Pos

#define TIM_CR1_UDIS_Msk

#define TIM_CR1_UDIS

#define TIM_CR1_URS_Pos

#define TIM_CR1_URS_Msk

#define TIM_CR1_URS

#define TIM_CR1_OPM_Pos

#define TIM_CR1_OPM_Msk

#define TIM_CR1_OPM

#define TIM_CR1_DIR_Pos

#define TIM_CR1_DIR_Msk

#define TIM_CR1_DIR

#define TIM_CR1_CMS_Pos

#define TIM_CR1_CMS_Msk

#define TIM_CR1_CMS

#define TIM_CR1_CMS_0

#define TIM_CR1_CMS_1

#define TIM_CR1_ARPE_Pos

#define TIM_CR1_ARPE_Msk

#define TIM_CR1_ARPE

#define TIM_CR1_CKD_Pos

#define TIM_CR1_CKD_Msk

#define TIM_CR1_CKD

#define TIM_CR1_CKD_0

#define TIM_CR1_CKD_1

Bit definition for TIM_CR2 register

#define TIM_CR2_CCPC_Pos

#define TIM_CR2_CCPC_Msk

#define TIM_CR2_CCPC

#define TIM_CR2_CCUS_Pos

#define TIM_CR2_CCUS_Msk

#define TIM_CR2_CCUS

#define TIM_CR2_CCDS_Pos

#define TIM_CR2_CCDS_Msk

#define TIM_CR2_CCDS

#define TIM_CR2_MMS_Pos

#define TIM_CR2_MMS_Msk

#define TIM_CR2_MMS

#define TIM_CR2_MMS_0

#define TIM_CR2_MMS_1

#define TIM_CR2_MMS_2

#define TIM_CR2_TI1S_Pos

#define TIM_CR2_TI1S_Msk

#define TIM_CR2_TI1S

#define TIM_CR2_OIS1_Pos

#define TIM_CR2_OIS1_Msk

#define TIM_CR2_OIS1

#define TIM_CR2_OIS1N_Pos

#define TIM_CR2_OIS1N_Msk

#define TIM_CR2_OIS1N

#define TIM_CR2_OIS2_Pos

#define TIM_CR2_OIS2_Msk

#define TIM_CR2_OIS2

#define TIM_CR2_OIS2N_Pos

#define TIM_CR2_OIS2N_Msk

#define TIM_CR2_OIS2N

#define TIM_CR2_OIS3_Pos

#define TIM_CR2_OIS3_Msk

#define TIM_CR2_OIS3

#define TIM_CR2_OIS3N_Pos

#define TIM_CR2_OIS3N_Msk

#define TIM_CR2_OIS3N

#define TIM_CR2_OIS4_Pos

#define TIM_CR2_OIS4_Msk

#define TIM_CR2_OIS4

Bit definition for TIM_SMCR register

#define TIM_SMCR_SMS_Pos

#define TIM_SMCR_SMS_Msk

#define TIM_SMCR_SMS

#define TIM_SMCR_SMS_0

#define TIM_SMCR_SMS_1

#define TIM_SMCR_SMS_2

#define TIM_SMCR_TS_Pos

#define TIM_SMCR_TS_Msk

#define TIM_SMCR_TS

#define TIM_SMCR_TS_0

#define TIM_SMCR_TS_1

#define TIM_SMCR_TS_2

#define TIM_SMCR_MSM_Pos

#define TIM_SMCR_MSM_Msk

#define TIM_SMCR_MSM

#define TIM_SMCR_ETF_Pos

#define TIM_SMCR_ETF_Msk

#define TIM_SMCR_ETF

#define TIM_SMCR_ETF_0

#define TIM_SMCR_ETF_1

#define TIM_SMCR_ETF_2

#define TIM_SMCR_ETF_3

#define TIM_SMCR_ETPS_Pos

#define TIM_SMCR_ETPS_Msk

#define TIM_SMCR_ETPS

#define TIM_SMCR_ETPS_0

#define TIM_SMCR_ETPS_1

#define TIM_SMCR_ECE_Pos

#define TIM_SMCR_ECE_Msk

#define TIM_SMCR_ECE

#define TIM_SMCR_ETP_Pos

#define TIM_SMCR_ETP_Msk

#define TIM_SMCR_ETP

Bit definition for TIM_DIER register

#define TIM_DIER_UIE_Pos

#define TIM_DIER_UIE_Msk

#define TIM_DIER_UIE

#define TIM_DIER_CC1IE_Pos

#define TIM_DIER_CC1IE_Msk

#define TIM_DIER_CC1IE

#define TIM_DIER_CC2IE_Pos

#define TIM_DIER_CC2IE_Msk

#define TIM_DIER_CC2IE

#define TIM_DIER_CC3IE_Pos

#define TIM_DIER_CC3IE_Msk

#define TIM_DIER_CC3IE

#define TIM_DIER_CC4IE_Pos

#define TIM_DIER_CC4IE_Msk

#define TIM_DIER_CC4IE

#define TIM_DIER_COMIE_Pos

#define TIM_DIER_COMIE_Msk

#define TIM_DIER_COMIE

#define TIM_DIER_TIE_Pos

#define TIM_DIER_TIE_Msk

#define TIM_DIER_TIE

#define TIM_DIER_BIE_Pos

#define TIM_DIER_BIE_Msk

#define TIM_DIER_BIE

#define TIM_DIER_UDE_Pos

#define TIM_DIER_UDE_Msk

#define TIM_DIER_UDE

#define TIM_DIER_CC1DE_Pos

#define TIM_DIER_CC1DE_Msk

#define TIM_DIER_CC1DE

#define TIM_DIER_CC2DE_Pos

#define TIM_DIER_CC2DE_Msk

#define TIM_DIER_CC2DE

#define TIM_DIER_CC3DE_Pos

#define TIM_DIER_CC3DE_Msk

#define TIM_DIER_CC3DE

#define TIM_DIER_CC4DE_Pos

#define TIM_DIER_CC4DE_Msk

#define TIM_DIER_CC4DE

#define TIM_DIER_COMDE_Pos

#define TIM_DIER_COMDE_Msk

#define TIM_DIER_COMDE

#define TIM_DIER_TDE_Pos

#define TIM_DIER_TDE_Msk

#define TIM_DIER_TDE

Bit definition for TIM_SR register

#define TIM_SR_UIF_Pos

#define TIM_SR_UIF_Msk

#define TIM_SR_UIF

#define TIM_SR_CC1IF_Pos

#define TIM_SR_CC1IF_Msk

#define TIM_SR_CC1IF

#define TIM_SR_CC2IF_Pos

#define TIM_SR_CC2IF_Msk

#define TIM_SR_CC2IF

#define TIM_SR_CC3IF_Pos

#define TIM_SR_CC3IF_Msk

#define TIM_SR_CC3IF

#define TIM_SR_CC4IF_Pos

#define TIM_SR_CC4IF_Msk

#define TIM_SR_CC4IF

#define TIM_SR_COMIF_Pos

#define TIM_SR_COMIF_Msk

#define TIM_SR_COMIF

#define TIM_SR_TIF_Pos

#define TIM_SR_TIF_Msk

#define TIM_SR_TIF

#define TIM_SR_BIF_Pos

#define TIM_SR_BIF_Msk

#define TIM_SR_BIF

#define TIM_SR_CC1OF_Pos

#define TIM_SR_CC1OF_Msk

#define TIM_SR_CC1OF

#define TIM_SR_CC2OF_Pos

#define TIM_SR_CC2OF_Msk

#define TIM_SR_CC2OF

#define TIM_SR_CC3OF_Pos

#define TIM_SR_CC3OF_Msk

#define TIM_SR_CC3OF

#define TIM_SR_CC4OF_Pos

#define TIM_SR_CC4OF_Msk

#define TIM_SR_CC4OF

Bit definition for TIM_EGR register

#define TIM_EGR_UG_Pos

#define TIM_EGR_UG_Msk

#define TIM_EGR_UG

#define TIM_EGR_CC1G_Pos

#define TIM_EGR_CC1G_Msk

#define TIM_EGR_CC1G

#define TIM_EGR_CC2G_Pos

#define TIM_EGR_CC2G_Msk

#define TIM_EGR_CC2G

#define TIM_EGR_CC3G_Pos

#define TIM_EGR_CC3G_Msk

#define TIM_EGR_CC3G

#define TIM_EGR_CC4G_Pos

#define TIM_EGR_CC4G_Msk

#define TIM_EGR_CC4G

#define TIM_EGR_COMG_Pos

#define TIM_EGR_COMG_Msk

#define TIM_EGR_COMG

#define TIM_EGR_TG_Pos

#define TIM_EGR_TG_Msk

#define TIM_EGR_TG

#define TIM_EGR_BG_Pos

#define TIM_EGR_BG_Msk

#define TIM_EGR_BG

Bit definition for TIM_CCMR1 register

#define TIM_CCMR1_CC1S_Pos

#define TIM_CCMR1_CC1S_Msk

#define TIM_CCMR1_CC1S

#define TIM_CCMR1_CC1S_0

#define TIM_CCMR1_CC1S_1

#define TIM_CCMR1_OC1FE_Pos

#define TIM_CCMR1_OC1FE_Msk

#define TIM_CCMR1_OC1FE

#define TIM_CCMR1_OC1PE_Pos

#define TIM_CCMR1_OC1PE_Msk

#define TIM_CCMR1_OC1PE

#define TIM_CCMR1_OC1M_Pos

#define TIM_CCMR1_OC1M_Msk

#define TIM_CCMR1_OC1M

#define TIM_CCMR1_OC1M_0

#define TIM_CCMR1_OC1M_1

#define TIM_CCMR1_OC1M_2

#define TIM_CCMR1_OC1CE_Pos

#define TIM_CCMR1_OC1CE_Msk

#define TIM_CCMR1_OC1CE

#define TIM_CCMR1_CC2S_Pos

#define TIM_CCMR1_CC2S_Msk

#define TIM_CCMR1_CC2S

#define TIM_CCMR1_CC2S_0

#define TIM_CCMR1_CC2S_1

#define TIM_CCMR1_OC2FE_Pos

#define TIM_CCMR1_OC2FE_Msk

#define TIM_CCMR1_OC2FE

#define TIM_CCMR1_OC2PE_Pos

#define TIM_CCMR1_OC2PE_Msk

#define TIM_CCMR1_OC2PE

#define TIM_CCMR1_OC2M_Pos

#define TIM_CCMR1_OC2M_Msk

#define TIM_CCMR1_OC2M

#define TIM_CCMR1_OC2M_0

#define TIM_CCMR1_OC2M_1

#define TIM_CCMR1_OC2M_2

#define TIM_CCMR1_OC2CE_Pos

#define TIM_CCMR1_OC2CE_Msk

#define TIM_CCMR1_OC2CE

#define TIM_CCMR1_IC1PSC_Pos

#define TIM_CCMR1_IC1PSC_Msk

#define TIM_CCMR1_IC1PSC

#define TIM_CCMR1_IC1PSC_0

#define TIM_CCMR1_IC1PSC_1

#define TIM_CCMR1_IC1F_Pos

#define TIM_CCMR1_IC1F_Msk

#define TIM_CCMR1_IC1F

#define TIM_CCMR1_IC1F_0

#define TIM_CCMR1_IC1F_1

#define TIM_CCMR1_IC1F_2

#define TIM_CCMR1_IC1F_3

#define TIM_CCMR1_IC2PSC_Pos

#define TIM_CCMR1_IC2PSC_Msk

#define TIM_CCMR1_IC2PSC

#define TIM_CCMR1_IC2PSC_0

#define TIM_CCMR1_IC2PSC_1

#define TIM_CCMR1_IC2F_Pos

#define TIM_CCMR1_IC2F_Msk

#define TIM_CCMR1_IC2F

#define TIM_CCMR1_IC2F_0

#define TIM_CCMR1_IC2F_1

#define TIM_CCMR1_IC2F_2

#define TIM_CCMR1_IC2F_3

Bit definition for TIM_CCMR2 register

#define TIM_CCMR2_CC3S_Pos

#define TIM_CCMR2_CC3S_Msk

#define TIM_CCMR2_CC3S

#define TIM_CCMR2_CC3S_0

#define TIM_CCMR2_CC3S_1

#define TIM_CCMR2_OC3FE_Pos

#define TIM_CCMR2_OC3FE_Msk

#define TIM_CCMR2_OC3FE

#define TIM_CCMR2_OC3PE_Pos

#define TIM_CCMR2_OC3PE_Msk

#define TIM_CCMR2_OC3PE

#define TIM_CCMR2_OC3M_Pos

#define TIM_CCMR2_OC3M_Msk

#define TIM_CCMR2_OC3M

#define TIM_CCMR2_OC3M_0

#define TIM_CCMR2_OC3M_1

#define TIM_CCMR2_OC3M_2

#define TIM_CCMR2_OC3CE_Pos

#define TIM_CCMR2_OC3CE_Msk

#define TIM_CCMR2_OC3CE

#define TIM_CCMR2_CC4S_Pos

#define TIM_CCMR2_CC4S_Msk

#define TIM_CCMR2_CC4S

#define TIM_CCMR2_CC4S_0

#define TIM_CCMR2_CC4S_1

#define TIM_CCMR2_OC4FE_Pos

#define TIM_CCMR2_OC4FE_Msk

#define TIM_CCMR2_OC4FE

#define TIM_CCMR2_OC4PE_Pos

#define TIM_CCMR2_OC4PE_Msk

#define TIM_CCMR2_OC4PE

#define TIM_CCMR2_OC4M_Pos

#define TIM_CCMR2_OC4M_Msk

#define TIM_CCMR2_OC4M

#define TIM_CCMR2_OC4M_0

#define TIM_CCMR2_OC4M_1

#define TIM_CCMR2_OC4M_2

#define TIM_CCMR2_OC4CE_Pos

#define TIM_CCMR2_OC4CE_Msk

#define TIM_CCMR2_OC4CE

#define TIM_CCMR2_IC3PSC_Pos

#define TIM_CCMR2_IC3PSC_Msk

#define TIM_CCMR2_IC3PSC

#define TIM_CCMR2_IC3PSC_0

#define TIM_CCMR2_IC3PSC_1

#define TIM_CCMR2_IC3F_Pos

#define TIM_CCMR2_IC3F_Msk

#define TIM_CCMR2_IC3F

#define TIM_CCMR2_IC3F_0

#define TIM_CCMR2_IC3F_1

#define TIM_CCMR2_IC3F_2

#define TIM_CCMR2_IC3F_3

#define TIM_CCMR2_IC4PSC_Pos

#define TIM_CCMR2_IC4PSC_Msk

#define TIM_CCMR2_IC4PSC

#define TIM_CCMR2_IC4PSC_0

#define TIM_CCMR2_IC4PSC_1

#define TIM_CCMR2_IC4F_Pos

#define TIM_CCMR2_IC4F_Msk

#define TIM_CCMR2_IC4F

#define TIM_CCMR2_IC4F_0

#define TIM_CCMR2_IC4F_1

#define TIM_CCMR2_IC4F_2

#define TIM_CCMR2_IC4F_3

Bit definition for TIM_CCER register

#define TIM_CCER_CC1E_Pos

#define TIM_CCER_CC1E_Msk

#define TIM_CCER_CC1E

#define TIM_CCER_CC1P_Pos

#define TIM_CCER_CC1P_Msk

#define TIM_CCER_CC1P

#define TIM_CCER_CC1NE_Pos

#define TIM_CCER_CC1NE_Msk

#define TIM_CCER_CC1NE

#define TIM_CCER_CC1NP_Pos

#define TIM_CCER_CC1NP_Msk

#define TIM_CCER_CC1NP

#define TIM_CCER_CC2E_Pos

#define TIM_CCER_CC2E_Msk

#define TIM_CCER_CC2E

#define TIM_CCER_CC2P_Pos

#define TIM_CCER_CC2P_Msk

#define TIM_CCER_CC2P

#define TIM_CCER_CC2NE_Pos

#define TIM_CCER_CC2NE_Msk

#define TIM_CCER_CC2NE

#define TIM_CCER_CC2NP_Pos

#define TIM_CCER_CC2NP_Msk

#define TIM_CCER_CC2NP

#define TIM_CCER_CC3E_Pos

#define TIM_CCER_CC3E_Msk

#define TIM_CCER_CC3E

#define TIM_CCER_CC3P_Pos

#define TIM_CCER_CC3P_Msk

#define TIM_CCER_CC3P

#define TIM_CCER_CC3NE_Pos

#define TIM_CCER_CC3NE_Msk

#define TIM_CCER_CC3NE

#define TIM_CCER_CC3NP_Pos

#define TIM_CCER_CC3NP_Msk

#define TIM_CCER_CC3NP

#define TIM_CCER_CC4E_Pos

#define TIM_CCER_CC4E_Msk

#define TIM_CCER_CC4E

#define TIM_CCER_CC4P_Pos

#define TIM_CCER_CC4P_Msk

#define TIM_CCER_CC4P

#define TIM_CCER_CC4NP_Pos

#define TIM_CCER_CC4NP_Msk

#define TIM_CCER_CC4NP

Bit definition for TIM_CNT register

#define TIM_CNT_CNT_Pos

#define TIM_CNT_CNT_Msk

#define TIM_CNT_CNT

Bit definition for TIM_PSC register

#define TIM_PSC_PSC_Pos

#define TIM_PSC_PSC_Msk

#define TIM_PSC_PSC

Bit definition for TIM_ARR register

#define TIM_ARR_ARR_Pos

#define TIM_ARR_ARR_Msk

#define TIM_ARR_ARR

Bit definition for TIM_RCR register

#define TIM_RCR_REP_Pos

#define TIM_RCR_REP_Msk

#define TIM_RCR_REP

Bit definition for TIM_CCR1 register

#define TIM_CCR1_CCR1_Pos

#define TIM_CCR1_CCR1_Msk

#define TIM_CCR1_CCR1

Bit definition for TIM_CCR2 register

#define TIM_CCR2_CCR2_Pos

#define TIM_CCR2_CCR2_Msk

#define TIM_CCR2_CCR2

Bit definition for TIM_CCR3 register

#define TIM_CCR3_CCR3_Pos

#define TIM_CCR3_CCR3_Msk

#define TIM_CCR3_CCR3

Bit definition for TIM_CCR4 register

#define TIM_CCR4_CCR4_Pos

#define TIM_CCR4_CCR4_Msk

#define TIM_CCR4_CCR4

Bit definition for TIM_BDTR register

#define TIM_BDTR_DTG_Pos

#define TIM_BDTR_DTG_Msk

#define TIM_BDTR_DTG

#define TIM_BDTR_DTG_0

#define TIM_BDTR_DTG_1

#define TIM_BDTR_DTG_2

#define TIM_BDTR_DTG_3

#define TIM_BDTR_DTG_4

#define TIM_BDTR_DTG_5

#define TIM_BDTR_DTG_6

#define TIM_BDTR_DTG_7

#define TIM_BDTR_LOCK_Pos

#define TIM_BDTR_LOCK_Msk

#define TIM_BDTR_LOCK

#define TIM_BDTR_LOCK_0

#define TIM_BDTR_LOCK_1

#define TIM_BDTR_OSSI_Pos

#define TIM_BDTR_OSSI_Msk

#define TIM_BDTR_OSSI

#define TIM_BDTR_OSSR_Pos

#define TIM_BDTR_OSSR_Msk

#define TIM_BDTR_OSSR

#define TIM_BDTR_BKE_Pos

#define TIM_BDTR_BKE_Msk

#define TIM_BDTR_BKE

#define TIM_BDTR_BKP_Pos

#define TIM_BDTR_BKP_Msk

#define TIM_BDTR_BKP

#define TIM_BDTR_AOE_Pos

#define TIM_BDTR_AOE_Msk

#define TIM_BDTR_AOE

#define TIM_BDTR_MOE_Pos

#define TIM_BDTR_MOE_Msk

#define TIM_BDTR_MOE

Bit definition for TIM_DCR register

#define TIM_DCR_DBA_Pos

#define TIM_DCR_DBA_Msk

#define TIM_DCR_DBA

#define TIM_DCR_DBA_0

#define TIM_DCR_DBA_1

#define TIM_DCR_DBA_2

#define TIM_DCR_DBA_3

#define TIM_DCR_DBA_4

#define TIM_DCR_DBL_Pos

#define TIM_DCR_DBL_Msk

#define TIM_DCR_DBL

#define TIM_DCR_DBL_0

#define TIM_DCR_DBL_1

#define TIM_DCR_DBL_2

#define TIM_DCR_DBL_3

#define TIM_DCR_DBL_4

Bit definition for TIM_DMAR register

#define TIM_DMAR_DMAB_Pos

#define TIM_DMAR_DMAB_Msk

#define TIM_DMAR_DMAB

Bit definition for TIM_OR register

#define TIM_OR_TI1_RMP_Pos

#define TIM_OR_TI1_RMP_Msk

#define TIM_OR_TI1_RMP

#define TIM_OR_TI1_RMP_0

#define TIM_OR_TI1_RMP_1

#define TIM_OR_TI4_RMP_Pos

#define TIM_OR_TI4_RMP_Msk

#define TIM_OR_TI4_RMP

#define TIM_OR_TI4_RMP_0

#define TIM_OR_TI4_RMP_1

#define TIM_OR_ITR1_RMP_Pos

#define TIM_OR_ITR1_RMP_Msk

#define TIM_OR_ITR1_RMP

#define TIM_OR_ITR1_RMP_0

#define TIM_OR_ITR1_RMP_1

...

Bit definition for USART_SR register

#define USART_SR_PE_Pos

#define USART_SR_PE_Msk

#define USART_SR_PE

#define USART_SR_FE_Pos

#define USART_SR_FE_Msk

#define USART_SR_FE

#define USART_SR_NE_Pos

#define USART_SR_NE_Msk

#define USART_SR_NE

#define USART_SR_ORE_Pos

#define USART_SR_ORE_Msk

#define USART_SR_ORE

#define USART_SR_IDLE_Pos

#define USART_SR_IDLE_Msk

#define USART_SR_IDLE

#define USART_SR_RXNE_Pos

#define USART_SR_RXNE_Msk

#define USART_SR_RXNE

#define USART_SR_TC_Pos

#define USART_SR_TC_Msk

#define USART_SR_TC

#define USART_SR_TXE_Pos

#define USART_SR_TXE_Msk

#define USART_SR_TXE

#define USART_SR_LBD_Pos

#define USART_SR_LBD_Msk

#define USART_SR_LBD

#define USART_SR_CTS_Pos

#define USART_SR_CTS_Msk

#define USART_SR_CTS

Bit definition for USART_DR register

#define USART_DR_DR_Pos

#define USART_DR_DR_Msk

#define USART_DR_DR

Bit definition for USART_BRR register

#define USART_BRR_DIV_Fraction_Pos

#define USART_BRR_DIV_Fraction_Msk

#define USART_BRR_DIV_Fraction

#define USART_BRR_DIV_Mantissa_Pos

#define USART_BRR_DIV_Mantissa_Msk

#define USART_BRR_DIV_Mantissa

Bit definition for USART_CR1 register

#define USART_CR1_SBK_Pos

#define USART_CR1_SBK_Msk

#define USART_CR1_SBK

#define USART_CR1_RWU_Pos

#define USART_CR1_RWU_Msk

#define USART_CR1_RWU

#define USART_CR1_RE_Pos

#define USART_CR1_RE_Msk

#define USART_CR1_RE

#define USART_CR1_TE_Pos

#define USART_CR1_TE_Msk

#define USART_CR1_TE

#define USART_CR1_IDLEIE_Pos

#define USART_CR1_IDLEIE_Msk

#define USART_CR1_IDLEIE

#define USART_CR1_RXNEIE_Pos

#define USART_CR1_RXNEIE_Msk

#define USART_CR1_RXNEIE

#define USART_CR1_TCIE_Pos

#define USART_CR1_TCIE_Msk

#define USART_CR1_TCIE

#define USART_CR1_TXEIE_Pos

#define USART_CR1_TXEIE_Msk

#define USART_CR1_TXEIE

#define USART_CR1_PEIE_Pos

#define USART_CR1_PEIE_Msk

#define USART_CR1_PEIE

#define USART_CR1_PS_Pos

#define USART_CR1_PS_Msk

#define USART_CR1_PS

#define USART_CR1_PCE_Pos

#define USART_CR1_PCE_Msk

#define USART_CR1_PCE

#define USART_CR1_WAKE_Pos

#define USART_CR1_WAKE_Msk

#define USART_CR1_WAKE

#define USART_CR1_M_Pos

#define USART_CR1_M_Msk

#define USART_CR1_M

#define USART_CR1_UE_Pos

#define USART_CR1_UE_Msk

#define USART_CR1_UE

#define USART_CR1_OVER8_Pos

#define USART_CR1_OVER8_Msk

#define USART_CR1_OVER8

Bit definition for USART_CR2 register

#define USART_CR2_ADD_Pos

#define USART_CR2_ADD_Msk

#define USART_CR2_ADD

#define USART_CR2_LBDL_Pos

#define USART_CR2_LBDL_Msk

#define USART_CR2_LBDL

#define USART_CR2_LBDIE_Pos

#define USART_CR2_LBDIE_Msk

#define USART_CR2_LBDIE

#define USART_CR2_LBCL_Pos

#define USART_CR2_LBCL_Msk

#define USART_CR2_LBCL

#define USART_CR2_CPHA_Pos

#define USART_CR2_CPHA_Msk

#define USART_CR2_CPHA

#define USART_CR2_CPOL_Pos

#define USART_CR2_CPOL_Msk

#define USART_CR2_CPOL

#define USART_CR2_CLKEN_Pos

#define USART_CR2_CLKEN_Msk

#define USART_CR2_CLKEN

#define USART_CR2_STOP_Pos

#define USART_CR2_STOP_Msk

#define USART_CR2_STOP

#define USART_CR2_STOP_0

#define USART_CR2_STOP_1

#define USART_CR2_LINEN_Pos

#define USART_CR2_LINEN_Msk

#define USART_CR2_LINEN

Bit definition for USART_CR3 register

#define USART_CR3_EIE_Pos

#define USART_CR3_EIE_Msk

#define USART_CR3_EIE

#define USART_CR3_IREN_Pos

#define USART_CR3_IREN_Msk

#define USART_CR3_IREN

#define USART_CR3_IRLP_Pos

#define USART_CR3_IRLP_Msk

#define USART_CR3_IRLP

#define USART_CR3_HDSEL_Pos

#define USART_CR3_HDSEL_Msk

#define USART_CR3_HDSEL

#define USART_CR3_NACK_Pos

#define USART_CR3_NACK_Msk

#define USART_CR3_NACK

#define USART_CR3_SCEN_Pos

#define USART_CR3_SCEN_Msk

#define USART_CR3_SCEN

#define USART_CR3_DMAR_Pos

#define USART_CR3_DMAR_Msk

#define USART_CR3_DMAR

#define USART_CR3_DMAT_Pos

#define USART_CR3_DMAT_Msk

#define USART_CR3_DMAT

#define USART_CR3_RTSE_Pos

#define USART_CR3_RTSE_Msk

#define USART_CR3_RTSE

#define USART_CR3_CTSE_Pos

#define USART_CR3_CTSE_Msk

#define USART_CR3_CTSE

#define USART_CR3_CTSIE_Pos

#define USART_CR3_CTSIE_Msk

#define USART_CR3_CTSIE

#define USART_CR3_ONEBIT_Pos

#define USART_CR3_ONEBIT_Msk

#define USART_CR3_ONEBIT

Bit definition for USART_GTPR register

#define USART_GTPR_PSC_Pos

#define USART_GTPR_PSC_Msk

#define USART_GTPR_PSC

#define USART_GTPR_PSC_0

#define USART_GTPR_PSC_1

#define USART_GTPR_PSC_2

#define USART_GTPR_PSC_3

#define USART_GTPR_PSC_4

#define USART_GTPR_PSC_5

#define USART_GTPR_PSC_6

#define USART_GTPR_PSC_7

#define USART_GTPR_GT_Pos

#define USART_GTPR_GT_Msk

#define USART_GTPR_GT

...

Bit definition for WWDG_CR register

#define WWDG_CR_T_Pos

#define WWDG_CR_T_Msk

#define WWDG_CR_T

#define WWDG_CR_T_0

#define WWDG_CR_T_1

#define WWDG_CR_T_2

#define WWDG_CR_T_3

#define WWDG_CR_T_4

#define WWDG_CR_T_5

#define WWDG_CR_T_6

#define WWDG_CR_T0

#define WWDG_CR_T1

#define WWDG_CR_T2

#define WWDG_CR_T3

#define WWDG_CR_T4

#define WWDG_CR_T5

#define WWDG_CR_T6

#define WWDG_CR_WDGA_Pos

#define WWDG_CR_WDGA_Msk

#define WWDG_CR_WDGA

Bit definition for WWDG_CFR register

#define WWDG_CFR_W_Pos

#define WWDG_CFR_W_Msk

#define WWDG_CFR_W

#define WWDG_CFR_W_0

#define WWDG_CFR_W_1

#define WWDG_CFR_W_2

#define WWDG_CFR_W_3

#define WWDG_CFR_W_4

#define WWDG_CFR_W_5

#define WWDG_CFR_W_6

#define WWDG_CFR_W0

#define WWDG_CFR_W1

#define WWDG_CFR_W2

#define WWDG_CFR_W3

#define WWDG_CFR_W4

#define WWDG_CFR_W5

#define WWDG_CFR_W6

#define WWDG_CFR_WDGTB_Pos

#define WWDG_CFR_WDGTB_Msk

#define WWDG_CFR_WDGTB

#define WWDG_CFR_WDGTB_0

#define WWDG_CFR_WDGTB_1

#define WWDG_CFR_WDGTB0

#define WWDG_CFR_WDGTB1

#define WWDG_CFR_EWI_Pos

#define WWDG_CFR_EWI_Msk

#define WWDG_CFR_EWI

Bit definition for WWDG_SR register

#define WWDG_SR_EWIF_Pos

#define WWDG_SR_EWIF_Msk

#define WWDG_SR_EWIF

...

Bit definition for DBGMCU_IDCODE register

#define DBGMCU_IDCODE_DEV_ID_Pos

#define DBGMCU_IDCODE_DEV_ID_Msk

#define DBGMCU_IDCODE_DEV_ID

#define DBGMCU_IDCODE_REV_ID_Pos

#define DBGMCU_IDCODE_REV_ID_Msk

#define DBGMCU_IDCODE_REV_ID

Bit definition for DBGMCU_CR register

#define DBGMCU_CR_DBG_SLEEP_Pos

#define DBGMCU_CR_DBG_SLEEP_Msk

#define DBGMCU_CR_DBG_SLEEP

#define DBGMCU_CR_DBG_STOP_Pos

#define DBGMCU_CR_DBG_STOP_Msk

#define DBGMCU_CR_DBG_STOP

#define DBGMCU_CR_DBG_STANDBY_Pos

#define DBGMCU_CR_DBG_STANDBY_Msk

#define DBGMCU_CR_DBG_STANDBY

#define DBGMCU_CR_TRACE_IOEN_Pos

#define DBGMCU_CR_TRACE_IOEN_Msk

#define DBGMCU_CR_TRACE_IOEN

#define DBGMCU_CR_TRACE_MODE_Pos

#define DBGMCU_CR_TRACE_MODE_Msk

#define DBGMCU_CR_TRACE_MODE

#define DBGMCU_CR_TRACE_MODE_0

#define DBGMCU_CR_TRACE_MODE_1

Bit definition for DBGMCU_APB1_FZ register

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP

#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM12_STOP

#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM13_STOP

#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM14_STOP

#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_RTC_STOP

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos

#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk

#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_CAN1_STOP

#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_CAN2_STOP

#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP

Bit definition for DBGMCU_APB2_FZ register

#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos

#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM1_STOP

#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos

#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM8_STOP

#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos

#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM9_STOP

#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos

#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM10_STOP

#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos

#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM11_STOP

...

#define ETH_MACCR_CSTF_Pos

#define ETH_MACCR_CSTF_Msk

#define ETH_MACCR_CSTF

#define ETH_MACCR_WD_Pos

#define ETH_MACCR_WD_Msk

#define ETH_MACCR_WD

#define ETH_MACCR_JD_Pos

#define ETH_MACCR_JD_Msk

#define ETH_MACCR_JD

#define ETH_MACCR_IFG_Pos

#define ETH_MACCR_IFG_Msk

#define ETH_MACCR_IFG

#define ETH_MACCR_IFG_96Bit

#define ETH_MACCR_IFG_88Bit

#define ETH_MACCR_IFG_80Bit

#define ETH_MACCR_IFG_72Bit

#define ETH_MACCR_IFG_64Bit

#define ETH_MACCR_IFG_56Bit

#define ETH_MACCR_IFG_48Bit

#define ETH_MACCR_IFG_40Bit

#define ETH_MACCR_CSD_Pos

#define ETH_MACCR_CSD_Msk

#define ETH_MACCR_CSD

#define ETH_MACCR_FES_Pos

#define ETH_MACCR_FES_Msk

#define ETH_MACCR_FES

#define ETH_MACCR_ROD_Pos

#define ETH_MACCR_ROD_Msk

#define ETH_MACCR_ROD

#define ETH_MACCR_LM_Pos

#define ETH_MACCR_LM_Msk

#define ETH_MACCR_LM

#define ETH_MACCR_DM_Pos

#define ETH_MACCR_DM_Msk

#define ETH_MACCR_DM

#define ETH_MACCR_IPCO_Pos

#define ETH_MACCR_IPCO_Msk

#define ETH_MACCR_IPCO

#define ETH_MACCR_RD_Pos

#define ETH_MACCR_RD_Msk

#define ETH_MACCR_RD

#define ETH_MACCR_APCS_Pos

#define ETH_MACCR_APCS_Msk

#define ETH_MACCR_APCS

#define ETH_MACCR_BL_Pos

#define ETH_MACCR_BL_Msk

#define ETH_MACCR_BL_10

#define ETH_MACCR_BL_8

#define ETH_MACCR_BL_4

#define ETH_MACCR_BL_1

#define ETH_MACCR_DC_Pos

#define ETH_MACCR_DC_Msk

#define ETH_MACCR_DC

#define ETH_MACCR_TE_Pos

#define ETH_MACCR_TE_Msk

#define ETH_MACCR_TE

#define ETH_MACCR_RE_Pos

#define ETH_MACCR_RE_Msk

#define ETH_MACCR_RE

#define ETH_MACFFR_RA_Pos

#define ETH_MACFFR_RA_Msk

#define ETH_MACFFR_RA

#define ETH_MACFFR_HPF_Pos

#define ETH_MACFFR_HPF_Msk

#define ETH_MACFFR_HPF

#define ETH_MACFFR_SAF_Pos

#define ETH_MACFFR_SAF_Msk

#define ETH_MACFFR_SAF

#define ETH_MACFFR_SAIF_Pos

#define ETH_MACFFR_SAIF_Msk

#define ETH_MACFFR_SAIF

#define ETH_MACFFR_PCF_Pos

#define ETH_MACFFR_PCF_Msk

#define ETH_MACFFR_PCF

#define ETH_MACFFR_PCF_BlockAll_Pos

#define ETH_MACFFR_PCF_BlockAll_Msk

#define ETH_MACFFR_PCF_BlockAll

#define ETH_MACFFR_PCF_ForwardAll_Pos

#define ETH_MACFFR_PCF_ForwardAll_Msk

#define ETH_MACFFR_PCF_ForwardAll

#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos

#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk

#define ETH_MACFFR_PCF_ForwardPassedAddrFilter

#define ETH_MACFFR_BFD_Pos

#define ETH_MACFFR_BFD_Msk

#define ETH_MACFFR_BFD

#define ETH_MACFFR_PAM_Pos

#define ETH_MACFFR_PAM_Msk

#define ETH_MACFFR_PAM

#define ETH_MACFFR_DAIF_Pos

#define ETH_MACFFR_DAIF_Msk

#define ETH_MACFFR_DAIF

#define ETH_MACFFR_HM_Pos

#define ETH_MACFFR_HM_Msk

#define ETH_MACFFR_HM

#define ETH_MACFFR_HU_Pos

#define ETH_MACFFR_HU_Msk

#define ETH_MACFFR_HU

#define ETH_MACFFR_PM_Pos

#define ETH_MACFFR_PM_Msk

#define ETH_MACFFR_PM

#define ETH_MACHTHR_HTH_Pos

#define ETH_MACHTHR_HTH_Msk

#define ETH_MACHTHR_HTH

#define ETH_MACHTLR_HTL_Pos

#define ETH_MACHTLR_HTL_Msk

#define ETH_MACHTLR_HTL

#define ETH_MACMIIAR_PA_Pos

#define ETH_MACMIIAR_PA_Msk

#define ETH_MACMIIAR_PA

#define ETH_MACMIIAR_MR_Pos

#define ETH_MACMIIAR_MR_Msk

#define ETH_MACMIIAR_MR

#define ETH_MACMIIAR_CR_Pos

#define ETH_MACMIIAR_CR_Msk

#define ETH_MACMIIAR_CR

#define ETH_MACMIIAR_CR_Div42

#define ETH_MACMIIAR_CR_Div62_Pos

#define ETH_MACMIIAR_CR_Div62_Msk

#define ETH_MACMIIAR_CR_Div62

#define ETH_MACMIIAR_CR_Div16_Pos

#define ETH_MACMIIAR_CR_Div16_Msk

#define ETH_MACMIIAR_CR_Div16

#define ETH_MACMIIAR_CR_Div26_Pos

#define ETH_MACMIIAR_CR_Div26_Msk

#define ETH_MACMIIAR_CR_Div26

#define ETH_MACMIIAR_CR_Div102_Pos

#define ETH_MACMIIAR_CR_Div102_Msk

#define ETH_MACMIIAR_CR_Div102

#define ETH_MACMIIAR_MW_Pos

#define ETH_MACMIIAR_MW_Msk

#define ETH_MACMIIAR_MW

#define ETH_MACMIIAR_MB_Pos

#define ETH_MACMIIAR_MB_Msk

#define ETH_MACMIIAR_MB

#define ETH_MACMIIDR_MD_Pos

#define ETH_MACMIIDR_MD_Msk

#define ETH_MACMIIDR_MD

#define ETH_MACFCR_PT_Pos

#define ETH_MACFCR_PT_Msk

#define ETH_MACFCR_PT

#define ETH_MACFCR_ZQPD_Pos

#define ETH_MACFCR_ZQPD_Msk

#define ETH_MACFCR_ZQPD

#define ETH_MACFCR_PLT_Pos

#define ETH_MACFCR_PLT_Msk

#define ETH_MACFCR_PLT

#define ETH_MACFCR_PLT_Minus4

#define ETH_MACFCR_PLT_Minus28_Pos

#define ETH_MACFCR_PLT_Minus28_Msk

#define ETH_MACFCR_PLT_Minus28

#define ETH_MACFCR_PLT_Minus144_Pos

#define ETH_MACFCR_PLT_Minus144_Msk

#define ETH_MACFCR_PLT_Minus144

#define ETH_MACFCR_PLT_Minus256_Pos

#define ETH_MACFCR_PLT_Minus256_Msk

#define ETH_MACFCR_PLT_Minus256

#define ETH_MACFCR_UPFD_Pos

#define ETH_MACFCR_UPFD_Msk

#define ETH_MACFCR_UPFD

#define ETH_MACFCR_RFCE_Pos

#define ETH_MACFCR_RFCE_Msk

#define ETH_MACFCR_RFCE

#define ETH_MACFCR_TFCE_Pos

#define ETH_MACFCR_TFCE_Msk

#define ETH_MACFCR_TFCE

#define ETH_MACFCR_FCBBPA_Pos

#define ETH_MACFCR_FCBBPA_Msk

#define ETH_MACFCR_FCBBPA

#define ETH_MACVLANTR_VLANTC_Pos

#define ETH_MACVLANTR_VLANTC_Msk

#define ETH_MACVLANTR_VLANTC

#define ETH_MACVLANTR_VLANTI_Pos

#define ETH_MACVLANTR_VLANTI_Msk

#define ETH_MACVLANTR_VLANTI

#define ETH_MACRWUFFR_D_Pos

#define ETH_MACRWUFFR_D_Msk

#define ETH_MACRWUFFR_D

#define ETH_MACPMTCSR_WFFRPR_Pos

#define ETH_MACPMTCSR_WFFRPR_Msk

#define ETH_MACPMTCSR_WFFRPR

#define ETH_MACPMTCSR_GU_Pos

#define ETH_MACPMTCSR_GU_Msk

#define ETH_MACPMTCSR_GU

#define ETH_MACPMTCSR_WFR_Pos

#define ETH_MACPMTCSR_WFR_Msk

#define ETH_MACPMTCSR_WFR

#define ETH_MACPMTCSR_MPR_Pos

#define ETH_MACPMTCSR_MPR_Msk

#define ETH_MACPMTCSR_MPR

#define ETH_MACPMTCSR_WFE_Pos

#define ETH_MACPMTCSR_WFE_Msk

#define ETH_MACPMTCSR_WFE

#define ETH_MACPMTCSR_MPE_Pos

#define ETH_MACPMTCSR_MPE_Msk

#define ETH_MACPMTCSR_MPE

#define ETH_MACPMTCSR_PD_Pos

#define ETH_MACPMTCSR_PD_Msk

#define ETH_MACPMTCSR_PD

#define ETH_MACDBGR_TFF_Pos

#define ETH_MACDBGR_TFF_Msk

#define ETH_MACDBGR_TFF

#define ETH_MACDBGR_TFNE_Pos

#define ETH_MACDBGR_TFNE_Msk

#define ETH_MACDBGR_TFNE

#define ETH_MACDBGR_TFWA_Pos

#define ETH_MACDBGR_TFWA_Msk

#define ETH_MACDBGR_TFWA

#define ETH_MACDBGR_TFRS_Pos

#define ETH_MACDBGR_TFRS_Msk

#define ETH_MACDBGR_TFRS

#define ETH_MACDBGR_TFRS_WRITING_Pos

#define ETH_MACDBGR_TFRS_WRITING_Msk

#define ETH_MACDBGR_TFRS_WRITING

#define ETH_MACDBGR_TFRS_WAITING_Pos

#define ETH_MACDBGR_TFRS_WAITING_Msk

#define ETH_MACDBGR_TFRS_WAITING

#define ETH_MACDBGR_TFRS_READ_Pos

#define ETH_MACDBGR_TFRS_READ_Msk

#define ETH_MACDBGR_TFRS_READ

#define ETH_MACDBGR_TFRS_IDLE

#define ETH_MACDBGR_MTP_Pos

#define ETH_MACDBGR_MTP_Msk

#define ETH_MACDBGR_MTP

#define ETH_MACDBGR_MTFCS_Pos

#define ETH_MACDBGR_MTFCS_Msk

#define ETH_MACDBGR_MTFCS

#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos

#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk

#define ETH_MACDBGR_MTFCS_TRANSFERRING

#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos

#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk

#define ETH_MACDBGR_MTFCS_GENERATINGPCF

#define ETH_MACDBGR_MTFCS_WAITING_Pos

#define ETH_MACDBGR_MTFCS_WAITING_Msk

#define ETH_MACDBGR_MTFCS_WAITING

#define ETH_MACDBGR_MTFCS_IDLE

#define ETH_MACDBGR_MMTEA_Pos

#define ETH_MACDBGR_MMTEA_Msk

#define ETH_MACDBGR_MMTEA

#define ETH_MACDBGR_RFFL_Pos

#define ETH_MACDBGR_RFFL_Msk

#define ETH_MACDBGR_RFFL

#define ETH_MACDBGR_RFFL_FULL_Pos

#define ETH_MACDBGR_RFFL_FULL_Msk

#define ETH_MACDBGR_RFFL_FULL

#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos

#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk

#define ETH_MACDBGR_RFFL_ABOVEFCT

#define ETH_MACDBGR_RFFL_BELOWFCT_Pos

#define ETH_MACDBGR_RFFL_BELOWFCT_Msk

#define ETH_MACDBGR_RFFL_BELOWFCT

#define ETH_MACDBGR_RFFL_EMPTY

#define ETH_MACDBGR_RFRCS_Pos

#define ETH_MACDBGR_RFRCS_Msk

#define ETH_MACDBGR_RFRCS

#define ETH_MACDBGR_RFRCS_FLUSHING_Pos

#define ETH_MACDBGR_RFRCS_FLUSHING_Msk

#define ETH_MACDBGR_RFRCS_FLUSHING

#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos

#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk

#define ETH_MACDBGR_RFRCS_STATUSREADING

#define ETH_MACDBGR_RFRCS_DATAREADING_Pos

#define ETH_MACDBGR_RFRCS_DATAREADING_Msk

#define ETH_MACDBGR_RFRCS_DATAREADING

#define ETH_MACDBGR_RFRCS_IDLE

#define ETH_MACDBGR_RFWRA_Pos

#define ETH_MACDBGR_RFWRA_Msk

#define ETH_MACDBGR_RFWRA

#define ETH_MACDBGR_MSFRWCS_Pos

#define ETH_MACDBGR_MSFRWCS_Msk

#define ETH_MACDBGR_MSFRWCS

#define ETH_MACDBGR_MSFRWCS_1

#define ETH_MACDBGR_MSFRWCS_0

#define ETH_MACDBGR_MMRPEA_Pos

#define ETH_MACDBGR_MMRPEA_Msk

#define ETH_MACDBGR_MMRPEA

#define ETH_MACSR_TSTS_Pos

#define ETH_MACSR_TSTS_Msk

#define ETH_MACSR_TSTS

#define ETH_MACSR_MMCTS_Pos

#define ETH_MACSR_MMCTS_Msk

#define ETH_MACSR_MMCTS

#define ETH_MACSR_MMMCRS_Pos

#define ETH_MACSR_MMMCRS_Msk

#define ETH_MACSR_MMMCRS

#define ETH_MACSR_MMCS_Pos

#define ETH_MACSR_MMCS_Msk

#define ETH_MACSR_MMCS

#define ETH_MACSR_PMTS_Pos

#define ETH_MACSR_PMTS_Msk

#define ETH_MACSR_PMTS

#define ETH_MACIMR_TSTIM_Pos

#define ETH_MACIMR_TSTIM_Msk

#define ETH_MACIMR_TSTIM

#define ETH_MACIMR_PMTIM_Pos

#define ETH_MACIMR_PMTIM_Msk

#define ETH_MACIMR_PMTIM

#define ETH_MACA0HR_MACA0H_Pos

#define ETH_MACA0HR_MACA0H_Msk

#define ETH_MACA0HR_MACA0H

#define ETH_MACA0LR_MACA0L_Pos

#define ETH_MACA0LR_MACA0L_Msk

#define ETH_MACA0LR_MACA0L

#define ETH_MACA1HR_AE_Pos

#define ETH_MACA1HR_AE_Msk

#define ETH_MACA1HR_AE

#define ETH_MACA1HR_SA_Pos

#define ETH_MACA1HR_SA_Msk

#define ETH_MACA1HR_SA

#define ETH_MACA1HR_MBC_Pos

#define ETH_MACA1HR_MBC_Msk

#define ETH_MACA1HR_MBC

#define ETH_MACA1HR_MBC_HBits15_8

#define ETH_MACA1HR_MBC_HBits7_0

#define ETH_MACA1HR_MBC_LBits31_24

#define ETH_MACA1HR_MBC_LBits23_16

#define ETH_MACA1HR_MBC_LBits15_8

#define ETH_MACA1HR_MBC_LBits7_0

#define ETH_MACA1HR_MACA1H_Pos

#define ETH_MACA1HR_MACA1H_Msk

#define ETH_MACA1HR_MACA1H

#define ETH_MACA1LR_MACA1L_Pos

#define ETH_MACA1LR_MACA1L_Msk

#define ETH_MACA1LR_MACA1L

#define ETH_MACA2HR_AE_Pos

#define ETH_MACA2HR_AE_Msk

#define ETH_MACA2HR_AE

#define ETH_MACA2HR_SA_Pos

#define ETH_MACA2HR_SA_Msk

#define ETH_MACA2HR_SA

#define ETH_MACA2HR_MBC_Pos

#define ETH_MACA2HR_MBC_Msk

#define ETH_MACA2HR_MBC

#define ETH_MACA2HR_MBC_HBits15_8

#define ETH_MACA2HR_MBC_HBits7_0

#define ETH_MACA2HR_MBC_LBits31_24

#define ETH_MACA2HR_MBC_LBits23_16

#define ETH_MACA2HR_MBC_LBits15_8

#define ETH_MACA2HR_MBC_LBits7_0

#define ETH_MACA2HR_MACA2H_Pos

#define ETH_MACA2HR_MACA2H_Msk

#define ETH_MACA2HR_MACA2H

#define ETH_MACA2LR_MACA2L_Pos

#define ETH_MACA2LR_MACA2L_Msk

#define ETH_MACA2LR_MACA2L

#define ETH_MACA3HR_AE_Pos

#define ETH_MACA3HR_AE_Msk

#define ETH_MACA3HR_AE

#define ETH_MACA3HR_SA_Pos

#define ETH_MACA3HR_SA_Msk

#define ETH_MACA3HR_SA

#define ETH_MACA3HR_MBC_Pos

#define ETH_MACA3HR_MBC_Msk

#define ETH_MACA3HR_MBC

#define ETH_MACA3HR_MBC_HBits15_8

#define ETH_MACA3HR_MBC_HBits7_0

#define ETH_MACA3HR_MBC_LBits31_24

#define ETH_MACA3HR_MBC_LBits23_16

#define ETH_MACA3HR_MBC_LBits15_8

#define ETH_MACA3HR_MBC_LBits7_0

#define ETH_MACA3HR_MACA3H_Pos

#define ETH_MACA3HR_MACA3H_Msk

#define ETH_MACA3HR_MACA3H

#define ETH_MACA3LR_MACA3L_Pos

#define ETH_MACA3LR_MACA3L_Msk

#define ETH_MACA3LR_MACA3L

...

#define ETH_MMCCR_MCFHP_Pos

#define ETH_MMCCR_MCFHP_Msk

#define ETH_MMCCR_MCFHP

#define ETH_MMCCR_MCP_Pos

#define ETH_MMCCR_MCP_Msk

#define ETH_MMCCR_MCP

#define ETH_MMCCR_MCF_Pos

#define ETH_MMCCR_MCF_Msk

#define ETH_MMCCR_MCF

#define ETH_MMCCR_ROR_Pos

#define ETH_MMCCR_ROR_Msk

#define ETH_MMCCR_ROR

#define ETH_MMCCR_CSR_Pos

#define ETH_MMCCR_CSR_Msk

#define ETH_MMCCR_CSR

#define ETH_MMCCR_CR_Pos

#define ETH_MMCCR_CR_Msk

#define ETH_MMCCR_CR

#define ETH_MMCRIR_RGUFS_Pos

#define ETH_MMCRIR_RGUFS_Msk

#define ETH_MMCRIR_RGUFS

#define ETH_MMCRIR_RFAES_Pos

#define ETH_MMCRIR_RFAES_Msk

#define ETH_MMCRIR_RFAES

#define ETH_MMCRIR_RFCES_Pos

#define ETH_MMCRIR_RFCES_Msk

#define ETH_MMCRIR_RFCES

#define ETH_MMCTIR_TGFS_Pos

#define ETH_MMCTIR_TGFS_Msk

#define ETH_MMCTIR_TGFS

#define ETH_MMCTIR_TGFMSCS_Pos

#define ETH_MMCTIR_TGFMSCS_Msk

#define ETH_MMCTIR_TGFMSCS

#define ETH_MMCTIR_TGFSCS_Pos

#define ETH_MMCTIR_TGFSCS_Msk

#define ETH_MMCTIR_TGFSCS

#define ETH_MMCRIMR_RGUFM_Pos

#define ETH_MMCRIMR_RGUFM_Msk

#define ETH_MMCRIMR_RGUFM

#define ETH_MMCRIMR_RFAEM_Pos

#define ETH_MMCRIMR_RFAEM_Msk

#define ETH_MMCRIMR_RFAEM

#define ETH_MMCRIMR_RFCEM_Pos

#define ETH_MMCRIMR_RFCEM_Msk

#define ETH_MMCRIMR_RFCEM

#define ETH_MMCTIMR_TGFM_Pos

#define ETH_MMCTIMR_TGFM_Msk

#define ETH_MMCTIMR_TGFM

#define ETH_MMCTIMR_TGFMSCM_Pos

#define ETH_MMCTIMR_TGFMSCM_Msk

#define ETH_MMCTIMR_TGFMSCM

#define ETH_MMCTIMR_TGFSCM_Pos

#define ETH_MMCTIMR_TGFSCM_Msk

#define ETH_MMCTIMR_TGFSCM

#define ETH_MMCTGFSCCR_TGFSCC_Pos

#define ETH_MMCTGFSCCR_TGFSCC_Msk

#define ETH_MMCTGFSCCR_TGFSCC

#define ETH_MMCTGFMSCCR_TGFMSCC_Pos

#define ETH_MMCTGFMSCCR_TGFMSCC_Msk

#define ETH_MMCTGFMSCCR_TGFMSCC

#define ETH_MMCTGFCR_TGFC_Pos

#define ETH_MMCTGFCR_TGFC_Msk

#define ETH_MMCTGFCR_TGFC

#define ETH_MMCRFCECR_RFCEC_Pos

#define ETH_MMCRFCECR_RFCEC_Msk

#define ETH_MMCRFCECR_RFCEC

#define ETH_MMCRFAECR_RFAEC_Pos

#define ETH_MMCRFAECR_RFAEC_Msk

#define ETH_MMCRFAECR_RFAEC

#define ETH_MMCRGUFCR_RGUFC_Pos

#define ETH_MMCRGUFCR_RGUFC_Msk

#define ETH_MMCRGUFCR_RGUFC

...

#define ETH_PTPTSCR_TSPFFMAE_Pos

#define ETH_PTPTSCR_TSPFFMAE_Msk

#define ETH_PTPTSCR_TSPFFMAE

#define ETH_PTPTSCR_TSCNT_Pos

#define ETH_PTPTSCR_TSCNT_Msk

#define ETH_PTPTSCR_TSCNT

#define ETH_PTPTSCR_TSSMRME_Pos

#define ETH_PTPTSCR_TSSMRME_Msk

#define ETH_PTPTSCR_TSSMRME

#define ETH_PTPTSCR_TSSEME_Pos

#define ETH_PTPTSCR_TSSEME_Msk

#define ETH_PTPTSCR_TSSEME

#define ETH_PTPTSCR_TSSIPV4FE_Pos

#define ETH_PTPTSCR_TSSIPV4FE_Msk

#define ETH_PTPTSCR_TSSIPV4FE

#define ETH_PTPTSCR_TSSIPV6FE_Pos

#define ETH_PTPTSCR_TSSIPV6FE_Msk

#define ETH_PTPTSCR_TSSIPV6FE

#define ETH_PTPTSCR_TSSPTPOEFE_Pos

#define ETH_PTPTSCR_TSSPTPOEFE_Msk

#define ETH_PTPTSCR_TSSPTPOEFE

#define ETH_PTPTSCR_TSPTPPSV2E_Pos

#define ETH_PTPTSCR_TSPTPPSV2E_Msk

#define ETH_PTPTSCR_TSPTPPSV2E

#define ETH_PTPTSCR_TSSSR_Pos

#define ETH_PTPTSCR_TSSSR_Msk

#define ETH_PTPTSCR_TSSSR

#define ETH_PTPTSCR_TSSARFE_Pos

#define ETH_PTPTSCR_TSSARFE_Msk

#define ETH_PTPTSCR_TSSARFE

#define ETH_PTPTSCR_TSARU_Pos

#define ETH_PTPTSCR_TSARU_Msk

#define ETH_PTPTSCR_TSARU

#define ETH_PTPTSCR_TSITE_Pos

#define ETH_PTPTSCR_TSITE_Msk

#define ETH_PTPTSCR_TSITE

#define ETH_PTPTSCR_TSSTU_Pos

#define ETH_PTPTSCR_TSSTU_Msk

#define ETH_PTPTSCR_TSSTU

#define ETH_PTPTSCR_TSSTI_Pos

#define ETH_PTPTSCR_TSSTI_Msk

#define ETH_PTPTSCR_TSSTI

#define ETH_PTPTSCR_TSFCU_Pos

#define ETH_PTPTSCR_TSFCU_Msk

#define ETH_PTPTSCR_TSFCU

#define ETH_PTPTSCR_TSE_Pos

#define ETH_PTPTSCR_TSE_Msk

#define ETH_PTPTSCR_TSE

#define ETH_PTPSSIR_STSSI_Pos

#define ETH_PTPSSIR_STSSI_Msk

#define ETH_PTPSSIR_STSSI

#define ETH_PTPTSHR_STS_Pos

#define ETH_PTPTSHR_STS_Msk

#define ETH_PTPTSHR_STS

#define ETH_PTPTSLR_STPNS_Pos

#define ETH_PTPTSLR_STPNS_Msk

#define ETH_PTPTSLR_STPNS

#define ETH_PTPTSLR_STSS_Pos

#define ETH_PTPTSLR_STSS_Msk

#define ETH_PTPTSLR_STSS

#define ETH_PTPTSHUR_TSUS_Pos

#define ETH_PTPTSHUR_TSUS_Msk

#define ETH_PTPTSHUR_TSUS

#define ETH_PTPTSLUR_TSUPNS_Pos

#define ETH_PTPTSLUR_TSUPNS_Msk

#define ETH_PTPTSLUR_TSUPNS

#define ETH_PTPTSLUR_TSUSS_Pos

#define ETH_PTPTSLUR_TSUSS_Msk

#define ETH_PTPTSLUR_TSUSS

#define ETH_PTPTSAR_TSA_Pos

#define ETH_PTPTSAR_TSA_Msk

#define ETH_PTPTSAR_TSA

#define ETH_PTPTTHR_TTSH_Pos

#define ETH_PTPTTHR_TTSH_Msk

#define ETH_PTPTTHR_TTSH

#define ETH_PTPTTLR_TTSL_Pos

#define ETH_PTPTTLR_TTSL_Msk

#define ETH_PTPTTLR_TTSL

#define ETH_PTPTSSR_TSTTR_Pos

#define ETH_PTPTSSR_TSTTR_Msk

#define ETH_PTPTSSR_TSTTR

#define ETH_PTPTSSR_TSSO_Pos

#define ETH_PTPTSSR_TSSO_Msk

#define ETH_PTPTSSR_TSSO

...

#define ETH_DMABMR_MB_Pos

#define ETH_DMABMR_MB_Msk

#define ETH_DMABMR_MB

#define ETH_DMABMR_AAB_Pos

#define ETH_DMABMR_AAB_Msk

#define ETH_DMABMR_AAB

#define ETH_DMABMR_FPM_Pos

#define ETH_DMABMR_FPM_Msk

#define ETH_DMABMR_FPM

#define ETH_DMABMR_USP_Pos

#define ETH_DMABMR_USP_Msk

#define ETH_DMABMR_USP

#define ETH_DMABMR_RDP_Pos

#define ETH_DMABMR_RDP_Msk

#define ETH_DMABMR_RDP

#define ETH_DMABMR_RDP_1Beat

#define ETH_DMABMR_RDP_2Beat

#define ETH_DMABMR_RDP_4Beat

#define ETH_DMABMR_RDP_8Beat

#define ETH_DMABMR_RDP_16Beat

#define ETH_DMABMR_RDP_32Beat

#define ETH_DMABMR_RDP_4xPBL_4Beat

#define ETH_DMABMR_RDP_4xPBL_8Beat

#define ETH_DMABMR_RDP_4xPBL_16Beat

#define ETH_DMABMR_RDP_4xPBL_32Beat

#define ETH_DMABMR_RDP_4xPBL_64Beat

#define ETH_DMABMR_RDP_4xPBL_128Beat

#define ETH_DMABMR_FB_Pos

#define ETH_DMABMR_FB_Msk

#define ETH_DMABMR_FB

#define ETH_DMABMR_RTPR_Pos

#define ETH_DMABMR_RTPR_Msk

#define ETH_DMABMR_RTPR

#define ETH_DMABMR_RTPR_1_1

#define ETH_DMABMR_RTPR_2_1

#define ETH_DMABMR_RTPR_3_1

#define ETH_DMABMR_RTPR_4_1

#define ETH_DMABMR_PBL_Pos

#define ETH_DMABMR_PBL_Msk

#define ETH_DMABMR_PBL

#define ETH_DMABMR_PBL_1Beat

#define ETH_DMABMR_PBL_2Beat

#define ETH_DMABMR_PBL_4Beat

#define ETH_DMABMR_PBL_8Beat

#define ETH_DMABMR_PBL_16Beat

#define ETH_DMABMR_PBL_32Beat

#define ETH_DMABMR_PBL_4xPBL_4Beat

#define ETH_DMABMR_PBL_4xPBL_8Beat

#define ETH_DMABMR_PBL_4xPBL_16Beat

#define ETH_DMABMR_PBL_4xPBL_32Beat

#define ETH_DMABMR_PBL_4xPBL_64Beat

#define ETH_DMABMR_PBL_4xPBL_128Beat

#define ETH_DMABMR_EDE_Pos

#define ETH_DMABMR_EDE_Msk

#define ETH_DMABMR_EDE

#define ETH_DMABMR_DSL_Pos

#define ETH_DMABMR_DSL_Msk

#define ETH_DMABMR_DSL

#define ETH_DMABMR_DA_Pos

#define ETH_DMABMR_DA_Msk

#define ETH_DMABMR_DA

#define ETH_DMABMR_SR_Pos

#define ETH_DMABMR_SR_Msk

#define ETH_DMABMR_SR

#define ETH_DMATPDR_TPD_Pos

#define ETH_DMATPDR_TPD_Msk

#define ETH_DMATPDR_TPD

#define ETH_DMARPDR_RPD_Pos

#define ETH_DMARPDR_RPD_Msk

#define ETH_DMARPDR_RPD

#define ETH_DMARDLAR_SRL_Pos

#define ETH_DMARDLAR_SRL_Msk

#define ETH_DMARDLAR_SRL

#define ETH_DMATDLAR_STL_Pos

#define ETH_DMATDLAR_STL_Msk

#define ETH_DMATDLAR_STL

#define ETH_DMASR_TSTS_Pos

#define ETH_DMASR_TSTS_Msk

#define ETH_DMASR_TSTS

#define ETH_DMASR_PMTS_Pos

#define ETH_DMASR_PMTS_Msk

#define ETH_DMASR_PMTS

#define ETH_DMASR_MMCS_Pos

#define ETH_DMASR_MMCS_Msk

#define ETH_DMASR_MMCS

#define ETH_DMASR_EBS_Pos

#define ETH_DMASR_EBS_Msk

#define ETH_DMASR_EBS

#define ETH_DMASR_EBS_DescAccess_Pos

#define ETH_DMASR_EBS_DescAccess_Msk

#define ETH_DMASR_EBS_DescAccess

#define ETH_DMASR_EBS_ReadTransf_Pos

#define ETH_DMASR_EBS_ReadTransf_Msk

#define ETH_DMASR_EBS_ReadTransf

#define ETH_DMASR_EBS_DataTransfTx_Pos

#define ETH_DMASR_EBS_DataTransfTx_Msk

#define ETH_DMASR_EBS_DataTransfTx

#define ETH_DMASR_TPS_Pos

#define ETH_DMASR_TPS_Msk

#define ETH_DMASR_TPS

#define ETH_DMASR_TPS_Stopped

#define ETH_DMASR_TPS_Fetching_Pos

#define ETH_DMASR_TPS_Fetching_Msk

#define ETH_DMASR_TPS_Fetching

#define ETH_DMASR_TPS_Waiting_Pos

#define ETH_DMASR_TPS_Waiting_Msk

#define ETH_DMASR_TPS_Waiting

#define ETH_DMASR_TPS_Reading_Pos

#define ETH_DMASR_TPS_Reading_Msk

#define ETH_DMASR_TPS_Reading

#define ETH_DMASR_TPS_Suspended_Pos

#define ETH_DMASR_TPS_Suspended_Msk

#define ETH_DMASR_TPS_Suspended

#define ETH_DMASR_TPS_Closing_Pos

#define ETH_DMASR_TPS_Closing_Msk

#define ETH_DMASR_TPS_Closing

#define ETH_DMASR_RPS_Pos

#define ETH_DMASR_RPS_Msk

#define ETH_DMASR_RPS

#define ETH_DMASR_RPS_Stopped

#define ETH_DMASR_RPS_Fetching_Pos

#define ETH_DMASR_RPS_Fetching_Msk

#define ETH_DMASR_RPS_Fetching

#define ETH_DMASR_RPS_Waiting_Pos

#define ETH_DMASR_RPS_Waiting_Msk

#define ETH_DMASR_RPS_Waiting

#define ETH_DMASR_RPS_Suspended_Pos

#define ETH_DMASR_RPS_Suspended_Msk

#define ETH_DMASR_RPS_Suspended

#define ETH_DMASR_RPS_Closing_Pos

#define ETH_DMASR_RPS_Closing_Msk

#define ETH_DMASR_RPS_Closing

#define ETH_DMASR_RPS_Queuing_Pos

#define ETH_DMASR_RPS_Queuing_Msk

#define ETH_DMASR_RPS_Queuing

#define ETH_DMASR_NIS_Pos

#define ETH_DMASR_NIS_Msk

#define ETH_DMASR_NIS

#define ETH_DMASR_AIS_Pos

#define ETH_DMASR_AIS_Msk

#define ETH_DMASR_AIS

#define ETH_DMASR_ERS_Pos

#define ETH_DMASR_ERS_Msk

#define ETH_DMASR_ERS

#define ETH_DMASR_FBES_Pos

#define ETH_DMASR_FBES_Msk

#define ETH_DMASR_FBES

#define ETH_DMASR_ETS_Pos

#define ETH_DMASR_ETS_Msk

#define ETH_DMASR_ETS

#define ETH_DMASR_RWTS_Pos

#define ETH_DMASR_RWTS_Msk

#define ETH_DMASR_RWTS

#define ETH_DMASR_RPSS_Pos

#define ETH_DMASR_RPSS_Msk

#define ETH_DMASR_RPSS

#define ETH_DMASR_RBUS_Pos

#define ETH_DMASR_RBUS_Msk

#define ETH_DMASR_RBUS

#define ETH_DMASR_RS_Pos

#define ETH_DMASR_RS_Msk

#define ETH_DMASR_RS

#define ETH_DMASR_TUS_Pos

#define ETH_DMASR_TUS_Msk

#define ETH_DMASR_TUS

#define ETH_DMASR_ROS_Pos

#define ETH_DMASR_ROS_Msk

#define ETH_DMASR_ROS

#define ETH_DMASR_TJTS_Pos

#define ETH_DMASR_TJTS_Msk

#define ETH_DMASR_TJTS

#define ETH_DMASR_TBUS_Pos

#define ETH_DMASR_TBUS_Msk

#define ETH_DMASR_TBUS

#define ETH_DMASR_TPSS_Pos

#define ETH_DMASR_TPSS_Msk

#define ETH_DMASR_TPSS

#define ETH_DMASR_TS_Pos

#define ETH_DMASR_TS_Msk

#define ETH_DMASR_TS

#define ETH_DMAOMR_DTCEFD_Pos

#define ETH_DMAOMR_DTCEFD_Msk

#define ETH_DMAOMR_DTCEFD

#define ETH_DMAOMR_RSF_Pos

#define ETH_DMAOMR_RSF_Msk

#define ETH_DMAOMR_RSF

#define ETH_DMAOMR_DFRF_Pos

#define ETH_DMAOMR_DFRF_Msk

#define ETH_DMAOMR_DFRF

#define ETH_DMAOMR_TSF_Pos

#define ETH_DMAOMR_TSF_Msk

#define ETH_DMAOMR_TSF

#define ETH_DMAOMR_FTF_Pos

#define ETH_DMAOMR_FTF_Msk

#define ETH_DMAOMR_FTF

#define ETH_DMAOMR_TTC_Pos

#define ETH_DMAOMR_TTC_Msk

#define ETH_DMAOMR_TTC

#define ETH_DMAOMR_TTC_64Bytes

#define ETH_DMAOMR_TTC_128Bytes

#define ETH_DMAOMR_TTC_192Bytes

#define ETH_DMAOMR_TTC_256Bytes

#define ETH_DMAOMR_TTC_40Bytes

#define ETH_DMAOMR_TTC_32Bytes

#define ETH_DMAOMR_TTC_24Bytes

#define ETH_DMAOMR_TTC_16Bytes

#define ETH_DMAOMR_ST_Pos

#define ETH_DMAOMR_ST_Msk

#define ETH_DMAOMR_ST

#define ETH_DMAOMR_FEF_Pos

#define ETH_DMAOMR_FEF_Msk

#define ETH_DMAOMR_FEF

#define ETH_DMAOMR_FUGF_Pos

#define ETH_DMAOMR_FUGF_Msk

#define ETH_DMAOMR_FUGF

#define ETH_DMAOMR_RTC_Pos

#define ETH_DMAOMR_RTC_Msk

#define ETH_DMAOMR_RTC

#define ETH_DMAOMR_RTC_64Bytes

#define ETH_DMAOMR_RTC_32Bytes

#define ETH_DMAOMR_RTC_96Bytes

#define ETH_DMAOMR_RTC_128Bytes

#define ETH_DMAOMR_OSF_Pos

#define ETH_DMAOMR_OSF_Msk

#define ETH_DMAOMR_OSF

#define ETH_DMAOMR_SR_Pos

#define ETH_DMAOMR_SR_Msk

#define ETH_DMAOMR_SR

#define ETH_DMAIER_NISE_Pos

#define ETH_DMAIER_NISE_Msk

#define ETH_DMAIER_NISE

#define ETH_DMAIER_AISE_Pos

#define ETH_DMAIER_AISE_Msk

#define ETH_DMAIER_AISE

#define ETH_DMAIER_ERIE_Pos

#define ETH_DMAIER_ERIE_Msk

#define ETH_DMAIER_ERIE

#define ETH_DMAIER_FBEIE_Pos

#define ETH_DMAIER_FBEIE_Msk

#define ETH_DMAIER_FBEIE

#define ETH_DMAIER_ETIE_Pos

#define ETH_DMAIER_ETIE_Msk

#define ETH_DMAIER_ETIE

#define ETH_DMAIER_RWTIE_Pos

#define ETH_DMAIER_RWTIE_Msk

#define ETH_DMAIER_RWTIE

#define ETH_DMAIER_RPSIE_Pos

#define ETH_DMAIER_RPSIE_Msk

#define ETH_DMAIER_RPSIE

#define ETH_DMAIER_RBUIE_Pos

#define ETH_DMAIER_RBUIE_Msk

#define ETH_DMAIER_RBUIE

#define ETH_DMAIER_RIE_Pos

#define ETH_DMAIER_RIE_Msk

#define ETH_DMAIER_RIE

#define ETH_DMAIER_TUIE_Pos

#define ETH_DMAIER_TUIE_Msk

#define ETH_DMAIER_TUIE

#define ETH_DMAIER_ROIE_Pos

#define ETH_DMAIER_ROIE_Msk

#define ETH_DMAIER_ROIE

#define ETH_DMAIER_TJTIE_Pos

#define ETH_DMAIER_TJTIE_Msk

#define ETH_DMAIER_TJTIE

#define ETH_DMAIER_TBUIE_Pos

#define ETH_DMAIER_TBUIE_Msk

#define ETH_DMAIER_TBUIE

#define ETH_DMAIER_TPSIE_Pos

#define ETH_DMAIER_TPSIE_Msk

#define ETH_DMAIER_TPSIE

#define ETH_DMAIER_TIE_Pos

#define ETH_DMAIER_TIE_Msk

#define ETH_DMAIER_TIE

#define ETH_DMAMFBOCR_OFOC_Pos

#define ETH_DMAMFBOCR_OFOC_Msk

#define ETH_DMAMFBOCR_OFOC

#define ETH_DMAMFBOCR_MFA_Pos

#define ETH_DMAMFBOCR_MFA_Msk

#define ETH_DMAMFBOCR_MFA

#define ETH_DMAMFBOCR_OMFC_Pos

#define ETH_DMAMFBOCR_OMFC_Msk

#define ETH_DMAMFBOCR_OMFC

#define ETH_DMAMFBOCR_MFC_Pos

#define ETH_DMAMFBOCR_MFC_Msk

#define ETH_DMAMFBOCR_MFC

#define ETH_DMACHTDR_HTDAP_Pos

#define ETH_DMACHTDR_HTDAP_Msk

#define ETH_DMACHTDR_HTDAP

#define ETH_DMACHRDR_HRDAP_Pos

#define ETH_DMACHRDR_HRDAP_Msk

#define ETH_DMACHRDR_HRDAP

#define ETH_DMACHTBAR_HTBAP_Pos

#define ETH_DMACHTBAR_HTBAP_Msk

#define ETH_DMACHTBAR_HTBAP

#define ETH_DMACHRBAR_HRBAP_Pos

#define ETH_DMACHRBAR_HRBAP_Msk

#define ETH_DMACHRBAR_HRBAP

...

Bit definition for USB_OTG_GOTGCTL register

#define USB_OTG_GOTGCTL_SRQSCS_Pos

#define USB_OTG_GOTGCTL_SRQSCS_Msk

#define USB_OTG_GOTGCTL_SRQSCS

#define USB_OTG_GOTGCTL_SRQ_Pos

#define USB_OTG_GOTGCTL_SRQ_Msk

#define USB_OTG_GOTGCTL_SRQ

#define USB_OTG_GOTGCTL_HNGSCS_Pos

#define USB_OTG_GOTGCTL_HNGSCS_Msk

#define USB_OTG_GOTGCTL_HNGSCS

#define USB_OTG_GOTGCTL_HNPRQ_Pos

#define USB_OTG_GOTGCTL_HNPRQ_Msk

#define USB_OTG_GOTGCTL_HNPRQ

#define USB_OTG_GOTGCTL_HSHNPEN_Pos

#define USB_OTG_GOTGCTL_HSHNPEN_Msk

#define USB_OTG_GOTGCTL_HSHNPEN

#define USB_OTG_GOTGCTL_DHNPEN_Pos

#define USB_OTG_GOTGCTL_DHNPEN_Msk

#define USB_OTG_GOTGCTL_DHNPEN

#define USB_OTG_GOTGCTL_CIDSTS_Pos

#define USB_OTG_GOTGCTL_CIDSTS_Msk

#define USB_OTG_GOTGCTL_CIDSTS

#define USB_OTG_GOTGCTL_DBCT_Pos

#define USB_OTG_GOTGCTL_DBCT_Msk

#define USB_OTG_GOTGCTL_DBCT

#define USB_OTG_GOTGCTL_ASVLD_Pos

#define USB_OTG_GOTGCTL_ASVLD_Msk

#define USB_OTG_GOTGCTL_ASVLD

#define USB_OTG_GOTGCTL_BSVLD_Pos

#define USB_OTG_GOTGCTL_BSVLD_Msk

#define USB_OTG_GOTGCTL_BSVLD

Bit definition forUSB_OTG_HCFG register

#define USB_OTG_HCFG_FSLSPCS_Pos

#define USB_OTG_HCFG_FSLSPCS_Msk

#define USB_OTG_HCFG_FSLSPCS

#define USB_OTG_HCFG_FSLSPCS_0

#define USB_OTG_HCFG_FSLSPCS_1

#define USB_OTG_HCFG_FSLSS_Pos

#define USB_OTG_HCFG_FSLSS_Msk

#define USB_OTG_HCFG_FSLSS

Bit definition for USB_OTG_DCFG register

#define USB_OTG_DCFG_DSPD_Pos

#define USB_OTG_DCFG_DSPD_Msk

#define USB_OTG_DCFG_DSPD

#define USB_OTG_DCFG_DSPD_0

#define USB_OTG_DCFG_DSPD_1

#define USB_OTG_DCFG_NZLSOHSK_Pos

#define USB_OTG_DCFG_NZLSOHSK_Msk

#define USB_OTG_DCFG_NZLSOHSK

#define USB_OTG_DCFG_DAD_Pos

#define USB_OTG_DCFG_DAD_Msk

#define USB_OTG_DCFG_DAD

#define USB_OTG_DCFG_DAD_0

#define USB_OTG_DCFG_DAD_1

#define USB_OTG_DCFG_DAD_2

#define USB_OTG_DCFG_DAD_3

#define USB_OTG_DCFG_DAD_4

#define USB_OTG_DCFG_DAD_5

#define USB_OTG_DCFG_DAD_6

#define USB_OTG_DCFG_PFIVL_Pos

#define USB_OTG_DCFG_PFIVL_Msk

#define USB_OTG_DCFG_PFIVL

#define USB_OTG_DCFG_PFIVL_0

#define USB_OTG_DCFG_PFIVL_1

#define USB_OTG_DCFG_XCVRDLY_Pos

#define USB_OTG_DCFG_XCVRDLY_Msk

#define USB_OTG_DCFG_XCVRDLY

#define USB_OTG_DCFG_ERRATIM_Pos

#define USB_OTG_DCFG_ERRATIM_Msk

#define USB_OTG_DCFG_ERRATIM

#define USB_OTG_DCFG_PERSCHIVL_Pos

#define USB_OTG_DCFG_PERSCHIVL_Msk

#define USB_OTG_DCFG_PERSCHIVL

#define USB_OTG_DCFG_PERSCHIVL_0

#define USB_OTG_DCFG_PERSCHIVL_1

Bit definition for USB_OTG_PCGCR register

#define USB_OTG_PCGCR_STPPCLK_Pos

#define USB_OTG_PCGCR_STPPCLK_Msk

#define USB_OTG_PCGCR_STPPCLK

#define USB_OTG_PCGCR_GATEHCLK_Pos

#define USB_OTG_PCGCR_GATEHCLK_Msk

#define USB_OTG_PCGCR_GATEHCLK

#define USB_OTG_PCGCR_PHYSUSP_Pos

#define USB_OTG_PCGCR_PHYSUSP_Msk

#define USB_OTG_PCGCR_PHYSUSP

Bit definition for USB_OTG_GOTGINT register

#define USB_OTG_GOTGINT_SEDET_Pos

#define USB_OTG_GOTGINT_SEDET_Msk

#define USB_OTG_GOTGINT_SEDET

#define USB_OTG_GOTGINT_SRSSCHG_Pos

#define USB_OTG_GOTGINT_SRSSCHG_Msk

#define USB_OTG_GOTGINT_SRSSCHG

#define USB_OTG_GOTGINT_HNSSCHG_Pos

#define USB_OTG_GOTGINT_HNSSCHG_Msk

#define USB_OTG_GOTGINT_HNSSCHG

#define USB_OTG_GOTGINT_HNGDET_Pos

#define USB_OTG_GOTGINT_HNGDET_Msk

#define USB_OTG_GOTGINT_HNGDET

#define USB_OTG_GOTGINT_ADTOCHG_Pos

#define USB_OTG_GOTGINT_ADTOCHG_Msk

#define USB_OTG_GOTGINT_ADTOCHG

#define USB_OTG_GOTGINT_DBCDNE_Pos

#define USB_OTG_GOTGINT_DBCDNE_Msk

#define USB_OTG_GOTGINT_DBCDNE

Bit definition for USB_OTG_DCTL register

#define USB_OTG_DCTL_RWUSIG_Pos

#define USB_OTG_DCTL_RWUSIG_Msk

#define USB_OTG_DCTL_RWUSIG

#define USB_OTG_DCTL_SDIS_Pos

#define USB_OTG_DCTL_SDIS_Msk

#define USB_OTG_DCTL_SDIS

#define USB_OTG_DCTL_GINSTS_Pos

#define USB_OTG_DCTL_GINSTS_Msk

#define USB_OTG_DCTL_GINSTS

#define USB_OTG_DCTL_GONSTS_Pos

#define USB_OTG_DCTL_GONSTS_Msk

#define USB_OTG_DCTL_GONSTS

#define USB_OTG_DCTL_TCTL_Pos

#define USB_OTG_DCTL_TCTL_Msk

#define USB_OTG_DCTL_TCTL

#define USB_OTG_DCTL_TCTL_0

#define USB_OTG_DCTL_TCTL_1

#define USB_OTG_DCTL_TCTL_2

#define USB_OTG_DCTL_SGINAK_Pos

#define USB_OTG_DCTL_SGINAK_Msk

#define USB_OTG_DCTL_SGINAK

#define USB_OTG_DCTL_CGINAK_Pos

#define USB_OTG_DCTL_CGINAK_Msk

#define USB_OTG_DCTL_CGINAK

#define USB_OTG_DCTL_SGONAK_Pos

#define USB_OTG_DCTL_SGONAK_Msk

#define USB_OTG_DCTL_SGONAK

#define USB_OTG_DCTL_CGONAK_Pos

#define USB_OTG_DCTL_CGONAK_Msk

#define USB_OTG_DCTL_CGONAK

#define USB_OTG_DCTL_POPRGDNE_Pos

#define USB_OTG_DCTL_POPRGDNE_Msk

#define USB_OTG_DCTL_POPRGDNE

Bit definition for USB_OTG_HFIR register

#define USB_OTG_HFIR_FRIVL_Pos

#define USB_OTG_HFIR_FRIVL_Msk

#define USB_OTG_HFIR_FRIVL

Bit definition for USB_OTG_HFNUM register

#define USB_OTG_HFNUM_FRNUM_Pos

#define USB_OTG_HFNUM_FRNUM_Msk

#define USB_OTG_HFNUM_FRNUM

#define USB_OTG_HFNUM_FTREM_Pos

#define USB_OTG_HFNUM_FTREM_Msk

#define USB_OTG_HFNUM_FTREM

Bit definition for USB_OTG_DSTS register

#define USB_OTG_DSTS_SUSPSTS_Pos

#define USB_OTG_DSTS_SUSPSTS_Msk

#define USB_OTG_DSTS_SUSPSTS

#define USB_OTG_DSTS_ENUMSPD_Pos

#define USB_OTG_DSTS_ENUMSPD_Msk

#define USB_OTG_DSTS_ENUMSPD

#define USB_OTG_DSTS_ENUMSPD_0

#define USB_OTG_DSTS_ENUMSPD_1

#define USB_OTG_DSTS_EERR_Pos

#define USB_OTG_DSTS_EERR_Msk

#define USB_OTG_DSTS_EERR

#define USB_OTG_DSTS_FNSOF_Pos

#define USB_OTG_DSTS_FNSOF_Msk

#define USB_OTG_DSTS_FNSOF

Bit definition for USB_OTG_GAHBCFG register

#define USB_OTG_GAHBCFG_GINT_Pos

#define USB_OTG_GAHBCFG_GINT_Msk

#define USB_OTG_GAHBCFG_GINT

#define USB_OTG_GAHBCFG_HBSTLEN_Pos

#define USB_OTG_GAHBCFG_HBSTLEN_Msk

#define USB_OTG_GAHBCFG_HBSTLEN

#define USB_OTG_GAHBCFG_HBSTLEN_0

#define USB_OTG_GAHBCFG_HBSTLEN_1

#define USB_OTG_GAHBCFG_HBSTLEN_2

#define USB_OTG_GAHBCFG_HBSTLEN_3

#define USB_OTG_GAHBCFG_HBSTLEN_4

#define USB_OTG_GAHBCFG_DMAEN_Pos

#define USB_OTG_GAHBCFG_DMAEN_Msk

#define USB_OTG_GAHBCFG_DMAEN

#define USB_OTG_GAHBCFG_TXFELVL_Pos

#define USB_OTG_GAHBCFG_TXFELVL_Msk

#define USB_OTG_GAHBCFG_TXFELVL

#define USB_OTG_GAHBCFG_PTXFELVL_Pos

#define USB_OTG_GAHBCFG_PTXFELVL_Msk

#define USB_OTG_GAHBCFG_PTXFELVL

Bit definition for USB_OTG_GUSBCFG register

#define USB_OTG_GUSBCFG_TOCAL_Pos

#define USB_OTG_GUSBCFG_TOCAL_Msk

#define USB_OTG_GUSBCFG_TOCAL

#define USB_OTG_GUSBCFG_TOCAL_0

#define USB_OTG_GUSBCFG_TOCAL_1

#define USB_OTG_GUSBCFG_TOCAL_2

#define USB_OTG_GUSBCFG_PHYSEL_Pos

#define USB_OTG_GUSBCFG_PHYSEL_Msk

#define USB_OTG_GUSBCFG_PHYSEL

#define USB_OTG_GUSBCFG_SRPCAP_Pos

#define USB_OTG_GUSBCFG_SRPCAP_Msk

#define USB_OTG_GUSBCFG_SRPCAP

#define USB_OTG_GUSBCFG_HNPCAP_Pos

#define USB_OTG_GUSBCFG_HNPCAP_Msk

#define USB_OTG_GUSBCFG_HNPCAP

#define USB_OTG_GUSBCFG_TRDT_Pos

#define USB_OTG_GUSBCFG_TRDT_Msk

#define USB_OTG_GUSBCFG_TRDT

#define USB_OTG_GUSBCFG_TRDT_0

#define USB_OTG_GUSBCFG_TRDT_1

#define USB_OTG_GUSBCFG_TRDT_2

#define USB_OTG_GUSBCFG_TRDT_3

#define USB_OTG_GUSBCFG_PHYLPCS_Pos

#define USB_OTG_GUSBCFG_PHYLPCS_Msk

#define USB_OTG_GUSBCFG_PHYLPCS

#define USB_OTG_GUSBCFG_ULPIFSLS_Pos

#define USB_OTG_GUSBCFG_ULPIFSLS_Msk

#define USB_OTG_GUSBCFG_ULPIFSLS

#define USB_OTG_GUSBCFG_ULPIAR_Pos

#define USB_OTG_GUSBCFG_ULPIAR_Msk

#define USB_OTG_GUSBCFG_ULPIAR

#define USB_OTG_GUSBCFG_ULPICSM_Pos

#define USB_OTG_GUSBCFG_ULPICSM_Msk

#define USB_OTG_GUSBCFG_ULPICSM

#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos

#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk

#define USB_OTG_GUSBCFG_ULPIEVBUSD

#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos

#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk

#define USB_OTG_GUSBCFG_ULPIEVBUSI

#define USB_OTG_GUSBCFG_TSDPS_Pos

#define USB_OTG_GUSBCFG_TSDPS_Msk

#define USB_OTG_GUSBCFG_TSDPS

#define USB_OTG_GUSBCFG_PCCI_Pos

#define USB_OTG_GUSBCFG_PCCI_Msk

#define USB_OTG_GUSBCFG_PCCI

#define USB_OTG_GUSBCFG_PTCI_Pos

#define USB_OTG_GUSBCFG_PTCI_Msk

#define USB_OTG_GUSBCFG_PTCI

#define USB_OTG_GUSBCFG_ULPIIPD_Pos

#define USB_OTG_GUSBCFG_ULPIIPD_Msk

#define USB_OTG_GUSBCFG_ULPIIPD

#define USB_OTG_GUSBCFG_FHMOD_Pos

#define USB_OTG_GUSBCFG_FHMOD_Msk

#define USB_OTG_GUSBCFG_FHMOD

#define USB_OTG_GUSBCFG_FDMOD_Pos

#define USB_OTG_GUSBCFG_FDMOD_Msk

#define USB_OTG_GUSBCFG_FDMOD

#define USB_OTG_GUSBCFG_CTXPKT_Pos

#define USB_OTG_GUSBCFG_CTXPKT_Msk

#define USB_OTG_GUSBCFG_CTXPKT

Bit definition for USB_OTG_GRSTCTL register

#define USB_OTG_GRSTCTL_CSRST_Pos

#define USB_OTG_GRSTCTL_CSRST_Msk

#define USB_OTG_GRSTCTL_CSRST

#define USB_OTG_GRSTCTL_HSRST_Pos

#define USB_OTG_GRSTCTL_HSRST_Msk

#define USB_OTG_GRSTCTL_HSRST

#define USB_OTG_GRSTCTL_FCRST_Pos

#define USB_OTG_GRSTCTL_FCRST_Msk

#define USB_OTG_GRSTCTL_FCRST

#define USB_OTG_GRSTCTL_RXFFLSH_Pos

#define USB_OTG_GRSTCTL_RXFFLSH_Msk

#define USB_OTG_GRSTCTL_RXFFLSH

#define USB_OTG_GRSTCTL_TXFFLSH_Pos

#define USB_OTG_GRSTCTL_TXFFLSH_Msk

#define USB_OTG_GRSTCTL_TXFFLSH

#define USB_OTG_GRSTCTL_TXFNUM_Pos

#define USB_OTG_GRSTCTL_TXFNUM_Msk

#define USB_OTG_GRSTCTL_TXFNUM

#define USB_OTG_GRSTCTL_TXFNUM_0

#define USB_OTG_GRSTCTL_TXFNUM_1

#define USB_OTG_GRSTCTL_TXFNUM_2

#define USB_OTG_GRSTCTL_TXFNUM_3

#define USB_OTG_GRSTCTL_TXFNUM_4

#define USB_OTG_GRSTCTL_DMAREQ_Pos

#define USB_OTG_GRSTCTL_DMAREQ_Msk

#define USB_OTG_GRSTCTL_DMAREQ

#define USB_OTG_GRSTCTL_AHBIDL_Pos

#define USB_OTG_GRSTCTL_AHBIDL_Msk

#define USB_OTG_GRSTCTL_AHBIDL

Bit definition for USB_OTG_DIEPMSK register

#define USB_OTG_DIEPMSK_XFRCM_Pos

#define USB_OTG_DIEPMSK_XFRCM_Msk

#define USB_OTG_DIEPMSK_XFRCM

#define USB_OTG_DIEPMSK_EPDM_Pos

#define USB_OTG_DIEPMSK_EPDM_Msk

#define USB_OTG_DIEPMSK_EPDM

#define USB_OTG_DIEPMSK_TOM_Pos

#define USB_OTG_DIEPMSK_TOM_Msk

#define USB_OTG_DIEPMSK_TOM

#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos

#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk

#define USB_OTG_DIEPMSK_ITTXFEMSK

#define USB_OTG_DIEPMSK_INEPNMM_Pos

#define USB_OTG_DIEPMSK_INEPNMM_Msk

#define USB_OTG_DIEPMSK_INEPNMM

#define USB_OTG_DIEPMSK_INEPNEM_Pos

#define USB_OTG_DIEPMSK_INEPNEM_Msk

#define USB_OTG_DIEPMSK_INEPNEM

#define USB_OTG_DIEPMSK_TXFURM_Pos

#define USB_OTG_DIEPMSK_TXFURM_Msk

#define USB_OTG_DIEPMSK_TXFURM

#define USB_OTG_DIEPMSK_BIM_Pos

#define USB_OTG_DIEPMSK_BIM_Msk

#define USB_OTG_DIEPMSK_BIM

Bit definition for USB_OTG_HPTXSTS register

#define USB_OTG_HPTXSTS_PTXFSAVL_Pos

#define USB_OTG_HPTXSTS_PTXFSAVL_Msk

#define USB_OTG_HPTXSTS_PTXFSAVL

#define USB_OTG_HPTXSTS_PTXQSAV_Pos

#define USB_OTG_HPTXSTS_PTXQSAV_Msk

#define USB_OTG_HPTXSTS_PTXQSAV

#define USB_OTG_HPTXSTS_PTXQSAV_0

#define USB_OTG_HPTXSTS_PTXQSAV_1

#define USB_OTG_HPTXSTS_PTXQSAV_2

#define USB_OTG_HPTXSTS_PTXQSAV_3

#define USB_OTG_HPTXSTS_PTXQSAV_4

#define USB_OTG_HPTXSTS_PTXQSAV_5

#define USB_OTG_HPTXSTS_PTXQSAV_6

#define USB_OTG_HPTXSTS_PTXQSAV_7

#define USB_OTG_HPTXSTS_PTXQTOP_Pos

#define USB_OTG_HPTXSTS_PTXQTOP_Msk

#define USB_OTG_HPTXSTS_PTXQTOP

#define USB_OTG_HPTXSTS_PTXQTOP_0

#define USB_OTG_HPTXSTS_PTXQTOP_1

#define USB_OTG_HPTXSTS_PTXQTOP_2

#define USB_OTG_HPTXSTS_PTXQTOP_3

#define USB_OTG_HPTXSTS_PTXQTOP_4

#define USB_OTG_HPTXSTS_PTXQTOP_5

#define USB_OTG_HPTXSTS_PTXQTOP_6

#define USB_OTG_HPTXSTS_PTXQTOP_7

Bit definition for USB_OTG_HAINT register

#define USB_OTG_HAINT_HAINT_Pos

#define USB_OTG_HAINT_HAINT_Msk

#define USB_OTG_HAINT_HAINT

Bit definition for USB_OTG_DOEPMSK register

#define USB_OTG_DOEPMSK_XFRCM_Pos

#define USB_OTG_DOEPMSK_XFRCM_Msk

#define USB_OTG_DOEPMSK_XFRCM

#define USB_OTG_DOEPMSK_EPDM_Pos

#define USB_OTG_DOEPMSK_EPDM_Msk

#define USB_OTG_DOEPMSK_EPDM

#define USB_OTG_DOEPMSK_AHBERRM_Pos

#define USB_OTG_DOEPMSK_AHBERRM_Msk

#define USB_OTG_DOEPMSK_AHBERRM

#define USB_OTG_DOEPMSK_STUPM_Pos

#define USB_OTG_DOEPMSK_STUPM_Msk

#define USB_OTG_DOEPMSK_STUPM

#define USB_OTG_DOEPMSK_OTEPDM_Pos

#define USB_OTG_DOEPMSK_OTEPDM_Msk

#define USB_OTG_DOEPMSK_OTEPDM

#define USB_OTG_DOEPMSK_OTEPSPRM_Pos

#define USB_OTG_DOEPMSK_OTEPSPRM_Msk

#define USB_OTG_DOEPMSK_OTEPSPRM

#define USB_OTG_DOEPMSK_B2BSTUP_Pos

#define USB_OTG_DOEPMSK_B2BSTUP_Msk

#define USB_OTG_DOEPMSK_B2BSTUP

#define USB_OTG_DOEPMSK_OPEM_Pos

#define USB_OTG_DOEPMSK_OPEM_Msk

#define USB_OTG_DOEPMSK_OPEM

#define USB_OTG_DOEPMSK_BOIM_Pos

#define USB_OTG_DOEPMSK_BOIM_Msk

#define USB_OTG_DOEPMSK_BOIM

#define USB_OTG_DOEPMSK_BERRM_Pos

#define USB_OTG_DOEPMSK_BERRM_Msk

#define USB_OTG_DOEPMSK_BERRM

#define USB_OTG_DOEPMSK_NAKM_Pos

#define USB_OTG_DOEPMSK_NAKM_Msk

#define USB_OTG_DOEPMSK_NAKM

#define USB_OTG_DOEPMSK_NYETM_Pos

#define USB_OTG_DOEPMSK_NYETM_Msk

#define USB_OTG_DOEPMSK_NYETM

Bit definition for USB_OTG_GINTSTS register

#define USB_OTG_GINTSTS_CMOD_Pos

#define USB_OTG_GINTSTS_CMOD_Msk

#define USB_OTG_GINTSTS_CMOD

#define USB_OTG_GINTSTS_MMIS_Pos

#define USB_OTG_GINTSTS_MMIS_Msk

#define USB_OTG_GINTSTS_MMIS

#define USB_OTG_GINTSTS_OTGINT_Pos

#define USB_OTG_GINTSTS_OTGINT_Msk

#define USB_OTG_GINTSTS_OTGINT

#define USB_OTG_GINTSTS_SOF_Pos

#define USB_OTG_GINTSTS_SOF_Msk

#define USB_OTG_GINTSTS_SOF

#define USB_OTG_GINTSTS_RXFLVL_Pos

#define USB_OTG_GINTSTS_RXFLVL_Msk

#define USB_OTG_GINTSTS_RXFLVL

#define USB_OTG_GINTSTS_NPTXFE_Pos

#define USB_OTG_GINTSTS_NPTXFE_Msk

#define USB_OTG_GINTSTS_NPTXFE

#define USB_OTG_GINTSTS_GINAKEFF_Pos

#define USB_OTG_GINTSTS_GINAKEFF_Msk

#define USB_OTG_GINTSTS_GINAKEFF

#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos

#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk

#define USB_OTG_GINTSTS_BOUTNAKEFF

#define USB_OTG_GINTSTS_ESUSP_Pos

#define USB_OTG_GINTSTS_ESUSP_Msk

#define USB_OTG_GINTSTS_ESUSP

#define USB_OTG_GINTSTS_USBSUSP_Pos

#define USB_OTG_GINTSTS_USBSUSP_Msk

#define USB_OTG_GINTSTS_USBSUSP

#define USB_OTG_GINTSTS_USBRST_Pos

#define USB_OTG_GINTSTS_USBRST_Msk

#define USB_OTG_GINTSTS_USBRST

#define USB_OTG_GINTSTS_ENUMDNE_Pos

#define USB_OTG_GINTSTS_ENUMDNE_Msk

#define USB_OTG_GINTSTS_ENUMDNE

#define USB_OTG_GINTSTS_ISOODRP_Pos

#define USB_OTG_GINTSTS_ISOODRP_Msk

#define USB_OTG_GINTSTS_ISOODRP

#define USB_OTG_GINTSTS_EOPF_Pos

#define USB_OTG_GINTSTS_EOPF_Msk

#define USB_OTG_GINTSTS_EOPF

#define USB_OTG_GINTSTS_IEPINT_Pos

#define USB_OTG_GINTSTS_IEPINT_Msk

#define USB_OTG_GINTSTS_IEPINT

#define USB_OTG_GINTSTS_OEPINT_Pos

#define USB_OTG_GINTSTS_OEPINT_Msk

#define USB_OTG_GINTSTS_OEPINT

#define USB_OTG_GINTSTS_IISOIXFR_Pos

#define USB_OTG_GINTSTS_IISOIXFR_Msk

#define USB_OTG_GINTSTS_IISOIXFR

#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos

#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk

#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT

#define USB_OTG_GINTSTS_DATAFSUSP_Pos

#define USB_OTG_GINTSTS_DATAFSUSP_Msk

#define USB_OTG_GINTSTS_DATAFSUSP

#define USB_OTG_GINTSTS_HPRTINT_Pos

#define USB_OTG_GINTSTS_HPRTINT_Msk

#define USB_OTG_GINTSTS_HPRTINT

#define USB_OTG_GINTSTS_HCINT_Pos

#define USB_OTG_GINTSTS_HCINT_Msk

#define USB_OTG_GINTSTS_HCINT

#define USB_OTG_GINTSTS_PTXFE_Pos

#define USB_OTG_GINTSTS_PTXFE_Msk

#define USB_OTG_GINTSTS_PTXFE

#define USB_OTG_GINTSTS_CIDSCHG_Pos

#define USB_OTG_GINTSTS_CIDSCHG_Msk

#define USB_OTG_GINTSTS_CIDSCHG

#define USB_OTG_GINTSTS_DISCINT_Pos

#define USB_OTG_GINTSTS_DISCINT_Msk

#define USB_OTG_GINTSTS_DISCINT

#define USB_OTG_GINTSTS_SRQINT_Pos

#define USB_OTG_GINTSTS_SRQINT_Msk

#define USB_OTG_GINTSTS_SRQINT

#define USB_OTG_GINTSTS_WKUINT_Pos

#define USB_OTG_GINTSTS_WKUINT_Msk

#define USB_OTG_GINTSTS_WKUINT

Bit definition for USB_OTG_GINTMSK register

#define USB_OTG_GINTMSK_MMISM_Pos

#define USB_OTG_GINTMSK_MMISM_Msk

#define USB_OTG_GINTMSK_MMISM

#define USB_OTG_GINTMSK_OTGINT_Pos

#define USB_OTG_GINTMSK_OTGINT_Msk

#define USB_OTG_GINTMSK_OTGINT

#define USB_OTG_GINTMSK_SOFM_Pos

#define USB_OTG_GINTMSK_SOFM_Msk

#define USB_OTG_GINTMSK_SOFM

#define USB_OTG_GINTMSK_RXFLVLM_Pos

#define USB_OTG_GINTMSK_RXFLVLM_Msk

#define USB_OTG_GINTMSK_RXFLVLM

#define USB_OTG_GINTMSK_NPTXFEM_Pos

#define USB_OTG_GINTMSK_NPTXFEM_Msk

#define USB_OTG_GINTMSK_NPTXFEM

#define USB_OTG_GINTMSK_GINAKEFFM_Pos

#define USB_OTG_GINTMSK_GINAKEFFM_Msk

#define USB_OTG_GINTMSK_GINAKEFFM

#define USB_OTG_GINTMSK_GONAKEFFM_Pos

#define USB_OTG_GINTMSK_GONAKEFFM_Msk

#define USB_OTG_GINTMSK_GONAKEFFM

#define USB_OTG_GINTMSK_ESUSPM_Pos

#define USB_OTG_GINTMSK_ESUSPM_Msk

#define USB_OTG_GINTMSK_ESUSPM

#define USB_OTG_GINTMSK_USBSUSPM_Pos

#define USB_OTG_GINTMSK_USBSUSPM_Msk

#define USB_OTG_GINTMSK_USBSUSPM

#define USB_OTG_GINTMSK_USBRST_Pos

#define USB_OTG_GINTMSK_USBRST_Msk

#define USB_OTG_GINTMSK_USBRST

#define USB_OTG_GINTMSK_ENUMDNEM_Pos

#define USB_OTG_GINTMSK_ENUMDNEM_Msk

#define USB_OTG_GINTMSK_ENUMDNEM

#define USB_OTG_GINTMSK_ISOODRPM_Pos

#define USB_OTG_GINTMSK_ISOODRPM_Msk

#define USB_OTG_GINTMSK_ISOODRPM

#define USB_OTG_GINTMSK_EOPFM_Pos

#define USB_OTG_GINTMSK_EOPFM_Msk

#define USB_OTG_GINTMSK_EOPFM

#define USB_OTG_GINTMSK_EPMISM_Pos

#define USB_OTG_GINTMSK_EPMISM_Msk

#define USB_OTG_GINTMSK_EPMISM

#define USB_OTG_GINTMSK_IEPINT_Pos

#define USB_OTG_GINTMSK_IEPINT_Msk

#define USB_OTG_GINTMSK_IEPINT

#define USB_OTG_GINTMSK_OEPINT_Pos

#define USB_OTG_GINTMSK_OEPINT_Msk

#define USB_OTG_GINTMSK_OEPINT

#define USB_OTG_GINTMSK_IISOIXFRM_Pos

#define USB_OTG_GINTMSK_IISOIXFRM_Msk

#define USB_OTG_GINTMSK_IISOIXFRM

#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos

#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk

#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM

#define USB_OTG_GINTMSK_FSUSPM_Pos

#define USB_OTG_GINTMSK_FSUSPM_Msk

#define USB_OTG_GINTMSK_FSUSPM

#define USB_OTG_GINTMSK_PRTIM_Pos

#define USB_OTG_GINTMSK_PRTIM_Msk

#define USB_OTG_GINTMSK_PRTIM

#define USB_OTG_GINTMSK_HCIM_Pos

#define USB_OTG_GINTMSK_HCIM_Msk

#define USB_OTG_GINTMSK_HCIM

#define USB_OTG_GINTMSK_PTXFEM_Pos

#define USB_OTG_GINTMSK_PTXFEM_Msk

#define USB_OTG_GINTMSK_PTXFEM

#define USB_OTG_GINTMSK_CIDSCHGM_Pos

#define USB_OTG_GINTMSK_CIDSCHGM_Msk

#define USB_OTG_GINTMSK_CIDSCHGM

#define USB_OTG_GINTMSK_DISCINT_Pos

#define USB_OTG_GINTMSK_DISCINT_Msk

#define USB_OTG_GINTMSK_DISCINT

#define USB_OTG_GINTMSK_SRQIM_Pos

#define USB_OTG_GINTMSK_SRQIM_Msk

#define USB_OTG_GINTMSK_SRQIM

#define USB_OTG_GINTMSK_WUIM_Pos

#define USB_OTG_GINTMSK_WUIM_Msk

#define USB_OTG_GINTMSK_WUIM

Bit definition for USB_OTG_DAINT register

#define USB_OTG_DAINT_IEPINT_Pos

#define USB_OTG_DAINT_IEPINT_Msk

#define USB_OTG_DAINT_IEPINT

#define USB_OTG_DAINT_OEPINT_Pos

#define USB_OTG_DAINT_OEPINT_Msk

#define USB_OTG_DAINT_OEPINT

Bit definition for USB_OTG_HAINTMSK register

#define USB_OTG_HAINTMSK_HAINTM_Pos

#define USB_OTG_HAINTMSK_HAINTM_Msk

#define USB_OTG_HAINTMSK_HAINTM

Bit definition for USB_OTG_GRXSTSP register

#define USB_OTG_GRXSTSP_EPNUM_Pos

#define USB_OTG_GRXSTSP_EPNUM_Msk

#define USB_OTG_GRXSTSP_EPNUM

#define USB_OTG_GRXSTSP_BCNT_Pos

#define USB_OTG_GRXSTSP_BCNT_Msk

#define USB_OTG_GRXSTSP_BCNT

#define USB_OTG_GRXSTSP_DPID_Pos

#define USB_OTG_GRXSTSP_DPID_Msk

#define USB_OTG_GRXSTSP_DPID

#define USB_OTG_GRXSTSP_PKTSTS_Pos

#define USB_OTG_GRXSTSP_PKTSTS_Msk

#define USB_OTG_GRXSTSP_PKTSTS

Bit definition for USB_OTG_DAINTMSK register

#define USB_OTG_DAINTMSK_IEPM_Pos

#define USB_OTG_DAINTMSK_IEPM_Msk

#define USB_OTG_DAINTMSK_IEPM

#define USB_OTG_DAINTMSK_OEPM_Pos

#define USB_OTG_DAINTMSK_OEPM_Msk

#define USB_OTG_DAINTMSK_OEPM

Bit definition for USB_OTG_GRXFSIZ register

#define USB_OTG_GRXFSIZ_RXFD_Pos

#define USB_OTG_GRXFSIZ_RXFD_Msk

#define USB_OTG_GRXFSIZ_RXFD

Bit definition for USB_OTG_DVBUSDIS register

#define USB_OTG_DVBUSDIS_VBUSDT_Pos

#define USB_OTG_DVBUSDIS_VBUSDT_Msk

#define USB_OTG_DVBUSDIS_VBUSDT

Bit definition for OTG register

#define USB_OTG_NPTXFSA_Pos

#define USB_OTG_NPTXFSA_Msk

#define USB_OTG_NPTXFSA

#define USB_OTG_NPTXFD_Pos

#define USB_OTG_NPTXFD_Msk

#define USB_OTG_NPTXFD

#define USB_OTG_TX0FSA_Pos

#define USB_OTG_TX0FSA_Msk

#define USB_OTG_TX0FSA

#define USB_OTG_TX0FD_Pos

#define USB_OTG_TX0FD_Msk

#define USB_OTG_TX0FD

Bit definition forUSB_OTG_DVBUSPULSE register

#define USB_OTG_DVBUSPULSE_DVBUSP_Pos

#define USB_OTG_DVBUSPULSE_DVBUSP_Msk

#define USB_OTG_DVBUSPULSE_DVBUSP

Bit definition for USB_OTG_GNPTXSTS register

#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos

#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk

#define USB_OTG_GNPTXSTS_NPTXFSAV

#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos

#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk

#define USB_OTG_GNPTXSTS_NPTQXSAV

#define USB_OTG_GNPTXSTS_NPTQXSAV_0

#define USB_OTG_GNPTXSTS_NPTQXSAV_1

#define USB_OTG_GNPTXSTS_NPTQXSAV_2

#define USB_OTG_GNPTXSTS_NPTQXSAV_3

#define USB_OTG_GNPTXSTS_NPTQXSAV_4

#define USB_OTG_GNPTXSTS_NPTQXSAV_5

#define USB_OTG_GNPTXSTS_NPTQXSAV_6

#define USB_OTG_GNPTXSTS_NPTQXSAV_7

#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos

#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk

#define USB_OTG_GNPTXSTS_NPTXQTOP

#define USB_OTG_GNPTXSTS_NPTXQTOP_0

#define USB_OTG_GNPTXSTS_NPTXQTOP_1

#define USB_OTG_GNPTXSTS_NPTXQTOP_2

#define USB_OTG_GNPTXSTS_NPTXQTOP_3

#define USB_OTG_GNPTXSTS_NPTXQTOP_4

#define USB_OTG_GNPTXSTS_NPTXQTOP_5

#define USB_OTG_GNPTXSTS_NPTXQTOP_6

Bit definition for USB_OTG_DTHRCTL register

#define USB_OTG_DTHRCTL_NONISOTHREN_Pos

#define USB_OTG_DTHRCTL_NONISOTHREN_Msk

#define USB_OTG_DTHRCTL_NONISOTHREN

#define USB_OTG_DTHRCTL_ISOTHREN_Pos

#define USB_OTG_DTHRCTL_ISOTHREN_Msk

#define USB_OTG_DTHRCTL_ISOTHREN

#define USB_OTG_DTHRCTL_TXTHRLEN_Pos

#define USB_OTG_DTHRCTL_TXTHRLEN_Msk

#define USB_OTG_DTHRCTL_TXTHRLEN

#define USB_OTG_DTHRCTL_TXTHRLEN_0

#define USB_OTG_DTHRCTL_TXTHRLEN_1

#define USB_OTG_DTHRCTL_TXTHRLEN_2

#define USB_OTG_DTHRCTL_TXTHRLEN_3

#define USB_OTG_DTHRCTL_TXTHRLEN_4

#define USB_OTG_DTHRCTL_TXTHRLEN_5

#define USB_OTG_DTHRCTL_TXTHRLEN_6

#define USB_OTG_DTHRCTL_TXTHRLEN_7

#define USB_OTG_DTHRCTL_TXTHRLEN_8

#define USB_OTG_DTHRCTL_RXTHREN_Pos

#define USB_OTG_DTHRCTL_RXTHREN_Msk

#define USB_OTG_DTHRCTL_RXTHREN

#define USB_OTG_DTHRCTL_RXTHRLEN_Pos

#define USB_OTG_DTHRCTL_RXTHRLEN_Msk

#define USB_OTG_DTHRCTL_RXTHRLEN

#define USB_OTG_DTHRCTL_RXTHRLEN_0

#define USB_OTG_DTHRCTL_RXTHRLEN_1

#define USB_OTG_DTHRCTL_RXTHRLEN_2

#define USB_OTG_DTHRCTL_RXTHRLEN_3

#define USB_OTG_DTHRCTL_RXTHRLEN_4

#define USB_OTG_DTHRCTL_RXTHRLEN_5

#define USB_OTG_DTHRCTL_RXTHRLEN_6

#define USB_OTG_DTHRCTL_RXTHRLEN_7

#define USB_OTG_DTHRCTL_RXTHRLEN_8

#define USB_OTG_DTHRCTL_ARPEN_Pos

#define USB_OTG_DTHRCTL_ARPEN_Msk

#define USB_OTG_DTHRCTL_ARPEN

Bit definition for USB_OTG_DIEPEMPMSK register

#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos

#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk

#define USB_OTG_DIEPEMPMSK_INEPTXFEM

Bit definition for USB_OTG_DEACHINT register

#define USB_OTG_DEACHINT_IEP1INT_Pos

#define USB_OTG_DEACHINT_IEP1INT_Msk

#define USB_OTG_DEACHINT_IEP1INT

#define USB_OTG_DEACHINT_OEP1INT_Pos

#define USB_OTG_DEACHINT_OEP1INT_Msk

#define USB_OTG_DEACHINT_OEP1INT

Bit definition for USB_OTG_GCCFG register

#define USB_OTG_GCCFG_PWRDWN_Pos

#define USB_OTG_GCCFG_PWRDWN_Msk

#define USB_OTG_GCCFG_PWRDWN

#define USB_OTG_GCCFG_I2CPADEN_Pos

#define USB_OTG_GCCFG_I2CPADEN_Msk

#define USB_OTG_GCCFG_I2CPADEN

#define USB_OTG_GCCFG_VBUSASEN_Pos

#define USB_OTG_GCCFG_VBUSASEN_Msk

#define USB_OTG_GCCFG_VBUSASEN

#define USB_OTG_GCCFG_VBUSBSEN_Pos

#define USB_OTG_GCCFG_VBUSBSEN_Msk

#define USB_OTG_GCCFG_VBUSBSEN

#define USB_OTG_GCCFG_SOFOUTEN_Pos

#define USB_OTG_GCCFG_SOFOUTEN_Msk

#define USB_OTG_GCCFG_SOFOUTEN

#define USB_OTG_GCCFG_NOVBUSSENS_Pos

#define USB_OTG_GCCFG_NOVBUSSENS_Msk

#define USB_OTG_GCCFG_NOVBUSSENS

Bit definition forUSB_OTG_DEACHINTMSK register

#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos

#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk

#define USB_OTG_DEACHINTMSK_IEP1INTM

#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos

#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk

#define USB_OTG_DEACHINTMSK_OEP1INTM

Bit definition for USB_OTG_CID register

#define USB_OTG_CID_PRODUCT_ID_Pos

#define USB_OTG_CID_PRODUCT_ID_Msk

#define USB_OTG_CID_PRODUCT_ID

Bit definition for USB_OTG_DIEPEACHMSK1 register

#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos

#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk

#define USB_OTG_DIEPEACHMSK1_XFRCM

#define USB_OTG_DIEPEACHMSK1_EPDM_Pos

#define USB_OTG_DIEPEACHMSK1_EPDM_Msk

#define USB_OTG_DIEPEACHMSK1_EPDM

#define USB_OTG_DIEPEACHMSK1_TOM_Pos

#define USB_OTG_DIEPEACHMSK1_TOM_Msk

#define USB_OTG_DIEPEACHMSK1_TOM

#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos

#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk

#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK

#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos

#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk

#define USB_OTG_DIEPEACHMSK1_INEPNMM

#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos

#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk

#define USB_OTG_DIEPEACHMSK1_INEPNEM

#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos

#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk

#define USB_OTG_DIEPEACHMSK1_TXFURM

#define USB_OTG_DIEPEACHMSK1_BIM_Pos

#define USB_OTG_DIEPEACHMSK1_BIM_Msk

#define USB_OTG_DIEPEACHMSK1_BIM

#define USB_OTG_DIEPEACHMSK1_NAKM_Pos

#define USB_OTG_DIEPEACHMSK1_NAKM_Msk

#define USB_OTG_DIEPEACHMSK1_NAKM

Bit definition for USB_OTG_HPRT register

#define USB_OTG_HPRT_PCSTS_Pos

#define USB_OTG_HPRT_PCSTS_Msk

#define USB_OTG_HPRT_PCSTS

#define USB_OTG_HPRT_PCDET_Pos

#define USB_OTG_HPRT_PCDET_Msk

#define USB_OTG_HPRT_PCDET

#define USB_OTG_HPRT_PENA_Pos

#define USB_OTG_HPRT_PENA_Msk

#define USB_OTG_HPRT_PENA

#define USB_OTG_HPRT_PENCHNG_Pos

#define USB_OTG_HPRT_PENCHNG_Msk

#define USB_OTG_HPRT_PENCHNG

#define USB_OTG_HPRT_POCA_Pos

#define USB_OTG_HPRT_POCA_Msk

#define USB_OTG_HPRT_POCA

#define USB_OTG_HPRT_POCCHNG_Pos

#define USB_OTG_HPRT_POCCHNG_Msk

#define USB_OTG_HPRT_POCCHNG

#define USB_OTG_HPRT_PRES_Pos

#define USB_OTG_HPRT_PRES_Msk

#define USB_OTG_HPRT_PRES

#define USB_OTG_HPRT_PSUSP_Pos

#define USB_OTG_HPRT_PSUSP_Msk

#define USB_OTG_HPRT_PSUSP

#define USB_OTG_HPRT_PRST_Pos

#define USB_OTG_HPRT_PRST_Msk

#define USB_OTG_HPRT_PRST

#define USB_OTG_HPRT_PLSTS_Pos

#define USB_OTG_HPRT_PLSTS_Msk

#define USB_OTG_HPRT_PLSTS

#define USB_OTG_HPRT_PLSTS_0

#define USB_OTG_HPRT_PLSTS_1

#define USB_OTG_HPRT_PPWR_Pos

#define USB_OTG_HPRT_PPWR_Msk

#define USB_OTG_HPRT_PPWR

#define USB_OTG_HPRT_PTCTL_Pos

#define USB_OTG_HPRT_PTCTL_Msk

#define USB_OTG_HPRT_PTCTL

#define USB_OTG_HPRT_PTCTL_0

#define USB_OTG_HPRT_PTCTL_1

#define USB_OTG_HPRT_PTCTL_2

#define USB_OTG_HPRT_PTCTL_3

#define USB_OTG_HPRT_PSPD_Pos

#define USB_OTG_HPRT_PSPD_Msk

#define USB_OTG_HPRT_PSPD

#define USB_OTG_HPRT_PSPD_0

#define USB_OTG_HPRT_PSPD_1

Bit definition for USB_OTG_DOEPEACHMSK1 register

#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos

#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk

#define USB_OTG_DOEPEACHMSK1_XFRCM

#define USB_OTG_DOEPEACHMSK1_EPDM_Pos

#define USB_OTG_DOEPEACHMSK1_EPDM_Msk

#define USB_OTG_DOEPEACHMSK1_EPDM

#define USB_OTG_DOEPEACHMSK1_TOM_Pos

#define USB_OTG_DOEPEACHMSK1_TOM_Msk

#define USB_OTG_DOEPEACHMSK1_TOM

#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos

#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk

#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK

#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos

#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk

#define USB_OTG_DOEPEACHMSK1_INEPNMM

#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos

#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk

#define USB_OTG_DOEPEACHMSK1_INEPNEM

#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos

#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk

#define USB_OTG_DOEPEACHMSK1_TXFURM

#define USB_OTG_DOEPEACHMSK1_BIM_Pos

#define USB_OTG_DOEPEACHMSK1_BIM_Msk

#define USB_OTG_DOEPEACHMSK1_BIM

#define USB_OTG_DOEPEACHMSK1_BERRM_Pos

#define USB_OTG_DOEPEACHMSK1_BERRM_Msk

#define USB_OTG_DOEPEACHMSK1_BERRM

#define USB_OTG_DOEPEACHMSK1_NAKM_Pos

#define USB_OTG_DOEPEACHMSK1_NAKM_Msk

#define USB_OTG_DOEPEACHMSK1_NAKM

#define USB_OTG_DOEPEACHMSK1_NYETM_Pos

#define USB_OTG_DOEPEACHMSK1_NYETM_Msk

#define USB_OTG_DOEPEACHMSK1_NYETM

Bit definition for USB_OTG_HPTXFSIZ register

#define USB_OTG_HPTXFSIZ_PTXSA_Pos

#define USB_OTG_HPTXFSIZ_PTXSA_Msk

#define USB_OTG_HPTXFSIZ_PTXSA

#define USB_OTG_HPTXFSIZ_PTXFD_Pos

#define USB_OTG_HPTXFSIZ_PTXFD_Msk

#define USB_OTG_HPTXFSIZ_PTXFD

Bit definition for USB_OTG_DIEPCTL register

#define USB_OTG_DIEPCTL_MPSIZ_Pos

#define USB_OTG_DIEPCTL_MPSIZ_Msk

#define USB_OTG_DIEPCTL_MPSIZ

#define USB_OTG_DIEPCTL_USBAEP_Pos

#define USB_OTG_DIEPCTL_USBAEP_Msk

#define USB_OTG_DIEPCTL_USBAEP

#define USB_OTG_DIEPCTL_EONUM_DPID_Pos

#define USB_OTG_DIEPCTL_EONUM_DPID_Msk

#define USB_OTG_DIEPCTL_EONUM_DPID

#define USB_OTG_DIEPCTL_NAKSTS_Pos

#define USB_OTG_DIEPCTL_NAKSTS_Msk

#define USB_OTG_DIEPCTL_NAKSTS

#define USB_OTG_DIEPCTL_EPTYP_Pos

#define USB_OTG_DIEPCTL_EPTYP_Msk

#define USB_OTG_DIEPCTL_EPTYP

#define USB_OTG_DIEPCTL_EPTYP_0

#define USB_OTG_DIEPCTL_EPTYP_1

#define USB_OTG_DIEPCTL_STALL_Pos

#define USB_OTG_DIEPCTL_STALL_Msk

#define USB_OTG_DIEPCTL_STALL

#define USB_OTG_DIEPCTL_TXFNUM_Pos

#define USB_OTG_DIEPCTL_TXFNUM_Msk

#define USB_OTG_DIEPCTL_TXFNUM

#define USB_OTG_DIEPCTL_TXFNUM_0

#define USB_OTG_DIEPCTL_TXFNUM_1

#define USB_OTG_DIEPCTL_TXFNUM_2

#define USB_OTG_DIEPCTL_TXFNUM_3

#define USB_OTG_DIEPCTL_CNAK_Pos

#define USB_OTG_DIEPCTL_CNAK_Msk

#define USB_OTG_DIEPCTL_CNAK

#define USB_OTG_DIEPCTL_SNAK_Pos

#define USB_OTG_DIEPCTL_SNAK_Msk

#define USB_OTG_DIEPCTL_SNAK

#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos

#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk

#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM

#define USB_OTG_DIEPCTL_SODDFRM_Pos

#define USB_OTG_DIEPCTL_SODDFRM_Msk

#define USB_OTG_DIEPCTL_SODDFRM

#define USB_OTG_DIEPCTL_EPDIS_Pos

#define USB_OTG_DIEPCTL_EPDIS_Msk

#define USB_OTG_DIEPCTL_EPDIS

#define USB_OTG_DIEPCTL_EPENA_Pos

#define USB_OTG_DIEPCTL_EPENA_Msk

#define USB_OTG_DIEPCTL_EPENA

Bit definition for USB_OTG_HCCHAR register

#define USB_OTG_HCCHAR_MPSIZ_Pos

#define USB_OTG_HCCHAR_MPSIZ_Msk

#define USB_OTG_HCCHAR_MPSIZ

#define USB_OTG_HCCHAR_EPNUM_Pos

#define USB_OTG_HCCHAR_EPNUM_Msk

#define USB_OTG_HCCHAR_EPNUM

#define USB_OTG_HCCHAR_EPNUM_0

#define USB_OTG_HCCHAR_EPNUM_1

#define USB_OTG_HCCHAR_EPNUM_2

#define USB_OTG_HCCHAR_EPNUM_3

#define USB_OTG_HCCHAR_EPDIR_Pos

#define USB_OTG_HCCHAR_EPDIR_Msk

#define USB_OTG_HCCHAR_EPDIR

#define USB_OTG_HCCHAR_LSDEV_Pos

#define USB_OTG_HCCHAR_LSDEV_Msk

#define USB_OTG_HCCHAR_LSDEV

#define USB_OTG_HCCHAR_EPTYP_Pos

#define USB_OTG_HCCHAR_EPTYP_Msk

#define USB_OTG_HCCHAR_EPTYP

#define USB_OTG_HCCHAR_EPTYP_0

#define USB_OTG_HCCHAR_EPTYP_1

#define USB_OTG_HCCHAR_MC_Pos

#define USB_OTG_HCCHAR_MC_Msk

#define USB_OTG_HCCHAR_MC

#define USB_OTG_HCCHAR_MC_0

#define USB_OTG_HCCHAR_MC_1

#define USB_OTG_HCCHAR_DAD_Pos

#define USB_OTG_HCCHAR_DAD_Msk

#define USB_OTG_HCCHAR_DAD

#define USB_OTG_HCCHAR_DAD_0

#define USB_OTG_HCCHAR_DAD_1

#define USB_OTG_HCCHAR_DAD_2

#define USB_OTG_HCCHAR_DAD_3

#define USB_OTG_HCCHAR_DAD_4

#define USB_OTG_HCCHAR_DAD_5

#define USB_OTG_HCCHAR_DAD_6

#define USB_OTG_HCCHAR_ODDFRM_Pos

#define USB_OTG_HCCHAR_ODDFRM_Msk

#define USB_OTG_HCCHAR_ODDFRM

#define USB_OTG_HCCHAR_CHDIS_Pos

#define USB_OTG_HCCHAR_CHDIS_Msk

#define USB_OTG_HCCHAR_CHDIS

#define USB_OTG_HCCHAR_CHENA_Pos

#define USB_OTG_HCCHAR_CHENA_Msk

#define USB_OTG_HCCHAR_CHENA

Bit definition for USB_OTG_HCSPLT register

#define USB_OTG_HCSPLT_PRTADDR_Pos

#define USB_OTG_HCSPLT_PRTADDR_Msk

#define USB_OTG_HCSPLT_PRTADDR

#define USB_OTG_HCSPLT_PRTADDR_0

#define USB_OTG_HCSPLT_PRTADDR_1

#define USB_OTG_HCSPLT_PRTADDR_2

#define USB_OTG_HCSPLT_PRTADDR_3

#define USB_OTG_HCSPLT_PRTADDR_4

#define USB_OTG_HCSPLT_PRTADDR_5

#define USB_OTG_HCSPLT_PRTADDR_6

#define USB_OTG_HCSPLT_HUBADDR_Pos

#define USB_OTG_HCSPLT_HUBADDR_Msk

#define USB_OTG_HCSPLT_HUBADDR

#define USB_OTG_HCSPLT_HUBADDR_0

#define USB_OTG_HCSPLT_HUBADDR_1

#define USB_OTG_HCSPLT_HUBADDR_2

#define USB_OTG_HCSPLT_HUBADDR_3

#define USB_OTG_HCSPLT_HUBADDR_4

#define USB_OTG_HCSPLT_HUBADDR_5

#define USB_OTG_HCSPLT_HUBADDR_6

#define USB_OTG_HCSPLT_XACTPOS_Pos

#define USB_OTG_HCSPLT_XACTPOS_Msk

#define USB_OTG_HCSPLT_XACTPOS

#define USB_OTG_HCSPLT_XACTPOS_0

#define USB_OTG_HCSPLT_XACTPOS_1

#define USB_OTG_HCSPLT_COMPLSPLT_Pos

#define USB_OTG_HCSPLT_COMPLSPLT_Msk

#define USB_OTG_HCSPLT_COMPLSPLT

#define USB_OTG_HCSPLT_SPLITEN_Pos

#define USB_OTG_HCSPLT_SPLITEN_Msk

#define USB_OTG_HCSPLT_SPLITEN

Bit definition for USB_OTG_HCINT register

#define USB_OTG_HCINT_XFRC_Pos

#define USB_OTG_HCINT_XFRC_Msk

#define USB_OTG_HCINT_XFRC

#define USB_OTG_HCINT_CHH_Pos

#define USB_OTG_HCINT_CHH_Msk

#define USB_OTG_HCINT_CHH

#define USB_OTG_HCINT_AHBERR_Pos

#define USB_OTG_HCINT_AHBERR_Msk

#define USB_OTG_HCINT_AHBERR

#define USB_OTG_HCINT_STALL_Pos

#define USB_OTG_HCINT_STALL_Msk

#define USB_OTG_HCINT_STALL

#define USB_OTG_HCINT_NAK_Pos

#define USB_OTG_HCINT_NAK_Msk

#define USB_OTG_HCINT_NAK

#define USB_OTG_HCINT_ACK_Pos

#define USB_OTG_HCINT_ACK_Msk

#define USB_OTG_HCINT_ACK

#define USB_OTG_HCINT_NYET_Pos

#define USB_OTG_HCINT_NYET_Msk

#define USB_OTG_HCINT_NYET

#define USB_OTG_HCINT_TXERR_Pos

#define USB_OTG_HCINT_TXERR_Msk

#define USB_OTG_HCINT_TXERR

#define USB_OTG_HCINT_BBERR_Pos

#define USB_OTG_HCINT_BBERR_Msk

#define USB_OTG_HCINT_BBERR

#define USB_OTG_HCINT_FRMOR_Pos

#define USB_OTG_HCINT_FRMOR_Msk

#define USB_OTG_HCINT_FRMOR

#define USB_OTG_HCINT_DTERR_Pos

#define USB_OTG_HCINT_DTERR_Msk

#define USB_OTG_HCINT_DTERR

Bit definition for USB_OTG_DIEPINT register

#define USB_OTG_DIEPINT_XFRC_Pos

#define USB_OTG_DIEPINT_XFRC_Msk

#define USB_OTG_DIEPINT_XFRC

#define USB_OTG_DIEPINT_EPDISD_Pos

#define USB_OTG_DIEPINT_EPDISD_Msk

#define USB_OTG_DIEPINT_EPDISD

#define USB_OTG_DIEPINT_AHBERR_Pos

#define USB_OTG_DIEPINT_AHBERR_Msk

#define USB_OTG_DIEPINT_AHBERR

#define USB_OTG_DIEPINT_TOC_Pos

#define USB_OTG_DIEPINT_TOC_Msk

#define USB_OTG_DIEPINT_TOC

#define USB_OTG_DIEPINT_ITTXFE_Pos

#define USB_OTG_DIEPINT_ITTXFE_Msk

#define USB_OTG_DIEPINT_ITTXFE

#define USB_OTG_DIEPINT_INEPNM_Pos

#define USB_OTG_DIEPINT_INEPNM_Msk

#define USB_OTG_DIEPINT_INEPNM

#define USB_OTG_DIEPINT_INEPNE_Pos

#define USB_OTG_DIEPINT_INEPNE_Msk

#define USB_OTG_DIEPINT_INEPNE

#define USB_OTG_DIEPINT_TXFE_Pos

#define USB_OTG_DIEPINT_TXFE_Msk

#define USB_OTG_DIEPINT_TXFE

#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos

#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk

#define USB_OTG_DIEPINT_TXFIFOUDRN

#define USB_OTG_DIEPINT_BNA_Pos

#define USB_OTG_DIEPINT_BNA_Msk

#define USB_OTG_DIEPINT_BNA

#define USB_OTG_DIEPINT_PKTDRPSTS_Pos

#define USB_OTG_DIEPINT_PKTDRPSTS_Msk

#define USB_OTG_DIEPINT_PKTDRPSTS

#define USB_OTG_DIEPINT_BERR_Pos

#define USB_OTG_DIEPINT_BERR_Msk

#define USB_OTG_DIEPINT_BERR

#define USB_OTG_DIEPINT_NAK_Pos

#define USB_OTG_DIEPINT_NAK_Msk

#define USB_OTG_DIEPINT_NAK

Bit definition forUSB_OTG_HCINTMSK register

#define USB_OTG_HCINTMSK_XFRCM_Pos

#define USB_OTG_HCINTMSK_XFRCM_Msk

#define USB_OTG_HCINTMSK_XFRCM

#define USB_OTG_HCINTMSK_CHHM_Pos

#define USB_OTG_HCINTMSK_CHHM_Msk

#define USB_OTG_HCINTMSK_CHHM

#define USB_OTG_HCINTMSK_AHBERR_Pos

#define USB_OTG_HCINTMSK_AHBERR_Msk

#define USB_OTG_HCINTMSK_AHBERR

#define USB_OTG_HCINTMSK_STALLM_Pos

#define USB_OTG_HCINTMSK_STALLM_Msk

#define USB_OTG_HCINTMSK_STALLM

#define USB_OTG_HCINTMSK_NAKM_Pos

#define USB_OTG_HCINTMSK_NAKM_Msk

#define USB_OTG_HCINTMSK_NAKM

#define USB_OTG_HCINTMSK_ACKM_Pos

#define USB_OTG_HCINTMSK_ACKM_Msk

#define USB_OTG_HCINTMSK_ACKM

#define USB_OTG_HCINTMSK_NYET_Pos

#define USB_OTG_HCINTMSK_NYET_Msk

#define USB_OTG_HCINTMSK_NYET

#define USB_OTG_HCINTMSK_TXERRM_Pos

#define USB_OTG_HCINTMSK_TXERRM_Msk

#define USB_OTG_HCINTMSK_TXERRM

#define USB_OTG_HCINTMSK_BBERRM_Pos

#define USB_OTG_HCINTMSK_BBERRM_Msk

#define USB_OTG_HCINTMSK_BBERRM

#define USB_OTG_HCINTMSK_FRMORM_Pos

#define USB_OTG_HCINTMSK_FRMORM_Msk

#define USB_OTG_HCINTMSK_FRMORM

#define USB_OTG_HCINTMSK_DTERRM_Pos

#define USB_OTG_HCINTMSK_DTERRM_Msk

#define USB_OTG_HCINTMSK_DTERRM

Bit definition for USB_OTG_DIEPTSIZ register

#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos

#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk

#define USB_OTG_DIEPTSIZ_XFRSIZ

#define USB_OTG_DIEPTSIZ_PKTCNT_Pos

#define USB_OTG_DIEPTSIZ_PKTCNT_Msk

#define USB_OTG_DIEPTSIZ_PKTCNT

#define USB_OTG_DIEPTSIZ_MULCNT_Pos

#define USB_OTG_DIEPTSIZ_MULCNT_Msk

#define USB_OTG_DIEPTSIZ_MULCNT

Bit definition for USB_OTG_HCTSIZ register

#define USB_OTG_HCTSIZ_XFRSIZ_Pos

#define USB_OTG_HCTSIZ_XFRSIZ_Msk

#define USB_OTG_HCTSIZ_XFRSIZ

#define USB_OTG_HCTSIZ_PKTCNT_Pos

#define USB_OTG_HCTSIZ_PKTCNT_Msk

#define USB_OTG_HCTSIZ_PKTCNT

#define USB_OTG_HCTSIZ_DOPING_Pos

#define USB_OTG_HCTSIZ_DOPING_Msk

#define USB_OTG_HCTSIZ_DOPING

#define USB_OTG_HCTSIZ_DPID_Pos

#define USB_OTG_HCTSIZ_DPID_Msk

#define USB_OTG_HCTSIZ_DPID

#define USB_OTG_HCTSIZ_DPID_0

#define USB_OTG_HCTSIZ_DPID_1

Bit definition for USB_OTG_DIEPDMA register

#define USB_OTG_DIEPDMA_DMAADDR_Pos

#define USB_OTG_DIEPDMA_DMAADDR_Msk

#define USB_OTG_DIEPDMA_DMAADDR

Bit definition for USB_OTG_HCDMA register

#define USB_OTG_HCDMA_DMAADDR_Pos

#define USB_OTG_HCDMA_DMAADDR_Msk

#define USB_OTG_HCDMA_DMAADDR

Bit definition for USB_OTG_DTXFSTS register

#define USB_OTG_DTXFSTS_INEPTFSAV_Pos

#define USB_OTG_DTXFSTS_INEPTFSAV_Msk

#define USB_OTG_DTXFSTS_INEPTFSAV

Bit definition for USB_OTG_DIEPTXF register

#define USB_OTG_DIEPTXF_INEPTXSA_Pos

#define USB_OTG_DIEPTXF_INEPTXSA_Msk

#define USB_OTG_DIEPTXF_INEPTXSA

#define USB_OTG_DIEPTXF_INEPTXFD_Pos

#define USB_OTG_DIEPTXF_INEPTXFD_Msk

#define USB_OTG_DIEPTXF_INEPTXFD

Bit definition for USB_OTG_DOEPCTL register

#define USB_OTG_DOEPCTL_MPSIZ_Pos

#define USB_OTG_DOEPCTL_MPSIZ_Msk

#define USB_OTG_DOEPCTL_MPSIZ

#define USB_OTG_DOEPCTL_USBAEP_Pos

#define USB_OTG_DOEPCTL_USBAEP_Msk

#define USB_OTG_DOEPCTL_USBAEP

#define USB_OTG_DOEPCTL_NAKSTS_Pos

#define USB_OTG_DOEPCTL_NAKSTS_Msk

#define USB_OTG_DOEPCTL_NAKSTS

#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos

#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk

#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM

#define USB_OTG_DOEPCTL_SODDFRM_Pos

#define USB_OTG_DOEPCTL_SODDFRM_Msk

#define USB_OTG_DOEPCTL_SODDFRM

#define USB_OTG_DOEPCTL_EPTYP_Pos

#define USB_OTG_DOEPCTL_EPTYP_Msk

#define USB_OTG_DOEPCTL_EPTYP

#define USB_OTG_DOEPCTL_EPTYP_0

#define USB_OTG_DOEPCTL_EPTYP_1

#define USB_OTG_DOEPCTL_SNPM_Pos

#define USB_OTG_DOEPCTL_SNPM_Msk

#define USB_OTG_DOEPCTL_SNPM

#define USB_OTG_DOEPCTL_STALL_Pos

#define USB_OTG_DOEPCTL_STALL_Msk

#define USB_OTG_DOEPCTL_STALL

#define USB_OTG_DOEPCTL_CNAK_Pos

#define USB_OTG_DOEPCTL_CNAK_Msk

#define USB_OTG_DOEPCTL_CNAK

#define USB_OTG_DOEPCTL_SNAK_Pos

#define USB_OTG_DOEPCTL_SNAK_Msk

#define USB_OTG_DOEPCTL_SNAK

#define USB_OTG_DOEPCTL_EPDIS_Pos

#define USB_OTG_DOEPCTL_EPDIS_Msk

#define USB_OTG_DOEPCTL_EPDIS

#define USB_OTG_DOEPCTL_EPENA_Pos

#define USB_OTG_DOEPCTL_EPENA_Msk

#define USB_OTG_DOEPCTL_EPENA

Bit definition for USB_OTG_DOEPINT register

#define USB_OTG_DOEPINT_XFRC_Pos

#define USB_OTG_DOEPINT_XFRC_Msk

#define USB_OTG_DOEPINT_XFRC

#define USB_OTG_DOEPINT_EPDISD_Pos

#define USB_OTG_DOEPINT_EPDISD_Msk

#define USB_OTG_DOEPINT_EPDISD

#define USB_OTG_DOEPINT_AHBERR_Pos

#define USB_OTG_DOEPINT_AHBERR_Msk

#define USB_OTG_DOEPINT_AHBERR

#define USB_OTG_DOEPINT_STUP_Pos

#define USB_OTG_DOEPINT_STUP_Msk

#define USB_OTG_DOEPINT_STUP

#define USB_OTG_DOEPINT_OTEPDIS_Pos

#define USB_OTG_DOEPINT_OTEPDIS_Msk

#define USB_OTG_DOEPINT_OTEPDIS

#define USB_OTG_DOEPINT_OTEPSPR_Pos

#define USB_OTG_DOEPINT_OTEPSPR_Msk

#define USB_OTG_DOEPINT_OTEPSPR

#define USB_OTG_DOEPINT_B2BSTUP_Pos

#define USB_OTG_DOEPINT_B2BSTUP_Msk

#define USB_OTG_DOEPINT_B2BSTUP

#define USB_OTG_DOEPINT_OUTPKTERR_Pos

#define USB_OTG_DOEPINT_OUTPKTERR_Msk

#define USB_OTG_DOEPINT_OUTPKTERR

#define USB_OTG_DOEPINT_NAK_Pos

#define USB_OTG_DOEPINT_NAK_Msk

#define USB_OTG_DOEPINT_NAK

#define USB_OTG_DOEPINT_NYET_Pos

#define USB_OTG_DOEPINT_NYET_Msk

#define USB_OTG_DOEPINT_NYET

#define USB_OTG_DOEPINT_STPKTRX_Pos

#define USB_OTG_DOEPINT_STPKTRX_Msk

#define USB_OTG_DOEPINT_STPKTRX

Bit definition for USB_OTG_DOEPTSIZ register

#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos

#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk

#define USB_OTG_DOEPTSIZ_XFRSIZ

#define USB_OTG_DOEPTSIZ_PKTCNT_Pos

#define USB_OTG_DOEPTSIZ_PKTCNT_Msk

#define USB_OTG_DOEPTSIZ_PKTCNT

#define USB_OTG_DOEPTSIZ_STUPCNT_Pos

#define USB_OTG_DOEPTSIZ_STUPCNT_Msk

#define USB_OTG_DOEPTSIZ_STUPCNT

#define USB_OTG_DOEPTSIZ_STUPCNT_0

#define USB_OTG_DOEPTSIZ_STUPCNT_1

Bit definition for PCGCCTL register

#define USB_OTG_PCGCCTL_STOPCLK_Pos

#define USB_OTG_PCGCCTL_STOPCLK_Msk

#define USB_OTG_PCGCCTL_STOPCLK

#define USB_OTG_PCGCCTL_GATECLK_Pos

#define USB_OTG_PCGCCTL_GATECLK_Msk

#define USB_OTG_PCGCCTL_GATECLK

#define USB_OTG_PCGCCTL_PHYSUSP_Pos

#define USB_OTG_PCGCCTL_PHYSUSP_Msk

#define USB_OTG_PCGCCTL_PHYSUSP

Bit definition for OTG register

#define USB_OTG_CHNUM_Pos

#define USB_OTG_CHNUM_Msk

#define USB_OTG_CHNUM

#define USB_OTG_CHNUM_0

#define USB_OTG_CHNUM_1

#define USB_OTG_CHNUM_2

#define USB_OTG_CHNUM_3

#define USB_OTG_BCNT_Pos

#define USB_OTG_BCNT_Msk

#define USB_OTG_BCNT

#define USB_OTG_DPID_Pos

#define USB_OTG_DPID_Msk

#define USB_OTG_DPID

#define USB_OTG_DPID_0

#define USB_OTG_DPID_1

#define USB_OTG_PKTSTS_Pos

#define USB_OTG_PKTSTS_Msk

#define USB_OTG_PKTSTS

#define USB_OTG_PKTSTS_0

#define USB_OTG_PKTSTS_1

#define USB_OTG_PKTSTS_2

#define USB_OTG_PKTSTS_3

#define USB_OTG_EPNUM_Pos

#define USB_OTG_EPNUM_Msk

#define USB_OTG_EPNUM

#define USB_OTG_EPNUM_0

#define USB_OTG_EPNUM_1

#define USB_OTG_EPNUM_2

#define USB_OTG_EPNUM_3

#define USB_OTG_FRMNUM_Pos

#define USB_OTG_FRMNUM_Msk

#define USB_OTG_FRMNUM

#define USB_OTG_FRMNUM_0

#define USB_OTG_FRMNUM_1

#define USB_OTG_FRMNUM_2

#define USB_OTG_FRMNUM_3

ADC Instances

#define IS_ADC_MULTIMODE_MASTER_INSTANCE

#define IS_ADC_COMMON_INSTANCE

CAN Instances

CRC Instances

#define IS_CRC_ALL_INSTANCE

DAC Instances

#define IS_DAC_ALL_INSTANCE

DCMI Instances

#define IS_DCMI_ALL_INSTANCE

DMA2D Instances

#define IS_DMA2D_ALL_INSTANCE

DMA Instances

GPIO Instances

I2C Instances

SMBUS Instances

#define IS_SMBUS_ALL_INSTANCE

I2S Instances

I2S Extended Instances

#define IS_I2S_ALL_INSTANCE_EXT

#define IS_LTDC_ALL_INSTANCE

RNG Instances

#define IS_RNG_ALL_INSTANCE

RTC Instances

#define IS_RTC_ALL_INSTANCE

SAI Instances

#define IS_SAI_BLOCK_PERIPH

SPI Instances

TIM Instances : All supported instances

TIM Instances : at least 1 capture/compare channel

TIM Instances : at least 2 capture/compare channels

TIM Instances : at least 3 capture/compare channels

TIM Instances : at least 4 capture/compare channels

TIM Instances : Advanced-control timers

TIM Instances : Timer input XOR function

TIM Instances : DMA requests generation (UDE)

TIM Instances : DMA requests generation (CCxDE)

TIM Instances : DMA requests generation (COMDE)

TIM Instances : DMA burst feature

TIM Instances : 32 bit Counter

TIM Instances : external trigger input available

TIM Instances : remapping capability

TIM Instances : output(s) available

TIM Instances : complementary output(s) available

TIM Instances : supporting clock division

TIM Instances : supporting OCxREF clear

TIM Instances : supporting repetition counter

TIM Instances : supporting encoder interface

TIM Instances : supporting Hall sensor interface

TIM Instances : supporting the break function

USART Instances : Synchronous mode

UART Instances : Half-Duplex mode

#define IS_UART_INSTANCE

UART Instances : Hardware Flow control

UART Instances : LIN mode

#define IS_UART_LIN_INSTANCE

UART Instances : Smart card mode

UART Instances : IRDA mode

PCD Instances

HCD Instances

SDIO Instances

#define IS_SDIO_ALL_INSTANCE

IWDG Instances

#define IS_IWDG_ALL_INSTANCE

WWDG Instances

#define IS_WWDG_ALL_INSTANCE

USB Exported Constants

#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR

#define USB_OTG_FS_MAX_IN_ENDPOINTS

#define USB_OTG_FS_MAX_OUT_ENDPOINTS

#define USB_OTG_FS_TOTAL_FIFO_SIZE

#define RCC_PLLCFGR_RST_VALUE

#define RCC_PLLI2SCFGR_RST_VALUE

#define RCC_PLLSAICFGR_RST_VALUE

#define RCC_MAX_FREQUENCY

#define RCC_MAX_FREQUENCY_SCALE1

#define RCC_MAX_FREQUENCY_SCALE2

#define RCC_MAX_FREQUENCY_SCALE3

#define RCC_PLLVCO_OUTPUT_MIN

#define RCC_PLLVCO_INPUT_MIN

#define RCC_PLLVCO_INPUT_MAX

#define RCC_PLLVCO_OUTPUT_MAX

#define RCC_PLLN_MIN_VALUE

#define RCC_PLLN_MAX_VALUE

#define FLASH_SCALE1_LATENCY1_FREQ

#define FLASH_SCALE1_LATENCY2_FREQ

#define FLASH_SCALE1_LATENCY3_FREQ

#define FLASH_SCALE1_LATENCY4_FREQ

#define FLASH_SCALE1_LATENCY5_FREQ

#define FLASH_SCALE2_LATENCY1_FREQ

#define FLASH_SCALE2_LATENCY2_FREQ

#define FLASH_SCALE2_LATENCY3_FREQ

#define FLASH_SCALE2_LATENCY4_FREQ

#define FLASH_SCALE2_LATENCY5_FREQ

#define FLASH_SCALE3_LATENCY1_FREQ

#define FLASH_SCALE3_LATENCY2_FREQ

#define FLASH_SCALE3_LATENCY3_FREQ

#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR

#define USB_OTG_HS_MAX_IN_ENDPOINTS

#define USB_OTG_HS_MAX_OUT_ENDPOINTS

#define USB_OTG_HS_TOTAL_FIFO_SIZE

...

#define FSMC_IRQn

#define FSMC_IRQHandler

Files

SourceVuSTM32 Libraries and SamplesCMSISDevice/ST/STM32F4xx/Include/stm32f429xx.h

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