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SourceVuESP-IDF Framework and ExamplesESP-IDFadc_hal_digi_sample_freq_config()

adc_hal_digi_sample_freq_config() function

For esp32s2 and later chips - Set ADC digital controller clock division factor. The clock is divided from `APLL` or `APB` clock. Expression: controller_clk = APLL/APB * (div_num + div_a / div_b + 1). - Enable clock and select clock source for ADC digital controller. For esp32, use I2S clock

Syntax

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Summary

Declaration

from adc_hal.c:119

static void adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t *hal, adc_continuous_clk_src_t clk_src, uint32_t clk_src_freq_hz, uint32_t sample_freq_hz);

Arguments

Argument

hal

clk_src

clk_src_freq_hz

sample_freq_hz

References

Code

Location

Referrer

static void adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t *hal, adc_continuous_clk_src_t clk_src, uint32_t clk_src_freq_hz, uint32_t sample_freq_hz)

adc_hal_digi_sample_freq_config(hal, cfg->clk_src, cfg->clk_src_freq_hz, cfg->sample_freq_hz);

adc_hal_digi_controller_config()

Call Tree

adc_hal_digi_sample_freq_config() is called by 1 function and calls 4 functions:

adc_hal_digi_controller_config()

adc_hal_digi_sample_freq_config()

i2s_ll_rx_clk_set_src()

i2s_ll_rx_set_bck_div_num()

i2s_ll_rx_set_mclk()

i2s_hal_calc_mclk_precise_division()

Data Use

adc_hal_digi_sample_freq_config() reads 2 variables:

soc_periph_i2s_clk_src_t::I2S_CLK_SRC_DEFAULT

adc_hal_i2s_dev

adc_hal_digi_sample_freq_config()

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