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SourceVuESP-IDF Framework and ExamplesESP-IDFFUN_DRV_V

FUN_DRV_V macro

Syntax

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Summary

Declaration

from io_mux_reg.h:60

#define FUN_DRV_V 0x3

References

Code

Location

#define FUN_DRV_V 0x3

io_mux_reg.h:60

SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_cs_io], FUN_DRV_V, 3, FUN_DRV_S);

esp_psram_impl_quad.c:822

SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV_V, 3, FUN_DRV_S);

esp_psram_impl_quad.c:823

SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_cs_io], FUN_DRV_V, 3, FUN_DRV_S);

esp_psram_impl_quad.c:824

SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], FUN_DRV_V, 3, FUN_DRV_S);

esp_psram_impl_quad.c:825

SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spiq_sd0_io], FUN_DRV_V, 3, FUN_DRV_S);

esp_psram_impl_quad.c:826

SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spid_sd1_io], FUN_DRV_V, 3, FUN_DRV_S);

esp_psram_impl_quad.c:827

SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spihd_sd2_io], FUN_DRV_V, 3, FUN_DRV_S);

esp_psram_impl_quad.c:828

SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spiwp_sd3_io], FUN_DRV_V, 3, FUN_DRV_S);

esp_psram_impl_quad.c:829

SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S);

*strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);

#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)

io_mux_reg.h:59