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SourceVuESP-IDF Framework and ExamplesESP-IDFpsram_io_t::flash_clk_io

psram_io_t::flash_clk_io field

Syntax

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Summary

Declaration

from esp_psram_impl_quad.c:151

uint8_t flash_clk_io;

References

Code

Location

Referrer

uint8_t flash_clk_io;

esp_psram_impl_quad.c:151

SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV, 3, FUN_DRV_S);

esp_psram_impl_quad.c:760

psram_gpio_config()

SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV, 3, FUN_DRV_S);

esp_psram_impl_quad.c:771

psram_gpio_config()

SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV, 2, FUN_DRV_S);

esp_psram_impl_quad.c:782

psram_gpio_config()

if ((psram_io->flash_clk_io == MSPI_IOMUX_PIN_NUM_CLK) && (psram_io->flash_clk_io != psram_io->psram_clk_io)) {

esp_psram_impl_quad.c:804

psram_gpio_config()

gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUNC_SD_CLK_SPICLK);

esp_psram_impl_quad.c:806

psram_gpio_config()

gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], PIN_FUNC_GPIO);

esp_psram_impl_quad.c:809

psram_gpio_config()

SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV_V, 3, FUN_DRV_S);

esp_psram_impl_quad.c:823

psram_gpio_config()

esp_gpio_reserve(BIT64(psram_io->flash_clk_io) |

esp_psram_impl_quad.c:833

psram_gpio_config()

psram_io.flash_clk_io = MSPI_IOMUX_PIN_NUM_CLK;

esp_psram_impl_quad.c:913

esp_psram_impl_enable()

psram_io.flash_clk_io = FLASH_HSPI_CLK_IO;

esp_psram_impl_quad.c:920

esp_psram_impl_enable()

psram_io.flash_clk_io = EFUSE_SPICONFIG_RET_SPICLK(spiconfig);

esp_psram_impl_quad.c:927

esp_psram_impl_enable()

if (psram_io.flash_clk_io == psram_io.psram_clk_io) {

esp_psram_impl_quad.c:935

esp_psram_impl_enable()

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Data Use

psram_io_t::flash_clk_io is written by 1 function and is read by 2 functions:

esp_psram_impl_enable()

psram_io_t::flash_clk_io

psram_gpio_config()

esp_psram_impl_enable()

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