mips32_cpu_support_sync() function

MIPS EJTAG information structure.

mips32_cpu_support_hazard_barrier - Checks CPU supports hazard barrier hazard barrier instructions EHB and *.HB was introduced to MIPS from release 2.

\b mips32_cp0_read Simulates mfc0 ASM instruction (Move From C0), i.e. implements copro C0 Register read.

\b mips32_cp0_write Simulates mtc0 ASM instruction (Move To C0), i.e. implements copro C0 Register read.

mips32_cp1_control_read Simulates cfc1 ASM instruction (Move Control Word From Floating Point), i.e. implements copro C1 Control Register read.

mips32_read_config_mmu - Reads MMU configuration and logs relevant information. Reads the MMU configuration from the CP0 register and calculates the number of TLB entries, ways, and sets. Handles different MMU types like VTLB only, root RPU/Fixed, and VTLB and FTLB.

mips32_cp0_get_all_regs - Print all CP0 registers and their values. Iterates over all CP0 registers, reads their values, and prints them. Only considers registers relevant to the current core, as defined by cp0_mask.

mips32_cp0_get_reg_by_name - Read and print a CP0 register's value by name. Finds a CP0 register by name, reads its value, and prints it. Handles error scenarios like register not found or read failure.

mips32_cp0_get_reg_by_number - Read and print a CP0 register's value by number. Reads a specific CP0 register (identified by number and selection) and prints its value. The register number and selection are parsed from the command arguments.

mips32_pracc_write_dsp_reg - Write a value to a MIPS32 DSP register Writes the specified value to the specified MIPS32 DSP register. This function initiates a sequence of instructions to write the given value to the specified DSP register.

mips32_read_config_fdc - Read Fast Debug Channel configuration Checks if the current target implements the Common Device Memory Map (CDMM) and Fast Debug Channel (FDC). This function examines the configuration registers and the Device Configuration Register (DCR) to determine if the current MIPS32 target supports the Common Device Memory Map (CDMM) and the Fast Debug Channel (FDC). If supported, it sets the corresponding flags in the MIPS32 common structure. \n NOTE:These are defined on MD00090, page 67 and MD00047F, page 82, respectively. MIPS Documents are pretty much all available online, it should pop up first when you search "MDxxxxx"

mips32_cp0_set_reg_by_name - Write to a CP0 register identified by name. Writes a value to a CP0 register specified by name. Updates internal cache if specific registers (STATUS, CAUSE, DEPC, GUESTCTL1) are modified.

mips32_cp0_set_reg_by_number - Write to a CP0 register identified by number. Writes a value to a CP0 register specified by number and selection. Handles special cases like updating the internal cache for certain registers.

mips32_pracc_read_dsp_reg - Read a value from a MIPS32 DSP register Reads the value from the specified MIPS32 DSP register using EJTAG access. This function initiates a sequence of instructions to read the value from the specified DSP register. It will enable dsp module if its not enabled and restoring the status registers after the read operation.

mips32_dsp_get_all_regs - Get values of all MIPS32 DSP registers This function iterates through all DSP registers, reads their values, and prints each register name along with its corresponding value.

mips32_dsp_get_register - Get the value of a MIPS32 DSP register Retrieves the value of a specified MIPS32 DSP register. If the register is found, it reads the register value and prints the result. If the register is not found, it prints an error message.

mips32_dsp_set_register - Set the value of a MIPS32 DSP register Sets the value of a specified MIPS32 DSP register. If the register is found, it writes provided value to the register. If the register is not found or there is an error in writing the value, it prints an error message.

\b mips32_pracc_sync_cache Synchronize Caches to Make Instruction Writes Effective (ref. doc. MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set, Document Number: MD00086, Revision 2.00, June 9, 2003) When the instruction stream is written, the SYNCI instruction should be used in conjunction with other instructions to make the newly-written instructions effective. Explanation : A program that loads another program into memory is actually writing the D- side cache. The instructions it has loaded can't be executed until they reach the I-cache. After the instructions have been written, the loader should arrange to write back any containing D-cache line and invalidate any locations already in the I-cache. If the cache coherency attribute (CCA) is set to zero, it's a write through cache, there is no need to write back. In the latest MIPS32/64 CPUs, MIPS provides the synci instruction, which does the whole job for a cache-line-sized chunk of the memory you just loaded: That is, it arranges a D-cache write-back (if CCA = 3) and an I-cache invalidate. The line size is obtained with the rdhwr SYNCI_Step in release 2 or from cp0 config 1 register in release 1.

mips32_pracc_fastdata_xfer_synchronize_cache - Synchronize cache for fast data transfer Synchronizes the cache for fast data transfer based on the specified address and cache configuration. If the region is cacheable (write-back cache or write-through cache), it synchronizes the cache for the specified range. The synchronization is performed using the MIPS32 cache synchronization function.