Configure multi channel delay block: Use DFSDM2 audio clock source as input clock for DFSDM1 and DFSDM2 filters to Synchronize DFSDMx filters. Set the path of the DFSDM2 clock output (dfsdm2_ckout) to the DFSDM1/2 CkInx and data inputs channels by configuring following MCHDLY muxes or demuxes: M1, M2, M3, M4, M5, M6, M7, M8, DM1, DM2, DM3, DM4, DM5, DM6, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20 based on the contains of the DFSDM_MultiChannelConfigTypeDef structure
The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called before HAL_DFSDM_ConfigMultiChannelDelay() The HAL_DFSDM_ConfigMultiChannelDelay() function clears the SYSCFG-MCHDLYCR register before setting the new configuration.
Examples
HAL_DFSDM_ConfigMultiChannelDelay() is referenced by 1 libraries and example projects: