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SourceVuSTM32 Libraries and SamplesHALLL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS

LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS macro

ADC group regular sequencer enable with 4 ranks in the sequence

Syntax

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Summary

Declaration

from stm32f4xx_ll_adc.h:720

#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)

Examples

References

from examples