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SourceVuSTM32 Libraries and SamplesHALLL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS

LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS macro

ADC group regular sequencer enable with 11 ranks in the sequence

Syntax

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Summary

Declaration

from stm32f4xx_ll_adc.h:727

#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )

Examples

References

from examples