Inc/stm32f4xx_ll_rcc.h (HAL)

Outline

#define __STM32F4xx_LL_RCC_H

#include "stm32f4xx.h"

Private variables

Private macros

Exported types

LL_RCC_ClocksTypeDef

Exported constants

#define HSE_VALUE

#define HSI_VALUE

#define LSE_VALUE

#define LSI_VALUE

#define EXTERNAL_CLOCK_VALUE

#define LL_RCC_CIR_LSIRDYC

#define LL_RCC_CIR_LSERDYC

#define LL_RCC_CIR_HSIRDYC

#define LL_RCC_CIR_HSERDYC

#define LL_RCC_CIR_PLLRDYC

#define LL_RCC_CIR_PLLI2SRDYC

#define LL_RCC_CIR_PLLSAIRDYC

#define LL_RCC_CIR_CSSC

#define LL_RCC_CIR_LSIRDYF

#define LL_RCC_CIR_LSERDYF

#define LL_RCC_CIR_HSIRDYF

#define LL_RCC_CIR_HSERDYF

#define LL_RCC_CIR_PLLRDYF

#define LL_RCC_CIR_PLLI2SRDYF

#define LL_RCC_CIR_PLLSAIRDYF

#define LL_RCC_CIR_CSSF

#define LL_RCC_CSR_LPWRRSTF

#define LL_RCC_CSR_PINRSTF

#define LL_RCC_CSR_PORRSTF

#define LL_RCC_CSR_SFTRSTF

#define LL_RCC_CSR_IWDGRSTF

#define LL_RCC_CSR_WWDGRSTF

#define LL_RCC_CSR_BORRSTF

#define LL_RCC_CIR_LSIRDYIE

#define LL_RCC_CIR_LSERDYIE

#define LL_RCC_CIR_HSIRDYIE

#define LL_RCC_CIR_HSERDYIE

#define LL_RCC_CIR_PLLRDYIE

#define LL_RCC_CIR_PLLI2SRDYIE

#define LL_RCC_CIR_PLLSAIRDYIE

#define LL_RCC_SYS_CLKSOURCE_HSI

#define LL_RCC_SYS_CLKSOURCE_HSE

#define LL_RCC_SYS_CLKSOURCE_PLL

#define LL_RCC_SYS_CLKSOURCE_PLLR

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE

#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL

#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR

#define LL_RCC_SYSCLK_DIV_1

#define LL_RCC_SYSCLK_DIV_2

#define LL_RCC_SYSCLK_DIV_4

#define LL_RCC_SYSCLK_DIV_8

#define LL_RCC_SYSCLK_DIV_16

#define LL_RCC_SYSCLK_DIV_64

#define LL_RCC_SYSCLK_DIV_128

#define LL_RCC_SYSCLK_DIV_256

#define LL_RCC_SYSCLK_DIV_512

#define LL_RCC_APB1_DIV_1

#define LL_RCC_APB1_DIV_2

#define LL_RCC_APB1_DIV_4

#define LL_RCC_APB1_DIV_8

#define LL_RCC_APB1_DIV_16

#define LL_RCC_APB2_DIV_1

#define LL_RCC_APB2_DIV_2

#define LL_RCC_APB2_DIV_4

#define LL_RCC_APB2_DIV_8

#define LL_RCC_APB2_DIV_16

#define LL_RCC_MCO1SOURCE_HSI

#define LL_RCC_MCO1SOURCE_LSE

#define LL_RCC_MCO1SOURCE_HSE

#define LL_RCC_MCO1SOURCE_PLLCLK

#define LL_RCC_MCO2SOURCE_SYSCLK

#define LL_RCC_MCO2SOURCE_PLLI2S

#define LL_RCC_MCO2SOURCE_HSE

#define LL_RCC_MCO2SOURCE_PLLCLK

#define LL_RCC_MCO1_DIV_1

#define LL_RCC_MCO1_DIV_2

#define LL_RCC_MCO1_DIV_3

#define LL_RCC_MCO1_DIV_4

#define LL_RCC_MCO1_DIV_5

#define LL_RCC_MCO2_DIV_1

#define LL_RCC_MCO2_DIV_2

#define LL_RCC_MCO2_DIV_3

#define LL_RCC_MCO2_DIV_4

#define LL_RCC_MCO2_DIV_5

#define LL_RCC_RTC_NOCLOCK

#define LL_RCC_RTC_HSE_DIV_2

#define LL_RCC_RTC_HSE_DIV_3

#define LL_RCC_RTC_HSE_DIV_4

#define LL_RCC_RTC_HSE_DIV_5

#define LL_RCC_RTC_HSE_DIV_6

#define LL_RCC_RTC_HSE_DIV_7

#define LL_RCC_RTC_HSE_DIV_8

#define LL_RCC_RTC_HSE_DIV_9

#define LL_RCC_RTC_HSE_DIV_10

#define LL_RCC_RTC_HSE_DIV_11

#define LL_RCC_RTC_HSE_DIV_12

#define LL_RCC_RTC_HSE_DIV_13

#define LL_RCC_RTC_HSE_DIV_14

#define LL_RCC_RTC_HSE_DIV_15

#define LL_RCC_RTC_HSE_DIV_16

#define LL_RCC_RTC_HSE_DIV_17

#define LL_RCC_RTC_HSE_DIV_18

#define LL_RCC_RTC_HSE_DIV_19

#define LL_RCC_RTC_HSE_DIV_20

#define LL_RCC_RTC_HSE_DIV_21

#define LL_RCC_RTC_HSE_DIV_22

#define LL_RCC_RTC_HSE_DIV_23

#define LL_RCC_RTC_HSE_DIV_24

#define LL_RCC_RTC_HSE_DIV_25

#define LL_RCC_RTC_HSE_DIV_26

#define LL_RCC_RTC_HSE_DIV_27

#define LL_RCC_RTC_HSE_DIV_28

#define LL_RCC_RTC_HSE_DIV_29

#define LL_RCC_RTC_HSE_DIV_30

#define LL_RCC_RTC_HSE_DIV_31

#define LL_RCC_PERIPH_FREQUENCY_NO

#define LL_RCC_PERIPH_FREQUENCY_NA

#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1

#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK

#define LL_RCC_FMPI2C1_CLKSOURCE_HSI

#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1

#define LL_RCC_LPTIM1_CLKSOURCE_HSI

#define LL_RCC_LPTIM1_CLKSOURCE_LSI

#define LL_RCC_LPTIM1_CLKSOURCE_LSE

#define LL_RCC_SAI1_CLKSOURCE_PLLSAI

#define LL_RCC_SAI1_CLKSOURCE_PLLI2S

#define LL_RCC_SAI1_CLKSOURCE_PLL

#define LL_RCC_SAI1_CLKSOURCE_PIN

#define LL_RCC_SAI2_CLKSOURCE_PLLSAI

#define LL_RCC_SAI2_CLKSOURCE_PLLI2S

#define LL_RCC_SAI2_CLKSOURCE_PLL

#define LL_RCC_SAI2_CLKSOURCE_PLLSRC

#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S

#define LL_RCC_SAI1_A_CLKSOURCE_PIN

#define LL_RCC_SAI1_A_CLKSOURCE_PLL

#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC

#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI

#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S

#define LL_RCC_SAI1_A_CLKSOURCE_PIN

#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S

#define LL_RCC_SAI1_B_CLKSOURCE_PIN

#define LL_RCC_SAI1_B_CLKSOURCE_PLL

#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC

#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI

#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S

#define LL_RCC_SAI1_B_CLKSOURCE_PIN

#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK

#define LL_RCC_SDIO_CLKSOURCE_SYSCLK

#define LL_RCC_DSI_CLKSOURCE_PHY

#define LL_RCC_DSI_CLKSOURCE_PLL

#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488

#define LL_RCC_CEC_CLKSOURCE_LSE

#define LL_RCC_I2S1_CLKSOURCE_PLLI2S

#define LL_RCC_I2S1_CLKSOURCE_PIN

#define LL_RCC_I2S1_CLKSOURCE_PLL

#define LL_RCC_I2S1_CLKSOURCE_PIN

#define LL_RCC_I2S1_CLKSOURCE_PLLSRC

#define LL_RCC_I2S1_CLKSOURCE_PLLI2S

#define LL_RCC_I2S1_CLKSOURCE_PIN

#define LL_RCC_I2S1_CLKSOURCE_PLL

#define LL_RCC_I2S1_CLKSOURCE_PLLSRC

#define LL_RCC_I2S2_CLKSOURCE_PLLI2S

#define LL_RCC_I2S2_CLKSOURCE_PIN

#define LL_RCC_I2S2_CLKSOURCE_PLL

#define LL_RCC_I2S2_CLKSOURCE_PLLSRC

#define LL_RCC_CK48M_CLKSOURCE_PLL

#define LL_RCC_CK48M_CLKSOURCE_PLLSAI

#define LL_RCC_CK48M_CLKSOURCE_PLL

#define LL_RCC_CK48M_CLKSOURCE_PLLSAI

#define LL_RCC_CK48M_CLKSOURCE_PLLI2S

#define LL_RCC_RNG_CLKSOURCE_PLL

#define LL_RCC_RNG_CLKSOURCE_PLLSAI

#define LL_RCC_RNG_CLKSOURCE_PLLI2S

#define LL_RCC_USB_CLKSOURCE_PLL

#define LL_RCC_USB_CLKSOURCE_PLLSAI

#define LL_RCC_USB_CLKSOURCE_PLLI2S

#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1

#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2

#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1

#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2

#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2

#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK

#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2

#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK

#define LL_RCC_FMPI2C1_CLKSOURCE

#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL

#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S

#define LL_RCC_LPTIM1_CLKSOURCE

#define LL_RCC_SAI1_A_CLKSOURCE

#define LL_RCC_SAI1_B_CLKSOURCE

#define LL_RCC_SAI1_CLKSOURCE

#define LL_RCC_SAI2_CLKSOURCE

#define LL_RCC_SDIO_CLKSOURCE

#define LL_RCC_CK48M_CLKSOURCE

#define LL_RCC_RNG_CLKSOURCE

#define LL_RCC_USB_CLKSOURCE

#define LL_RCC_CEC_CLKSOURCE

#define LL_RCC_I2S1_CLKSOURCE

#define LL_RCC_I2S2_CLKSOURCE

#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE

#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE

#define LL_RCC_DFSDM1_CLKSOURCE

#define LL_RCC_DFSDM2_CLKSOURCE

#define LL_RCC_SPDIFRX1_CLKSOURCE

#define LL_RCC_DSI_CLKSOURCE

#define LL_RCC_LTDC_CLKSOURCE

#define LL_RCC_RTC_CLKSOURCE_NONE

#define LL_RCC_RTC_CLKSOURCE_LSE

#define LL_RCC_RTC_CLKSOURCE_LSI

#define LL_RCC_RTC_CLKSOURCE_HSE

#define LL_RCC_TIM_PRESCALER_TWICE

#define LL_RCC_TIM_PRESCALER_FOUR_TIMES

#define LL_RCC_PLLSOURCE_HSI

#define LL_RCC_PLLSOURCE_HSE

#define LL_RCC_PLLI2SSOURCE_PIN

#define LL_RCC_PLLM_DIV_2

#define LL_RCC_PLLM_DIV_3

#define LL_RCC_PLLM_DIV_4

#define LL_RCC_PLLM_DIV_5

#define LL_RCC_PLLM_DIV_6

#define LL_RCC_PLLM_DIV_7

#define LL_RCC_PLLM_DIV_8

#define LL_RCC_PLLM_DIV_9

#define LL_RCC_PLLM_DIV_10

#define LL_RCC_PLLM_DIV_11

#define LL_RCC_PLLM_DIV_12

#define LL_RCC_PLLM_DIV_13

#define LL_RCC_PLLM_DIV_14

#define LL_RCC_PLLM_DIV_15

#define LL_RCC_PLLM_DIV_16

#define LL_RCC_PLLM_DIV_17

#define LL_RCC_PLLM_DIV_18

#define LL_RCC_PLLM_DIV_19

#define LL_RCC_PLLM_DIV_20

#define LL_RCC_PLLM_DIV_21

#define LL_RCC_PLLM_DIV_22

#define LL_RCC_PLLM_DIV_23

#define LL_RCC_PLLM_DIV_24

#define LL_RCC_PLLM_DIV_25

#define LL_RCC_PLLM_DIV_26

#define LL_RCC_PLLM_DIV_27

#define LL_RCC_PLLM_DIV_28

#define LL_RCC_PLLM_DIV_29

#define LL_RCC_PLLM_DIV_30

#define LL_RCC_PLLM_DIV_31

#define LL_RCC_PLLM_DIV_32

#define LL_RCC_PLLM_DIV_33

#define LL_RCC_PLLM_DIV_34

#define LL_RCC_PLLM_DIV_35

#define LL_RCC_PLLM_DIV_36

#define LL_RCC_PLLM_DIV_37

#define LL_RCC_PLLM_DIV_38

#define LL_RCC_PLLM_DIV_39

#define LL_RCC_PLLM_DIV_40

#define LL_RCC_PLLM_DIV_41

#define LL_RCC_PLLM_DIV_42

#define LL_RCC_PLLM_DIV_43

#define LL_RCC_PLLM_DIV_44

#define LL_RCC_PLLM_DIV_45

#define LL_RCC_PLLM_DIV_46

#define LL_RCC_PLLM_DIV_47

#define LL_RCC_PLLM_DIV_48

#define LL_RCC_PLLM_DIV_49

#define LL_RCC_PLLM_DIV_50

#define LL_RCC_PLLM_DIV_51

#define LL_RCC_PLLM_DIV_52

#define LL_RCC_PLLM_DIV_53

#define LL_RCC_PLLM_DIV_54

#define LL_RCC_PLLM_DIV_55

#define LL_RCC_PLLM_DIV_56

#define LL_RCC_PLLM_DIV_57

#define LL_RCC_PLLM_DIV_58

#define LL_RCC_PLLM_DIV_59

#define LL_RCC_PLLM_DIV_60

#define LL_RCC_PLLM_DIV_61

#define LL_RCC_PLLM_DIV_62

#define LL_RCC_PLLM_DIV_63

#define LL_RCC_PLLR_DIV_2

#define LL_RCC_PLLR_DIV_3

#define LL_RCC_PLLR_DIV_4

#define LL_RCC_PLLR_DIV_5

#define LL_RCC_PLLR_DIV_6

#define LL_RCC_PLLR_DIV_7

#define LL_RCC_PLLDIVR_DIV_1

#define LL_RCC_PLLDIVR_DIV_2

#define LL_RCC_PLLDIVR_DIV_3

#define LL_RCC_PLLDIVR_DIV_4

#define LL_RCC_PLLDIVR_DIV_5

#define LL_RCC_PLLDIVR_DIV_6

#define LL_RCC_PLLDIVR_DIV_7

#define LL_RCC_PLLDIVR_DIV_8

#define LL_RCC_PLLDIVR_DIV_9

#define LL_RCC_PLLDIVR_DIV_10

#define LL_RCC_PLLDIVR_DIV_11

#define LL_RCC_PLLDIVR_DIV_12

#define LL_RCC_PLLDIVR_DIV_13

#define LL_RCC_PLLDIVR_DIV_14

#define LL_RCC_PLLDIVR_DIV_15

#define LL_RCC_PLLDIVR_DIV_16

#define LL_RCC_PLLDIVR_DIV_17

#define LL_RCC_PLLDIVR_DIV_18

#define LL_RCC_PLLDIVR_DIV_19

#define LL_RCC_PLLDIVR_DIV_20

#define LL_RCC_PLLDIVR_DIV_21

#define LL_RCC_PLLDIVR_DIV_22

#define LL_RCC_PLLDIVR_DIV_23

#define LL_RCC_PLLDIVR_DIV_24

#define LL_RCC_PLLDIVR_DIV_25

#define LL_RCC_PLLDIVR_DIV_26

#define LL_RCC_PLLDIVR_DIV_27

#define LL_RCC_PLLDIVR_DIV_28

#define LL_RCC_PLLDIVR_DIV_29

#define LL_RCC_PLLDIVR_DIV_30

#define LL_RCC_PLLDIVR_DIV_31

#define LL_RCC_PLLP_DIV_2

#define LL_RCC_PLLP_DIV_4

#define LL_RCC_PLLP_DIV_6

#define LL_RCC_PLLP_DIV_8

#define LL_RCC_PLLQ_DIV_2

#define LL_RCC_PLLQ_DIV_3

#define LL_RCC_PLLQ_DIV_4

#define LL_RCC_PLLQ_DIV_5

#define LL_RCC_PLLQ_DIV_6

#define LL_RCC_PLLQ_DIV_7

#define LL_RCC_PLLQ_DIV_8

#define LL_RCC_PLLQ_DIV_9

#define LL_RCC_PLLQ_DIV_10

#define LL_RCC_PLLQ_DIV_11

#define LL_RCC_PLLQ_DIV_12

#define LL_RCC_PLLQ_DIV_13

#define LL_RCC_PLLQ_DIV_14

#define LL_RCC_PLLQ_DIV_15

#define LL_RCC_SPREAD_SELECT_CENTER

#define LL_RCC_SPREAD_SELECT_DOWN

#define LL_RCC_PLLI2SM_DIV_2

#define LL_RCC_PLLI2SM_DIV_3

#define LL_RCC_PLLI2SM_DIV_4

#define LL_RCC_PLLI2SM_DIV_5

#define LL_RCC_PLLI2SM_DIV_6

#define LL_RCC_PLLI2SM_DIV_7

#define LL_RCC_PLLI2SM_DIV_8

#define LL_RCC_PLLI2SM_DIV_9

#define LL_RCC_PLLI2SM_DIV_10

#define LL_RCC_PLLI2SM_DIV_11

#define LL_RCC_PLLI2SM_DIV_12

#define LL_RCC_PLLI2SM_DIV_13

#define LL_RCC_PLLI2SM_DIV_14

#define LL_RCC_PLLI2SM_DIV_15

#define LL_RCC_PLLI2SM_DIV_16

#define LL_RCC_PLLI2SM_DIV_17

#define LL_RCC_PLLI2SM_DIV_18

#define LL_RCC_PLLI2SM_DIV_19

#define LL_RCC_PLLI2SM_DIV_20

#define LL_RCC_PLLI2SM_DIV_21

#define LL_RCC_PLLI2SM_DIV_22

#define LL_RCC_PLLI2SM_DIV_23

#define LL_RCC_PLLI2SM_DIV_24

#define LL_RCC_PLLI2SM_DIV_25

#define LL_RCC_PLLI2SM_DIV_26

#define LL_RCC_PLLI2SM_DIV_27

#define LL_RCC_PLLI2SM_DIV_28

#define LL_RCC_PLLI2SM_DIV_29

#define LL_RCC_PLLI2SM_DIV_30

#define LL_RCC_PLLI2SM_DIV_31

#define LL_RCC_PLLI2SM_DIV_32

#define LL_RCC_PLLI2SM_DIV_33

#define LL_RCC_PLLI2SM_DIV_34

#define LL_RCC_PLLI2SM_DIV_35

#define LL_RCC_PLLI2SM_DIV_36

#define LL_RCC_PLLI2SM_DIV_37

#define LL_RCC_PLLI2SM_DIV_38

#define LL_RCC_PLLI2SM_DIV_39

#define LL_RCC_PLLI2SM_DIV_40

#define LL_RCC_PLLI2SM_DIV_41

#define LL_RCC_PLLI2SM_DIV_42

#define LL_RCC_PLLI2SM_DIV_43

#define LL_RCC_PLLI2SM_DIV_44

#define LL_RCC_PLLI2SM_DIV_45

#define LL_RCC_PLLI2SM_DIV_46

#define LL_RCC_PLLI2SM_DIV_47

#define LL_RCC_PLLI2SM_DIV_48

#define LL_RCC_PLLI2SM_DIV_49

#define LL_RCC_PLLI2SM_DIV_50

#define LL_RCC_PLLI2SM_DIV_51

#define LL_RCC_PLLI2SM_DIV_52

#define LL_RCC_PLLI2SM_DIV_53

#define LL_RCC_PLLI2SM_DIV_54

#define LL_RCC_PLLI2SM_DIV_55

#define LL_RCC_PLLI2SM_DIV_56

#define LL_RCC_PLLI2SM_DIV_57

#define LL_RCC_PLLI2SM_DIV_58

#define LL_RCC_PLLI2SM_DIV_59

#define LL_RCC_PLLI2SM_DIV_60

#define LL_RCC_PLLI2SM_DIV_61

#define LL_RCC_PLLI2SM_DIV_62

#define LL_RCC_PLLI2SM_DIV_63

#define LL_RCC_PLLI2SM_DIV_2

#define LL_RCC_PLLI2SM_DIV_3

#define LL_RCC_PLLI2SM_DIV_4

#define LL_RCC_PLLI2SM_DIV_5

#define LL_RCC_PLLI2SM_DIV_6

#define LL_RCC_PLLI2SM_DIV_7

#define LL_RCC_PLLI2SM_DIV_8

#define LL_RCC_PLLI2SM_DIV_9

#define LL_RCC_PLLI2SM_DIV_10

#define LL_RCC_PLLI2SM_DIV_11

#define LL_RCC_PLLI2SM_DIV_12

#define LL_RCC_PLLI2SM_DIV_13

#define LL_RCC_PLLI2SM_DIV_14

#define LL_RCC_PLLI2SM_DIV_15

#define LL_RCC_PLLI2SM_DIV_16

#define LL_RCC_PLLI2SM_DIV_17

#define LL_RCC_PLLI2SM_DIV_18

#define LL_RCC_PLLI2SM_DIV_19

#define LL_RCC_PLLI2SM_DIV_20

#define LL_RCC_PLLI2SM_DIV_21

#define LL_RCC_PLLI2SM_DIV_22

#define LL_RCC_PLLI2SM_DIV_23

#define LL_RCC_PLLI2SM_DIV_24

#define LL_RCC_PLLI2SM_DIV_25

#define LL_RCC_PLLI2SM_DIV_26

#define LL_RCC_PLLI2SM_DIV_27

#define LL_RCC_PLLI2SM_DIV_28

#define LL_RCC_PLLI2SM_DIV_29

#define LL_RCC_PLLI2SM_DIV_30

#define LL_RCC_PLLI2SM_DIV_31

#define LL_RCC_PLLI2SM_DIV_32

#define LL_RCC_PLLI2SM_DIV_33

#define LL_RCC_PLLI2SM_DIV_34

#define LL_RCC_PLLI2SM_DIV_35

#define LL_RCC_PLLI2SM_DIV_36

#define LL_RCC_PLLI2SM_DIV_37

#define LL_RCC_PLLI2SM_DIV_38

#define LL_RCC_PLLI2SM_DIV_39

#define LL_RCC_PLLI2SM_DIV_40

#define LL_RCC_PLLI2SM_DIV_41

#define LL_RCC_PLLI2SM_DIV_42

#define LL_RCC_PLLI2SM_DIV_43

#define LL_RCC_PLLI2SM_DIV_44

#define LL_RCC_PLLI2SM_DIV_45

#define LL_RCC_PLLI2SM_DIV_46

#define LL_RCC_PLLI2SM_DIV_47

#define LL_RCC_PLLI2SM_DIV_48

#define LL_RCC_PLLI2SM_DIV_49

#define LL_RCC_PLLI2SM_DIV_50

#define LL_RCC_PLLI2SM_DIV_51

#define LL_RCC_PLLI2SM_DIV_52

#define LL_RCC_PLLI2SM_DIV_53

#define LL_RCC_PLLI2SM_DIV_54

#define LL_RCC_PLLI2SM_DIV_55

#define LL_RCC_PLLI2SM_DIV_56

#define LL_RCC_PLLI2SM_DIV_57

#define LL_RCC_PLLI2SM_DIV_58

#define LL_RCC_PLLI2SM_DIV_59

#define LL_RCC_PLLI2SM_DIV_60

#define LL_RCC_PLLI2SM_DIV_61

#define LL_RCC_PLLI2SM_DIV_62

#define LL_RCC_PLLI2SM_DIV_63

#define LL_RCC_PLLI2SQ_DIV_2

#define LL_RCC_PLLI2SQ_DIV_3

#define LL_RCC_PLLI2SQ_DIV_4

#define LL_RCC_PLLI2SQ_DIV_5

#define LL_RCC_PLLI2SQ_DIV_6

#define LL_RCC_PLLI2SQ_DIV_7

#define LL_RCC_PLLI2SQ_DIV_8

#define LL_RCC_PLLI2SQ_DIV_9

#define LL_RCC_PLLI2SQ_DIV_10

#define LL_RCC_PLLI2SQ_DIV_11

#define LL_RCC_PLLI2SQ_DIV_12

#define LL_RCC_PLLI2SQ_DIV_13

#define LL_RCC_PLLI2SQ_DIV_14

#define LL_RCC_PLLI2SQ_DIV_15

#define LL_RCC_PLLI2SDIVQ_DIV_1

#define LL_RCC_PLLI2SDIVQ_DIV_2

#define LL_RCC_PLLI2SDIVQ_DIV_3

#define LL_RCC_PLLI2SDIVQ_DIV_4

#define LL_RCC_PLLI2SDIVQ_DIV_5

#define LL_RCC_PLLI2SDIVQ_DIV_6

#define LL_RCC_PLLI2SDIVQ_DIV_7

#define LL_RCC_PLLI2SDIVQ_DIV_8

#define LL_RCC_PLLI2SDIVQ_DIV_9

#define LL_RCC_PLLI2SDIVQ_DIV_10

#define LL_RCC_PLLI2SDIVQ_DIV_11

#define LL_RCC_PLLI2SDIVQ_DIV_12

#define LL_RCC_PLLI2SDIVQ_DIV_13

#define LL_RCC_PLLI2SDIVQ_DIV_14

#define LL_RCC_PLLI2SDIVQ_DIV_15

#define LL_RCC_PLLI2SDIVQ_DIV_16

#define LL_RCC_PLLI2SDIVQ_DIV_17

#define LL_RCC_PLLI2SDIVQ_DIV_18

#define LL_RCC_PLLI2SDIVQ_DIV_19

#define LL_RCC_PLLI2SDIVQ_DIV_20

#define LL_RCC_PLLI2SDIVQ_DIV_21

#define LL_RCC_PLLI2SDIVQ_DIV_22

#define LL_RCC_PLLI2SDIVQ_DIV_23

#define LL_RCC_PLLI2SDIVQ_DIV_24

#define LL_RCC_PLLI2SDIVQ_DIV_25

#define LL_RCC_PLLI2SDIVQ_DIV_26

#define LL_RCC_PLLI2SDIVQ_DIV_27

#define LL_RCC_PLLI2SDIVQ_DIV_28

#define LL_RCC_PLLI2SDIVQ_DIV_29

#define LL_RCC_PLLI2SDIVQ_DIV_30

#define LL_RCC_PLLI2SDIVQ_DIV_31

#define LL_RCC_PLLI2SDIVQ_DIV_32

#define LL_RCC_PLLI2SDIVR_DIV_1

#define LL_RCC_PLLI2SDIVR_DIV_2

#define LL_RCC_PLLI2SDIVR_DIV_3

#define LL_RCC_PLLI2SDIVR_DIV_4

#define LL_RCC_PLLI2SDIVR_DIV_5

#define LL_RCC_PLLI2SDIVR_DIV_6

#define LL_RCC_PLLI2SDIVR_DIV_7

#define LL_RCC_PLLI2SDIVR_DIV_8

#define LL_RCC_PLLI2SDIVR_DIV_9

#define LL_RCC_PLLI2SDIVR_DIV_10

#define LL_RCC_PLLI2SDIVR_DIV_11

#define LL_RCC_PLLI2SDIVR_DIV_12

#define LL_RCC_PLLI2SDIVR_DIV_13

#define LL_RCC_PLLI2SDIVR_DIV_14

#define LL_RCC_PLLI2SDIVR_DIV_15

#define LL_RCC_PLLI2SDIVR_DIV_16

#define LL_RCC_PLLI2SDIVR_DIV_17

#define LL_RCC_PLLI2SDIVR_DIV_18

#define LL_RCC_PLLI2SDIVR_DIV_19

#define LL_RCC_PLLI2SDIVR_DIV_20

#define LL_RCC_PLLI2SDIVR_DIV_21

#define LL_RCC_PLLI2SDIVR_DIV_22

#define LL_RCC_PLLI2SDIVR_DIV_23

#define LL_RCC_PLLI2SDIVR_DIV_24

#define LL_RCC_PLLI2SDIVR_DIV_25

#define LL_RCC_PLLI2SDIVR_DIV_26

#define LL_RCC_PLLI2SDIVR_DIV_27

#define LL_RCC_PLLI2SDIVR_DIV_28

#define LL_RCC_PLLI2SDIVR_DIV_29

#define LL_RCC_PLLI2SDIVR_DIV_30

#define LL_RCC_PLLI2SDIVR_DIV_31

#define LL_RCC_PLLI2SR_DIV_2

#define LL_RCC_PLLI2SR_DIV_3

#define LL_RCC_PLLI2SR_DIV_4

#define LL_RCC_PLLI2SR_DIV_5

#define LL_RCC_PLLI2SR_DIV_6

#define LL_RCC_PLLI2SR_DIV_7

#define LL_RCC_PLLI2SP_DIV_2

#define LL_RCC_PLLI2SP_DIV_4

#define LL_RCC_PLLI2SP_DIV_6

#define LL_RCC_PLLI2SP_DIV_8

#define LL_RCC_PLLSAIM_DIV_2

#define LL_RCC_PLLSAIM_DIV_3

#define LL_RCC_PLLSAIM_DIV_4

#define LL_RCC_PLLSAIM_DIV_5

#define LL_RCC_PLLSAIM_DIV_6

#define LL_RCC_PLLSAIM_DIV_7

#define LL_RCC_PLLSAIM_DIV_8

#define LL_RCC_PLLSAIM_DIV_9

#define LL_RCC_PLLSAIM_DIV_10

#define LL_RCC_PLLSAIM_DIV_11

#define LL_RCC_PLLSAIM_DIV_12

#define LL_RCC_PLLSAIM_DIV_13

#define LL_RCC_PLLSAIM_DIV_14

#define LL_RCC_PLLSAIM_DIV_15

#define LL_RCC_PLLSAIM_DIV_16

#define LL_RCC_PLLSAIM_DIV_17

#define LL_RCC_PLLSAIM_DIV_18

#define LL_RCC_PLLSAIM_DIV_19

#define LL_RCC_PLLSAIM_DIV_20

#define LL_RCC_PLLSAIM_DIV_21

#define LL_RCC_PLLSAIM_DIV_22

#define LL_RCC_PLLSAIM_DIV_23

#define LL_RCC_PLLSAIM_DIV_24

#define LL_RCC_PLLSAIM_DIV_25

#define LL_RCC_PLLSAIM_DIV_26

#define LL_RCC_PLLSAIM_DIV_27

#define LL_RCC_PLLSAIM_DIV_28

#define LL_RCC_PLLSAIM_DIV_29

#define LL_RCC_PLLSAIM_DIV_30

#define LL_RCC_PLLSAIM_DIV_31

#define LL_RCC_PLLSAIM_DIV_32

#define LL_RCC_PLLSAIM_DIV_33

#define LL_RCC_PLLSAIM_DIV_34

#define LL_RCC_PLLSAIM_DIV_35

#define LL_RCC_PLLSAIM_DIV_36

#define LL_RCC_PLLSAIM_DIV_37

#define LL_RCC_PLLSAIM_DIV_38

#define LL_RCC_PLLSAIM_DIV_39

#define LL_RCC_PLLSAIM_DIV_40

#define LL_RCC_PLLSAIM_DIV_41

#define LL_RCC_PLLSAIM_DIV_42

#define LL_RCC_PLLSAIM_DIV_43

#define LL_RCC_PLLSAIM_DIV_44

#define LL_RCC_PLLSAIM_DIV_45

#define LL_RCC_PLLSAIM_DIV_46

#define LL_RCC_PLLSAIM_DIV_47

#define LL_RCC_PLLSAIM_DIV_48

#define LL_RCC_PLLSAIM_DIV_49

#define LL_RCC_PLLSAIM_DIV_50

#define LL_RCC_PLLSAIM_DIV_51

#define LL_RCC_PLLSAIM_DIV_52

#define LL_RCC_PLLSAIM_DIV_53

#define LL_RCC_PLLSAIM_DIV_54

#define LL_RCC_PLLSAIM_DIV_55

#define LL_RCC_PLLSAIM_DIV_56

#define LL_RCC_PLLSAIM_DIV_57

#define LL_RCC_PLLSAIM_DIV_58

#define LL_RCC_PLLSAIM_DIV_59

#define LL_RCC_PLLSAIM_DIV_60

#define LL_RCC_PLLSAIM_DIV_61

#define LL_RCC_PLLSAIM_DIV_62

#define LL_RCC_PLLSAIM_DIV_63

#define LL_RCC_PLLSAIM_DIV_2

#define LL_RCC_PLLSAIM_DIV_3

#define LL_RCC_PLLSAIM_DIV_4

#define LL_RCC_PLLSAIM_DIV_5

#define LL_RCC_PLLSAIM_DIV_6

#define LL_RCC_PLLSAIM_DIV_7

#define LL_RCC_PLLSAIM_DIV_8

#define LL_RCC_PLLSAIM_DIV_9

#define LL_RCC_PLLSAIM_DIV_10

#define LL_RCC_PLLSAIM_DIV_11

#define LL_RCC_PLLSAIM_DIV_12

#define LL_RCC_PLLSAIM_DIV_13

#define LL_RCC_PLLSAIM_DIV_14

#define LL_RCC_PLLSAIM_DIV_15

#define LL_RCC_PLLSAIM_DIV_16

#define LL_RCC_PLLSAIM_DIV_17

#define LL_RCC_PLLSAIM_DIV_18

#define LL_RCC_PLLSAIM_DIV_19

#define LL_RCC_PLLSAIM_DIV_20

#define LL_RCC_PLLSAIM_DIV_21

#define LL_RCC_PLLSAIM_DIV_22

#define LL_RCC_PLLSAIM_DIV_23

#define LL_RCC_PLLSAIM_DIV_24

#define LL_RCC_PLLSAIM_DIV_25

#define LL_RCC_PLLSAIM_DIV_26

#define LL_RCC_PLLSAIM_DIV_27

#define LL_RCC_PLLSAIM_DIV_28

#define LL_RCC_PLLSAIM_DIV_29

#define LL_RCC_PLLSAIM_DIV_30

#define LL_RCC_PLLSAIM_DIV_31

#define LL_RCC_PLLSAIM_DIV_32

#define LL_RCC_PLLSAIM_DIV_33

#define LL_RCC_PLLSAIM_DIV_34

#define LL_RCC_PLLSAIM_DIV_35

#define LL_RCC_PLLSAIM_DIV_36

#define LL_RCC_PLLSAIM_DIV_37

#define LL_RCC_PLLSAIM_DIV_38

#define LL_RCC_PLLSAIM_DIV_39

#define LL_RCC_PLLSAIM_DIV_40

#define LL_RCC_PLLSAIM_DIV_41

#define LL_RCC_PLLSAIM_DIV_42

#define LL_RCC_PLLSAIM_DIV_43

#define LL_RCC_PLLSAIM_DIV_44

#define LL_RCC_PLLSAIM_DIV_45

#define LL_RCC_PLLSAIM_DIV_46

#define LL_RCC_PLLSAIM_DIV_47

#define LL_RCC_PLLSAIM_DIV_48

#define LL_RCC_PLLSAIM_DIV_49

#define LL_RCC_PLLSAIM_DIV_50

#define LL_RCC_PLLSAIM_DIV_51

#define LL_RCC_PLLSAIM_DIV_52

#define LL_RCC_PLLSAIM_DIV_53

#define LL_RCC_PLLSAIM_DIV_54

#define LL_RCC_PLLSAIM_DIV_55

#define LL_RCC_PLLSAIM_DIV_56

#define LL_RCC_PLLSAIM_DIV_57

#define LL_RCC_PLLSAIM_DIV_58

#define LL_RCC_PLLSAIM_DIV_59

#define LL_RCC_PLLSAIM_DIV_60

#define LL_RCC_PLLSAIM_DIV_61

#define LL_RCC_PLLSAIM_DIV_62

#define LL_RCC_PLLSAIM_DIV_63

#define LL_RCC_PLLSAIQ_DIV_2

#define LL_RCC_PLLSAIQ_DIV_3

#define LL_RCC_PLLSAIQ_DIV_4

#define LL_RCC_PLLSAIQ_DIV_5

#define LL_RCC_PLLSAIQ_DIV_6

#define LL_RCC_PLLSAIQ_DIV_7

#define LL_RCC_PLLSAIQ_DIV_8

#define LL_RCC_PLLSAIQ_DIV_9

#define LL_RCC_PLLSAIQ_DIV_10

#define LL_RCC_PLLSAIQ_DIV_11

#define LL_RCC_PLLSAIQ_DIV_12

#define LL_RCC_PLLSAIQ_DIV_13

#define LL_RCC_PLLSAIQ_DIV_14

#define LL_RCC_PLLSAIQ_DIV_15

#define LL_RCC_PLLSAIDIVQ_DIV_1

#define LL_RCC_PLLSAIDIVQ_DIV_2

#define LL_RCC_PLLSAIDIVQ_DIV_3

#define LL_RCC_PLLSAIDIVQ_DIV_4

#define LL_RCC_PLLSAIDIVQ_DIV_5

#define LL_RCC_PLLSAIDIVQ_DIV_6

#define LL_RCC_PLLSAIDIVQ_DIV_7

#define LL_RCC_PLLSAIDIVQ_DIV_8

#define LL_RCC_PLLSAIDIVQ_DIV_9

#define LL_RCC_PLLSAIDIVQ_DIV_10

#define LL_RCC_PLLSAIDIVQ_DIV_11

#define LL_RCC_PLLSAIDIVQ_DIV_12

#define LL_RCC_PLLSAIDIVQ_DIV_13

#define LL_RCC_PLLSAIDIVQ_DIV_14

#define LL_RCC_PLLSAIDIVQ_DIV_15

#define LL_RCC_PLLSAIDIVQ_DIV_16

#define LL_RCC_PLLSAIDIVQ_DIV_17

#define LL_RCC_PLLSAIDIVQ_DIV_18

#define LL_RCC_PLLSAIDIVQ_DIV_19

#define LL_RCC_PLLSAIDIVQ_DIV_20

#define LL_RCC_PLLSAIDIVQ_DIV_21

#define LL_RCC_PLLSAIDIVQ_DIV_22

#define LL_RCC_PLLSAIDIVQ_DIV_23

#define LL_RCC_PLLSAIDIVQ_DIV_24

#define LL_RCC_PLLSAIDIVQ_DIV_25

#define LL_RCC_PLLSAIDIVQ_DIV_26

#define LL_RCC_PLLSAIDIVQ_DIV_27

#define LL_RCC_PLLSAIDIVQ_DIV_28

#define LL_RCC_PLLSAIDIVQ_DIV_29

#define LL_RCC_PLLSAIDIVQ_DIV_30

#define LL_RCC_PLLSAIDIVQ_DIV_31

#define LL_RCC_PLLSAIDIVQ_DIV_32

#define LL_RCC_PLLSAIR_DIV_2

#define LL_RCC_PLLSAIR_DIV_3

#define LL_RCC_PLLSAIR_DIV_4

#define LL_RCC_PLLSAIR_DIV_5

#define LL_RCC_PLLSAIR_DIV_6

#define LL_RCC_PLLSAIR_DIV_7

#define LL_RCC_PLLSAIDIVR_DIV_2

#define LL_RCC_PLLSAIDIVR_DIV_4

#define LL_RCC_PLLSAIDIVR_DIV_8

#define LL_RCC_PLLSAIDIVR_DIV_16

#define LL_RCC_PLLSAIP_DIV_2

#define LL_RCC_PLLSAIP_DIV_4

#define LL_RCC_PLLSAIP_DIV_6

#define LL_RCC_PLLSAIP_DIV_8

Exported macro

#define LL_RCC_WriteReg

#define LL_RCC_ReadReg

#define __LL_RCC_CALC_HCLK_FREQ

#define __LL_RCC_CALC_PCLK1_FREQ

#define __LL_RCC_CALC_PCLK2_FREQ

LL_RCC_HSE_EnableCSS()

LL_RCC_HSE_EnableBypass()

LL_RCC_HSE_DisableBypass()

LL_RCC_HSE_Enable()

LL_RCC_HSE_Disable()

LL_RCC_HSE_IsReady()

LL_RCC_HSI_Enable()

LL_RCC_HSI_Disable()

LL_RCC_HSI_IsReady()

LL_RCC_HSI_GetCalibration()

LL_RCC_HSI_SetCalibTrimming(uint32_t)

LL_RCC_HSI_GetCalibTrimming()

LL_RCC_LSE_Enable()

LL_RCC_LSE_Disable()

LL_RCC_LSE_EnableBypass()

LL_RCC_LSE_DisableBypass()

LL_RCC_LSE_IsReady()

LL_RCC_LSE_EnableHighDriveMode()

LL_RCC_LSE_DisableHighDriveMode()

LL_RCC_LSI_Enable()

LL_RCC_LSI_Disable()

LL_RCC_LSI_IsReady()

LL_RCC_SetSysClkSource(uint32_t)

LL_RCC_GetSysClkSource()

LL_RCC_SetAHBPrescaler(uint32_t)

LL_RCC_SetAPB1Prescaler(uint32_t)

LL_RCC_SetAPB2Prescaler(uint32_t)

LL_RCC_GetAHBPrescaler()

LL_RCC_GetAPB1Prescaler()

LL_RCC_GetAPB2Prescaler()

LL_RCC_MCO1_Enable()

LL_RCC_MCO1_Disable()

LL_RCC_ConfigMCO(uint32_t, uint32_t)

LL_RCC_SetFMPI2CClockSource(uint32_t)

LL_RCC_SetLPTIMClockSource(uint32_t)

LL_RCC_SetI2SClockSource(uint32_t)

LL_RCC_GetFMPI2CClockSource(uint32_t)

LL_RCC_GetLPTIMClockSource(uint32_t)

LL_RCC_GetI2SClockSource(uint32_t)

LL_RCC_SetRTCClockSource(uint32_t)

LL_RCC_GetRTCClockSource()

LL_RCC_EnableRTC()

LL_RCC_DisableRTC()

LL_RCC_IsEnabledRTC()

LL_RCC_ForceBackupDomainReset()

LL_RCC_ReleaseBackupDomainReset()

LL_RCC_SetRTC_HSEPrescaler(uint32_t)

LL_RCC_GetRTC_HSEPrescaler()

LL_RCC_SetTIMPrescaler(uint32_t)

LL_RCC_GetTIMPrescaler()

LL_RCC_PLL_Enable()

LL_RCC_PLL_Disable()

LL_RCC_PLL_IsReady()

LL_RCC_PLL_ConfigDomain_SYS(uint32_t, uint32_t, uint32_t, uint32_t)

LL_RCC_PLL_ConfigDomain_48M(uint32_t, uint32_t, uint32_t, uint32_t)

LL_RCC_PLL_ConfigDomain_I2S(uint32_t, uint32_t, uint32_t, uint32_t)

LL_RCC_PLL_SetMainSource(uint32_t)

LL_RCC_PLL_GetMainSource()

LL_RCC_PLL_GetN()

LL_RCC_PLL_GetP()

LL_RCC_PLL_GetQ()

LL_RCC_PLL_GetR()

LL_RCC_PLL_GetDivider()

LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t, uint32_t, uint32_t)

LL_RCC_PLL_GetPeriodModulation()

LL_RCC_PLL_GetStepIncrementation()

LL_RCC_PLL_GetSpreadSelection()

LL_RCC_PLL_SpreadSpectrum_Enable()

LL_RCC_PLL_SpreadSpectrum_Disable()

LL_RCC_ClearFlag_LSIRDY()

LL_RCC_ClearFlag_LSERDY()

LL_RCC_ClearFlag_HSIRDY()

LL_RCC_ClearFlag_HSERDY()

LL_RCC_ClearFlag_PLLRDY()

LL_RCC_ClearFlag_HSECSS()

LL_RCC_IsActiveFlag_LSIRDY()

LL_RCC_IsActiveFlag_LSERDY()

LL_RCC_IsActiveFlag_HSIRDY()

LL_RCC_IsActiveFlag_HSERDY()

LL_RCC_IsActiveFlag_PLLRDY()

LL_RCC_IsActiveFlag_HSECSS()

LL_RCC_IsActiveFlag_IWDGRST()

LL_RCC_IsActiveFlag_LPWRRST()

LL_RCC_IsActiveFlag_PINRST()

LL_RCC_IsActiveFlag_PORRST()

LL_RCC_IsActiveFlag_SFTRST()

LL_RCC_IsActiveFlag_WWDGRST()

LL_RCC_IsActiveFlag_BORRST()

LL_RCC_ClearResetFlags()

LL_RCC_EnableIT_LSIRDY()

LL_RCC_EnableIT_LSERDY()

LL_RCC_EnableIT_HSIRDY()

LL_RCC_EnableIT_HSERDY()

LL_RCC_EnableIT_PLLRDY()

LL_RCC_DisableIT_LSIRDY()

LL_RCC_DisableIT_LSERDY()

LL_RCC_DisableIT_HSIRDY()

LL_RCC_DisableIT_HSERDY()

LL_RCC_DisableIT_PLLRDY()

LL_RCC_IsEnabledIT_LSIRDY()

LL_RCC_IsEnabledIT_LSERDY()

LL_RCC_IsEnabledIT_HSIRDY()

LL_RCC_IsEnabledIT_HSERDY()

LL_RCC_IsEnabledIT_PLLRDY()

LL_RCC_DeInit();

LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *);

LL_RCC_GetFMPI2CClockFreq(uint32_t);

LL_RCC_GetLPTIMClockFreq(uint32_t);

LL_RCC_GetRNGClockFreq(uint32_t);

LL_RCC_GetI2SClockFreq(uint32_t);

Files

SourceVuSTM32 Libraries and SamplesHALInc/stm32f4xx_ll_rcc.h

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

357

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

452

453

454

455

456

457

458

459

460

461

462

463

464

465

466

467

468

469

470

471

472

473

474

475

476

477

478

479

480

481

482

483

484

485

486

487

488

489

490

491

492

493

494

495

496

497

498

499

500

501

502

503

504

505

506

507

508

509

510

511

512

513

514

515

516

517

518

519

520

521

522

523

524

525

526

527

528

529

530

531

532

533

534

535

536

537

538

539

540

541

542

543

544

545

546

547

548

549

550

551

552

553

554

555

556

557

558

559

560

561

562

563

564

565

566

567

568

569

570

571

572

573

574

575

576

577

578

579

580

581

582

583

584

585

586

587

588

589

590

591

592

593

594

595

596

597

598

599

600

601

602

603

604

605

606

607

608

609

610

611

612

613

614

615

616

617

618

619

620

621

622

623

624

625

626

627

628

629

630

631

632

633

634

635

636

637

638

639

640

641

642

643

644

645

646

647

648

649

650

651

652

653

654

655

656

657

658

659

660

661

662

663

664

665

666

667

668

669

670

671

672

673

674

675

676

677

678

679

680

681

682

683

684

685

686

687

688

689

690

691

692

693

694

695

696

697

698

699

700

701

702

703

704

705

706

707

708

709

710

711

712

713

714

715

716

717

718

719

720

721

722

723

724

725

726

727

728

729

730

731

732

733

734

735

736

737

738

739

740

741

742

743

744

745

746

747

748

749

750

751

752

753

754

755

756

757

758

759

760

761

762

763

764

765

766

767

768

769

770

771

772

773

774

775

776

777

778

779

780

781

782

783

784

785

786

787

788

789

790

791

792

793

794

795

796

797

798

799

800

801

802

803

804

805

806

807

808

809

810

811

812

813

814

815

816

817

818

819

820

821

822

823

824

825

826

827

828

829

830

831

832

833

834

835

836

837

838

839

840

841

842

843

844

845

846

847

848

849

850

851

852

853

854

855

856

857

858

859

860

861

862

863

864

865

866

867

868

869

870

871

872

873

874

875

876

877

878

879

880

881

882

883

884

885

886

887

888

889

890

891

892

893

894

895

896

897

898

899

900

901

902

903

904

905

906

907

908

909

910

911

912

913

914

915

916

917

918

919

920

921

922

923

924

925

926

927

928

929

930

931

932

933

934

935

936

937

938

939

940

941

942

943

944

945

946

947

948

949

950

951

952

953

954

955

956

957

958

959

960

961

962

963

964

965

966

967

968

969

970

971

972

973

974

975

976

977

978

979

980

981

982

983

984

985

986

987

988

989

990

991

992

993

994

995

996

997

998

999

1000

1001

1002

1003

1004

1005

1006

1007

1008

1009

1010

1011

1012

1013

1014

1015

1016

1017

1018

1019

1020

1021

1022

1023

1024

1025

1026

1027

1028

1029

1030

1031

1032

1033

1034

1035

1036

1037

1038

1039

1040

1041

1042

1043

1044

1045

1046

1047

1048

1049

1050

1051

1052

1053

1054

1055

1056

1057

1058

1059

1060

1061

1062

1063

1064

1065

1066

1067

1068

1069

1070

1071

1072

1073

1074

1075

1076

1077

1078

1079

1080

1081

1082

1083

1084

1085

1086

1087

1088

1089

1090

1091

1092

1093

1094

1095

1096

1097

1098

1099

1100

1101

1102

1103

1104

1105

1106

1107

1108

1109

1110

1111

1112

1113

1114

1115

1116

1117

1118

1119

1120

1121

1122

1123

1124

1125

1126

1127

1128

1129

1130

1131

1132

1133

1134

1135

1136

1137

1138

1139

1140

1141

1142

1143

1144

1145

1146

1147

1148

1149

1150

1151

1152

1153

1154

1155

1156

1157

1158

1159

1160

1161

1162

1163

1164

1165

1166

1167

1168

1169

1170

1171

1172

1173

1174

1175

1176

1177

1178

1179

1180

1181

1182

1183

1184

1185

1186

1187

1188

1189

1190

1191

1192

1193

1194

1195

1196

1197

1198

1199

1200

1201

1202

1203

1204

1205

1206

1207

1208

1209

1210

1211

1212

1213

1214

1215

1216

1217

1218

1219

1220

1221

1222

1223

1224

1225

1226

1227

1228

1229

1230

1231

1232

1233

1234

1235

1236

1237

1238

1239

1240

1241

1242

1243

1244

1245

1246

1247

1248

1249

1250

1251

1252

1253

1254

1255

1256

1257

1258

1259

1260

1261

1262

1263

1264

1265

1266

1267

1268

1269

1270

1271

1272

1273

1274

1275

1276

1277

1278

1279

1280

1281

1282

1283

1284

1285

1286

1287

1288

1289

1290

1291

1292

1293

1294

1295

1296

1297

1298

1299

1300

1301

1302

1303

1304

1305

1306

1307

1308

1309

1310

1311

1312

1313

1314

1315

1316

1317

1318

1319

1320

1321

1322

1323

1324

1325

1326

1327

1328

1329

1330

1331

1332

1333

1334

1335

1336

1337

1338

1339

1340

1341

1342

1343

1344

1345

1346

1347

1348

1349

1350

1351

1352

1353

1354

1355

1356

1357

1358

1359

1360

1361

1362

1363

1364

1365

1366

1367

1368

1369

1370

1371

1372

1373

1374

1375

1376

1377

1378

1379

1380

1381

1382

1383

1384

1385

1386

1387

1388

1389

1390

1391

1392

1393

1394

1395

1396

1397

1398

1399

1400

1401

1402

1403

1404

1405

1406

1407

1408

1409

1410

1411

1412

1413

1414

1415

1416

1417

1418

1419

1420

1421

1422

1423

1424

1425

1426

1427

1428

1429

1430

1431

1432

1433

1434

1435

1436

1437

1438

1439

1440

1441

1442

1443

1444

1445

1446

1447

1448

1449

1450

1451

1452

1453

1454

1455

1456

1457

1458

1459

1460

1461

1462

1463

1464

1465

1466

1467

1468

1469

1470

1471

1472

1473

1474

1475

1476

1477

1478

1479

1480

1481

1482

1483

1484

1485

1486

1487

1488

1489

1490

1491

1492

1493

1494

1495

1496

1497

1498

1499

1500

1501

1502

1503

1504

1505

1506

1507

1508

1509

1510

1511

1512

1513

1514

1515

1516

1517

1518

1519

1520

1521

1522

1523

1524

1525

1526

1527

1528

1529

1530

1531

1532

1533

1534

1535

1536

1537

1538

1539

1540

1541

1542

1543

1544

1545

1546

1547

1548

1549

1550

1551

1552

1553

1554

1555

1556

1557

1558

1559

1560

1561

1562

1563

1564

1565

1566

1567

1568

1569

1570

1571

1572

1573

1574

1575

1576

1577

1578

1579

1580

1581

1582

1583

1584

1585

1586

1587

1588

1589

1590

1591

1592

1593

1594

1595

1596

1597

1598

1599

1600

1601

1602

1603

1604

1605

1606

1607

1608

1609

1610

1611

1612

1613

1614

1615

1616

1617

1618

1619

1620

1621

1622

1623

1624

1625

1626

1627

1628

1629

1630

1631

1632

1633

1634

1635

1636

1637

1638

1639

1640

1641

1642

1643

1644

1645

1646

1647

1648

1649

1650

1651

1652

1653

1654

1655

1656

1657

1658

1659

1660

1661

1662

1663

1664

1665

1666

1667

1668

1669

1670

1671

1672

1673

1674

1675

1676

1677

1678

1679

1680

1681

1682

1683

1684

1685

1686

1687

1688

1689

1690

1691

1692

1693

1694

1695

1696

1697

1698

1699

1700

1701

1702

1703

1704

1705

1706

1707

1708

1709

1710

1711

1712

1713

1714

1715

1716

1717

1718

1719

1720

1721

1722

1723

1724

1725

1726

1727

1728

1729

1730

1731

1732

1733

1734

1735

1736

1737

1738

1739

1740

1741

1742

1743

1744

1745

1746

1747

1748

1749

1750

1751

1752

1753

1754

1755

1756

1757

1758

1759

1760

1761

1762

1763

1764

1765

1766

1767

1768

1769

1770

1771

1772

1773

1774

1775

1776

1777

1778

1779

1780

1781

1782

1783

1784

1785

1786

1787

1788

1789

1790

1791

1792

1793

1794

1795

1796

1797

1798

1799

1800

1801

1802

1803

1804

1805

1806

1807

1808

1809

1810

1811

1812

1813

1814

1815

1816

1817

1818

1819

1820

1821

1822

1823

1824

1825

1826

1827

1828

1829

1830

1831

1832

1833

1834

1835

1836

1837

1838

1839

1840

1841

1842

1843

1844

1845

1846

1847

1848

1849

1850

1851

1852

1853

1854

1855

1856

1857

1858

1859

1860

1861

1862

1863

1864

1865

1866

1867

1868

1869

1870

1871

1872

1873

1874

1875

1876

1877

1878

1879

1880

1881

1882

1883

1884

1885

1886

1887

1888

1889

1890

1891

1892

1893

1894

1895

1896

1897

1898

1899

1900

1901

1902

1903

1904

1905

1906

1907

1908

1909

1910

1911

1912

1913

1914

1915

1916

1917

1918

1919

1920

1921

1922

1923

1924

1925

1926

1927

1928

1929

1930

1931

1932

1933

1934

1935

1936

1937

1938

1939

1940

1941

1942

1943

1944

1945

1946

1947

1948

1949

1950

1951

1952

1953

1954

1955

1956

1957

1958

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

1976

1977

1978

1979

1980

1981

1982

1983

1984

1985

1986

1987

1988

1989

1990

1991

1992

1993

1994

1995

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

2016

2017

2018

2019

2020

2021

2022

2023

2024

2025

2026

2027

2028

2029

2030

2031

2032

2033

2034

2035

2036

2037

2038

2039

2040

2041

2042

2043

2044

2045

2046

2047

2048

2049

2050

2051

2052

2053

2054

2055

2056

2057

2058

2059

2060

2061

2062

2063

2064

2065

2066

2067

2068

2069

2070

2071

2072

2073

2074

2075

2076

2077

2078

2079

2080

2081

2082

2083

2084

2085

2086

2087

2088

2089

2090

2091

2092

2093

2094

2095

2096

2097

2098

2099

2100

2101

2102

2103

2104

2105

2106

2107

2108

2109

2110

2111

2112

2113

2114

2115

2116

2117

2118

2119

2120

2121

2122

2123

2124

2125

2126

2127

2128

2129

2130

2131

2132

2133

2134

2135

2136

2137

2138

2139

2140

2141

2142

2143

2144

2145

2146

2147

2148

2149

2150

2151

2152

2153

2154

2155

2156

2157

2158

2159

2160

2161

2162

2163

2164

2165

2166

2167

2168

2169

2170

2171

2172

2173

2174

2175

2176

2177

2178

2179

2180

2181

2182

2183

2184

2185

2186

2187

2188

2189

2190

2191

2192

2193

2194

2195

2196

2197

2198

2199

2200

2201

2202

2203

2204

2205

2206

2207

2208

2209

2210

2211

2212

2213

2214

2215

2216

2217

2218

2219

2220

2221

2222

2223

2224

2225

2226

2227

2228

2229

2230

2231

2232

2233

2234

2235

2236

2237

2238

2239

2240

2241

2242

2243

2244

2245

2246

2247

2248

2249

2250

2251

2252

2253

2254

2255

2256

2257

2258

2259

2260

2261

2262

2263

2264

2265

2266

2267

2268

2269

2270

2271

2272

2273

2274

2275

2276

2277

2278

2279

2280

2281

2282

2283

2284

2285

2286

2287

2288

2289

2290

2291

2292

2293

2294

2295

2296

2297

2298

2299

2300

2301

2302

2303

2304

2305

2306

2307

2308

2309

2310

2311

2312

2313

2314

2315

2316

2317

2318

2319

2320

2321

2322

2323

2324

2325

2326

2327

2328

2329

2330

2331

2332

2333

2334

2335

2336

2337

2338

2339

2340

2341

2342

2343

2344

2345

2346

2347

2348

2349

2350

2351

2352

2353

2354

2355

2356

2357

2358

2359

2360

2361

2362

2363

2364

2365

2366

2367

2368

2369

2370

2371

2372

2373

2374

2375

2376

2377

2378

2379

2380

2381

2382

2383

2384

2385

2386

2387

2388

2389

2390

2391

2392

2393

2394

2395

2396

2397

2398

2399

2400

2401

2402

2403

2404

2405

2406

2407

2408

2409

2410

2411

2412

2413

2414

2415

2416

2417

2418

2419

2420

2421

2422

2423

2424

2425

2426

2427

2428

2429

2430

2431

2432

2433

2434

2435

2436

2437

2438

2439

2440

2441

2442

2443

2444

2445

2446

2447

2448

2449

2450

2451

2452

2453

2454

2455

2456

2457

2458

2459

2460

2461

2462

2463

2464

2465

2466

2467

2468

2469

2470

2471

2472

2473

2474

2475

2476

2477

2478

2479

2480

2481

2482

2483

2484

2485

2486

2487

2488

2489

2490

2491

2492

2493

2494

2495

2496

2497

2498

2499

2500

2501

2502

2503

2504

2505

2506

2507

2508

2509

2510

2511

2512

2513

2514

2515

2516

2517

2518

2519

2520

2521

2522

2523

2524

2525

2526

2527

2528

2529

2530

2531

2532

2533

2534

2535

2536

2537

2538

2539

2540

2541

2542

2543

2544

2545

2546

2547

2548

2549

2550

2551

2552

2553

2554

2555

2556

2557

2558

2559

2560

2561

2562

2563

2564

2565

2566

2567

2568

2569

2570

2571

2572

2573

2574

2575

2576

2577

2578

2579

2580

2581

2582

2583

2584

2585

2586

2587

2588

2589

2590

2591

2592

2593

2594

2595

2596

2597

2598

2599

2600

2601

2602

2603

2604

2605

2606

2607

2608

2609

2610

2611

2612

2613

2614

2615

2616

2617

2618

2619

2620

2621

2622

2623

2624

2625

2626

2627

2628

2629

2630

2631

2632

2633

2634

2635

2636

2637

2638

2639

2640

2641

2642

2643

2644

2645

2646

2647

2648

2649

2650

2651

2652

2653

2654

2655

2656

2657

2658

2659

2660

2661

2662

2663

2664

2665

2666

2667

2668

2669

2670

2671

2672

2673

2674

2675

2676

2677

2678

2679

2680

2681

2682

2683

2684

2685

2686

2687

2688

2689

2690

2691

2692

2693

2694

2695

2696

2697

2698

2699

2700

2701

2702

2703

2704

2705

2706

2707

2708

2709

2710

2711

2712

2713

2714

2715

2716

2717

2718

2719

2720

2721

2722

2723

2724

2725

2726

2727

2728

2729

2730

2731

2732

2733

2734

2735

2736

2737

2738

2739

2740

2741

2742

2743

2744

2745

2746

2747

2748

2749

2750

2751

2752

2753

2754

2755

2756

2757

2758

2759

2760

2761

2762

2763

2764

2765

2766

2767

2768

2769

2770

2771

2772

2773

2774

2775

2776

2777

2778

2779

2780

2781

2782

2783

2784

2785

2786

2787

2788

2789

2790

2791

2792

2793

2794

2795

2796

2797

2798

2799

2800

2801

2802

2803

2804

2805

2806

2807

2808

2809

2810

2811

2812

2813

2814

2815

2816

2817

2818

2819

2820

2821

2822

2823

2824

2825

2826

2827

2828

2829

2830

2831

2832

2833

2834

2835

2836

2837

2838

2839

2840

2841

2842

2843

2844

2845

2846

2847

2848

2849

2850

2851

2852

2853

2854

2855

2856

2857

2858

2859

2860

2861

2862

2863

2864

2865

2866

2867

2868

2869

2870

2871

2872

2873

2874

2875

2876

2877

2878

2879

2880

2881

2882

2883

2884

2885

2886

2887

2888

2889

2890

2891

2892

2893

2894

2895

2896

2897

2898

2899

2900

2901

2902

2903

2904

2905

2906

2907

2908

2909

2910

2911

2912

2913

2914

2915

2916

2917

2918

2919

2920

2921

2922

2923

2924

2925

2926

2927

2928

2929

2930

2931

2932

2933

2934

2935

2936

2937

2938

2939

2940

2941

2942

2943

2944

2945

2946

2947

2948

2949

2950

2951

2952

2953

2954

2955

2956

2957

2958

2959

2960

2961

2962

2963

2964

2965

2966

2967

2968

2969

2970

2971

2972

2973

2974

2975

2976

2977

2978

2979

2980

2981

2982

2983

2984

2985

2986

2987

2988

2989

2990

2991

2992

2993

2994

2995

2996

2997

2998

2999

3000

3001

3002

3003

3004

3005

3006

3007

3008

3009

3010

3011

3012

3013

3014

3015

3016

3017

3018

3019

3020

3021

3022

3023

3024

3025

3026

3027

3028

3029

3030

3031

3032

3033

3034

3035

3036

3037

3038

3039

3040

3041

3042

3043

3044

3045

3046

3047

3048

3049

3050

3051

3052

3053

3054

3055

3056

3057

3058

3059

3060

3061

3062

3063

3064

3065

3066

3067

3068

3069

3070

3071

3072

3073

3074

3075

3076

3077

3078

3079

3080

3081

3082

3083

3084

3085

3086

3087

3088

3089

3090

3091

3092

3093

3094

3095

3096

3097

3098

3099

3100

3101

3102

3103

3104

3105

3106

3107

3108

3109

3110

3111

3112

3113

3114

3115

3116

3117

3118

3119

3120

3121

3122

3123

3124

3125

3126

3127

3128

3129

3130

3131

3132

3133

3134

3135

3136

3137

3138

3139

3140

3141

3142

3143

3144

3145

3146

3147

3148

3149

3150

3151

3152

3153

3154

3155

3156

3157

3158

3159

3160

3161

3162

3163

3164

3165

3166

3167

3168

3169

3170

3171

3172

3173

3174

3175

3176

3177

3178

3179

3180

3181

3182

3183

3184

3185

3186

3187

3188

3189

3190

3191

3192

3193

3194

3195

3196

3197

3198

3199

3200

3201

3202

3203

3204

3205

3206

3207

3208

3209

3210

3211

3212

3213

3214

3215

3216

3217

3218

3219

3220

3221

3222

3223

3224

3225

3226

3227

3228

3229

3230

3231

3232

3233

3234

3235

3236

3237

3238

3239

3240

3241

3242

3243

3244

3245

3246

3247

3248

3249

3250

3251

3252

3253

3254

3255

3256

3257

3258

3259

3260

3261

3262

3263

3264

3265

3266

3267

3268

3269

3270

3271

3272

3273

3274

3275

3276

3277

3278

3279

3280

3281

3282

3283

3284

3285

3286

3287

3288

3289

3290

3291

3292

3293

3294

3295

3296

3297

3298

3299

3300

3301

3302

3303

3304

3305

3306

3307

3308

3309

3310

3311

3312

3313

3314

3315

3316

3317

3318

3319

3320

3321

3322

3323

3324

3325

3326

3327

3328

3329

3330

3331

3332

3333

3334

3335

3336

3337

3338

3339

3340

3341

3342

3343

3344

3345

3346

3347

3348

3349

3350

3351

3352

3353

3354

3355

3356

3357

3358

3359

3360

3361

3362

3363

3364

3365

3366

3367

3368

3369

3370

3371

3372

3373

3374

3375

3376

3377

3378

3379

3380

3381

3382

3383

3384

3385

3386

3387

3388

3389

3390

3391

3392

3393

3394

3395

3396

3397

3398

3399

3400

3401

3402

3403

3404

3405

3406

3407

3408

3409

3410

3411

3412

3413

3414

3415

3416

3417

3418

3419

3420

3421

3422

3423

3424

3425

3426

3427

3428

3429

3430

3431

3432

3433

3434

3435

3436

3437

3438

3439

3440

3441

3442

3443

3444

3445

3446

3447

3448

3449

3450

3451

3452

3453

3454

3455

3456

3457

3458

3459

3460

3461

3462

3463

3464

3465

3466

3467

3468

3469

3470

3471

3472

3473

3474

3475

3476

3477

3478

3479

3480

3481

3482

3483

3484

3485

3486

3487

3488

3489

3490

3491

3492

3493

3494

3495

3496

3497

3498

3499

3500

3501

3502

3503

3504

3505

3506

3507

3508

3509

3510

3511

3512

3513

3514

3515

3516

3517

3518

3519

3520

3521

3522

3523

3524

3525

3526

3527

3528

3529

3530

3531

3532

3533

3534

3535

3536

3537

3538

3539

3540

3541

3542

3543

3544

3545

3546

3547

3548

3549

3550

3551

3552

3553

3554

3555

3556

3557

3558

3559

3560

3561

3562

3563

3564

3565

3566

3567

3568

3569

3570

3571

3572

3573

3574

3575

3576

3577

3578

3579

3580

3581

3582

3583

3584

3585

3586

3587

3588

3589

3590

3591

3592

3593

3594

3595

3596

3597

3598

3599

3600

3601

3602

3603

3604

3605

3606

3607

3608

3609

3610

3611

3612

3613

3614

3615

3616

3617

3618

3619

3620

3621

3622

3623

3624

3625

3626

3627

3628

3629

3630

3631

3632

3633

3634

3635

3636

3637

3638

3639

3640

3641

3642

3643

3644

3645

3646

3647

3648

3649

3650

3651

3652

3653

3654

3655

3656

3657

3658

3659

3660

3661

3662

3663

3664

3665

3666

3667

3668

3669

3670

3671

3672

3673

3674

3675

3676

3677

3678

3679

3680

3681

3682

3683

3684

3685

3686

3687

3688

3689

3690

3691

3692

3693

3694

3695

3696

3697

3698

3699

3700

3701

3702

3703

3704

3705

3706

3707

3708

3709

3710

3711

3712

3713

3714

3715

3716

3717

3718

3719

3720

3721

3722

3723

3724

3725

3726

3727

3728

3729

3730

3731

3732

3733

3734

3735

3736

3737

3738

3739

3740

3741

3742

3743

3744

3745

3746

3747

3748

3749

3750

3751

3752

3753

3754

3755

3756

3757

3758

3759

3760

3761

3762

3763

3764

3765

3766

3767

3768

3769

3770

3771

3772

3773

3774

3775

3776

3777

3778

3779

3780

3781

3782

3783

3784

3785

3786

3787

3788

3789

3790

3791

3792

3793

3794

3795

3796

3797

3798

3799

3800

3801

3802

3803

3804

3805

3806

3807

3808

3809

3810

3811

3812

3813

3814

3815

3816

3817

3818

3819

3820

3821

3822

3823

3824

3825

3826

3827

3828

3829

3830

3831

3832

3833

3834

3835

3836

3837

3838

3839

3840

3841

3842

3843

3844

3845

3846

3847

3848

3849

3850

3851

3852

3853

3854

3855

3856

3857

3858

3859

3860

3861

3862

3863

3864

3865

3866

3867

3868

3869

3870

3871

3872

3873

3874

3875

3876

3877

3878

3879

3880

3881

3882

3883

3884

3885

3886

3887

3888

3889

3890

3891

3892

3893

3894

3895

3896

3897

3898

3899

3900

3901

3902

3903

3904

3905

3906

3907

3908

3909

3910

3911

3912

3913

3914

3915

3916

3917

3918

3919

3920

3921

3922

3923

3924

3925

3926

3927

3928

3929

3930

3931

3932

3933

3934

3935

3936

3937

3938

3939

3940

3941

3942

3943

3944

3945

3946

3947

3948

3949

3950

3951

3952

3953

3954

3955

3956

3957

3958

3959

3960

3961

3962

3963

3964

3965

3966

3967

3968

3969

3970

3971

3972

3973

3974

3975

3976

3977

3978

3979

3980

3981

3982

3983

3984

3985

3986

3987

3988

3989

3990

3991

3992

3993

3994

3995

3996

3997

3998

3999

4000

4001

4002

4003

4004

4005

4006

4007

4008

4009

4010

4011

4012

4013

4014

4015

4016

4017

4018

4019

4020

4021

4022

4023

4024

4025

4026

4027

4028

4029

4030

4031

4032

4033

4034

4035

4036

4037

4038

4039

4040

4041

4042

4043

4044

4045

4046

4047

4048

4049

4050

4051

4052

4053

4054

4055

4056

4057

4058

4059

4060

4061

4062

4063

4064

4065

4066

4067

4068

4069

4070

4071

4072

4073

4074

4075

4076

4077

4078

4079

4080

4081

4082

4083

4084

4085

4086

4087

4088

4089

4090

4091

4092

4093

4094

4095

4096

4097

4098

4099

4100

4101

4102

4103

4104

4105

4106

4107

4108

4109

4110

4111

4112

4113

4114

4115

4116

4117

4118

4119

4120

4121

4122

4123

4124

4125

4126

4127

4128

4129

4130

4131

4132

4133

4134

4135

4136

4137

4138

4139

4140

4141

4142

4143

4144

4145

4146

4147

4148

4149

4150

4151

4152

4153

4154

4155

4156

4157

4158

4159

4160

4161

4162

4163

4164

4165

4166

4167

4168

4169

4170

4171

4172

4173

4174

4175

4176

4177

4178

4179

4180

4181

4182

4183

4184

4185

4186

4187

4188

4189

4190

4191

4192

4193

4194

4195

4196

4197

4198

4199

4200

4201

4202

4203

4204

4205

4206

4207

4208

4209

4210

4211

4212

4213

4214

4215

4216

4217

4218

4219

4220

4221

4222

4223

4224

4225

4226

4227

4228

4229

4230

4231

4232

4233

4234

4235

4236

4237

4238

4239

4240

4241

4242

4243

4244

4245

4246

4247

4248

4249

4250

4251

4252

4253

4254

4255

4256

4257

4258

4259

4260

4261

4262

4263

4264

4265

4266

4267

4268

4269

4270

4271

4272

4273

4274

4275

4276

4277

4278

4279

4280

4281

4282

4283

4284

4285

4286

4287

4288

4289

4290

4291

4292

4293

4294

4295

4296

4297

4298

4299

4300

4301

4302

4303

4304

4305

4306

4307

4308

4309

4310

4311

4312

4313

4314

4315

4316

4317

4318

4319

4320

4321

4322

4323

4324

4325

4326

4327

4328

4329

4330

4331

4332

4333

4334

4335

4336

4337

4338

4339

4340

4341

4342

4343

4344

4345

4346

4347

4348

4349

4350

4351

4352

4353

4354

4355

4356

4357

4358

4359

4360

4361

4362

4363

4364

4365

4366

4367

4368

4369

4370

4371

4372

4373

4374

4375

4376

4377

4378

4379

4380

4381

4382

4383

4384

4385

4386

4387

4388

4389

4390

4391

4392

4393

4394

4395

4396

4397

4398

4399

4400

4401

4402

4403

4404

4405

4406

4407

4408

4409

4410

4411

4412

4413

4414

4415

4416

4417

4418

4419

4420

4421

4422

4423

4424

4425

4426

4427

4428

4429

4430

4431

4432

4433

4434

4435

4436

4437

4438

4439

4440

4441

4442

4443

4444

4445

4446

4447

4448

4449

4450

4451

4452

4453

4454

4455

4456

4457

4458

4459

4460

4461

4462

4463

4464

4465

4466

4467

4468

4469

4470

4471

4472

4473

4474

4475

4476

4477

4478

4479

4480

4481

4482

4483

4484

4485

4486

4487

4488

4489

4490

4491

4492

4493

4494

4495

4496

4497

4498

4499

4500

4501

4502

4503

4504

4505

4506

4507

4508

4509

4510

4511

4512

4513

4514

4515

4516

4517

4518

4519

4520

4521

4522

4523

4524

4525

4526

4527

4528

4529

4530

4531

4532

4533

4534

4535

4536

4537

4538

4539

4540

4541

4542

4543

4544

4545

4546

4547

4548

4549

4550

4551

4552

4553

4554

4555

4556

4557

4558

4559

4560

4561

4562

4563

4564

4565

4566

4567

4568

4569

4570

4571

4572

4573

4574

4575

4576

4577

4578

4579

4580

4581

4582

4583

4584

4585

4586

4587

4588

4589

4590

4591

4592

4593

4594

4595

4596

4597

4598

4599

4600

4601

4602

4603

4604

4605

4606

4607

4608

4609

4610

4611

4612

4613

4614

4615

4616

4617

4618

4619

4620

4621

4622

4623

4624

4625

4626

4627

4628

4629

4630

4631

4632

4633

4634

4635

4636

4637

4638

4639

4640

4641

4642

4643

4644

4645

4646

4647

4648

4649

4650

4651

4652

4653

4654

4655

4656

4657

4658

4659

4660

4661

4662

4663

4664

4665

4666

4667

4668

4669

4670

4671

4672

4673

4674

4675

4676

4677

4678

4679

4680

4681

4682

4683

4684

4685

4686

4687

4688

4689

4690

4691

4692

4693

4694

4695

4696

4697

4698

4699

4700

4701

4702

4703

4704

4705

4706

4707

4708

4709

4710

4711

4712

4713

4714

4715

4716

4717

4718

4719

4720

4721

4722

4723

4724

4725

4726

4727

4728

4729

4730

4731

4732

4733

4734

4735

4736

4737

4738

4739

4740

4741

4742

4743

4744

4745

4746

4747

4748

4749

4750

4751

4752

4753

4754

4755

4756

4757

4758

4759

4760

4761

4762

4763

4764

4765

4766

4767

4768

4769

4770

4771

4772

4773

4774

4775

4776

4777

4778

4779

4780

4781

4782

4783

4784

4785

4786

4787

4788

4789

4790

4791

4792

4793

4794

4795

4796

4797

4798

4799

4800

4801

4802

4803

4804

4805

4806

4807

4808

4809

4810

4811

4812

4813

4814

4815

4816

4817

4818

4819

4820

4821

4822

4823

4824

4825

4826

4827

4828

4829

4830

4831

4832

4833

4834

4835

4836

4837

4838

4839

4840

4841

4842

4843

4844

4845

4846

4847

4848

4849

4850

4851

4852

4853

4854

4855

4856

4857

4858

4859

4860

4861

4862

4863

4864

4865

4866

4867

4868

4869

4870

4871

4872

4873

4874

4875

4876

4877

4878

4879

4880

4881

4882

4883

4884

4885

4886

4887

4888

4889

4890

4891

4892

4893

4894

4895

4896

4897

4898

4899

4900

4901

4902

4903

4904

4905

4906

4907

4908

4909

4910

4911

4912

4913

4914

4915

4916

4917

4918

4919

4920

4921

4922

4923

4924

4925

4926

4927

4928

4929

4930

4931

4932

4933

4934

4935

4936

4937

4938

4939

4940

4941

4942

4943

4944

4945

4946

4947

4948

4949

4950

4951

4952

4953

4954

4955

4956

4957

4958

4959

4960

4961

4962

4963

4964

4965

4966

4967

4968

4969

4970

4971

4972

4973

4974

4975

4976

4977

4978

4979

4980

4981

4982

4983

4984

4985

4986

4987

4988

4989

4990

4991

4992

4993

4994

4995

4996

4997

4998

4999

5000

5001

5002

5003

5004

5005

5006

5007

5008

5009

5010

5011

5012

5013

5014

5015

5016

5017

5018

5019

5020

5021

5022

5023

5024

5025

5026

5027

5028

5029

5030

5031

5032

5033

5034

5035

5036

5037

5038

5039

5040

5041

5042

5043

5044

5045

5046

5047

5048

5049

5050

5051

5052

5053

5054

5055

5056

5057

5058

5059

5060

5061

5062

5063

5064

5065

5066

5067

5068

5069

5070

5071

5072

5073

5074

5075

5076

5077

5078

5079

5080

5081

5082

5083

5084

5085

5086

5087

5088

5089

5090

5091

5092

5093

5094

5095

5096

5097

5098

5099

5100

5101

5102

5103

5104

5105

5106

5107

5108

5109

5110

5111

5112

5113

5114

5115

5116

5117

5118

5119

5120

5121

5122

5123

5124

5125

5126

5127

5128

5129

5130

5131

5132

5133

5134

5135

5136

5137

5138

5139

5140

5141

5142

5143

5144

5145

5146

5147

5148

5149

5150

5151

5152

5153

5154

5155

5156

5157

5158

5159

5160

5161

5162

5163

5164

5165

5166

5167

5168

5169

5170

5171

5172

5173

5174

5175

5176

5177

5178

5179

5180

5181

5182

5183

5184

5185

5186

5187

5188

5189

5190

5191

5192

5193

5194

5195

5196

5197

5198

5199

5200

5201

5202

5203

5204

5205

5206

5207

5208

5209

5210

5211

5212

5213

5214

5215

5216

5217

5218

5219

5220

5221

5222

5223

5224

5225

5226

5227

5228

5229

5230

5231

5232

5233

5234

5235

5236

5237

5238

5239

5240

5241

5242

5243

5244

5245

5246

5247

5248

5249

5250

5251

5252

5253

5254

5255

5256

5257

5258

5259

5260

5261

5262

5263

5264

5265

5266

5267

5268

5269

5270

5271

5272

5273

5274

5275

5276

5277

5278

5279

5280

5281

5282

5283

5284

5285

5286

5287

5288

5289

5290

5291

5292

5293

5294

5295

5296

5297

5298

5299

5300

5301

5302

5303

5304

5305

5306

5307

5308

5309

5310

5311

5312

5313

5314

5315

5316

5317

5318

5319

5320

5321

5322

5323

5324

5325

5326

5327

5328

5329

5330

5331

5332

5333

5334

5335

5336

5337

5338

5339

5340

5341

5342

5343

5344

5345

5346

5347

5348

5349

5350

5351

5352

5353

5354

5355

5356

5357

5358

5359

5360

5361

5362

5363

5364

5365

5366

5367

5368

5369

5370

5371

5372

5373

5374

5375

5376

5377

5378

5379

5380

5381

5382

5383

5384

5385

5386

5387

5388

5389

5390

5391

5392

5393

5394

5395

5396

5397

5398

5399

5400

5401

5402

5403

5404

5405

5406

5407

5408

5409

5410

5411

5412

5413

5414

5415

5416

5417

5418

5419

5420

5421

5422

5423

5424

5425

5426

5427

5428

5429

5430

5431

5432

5433

5434

5435

5436

5437

5438

5439

5440

5441

5442

5443

5444

5445

5446

5447

5448

5449

5450

5451

5452

5453

5454

5455

5456

5457

5458

5459

5460

5461

5462

5463

5464

5465

5466

5467

5468

5469

5470

5471

5472

5473

5474

5475

5476

5477

5478

5479

5480

5481

5482

5483

5484

5485

5486

5487

5488

5489

5490

5491

5492

5493

5494

5495

5496

5497

5498

5499

5500

5501

5502

5503

5504

5505

5506

5507

5508

5509

5510

5511

5512

5513

5514

5515

5516

5517

5518

5519

5520

5521

5522

5523

5524

5525

5526

5527

5528

5529

5530

5531

5532

5533

5534

5535

5536

5537

5538

5539

5540

5541

5542

5543

5544

5545

5546

5547

5548

5549

5550

5551

5552

5553

5554

5555

5556

5557

5558

5559

5560

5561

5562

5563

5564

5565

5566

5567

5568

5569

5570

5571

5572

5573

5574

5575

5576

5577

5578

5579

5580

5581

5582

5583

5584

5585

5586

5587

5588

5589

5590

5591

5592

5593

5594

5595

5596

5597

5598

5599

5600

5601

5602

5603

5604

5605

5606

5607

5608

5609

5610

5611

5612

5613

5614

5615

5616

5617

5618

5619

5620

5621

5622

5623

5624

5625

5626

5627

5628

5629

5630

5631

5632

5633

5634

5635

5636

5637

5638

5639

5640

5641

5642

5643

5644

5645

5646

5647

5648

5649

5650

5651

5652

5653

5654

5655

5656

5657

5658

5659

5660

5661

5662

5663

5664

5665

5666

5667

5668

5669

5670

5671

5672

5673

5674

5675

5676

5677

5678

5679

5680

5681

5682

5683

5684

5685

5686

5687

5688

5689

5690

5691

5692

5693

5694

5695

5696

5697

5698

5699

5700

5701

5702

5703

5704

5705

5706

5707

5708

5709

5710

5711

5712

5713

5714

5715

5716

5717

5718

5719

5720

5721

5722

5723

5724

5725

5726

5727

5728

5729

5730

5731

5732

5733

5734

5735

5736

5737

5738

5739

5740

5741

5742

5743

5744

5745

5746

5747

5748

5749

5750

5751

5752

5753

5754

5755

5756

5757

5758

5759

5760

5761

5762

5763

5764

5765

5766

5767

5768

5769

5770

5771

5772

5773

5774

5775

5776

5777

5778

5779

5780

5781

5782

5783

5784

5785

5786

5787

5788

5789

5790

5791

5792

5793

5794

5795

5796

5797

5798

5799

5800

5801

5802

5803

5804

5805

5806

5807

5808

5809

5810

5811

5812

5813

5814

5815

5816

5817

5818

5819

5820

5821

5822

5823

5824

5825

5826

5827

5828

5829

5830

5831

5832

5833

5834

5835

5836

5837

5838

5839

5840

5841

5842

5843

5844

5845

5846

5847

5848

5849

5850

5851

5852

5853

5854

5855

5856

5857

5858

5859

5860

5861

5862

5863

5864

5865

5866

5867

5868

5869

5870

5871

5872

5873

5874

5875

5876

5877

5878

5879

5880

5881

5882

5883

5884

5885

5886

5887

5888

5889

5890

5891

5892

5893

5894

5895

5896

5897

5898

5899

5900

5901

5902

5903

5904

5905

5906

5907

5908

5909

5910

5911

5912

5913

5914

5915

5916

5917

5918

5919

5920

5921

5922

5923

5924

5925

5926

5927

5928

5929

5930

5931

5932

5933

5934

5935

5936

5937

5938

5939

5940

5941

5942

5943

5944

5945

5946

5947

5948

5949

5950

5951

5952

5953

5954

5955

5956

5957

5958

5959

5960

5961

5962

5963

5964

5965

5966

5967

5968

5969

5970

5971

5972

5973

5974

5975

5976

5977

5978

5979

5980

5981

5982

5983

5984

5985

5986

5987

5988

5989

5990

5991

5992

5993

5994

5995

5996

5997

5998

5999

6000

6001

6002

6003

6004

6005

6006

6007

6008

6009

6010

6011

6012

6013

6014

6015

6016

6017

6018

6019

6020

6021

6022

6023

6024

6025

6026

6027

6028

6029

6030

6031

6032

6033

6034

6035

6036

6037

6038

6039

6040

6041

6042

6043

6044

6045

6046

6047

6048

6049

6050

6051

6052

6053

6054

6055

6056

6057

6058

6059

6060

6061

6062

6063

6064

6065

6066

6067

6068

6069

6070

6071

6072

6073

6074

6075

6076

6077

6078

6079

6080

6081

6082

6083

6084

6085

6086

6087

6088

6089

6090

6091

6092

6093

6094

6095

6096

6097

6098

6099

6100

6101

6102

6103

6104

6105

6106

6107

6108

6109

6110

6111

6112

6113

6114

6115

6116

6117

6118

6119

6120

6121

6122

6123

6124

6125

6126

6127

6128

6129

6130

6131

6132

6133

6134

6135

6136

6137

6138

6139

6140

6141

6142

6143

6144

6145

6146

6147

6148

6149

6150

6151

6152

6153

6154

6155

6156

6157

6158

6159

6160

6161

6162

6163

6164

6165

6166

6167

6168

6169

6170

6171

6172

6173

6174

6175

6176

6177

6178

6179

6180

6181

6182

6183

6184

6185

6186

6187

6188

6189

6190

6191

6192

6193

6194

6195

6196

6197

6198

6199

6200

6201

6202

6203

6204

6205

6206

6207

6208

6209

6210

6211

6212

6213

6214

6215

6216

6217

6218

6219

6220

6221

6222

6223

6224

6225

6226

6227

6228

6229

6230

6231

6232

6233

6234

6235

6236

6237

6238

6239

6240

6241

6242

6243

6244

6245

6246

6247

6248

6249

6250

6251

6252

6253

6254

6255

6256

6257

6258

6259

6260

6261

6262

6263

6264

6265

6266

6267

6268

6269

6270

6271

6272

6273

6274

6275

6276

6277

6278

6279

6280

6281

6282

6283

6284

6285

6286

6287

6288

6289

6290

6291

6292

6293

6294

6295

6296

6297

6298

6299

6300

6301

6302

6303

6304

6305

6306

6307

6308

6309

6310

6311

6312

6313

6314

6315

6316

6317

6318

6319

6320

6321

6322

6323

6324

6325

6326

6327

6328

6329

6330

6331

6332

6333

6334

6335

6336

6337

6338

6339

6340

6341

6342

6343

6344

6345

6346

6347

6348

6349

6350

6351

6352

6353

6354

6355

6356

6357

6358

6359

6360

6361

6362

6363

6364

6365

6366

6367

6368

6369

6370

6371

6372

6373

6374

6375

6376

6377

6378

6379

6380

6381

6382

6383

6384

6385

6386

6387

6388

6389

6390

6391

6392

6393

6394

6395

6396

6397

6398

6399

6400

6401

6402

6403

6404

6405

6406

6407

6408

6409

6410

6411

6412

6413

6414

6415

6416

6417

6418

6419

6420

6421

6422

6423

6424

6425

6426

6427

6428

6429

6430

6431

6432

6433

6434

6435

6436

6437

6438

6439

6440

6441

6442

6443

6444

6445

6446

6447

6448

6449

6450

6451

6452

6453

6454

6455

6456

6457

6458

6459

6460

6461

6462

6463

6464

6465

6466

6467

6468

6469

6470

6471

6472

6473

6474

6475

6476

6477

6478

6479

6480

6481

6482

6483

6484

6485

6486

6487

6488

6489

6490

6491

6492

6493

6494

6495

6496

6497

6498

6499

6500

6501

6502

6503

6504

6505

6506

6507

6508

6509

6510

6511

6512

6513

6514

6515

6516

6517

6518

6519

6520

6521

6522

6523

6524

6525

6526

6527

6528

6529

6530

6531

6532

6533

6534

6535

6536

6537

6538

6539

6540

6541

6542

6543

6544

6545

6546

6547

6548

6549

6550

6551

6552

6553

6554

6555

6556

6557

6558

6559

6560

6561

6562

6563

6564

6565

6566

6567

6568

6569

6570

6571

6572

6573

6574

6575

6576

6577

6578

6579

6580

6581

6582

6583

6584

6585

6586

6587

6588

6589

6590

6591

6592

6593

6594

6595

6596

6597

6598

6599

6600

6601

6602

6603

6604

6605

6606

6607

6608

6609

6610

6611

6612

6613

6614

6615

6616

6617

6618

6619

6620

6621

6622

6623

6624

6625

6626

6627

6628

6629

6630

6631

6632

6633

6634

6635

6636

6637

6638

6639

6640

6641

6642

6643

6644

6645

6646

6647

6648

6649

6650

6651

6652

6653

6654

6655

6656

6657

6658

6659

6660

6661

6662

6663

6664

6665

6666

6667

6668

6669

6670

6671

6672

6673

6674

6675

6676

6677

6678

6679

6680

6681

6682

6683

6684

6685

6686

6687

6688

6689

6690

6691

6692

6693

6694

6695

6696

6697

6698

6699

6700

6701

6702

6703

6704

6705

6706

6707

6708

6709

6710

6711

6712

6713

6714

6715

6716

6717

6718

6719

6720

6721

6722

6723

6724

6725

6726

6727

6728

6729

6730

6731

6732

6733

6734

6735

6736

6737

6738

6739

6740

6741

6742

6743

6744

6745

6746

6747

6748

6749

6750

6751

6752

6753

6754

6755

6756

6757

6758

6759

6760

6761

6762

6763

6764

6765

6766

6767

6768

6769

6770

6771

6772

6773

6774

6775

6776

6777

6778

6779

6780

6781

6782

6783

6784

6785

6786

6787

6788

6789

6790

6791

6792

6793

6794

6795

6796

6797

6798

6799

6800

6801

6802

6803

6804

6805

6806

6807

6808

6809

6810

6811

6812

6813

6814

6815

6816

6817

6818

6819

6820

6821

6822

6823

6824

6825

6826

6827

6828

6829

6830

6831

6832

6833

6834

6835

6836

6837

6838

6839

6840

6841

6842

6843

6844

6845

6846

6847

6848

6849

6850

6851

6852

6853

6854

6855

6856

6857

6858

6859

6860

6861

6862

6863

6864

6865

6866

6867

6868

6869

6870

6871

6872

6873

6874

6875

6876

6877

6878

6879

6880

6881

6882

6883

6884

6885

6886

6887

6888

6889

6890

6891

6892

6893

6894

6895

6896

6897

6898

6899

6900

6901

6902

6903

6904

6905

6906

6907

6908

6909

6910

6911

6912

6913

6914

6915

6916

6917

6918

6919

6920

6921

6922

6923

6924

6925

6926

6927

6928

6929

6930

6931

6932

6933

6934

6935

6936

6937

6938

6939

6940

6941

6942

6943

6944

6945

6946

6947

6948

6949

6950

6951

6952

6953

6954

6955

6956

6957

6958

6959

6960

6961

6962

6963

6964

6965

6966

6967

6968

6969

6970

6971

6972

6973

6974

6975

6976

6977

6978

6979

6980

6981

6982

6983

6984

6985

6986

6987

6988

6989

6990

6991

6992

6993

6994

6995

6996

6997

6998

6999

7000

7001

7002

7003

7004

7005

7006

7007

7008

7009

7010

7011

7012

7013

7014

7015

7016

7017

7018

7019

7020

7021

7022

7023

7024

7025

7026

7027

7028

7029

7030

7031

7032

7033

7034

7035

7036

7037

7038

7039

7040

7041

7042

7043

7044

7045

7046

7047

7048

7049

7050

7051

7052

7053

7054

7055

7056

7057

7058

7059

7060

7061

7062

7063

7064

7065

7066

7067

7068

7069

7070

7071

7072

7073

7074

7075

7076

7077

7078

7079

7080

7081

7082

7083

7084

7085

7086

7087

7088

7089

7090

7091

7092

7093

7094

7095

7096

/** ****************************************************************************** * @file stm32f4xx_ll_rcc.h * @author MCD Application Team * @brief Header file of RCC LL module. ****************************************************************************** * @attention * * Copyright (c) 2017 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_LL_RCC_H #define __STM32F4xx_LL_RCC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_LL_Driver * @{ */ #if defined(RCC) /** @defgroup RCC_LL RCC * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @defgroup RCC_LL_Private_Variables RCC Private Variables * @{ */ #if defined(RCC_DCKCFGR_PLLSAIDIVR) static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16}; #endif /* RCC_DCKCFGR_PLLSAIDIVR */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_Private_Macros RCC Private Macros * @{ */ /** * @} */ #endif /*USE_FULL_LL_DRIVER*/ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_Exported_Types RCC Exported Types * @{ */ /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure * @{ */ /** * @brief RCC Clocks Frequency Structure */ typedef struct { uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ } LL_RCC_ClocksTypeDef; /** * @} */ /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /* Exported constants --------------------------------------------------------*/ /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants * @{ */ /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation * @brief Defines used to adapt values of different oscillators * @note These values could be modified in the user environment according to * HW set-up. * @{ */ #if !defined (HSE_VALUE) #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ #endif /* HSI_VALUE */ #if !defined (LSE_VALUE) #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ #endif /* LSE_VALUE */ #if !defined (LSI_VALUE) #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ #endif /* EXTERNAL_CLOCK_VALUE */ /** * @} */ /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines * @brief Flags defines which can be used with LL_RCC_WriteReg function * @{ */ #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ #if defined(RCC_PLLI2S_SUPPORT) #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */ #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_PLLSAI_SUPPORT) #define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */ #endif /* RCC_PLLSAI_SUPPORT */ #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ /** * @} */ /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines * @brief Flags defines which can be used with LL_RCC_ReadReg function * @{ */ #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ #if defined(RCC_PLLI2S_SUPPORT) #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */ #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_PLLSAI_SUPPORT) #define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */ #endif /* RCC_PLLSAI_SUPPORT */ #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ #if defined(RCC_CSR_BORRSTF) #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ #endif /* RCC_CSR_BORRSTF */ /** * @} */ /** @defgroup RCC_LL_EC_IT IT Defines * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions * @{ */ #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ #if defined(RCC_PLLI2S_SUPPORT) #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */ #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_PLLSAI_SUPPORT) #define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */ #endif /* RCC_PLLSAI_SUPPORT */ /** * @} */ /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch * @{ */ #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ #if defined(RCC_CFGR_SW_PLLR) #define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /*!< PLLR selection as system clock */ #endif /* RCC_CFGR_SW_PLLR */ /** * @} */ /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status * @{ */ #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ #if defined(RCC_PLLR_SYSCLK_SUPPORT) #define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /*!< PLLR used as system clock */ #endif /* RCC_PLLR_SYSCLK_SUPPORT */ /** * @} */ /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler * @{ */ #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ /** * @} */ /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) * @{ */ #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ /** * @} */ /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) * @{ */ #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ /** * @} */ /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection * @{ */ #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */ #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */ #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */ #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */ #if defined(RCC_CFGR_MCO2) #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */ #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */ #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */ #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */ #endif /* RCC_CFGR_MCO2 */ /** * @} */ /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler * @{ */ #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */ #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */ #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */ #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */ #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */ #if defined(RCC_CFGR_MCO2PRE) #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */ #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */ #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */ #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */ #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */ #endif /* RCC_CFGR_MCO2PRE */ /** * @} */ /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock * @{ */ #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */ #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */ #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */ #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */ #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */ #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */ #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */ #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */ #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */ #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */ #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */ #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */ #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */ #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */ #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */ #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */ #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */ #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */ #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */ #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */ #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */ #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */ #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */ #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */ #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */ #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */ #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */ #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */ #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */ #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */ #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */ /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency * @{ */ #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ /** * @} */ #endif /* USE_FULL_LL_DRIVER */ #if defined(FMPI2C1) /** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection * @{ */ #define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as FMPI2C1 clock source */ #define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */ #define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */ /** * @} */ #endif /* FMPI2C1 */ #if defined(LPTIM1) /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection * @{ */ #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */ #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */ #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */ #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */ /** * @} */ #endif /* LPTIM1 */ #if defined(SAI1) /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection * @{ */ #if defined(RCC_DCKCFGR_SAI1SRC) #define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */ #define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 clock source */ #define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /*!< PLL clock used as SAI1 clock source */ #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16)) /*!< External pin clock used as SAI1 clock source */ #endif /* RCC_DCKCFGR_SAI1SRC */ #if defined(RCC_DCKCFGR_SAI2SRC) #define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */ #define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /*!< PLLI2S clock used as SAI2 clock source */ #define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /*!< PLL clock used as SAI2 clock source */ #define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16)) /*!< PLL Main clock used as SAI2 clock source */ #endif /* RCC_DCKCFGR_SAI2SRC */ #if defined(RCC_DCKCFGR_SAI1ASRC) #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT) #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block A clock source */ #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */ #define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */ #define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16)) /*!< PLL Main clock used as SAI1 block A clock source */ #else #define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block A clock source */ #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */ #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */ #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */ #endif /* RCC_DCKCFGR_SAI1ASRC */ #if defined(RCC_DCKCFGR_SAI1BSRC) #if defined(RCC_SAI1B_PLLSOURCE_SUPPORT) #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block B clock source */ #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */ #define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */ #define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16)) /*!< PLL Main clock used as SAI1 block B clock source */ #else #define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block B clock source */ #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */ #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */ #endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */ #endif /* RCC_DCKCFGR_SAI1BSRC */ /** * @} */ #endif /* SAI1 */ #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) /** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection * @{ */ #define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /*!< PLL 48M domain clock used as SDIO clock */ #if defined(RCC_DCKCFGR_SDIOSEL) #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /*!< System clock clock used as SDIO clock */ #else #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /*!< System clock clock used as SDIO clock */ #endif /* RCC_DCKCFGR_SDIOSEL */ /** * @} */ #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ #if defined(DSI) /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection * @{ */ #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */ #define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /*!< PLL clock used as DSI byte lane clock source */ /** * @} */ #endif /* DSI */ #if defined(CEC) /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection * @{ */ #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */ #define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /*!< LSE oscillator clock used as CEC clock */ /** * @} */ #endif /* CEC */ /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection * @{ */ #if defined(RCC_CFGR_I2SSRC) #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */ #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */ #endif /* RCC_CFGR_I2SSRC */ #if defined(RCC_DCKCFGR_I2SSRC) #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U) /*!< PLL clock used as I2S1 clock source */ #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16)) /*!< External pin used as I2S1 clock source */ #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16)) /*!< PLL Main clock used as I2S1 clock source */ #endif /* RCC_DCKCFGR_I2SSRC */ #if defined(RCC_DCKCFGR_I2S1SRC) #define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U) /*!< PLLI2S clock used as I2S1 clock source */ #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */ #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */ #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16)) /*!< PLL Main clock used as I2S1 clock source */ #endif /* RCC_DCKCFGR_I2S1SRC */ #if defined(RCC_DCKCFGR_I2S2SRC) #define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U) /*!< PLLI2S clock used as I2S2 clock source */ #define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */ #define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */ #define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16)) /*!< PLL Main clock used as I2S2 clock source */ #endif /* RCC_DCKCFGR_I2S2SRC */ /** * @} */ #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection * @{ */ #if defined(RCC_DCKCFGR_CK48MSEL) #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ #endif /* RCC_DCKCFGR_CK48MSEL */ #if defined(RCC_DCKCFGR2_CK48MSEL) #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ #if defined(RCC_PLLSAI_SUPPORT) #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ #endif /* RCC_PLLSAI_SUPPORT */ #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) #define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /*!< PLLI2S oscillator clock used as 48Mhz domain clock */ #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ #endif /* RCC_DCKCFGR2_CK48MSEL */ /** * @} */ #if defined(RNG) /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection * @{ */ #define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as RNG clock source */ #if defined(RCC_PLLSAI_SUPPORT) #define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as RNG clock source */ #endif /* RCC_PLLSAI_SUPPORT */ #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) #define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as RNG clock source */ #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ /** * @} */ #endif /* RNG */ #if defined(USB_OTG_FS) || defined(USB_OTG_HS) /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection * @{ */ #define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as USB clock source */ #if defined(RCC_PLLSAI_SUPPORT) #define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as USB clock source */ #endif /* RCC_PLLSAI_SUPPORT */ #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) #define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as USB clock source */ #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ /** * @} */ #endif /* USB_OTG_FS || USB_OTG_HS */ #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0) /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection * @{ */ #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM1 Audio clock source */ #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */ #if defined(DFSDM2_Channel0) #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM2 Audio clock source */ #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */ #endif /* DFSDM2_Channel0 */ /** * @} */ /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection * @{ */ #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */ #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM1 clock */ #if defined(DFSDM2_Channel0) #define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM2 clock */ #define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM2 clock */ #endif /* DFSDM2_Channel0 */ /** * @} */ #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */ #if defined(FMPI2C1) /** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source * @{ */ #define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /*!< FMPI2C1 Clock source selection */ /** * @} */ #endif /* FMPI2C1 */ #if defined(SPDIFRX) /** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection * @{ */ #define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as SPDIFRX clock source */ #define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */ /** * @} */ #endif /* SPDIFRX */ #if defined(LPTIM1) /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source * @{ */ #define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */ /** * @} */ #endif /* LPTIM1 */ #if defined(SAI1) /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source * @{ */ #if defined(RCC_DCKCFGR_SAI1ASRC) #define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */ #endif /* RCC_DCKCFGR_SAI1ASRC */ #if defined(RCC_DCKCFGR_SAI1BSRC) #define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */ #endif /* RCC_DCKCFGR_SAI1BSRC */ #if defined(RCC_DCKCFGR_SAI1SRC) #define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /*!< SAI1 Clock source selection */ #endif /* RCC_DCKCFGR_SAI1SRC */ #if defined(RCC_DCKCFGR_SAI2SRC) #define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /*!< SAI2 Clock source selection */ #endif /* RCC_DCKCFGR_SAI2SRC */ /** * @} */ #endif /* SAI1 */ #if defined(SDIO) /** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source * @{ */ #if defined(RCC_DCKCFGR_SDIOSEL) #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /*!< SDIO Clock source selection */ #elif defined(RCC_DCKCFGR2_SDIOSEL) #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /*!< SDIO Clock source selection */ #else #define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< SDIO Clock source selection */ #endif /** * @} */ #endif /* SDIO */ #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) /** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source * @{ */ #if defined(RCC_DCKCFGR_CK48MSEL) #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /*!< CK48M Domain clock source selection */ #endif /* RCC_DCKCFGR_CK48MSEL */ #if defined(RCC_DCKCFGR2_CK48MSEL) #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */ #endif /* RCC_DCKCFGR_CK48MSEL */ /** * @} */ #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ #if defined(RNG) /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source * @{ */ #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) #define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */ #else #define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< RNG Clock source selection */ #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ /** * @} */ #endif /* RNG */ #if defined(USB_OTG_FS) || defined(USB_OTG_HS) /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source * @{ */ #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) #define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */ #else #define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< USB Clock source selection */ #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ /** * @} */ #endif /* USB_OTG_FS || USB_OTG_HS */ #if defined(CEC) /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source * @{ */ #define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */ /** * @} */ #endif /* CEC */ /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source * @{ */ #if defined(RCC_CFGR_I2SSRC) #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */ #endif /* RCC_CFGR_I2SSRC */ #if defined(RCC_DCKCFGR_I2SSRC) #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /*!< I2S1 Clock source selection */ #endif /* RCC_DCKCFGR_I2SSRC */ #if defined(RCC_DCKCFGR_I2S1SRC) #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */ #endif /* RCC_DCKCFGR_I2S1SRC */ #if defined(RCC_DCKCFGR_I2S2SRC) #define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */ #endif /* RCC_DCKCFGR_I2S2SRC */ /** * @} */ #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0) /** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source * @{ */ #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */ #if defined(DFSDM2_Channel0) #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */ #endif /* DFSDM2_Channel0 */ /** * @} */ /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source * @{ */ #define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */ #if defined(DFSDM2_Channel0) #define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */ #endif /* DFSDM2_Channel0 */ /** * @} */ #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */ #if defined(SPDIFRX) /** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source * @{ */ #define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */ /** * @} */ #endif /* SPDIFRX */ #if defined(DSI) /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source * @{ */ #define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */ /** * @} */ #endif /* DSI */ #if defined(LTDC) /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source * @{ */ #define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */ /** * @} */ #endif /* LTDC */ /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection * @{ */ #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */ /** * @} */ #if defined(RCC_DCKCFGR_TIMPRE) /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection * @{ */ #define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */ #define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /*!< Timers clock to four time PCLK */ /** * @} */ #endif /* RCC_DCKCFGR_TIMPRE */ /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source * @{ */ #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ #if defined(RCC_PLLI2SCFGR_PLLI2SSRC) #define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U) /*!< I2S External pin input clock selected as PLLI2S entry clock source */ #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ /** * @} */ /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor * @{ */ #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */ #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */ #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */ #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */ #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */ #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */ #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */ #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */ #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */ #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */ #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */ #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */ #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */ #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */ #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */ #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */ #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */ #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */ #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */ #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */ #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */ #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */ #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */ #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */ #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */ #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */ #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */ #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */ #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */ #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */ #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */ #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */ #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */ #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */ #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */ #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */ #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */ #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */ #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */ #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */ #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */ #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */ #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */ #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */ #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */ #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */ #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */ #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */ #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */ #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */ #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */ #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */ #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */ #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */ #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */ #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */ #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */ #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */ #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */ #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */ #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */ #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */ /** * @} */ #if defined(RCC_PLLCFGR_PLLR) /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) * @{ */ #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */ #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */ #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */ /** * @} */ #endif /* RCC_PLLCFGR_PLLR */ #if defined(RCC_DCKCFGR_PLLDIVR) /** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR) * @{ */ #define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 1 */ #define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 2 */ #define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 3 */ #define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 4 */ #define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 5 */ #define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 6 */ #define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 7 */ #define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 8 */ #define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 9 */ #define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 10 */ #define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 11 */ #define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 12 */ #define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 13 */ #define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 14 */ #define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 15 */ #define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /*!< PLL division factor for PLLDIVR output by 16 */ #define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 17 */ #define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 18 */ #define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 19 */ #define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 20 */ #define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 21 */ #define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 22 */ #define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 23 */ #define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 24 */ #define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 25 */ #define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 26 */ #define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 27 */ #define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 28 */ #define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 29 */ #define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 30 */ #define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 31 */ /** * @} */ #endif /* RCC_DCKCFGR_PLLDIVR */ /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) * @{ */ #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */ #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */ #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */ #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */ /** * @} */ /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) * @{ */ #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */ #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */ #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */ #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */ #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */ #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */ #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */ #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */ #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */ #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */ #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */ #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */ #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */ #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */ /** * @} */ /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection * @{ */ #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */ #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */ /** * @} */ #if defined(RCC_PLLI2S_SUPPORT) /** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM) * @{ */ #if defined(RCC_PLLI2SCFGR_PLLI2SM) #define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */ #define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */ #define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */ #define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */ #define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */ #define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */ #define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */ #define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */ #define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */ #define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */ #define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */ #define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */ #define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */ #define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */ #define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */ #define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */ #define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */ #define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */ #define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */ #define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */ #define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */ #define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */ #define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */ #define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */ #define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */ #define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */ #define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */ #define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */ #define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */ #define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */ #define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */ #define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */ #define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */ #define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */ #define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */ #define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */ #define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */ #define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */ #define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */ #define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */ #define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */ #define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */ #define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */ #define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */ #define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */ #define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */ #define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */ #define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */ #define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */ #define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */ #define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */ #define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */ #define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */ #define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */ #define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */ #define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */ #define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */ #define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */ #define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */ #define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */ #define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */ #define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */ #else #define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLI2S division factor for PLLI2SM output by 2 */ #define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLI2S division factor for PLLI2SM output by 3 */ #define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLI2S division factor for PLLI2SM output by 4 */ #define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLI2S division factor for PLLI2SM output by 5 */ #define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLI2S division factor for PLLI2SM output by 6 */ #define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLI2S division factor for PLLI2SM output by 7 */ #define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLI2S division factor for PLLI2SM output by 8 */ #define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLI2S division factor for PLLI2SM output by 9 */ #define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLI2S division factor for PLLI2SM output by 10 */ #define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLI2S division factor for PLLI2SM output by 11 */ #define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLI2S division factor for PLLI2SM output by 12 */ #define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLI2S division factor for PLLI2SM output by 13 */ #define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLI2S division factor for PLLI2SM output by 14 */ #define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLI2S division factor for PLLI2SM output by 15 */ #define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLI2S division factor for PLLI2SM output by 16 */ #define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLI2S division factor for PLLI2SM output by 17 */ #define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLI2S division factor for PLLI2SM output by 18 */ #define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLI2S division factor for PLLI2SM output by 19 */ #define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLI2S division factor for PLLI2SM output by 20 */ #define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLI2S division factor for PLLI2SM output by 21 */ #define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLI2S division factor for PLLI2SM output by 22 */ #define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLI2S division factor for PLLI2SM output by 23 */ #define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLI2S division factor for PLLI2SM output by 24 */ #define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLI2S division factor for PLLI2SM output by 25 */ #define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLI2S division factor for PLLI2SM output by 26 */ #define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLI2S division factor for PLLI2SM output by 27 */ #define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLI2S division factor for PLLI2SM output by 28 */ #define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLI2S division factor for PLLI2SM output by 29 */ #define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLI2S division factor for PLLI2SM output by 30 */ #define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLI2S division factor for PLLI2SM output by 31 */ #define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLI2S division factor for PLLI2SM output by 32 */ #define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLI2S division factor for PLLI2SM output by 33 */ #define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLI2S division factor for PLLI2SM output by 34 */ #define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLI2S division factor for PLLI2SM output by 35 */ #define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLI2S division factor for PLLI2SM output by 36 */ #define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLI2S division factor for PLLI2SM output by 37 */ #define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLI2S division factor for PLLI2SM output by 38 */ #define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLI2S division factor for PLLI2SM output by 39 */ #define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLI2S division factor for PLLI2SM output by 40 */ #define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLI2S division factor for PLLI2SM output by 41 */ #define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLI2S division factor for PLLI2SM output by 42 */ #define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLI2S division factor for PLLI2SM output by 43 */ #define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLI2S division factor for PLLI2SM output by 44 */ #define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLI2S division factor for PLLI2SM output by 45 */ #define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLI2S division factor for PLLI2SM output by 46 */ #define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLI2S division factor for PLLI2SM output by 47 */ #define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLI2S division factor for PLLI2SM output by 48 */ #define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLI2S division factor for PLLI2SM output by 49 */ #define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLI2S division factor for PLLI2SM output by 50 */ #define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLI2S division factor for PLLI2SM output by 51 */ #define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLI2S division factor for PLLI2SM output by 52 */ #define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLI2S division factor for PLLI2SM output by 53 */ #define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLI2S division factor for PLLI2SM output by 54 */ #define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLI2S division factor for PLLI2SM output by 55 */ #define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLI2S division factor for PLLI2SM output by 56 */ #define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLI2S division factor for PLLI2SM output by 57 */ #define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLI2S division factor for PLLI2SM output by 58 */ #define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLI2S division factor for PLLI2SM output by 59 */ #define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLI2S division factor for PLLI2SM output by 60 */ #define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLI2S division factor for PLLI2SM output by 61 */ #define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLI2S division factor for PLLI2SM output by 62 */ #define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLI2S division factor for PLLI2SM output by 63 */ #endif /* RCC_PLLI2SCFGR_PLLI2SM */ /** * @} */ #if defined(RCC_PLLI2SCFGR_PLLI2SQ) /** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ) * @{ */ #define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */ #define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */ #define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */ #define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */ #define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */ #define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */ #define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */ #define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */ #define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */ #define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */ #define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */ #define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */ #define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */ #define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */ /** * @} */ #endif /* RCC_PLLI2SCFGR_PLLI2SQ */ #if defined(RCC_DCKCFGR_PLLI2SDIVQ) /** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ) * @{ */ #define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */ #define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */ #define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */ #define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */ #define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */ #define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */ #define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */ #define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */ #define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */ #define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */ #define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */ #define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */ #define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */ #define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */ #define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */ #define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */ #define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */ #define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */ #define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */ #define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */ #define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */ #define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */ #define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */ #define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */ #define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */ #define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */ #define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */ #define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */ #define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */ #define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */ #define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */ #define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */ /** * @} */ #endif /* RCC_DCKCFGR_PLLI2SDIVQ */ #if defined(RCC_DCKCFGR_PLLI2SDIVR) /** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR) * @{ */ #define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */ #define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */ #define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */ #define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */ #define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */ #define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */ #define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */ #define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */ #define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */ #define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */ #define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */ #define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */ #define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */ #define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */ #define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */ #define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */ #define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */ #define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */ #define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */ #define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */ #define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */ #define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */ #define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */ #define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */ #define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */ #define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */ #define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */ #define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */ #define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */ #define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */ #define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */ /** * @} */ #endif /* RCC_DCKCFGR_PLLI2SDIVR */ /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR) * @{ */ #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */ #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */ #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */ #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */ #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */ #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */ /** * @} */ #if defined(RCC_PLLI2SCFGR_PLLI2SP) /** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP) * @{ */ #define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */ #define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */ #define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */ #define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */ /** * @} */ #endif /* RCC_PLLI2SCFGR_PLLI2SP */ #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_PLLSAI_SUPPORT) /** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM) * @{ */ #if defined(RCC_PLLSAICFGR_PLLSAIM) #define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */ #define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */ #define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */ #define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */ #define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */ #define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */ #define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */ #define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */ #define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */ #define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */ #define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */ #define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */ #define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */ #define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */ #define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */ #define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */ #define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */ #define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */ #define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */ #define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */ #define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */ #define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */ #define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */ #define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */ #define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */ #define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */ #define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */ #define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */ #define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */ #define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */ #define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */ #define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */ #define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */ #define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */ #define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */ #define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */ #define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */ #define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */ #define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */ #define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */ #define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */ #define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */ #define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */ #define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */ #define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */ #define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */ #define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */ #define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */ #define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */ #define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */ #define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */ #define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */ #define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */ #define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */ #define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */ #define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */ #define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */ #define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */ #define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */ #define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */ #define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */ #define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */ #else #define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLSAI division factor for PLLSAIM output by 2 */ #define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLSAI division factor for PLLSAIM output by 3 */ #define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLSAI division factor for PLLSAIM output by 4 */ #define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLSAI division factor for PLLSAIM output by 5 */ #define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLSAI division factor for PLLSAIM output by 6 */ #define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLSAI division factor for PLLSAIM output by 7 */ #define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLSAI division factor for PLLSAIM output by 8 */ #define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLSAI division factor for PLLSAIM output by 9 */ #define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLSAI division factor for PLLSAIM output by 10 */ #define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLSAI division factor for PLLSAIM output by 11 */ #define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLSAI division factor for PLLSAIM output by 12 */ #define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLSAI division factor for PLLSAIM output by 13 */ #define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLSAI division factor for PLLSAIM output by 14 */ #define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLSAI division factor for PLLSAIM output by 15 */ #define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLSAI division factor for PLLSAIM output by 16 */ #define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLSAI division factor for PLLSAIM output by 17 */ #define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLSAI division factor for PLLSAIM output by 18 */ #define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLSAI division factor for PLLSAIM output by 19 */ #define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLSAI division factor for PLLSAIM output by 20 */ #define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLSAI division factor for PLLSAIM output by 21 */ #define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLSAI division factor for PLLSAIM output by 22 */ #define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLSAI division factor for PLLSAIM output by 23 */ #define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLSAI division factor for PLLSAIM output by 24 */ #define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLSAI division factor for PLLSAIM output by 25 */ #define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLSAI division factor for PLLSAIM output by 26 */ #define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLSAI division factor for PLLSAIM output by 27 */ #define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLSAI division factor for PLLSAIM output by 28 */ #define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLSAI division factor for PLLSAIM output by 29 */ #define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLSAI division factor for PLLSAIM output by 30 */ #define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLSAI division factor for PLLSAIM output by 31 */ #define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLSAI division factor for PLLSAIM output by 32 */ #define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLSAI division factor for PLLSAIM output by 33 */ #define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLSAI division factor for PLLSAIM output by 34 */ #define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLSAI division factor for PLLSAIM output by 35 */ #define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLSAI division factor for PLLSAIM output by 36 */ #define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLSAI division factor for PLLSAIM output by 37 */ #define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLSAI division factor for PLLSAIM output by 38 */ #define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLSAI division factor for PLLSAIM output by 39 */ #define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLSAI division factor for PLLSAIM output by 40 */ #define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLSAI division factor for PLLSAIM output by 41 */ #define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLSAI division factor for PLLSAIM output by 42 */ #define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLSAI division factor for PLLSAIM output by 43 */ #define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLSAI division factor for PLLSAIM output by 44 */ #define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLSAI division factor for PLLSAIM output by 45 */ #define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLSAI division factor for PLLSAIM output by 46 */ #define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLSAI division factor for PLLSAIM output by 47 */ #define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLSAI division factor for PLLSAIM output by 48 */ #define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLSAI division factor for PLLSAIM output by 49 */ #define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLSAI division factor for PLLSAIM output by 50 */ #define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLSAI division factor for PLLSAIM output by 51 */ #define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLSAI division factor for PLLSAIM output by 52 */ #define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLSAI division factor for PLLSAIM output by 53 */ #define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLSAI division factor for PLLSAIM output by 54 */ #define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLSAI division factor for PLLSAIM output by 55 */ #define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLSAI division factor for PLLSAIM output by 56 */ #define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLSAI division factor for PLLSAIM output by 57 */ #define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLSAI division factor for PLLSAIM output by 58 */ #define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLSAI division factor for PLLSAIM output by 59 */ #define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLSAI division factor for PLLSAIM output by 60 */ #define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLSAI division factor for PLLSAIM output by 61 */ #define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLSAI division factor for PLLSAIM output by 62 */ #define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLSAI division factor for PLLSAIM output by 63 */ #endif /* RCC_PLLSAICFGR_PLLSAIM */ /** * @} */ /** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ) * @{ */ #define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */ #define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */ #define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */ #define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */ #define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */ #define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */ #define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */ #define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */ #define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */ #define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */ #define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */ #define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */ #define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */ #define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */ /** * @} */ #if defined(RCC_DCKCFGR_PLLSAIDIVQ) /** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ) * @{ */ #define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */ #define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */ #define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */ #define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */ #define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */ #define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */ #define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */ #define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */ #define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */ #define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */ #define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */ #define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */ #define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */ #define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */ #define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */ #define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */ #define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */ #define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */ #define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */ #define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */ #define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */ #define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */ #define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */ #define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */ #define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */ #define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */ #define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */ #define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */ #define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */ #define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */ #define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */ #define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */ /** * @} */ #endif /* RCC_DCKCFGR_PLLSAIDIVQ */ #if defined(RCC_PLLSAICFGR_PLLSAIR) /** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR) * @{ */ #define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */ #define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */ #define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */ #define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */ #define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */ #define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */ /** * @} */ #endif /* RCC_PLLSAICFGR_PLLSAIR */ #if defined(RCC_DCKCFGR_PLLSAIDIVR) /** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR) * @{ */ #define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */ #define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */ #define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */ #define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */ /** * @} */ #endif /* RCC_DCKCFGR_PLLSAIDIVR */ #if defined(RCC_PLLSAICFGR_PLLSAIP) /** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP) * @{ */ #define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */ #define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */ #define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */ #define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */ /** * @} */ #endif /* RCC_PLLSAICFGR_PLLSAIP */ #endif /* RCC_PLLSAI_SUPPORT */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros * @{ */ /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros * @{ */ /** * @brief Write a value in RCC register * @param __REG__ Register to be written * @param __VALUE__ Value to be written in the register * @retval None */ #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) /** * @brief Read a value in RCC register * @param __REG__ Register to be read * @retval Register value */ #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) /** * @} */ /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies * @{ */ /** * @brief Helper macro to calculate the PLLCLK frequency on system domain * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLM__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLM_DIV_2 * @arg @ref LL_RCC_PLLM_DIV_3 * @arg @ref LL_RCC_PLLM_DIV_4 * @arg @ref LL_RCC_PLLM_DIV_5 * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 * @arg @ref LL_RCC_PLLM_DIV_9 * @arg @ref LL_RCC_PLLM_DIV_10 * @arg @ref LL_RCC_PLLM_DIV_11 * @arg @ref LL_RCC_PLLM_DIV_12 * @arg @ref LL_RCC_PLLM_DIV_13 * @arg @ref LL_RCC_PLLM_DIV_14 * @arg @ref LL_RCC_PLLM_DIV_15 * @arg @ref LL_RCC_PLLM_DIV_16 * @arg @ref LL_RCC_PLLM_DIV_17 * @arg @ref LL_RCC_PLLM_DIV_18 * @arg @ref LL_RCC_PLLM_DIV_19 * @arg @ref LL_RCC_PLLM_DIV_20 * @arg @ref LL_RCC_PLLM_DIV_21 * @arg @ref LL_RCC_PLLM_DIV_22 * @arg @ref LL_RCC_PLLM_DIV_23 * @arg @ref LL_RCC_PLLM_DIV_24 * @arg @ref LL_RCC_PLLM_DIV_25 * @arg @ref LL_RCC_PLLM_DIV_26 * @arg @ref LL_RCC_PLLM_DIV_27 * @arg @ref LL_RCC_PLLM_DIV_28 * @arg @ref LL_RCC_PLLM_DIV_29 * @arg @ref LL_RCC_PLLM_DIV_30 * @arg @ref LL_RCC_PLLM_DIV_31 * @arg @ref LL_RCC_PLLM_DIV_32 * @arg @ref LL_RCC_PLLM_DIV_33 * @arg @ref LL_RCC_PLLM_DIV_34 * @arg @ref LL_RCC_PLLM_DIV_35 * @arg @ref LL_RCC_PLLM_DIV_36 * @arg @ref LL_RCC_PLLM_DIV_37 * @arg @ref LL_RCC_PLLM_DIV_38 * @arg @ref LL_RCC_PLLM_DIV_39 * @arg @ref LL_RCC_PLLM_DIV_40 * @arg @ref LL_RCC_PLLM_DIV_41 * @arg @ref LL_RCC_PLLM_DIV_42 * @arg @ref LL_RCC_PLLM_DIV_43 * @arg @ref LL_RCC_PLLM_DIV_44 * @arg @ref LL_RCC_PLLM_DIV_45 * @arg @ref LL_RCC_PLLM_DIV_46 * @arg @ref LL_RCC_PLLM_DIV_47 * @arg @ref LL_RCC_PLLM_DIV_48 * @arg @ref LL_RCC_PLLM_DIV_49 * @arg @ref LL_RCC_PLLM_DIV_50 * @arg @ref LL_RCC_PLLM_DIV_51 * @arg @ref LL_RCC_PLLM_DIV_52 * @arg @ref LL_RCC_PLLM_DIV_53 * @arg @ref LL_RCC_PLLM_DIV_54 * @arg @ref LL_RCC_PLLM_DIV_55 * @arg @ref LL_RCC_PLLM_DIV_56 * @arg @ref LL_RCC_PLLM_DIV_57 * @arg @ref LL_RCC_PLLM_DIV_58 * @arg @ref LL_RCC_PLLM_DIV_59 * @arg @ref LL_RCC_PLLM_DIV_60 * @arg @ref LL_RCC_PLLM_DIV_61 * @arg @ref LL_RCC_PLLM_DIV_62 * @arg @ref LL_RCC_PLLM_DIV_63 * @param __PLLN__ Between 50/192(*) and 432 * * (*) value not defined in all devices. * @param __PLLP__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLP_DIV_2 * @arg @ref LL_RCC_PLLP_DIV_4 * @arg @ref LL_RCC_PLLP_DIV_6 * @arg @ref LL_RCC_PLLP_DIV_8 * @retval PLL clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U)) #if defined(RCC_PLLR_SYSCLK_SUPPORT) /** * @brief Helper macro to calculate the PLLRCLK frequency on system domain * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLM__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLM_DIV_2 * @arg @ref LL_RCC_PLLM_DIV_3 * @arg @ref LL_RCC_PLLM_DIV_4 * @arg @ref LL_RCC_PLLM_DIV_5 * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 * @arg @ref LL_RCC_PLLM_DIV_9 * @arg @ref LL_RCC_PLLM_DIV_10 * @arg @ref LL_RCC_PLLM_DIV_11 * @arg @ref LL_RCC_PLLM_DIV_12 * @arg @ref LL_RCC_PLLM_DIV_13 * @arg @ref LL_RCC_PLLM_DIV_14 * @arg @ref LL_RCC_PLLM_DIV_15 * @arg @ref LL_RCC_PLLM_DIV_16 * @arg @ref LL_RCC_PLLM_DIV_17 * @arg @ref LL_RCC_PLLM_DIV_18 * @arg @ref LL_RCC_PLLM_DIV_19 * @arg @ref LL_RCC_PLLM_DIV_20 * @arg @ref LL_RCC_PLLM_DIV_21 * @arg @ref LL_RCC_PLLM_DIV_22 * @arg @ref LL_RCC_PLLM_DIV_23 * @arg @ref LL_RCC_PLLM_DIV_24 * @arg @ref LL_RCC_PLLM_DIV_25 * @arg @ref LL_RCC_PLLM_DIV_26 * @arg @ref LL_RCC_PLLM_DIV_27 * @arg @ref LL_RCC_PLLM_DIV_28 * @arg @ref LL_RCC_PLLM_DIV_29 * @arg @ref LL_RCC_PLLM_DIV_30 * @arg @ref LL_RCC_PLLM_DIV_31 * @arg @ref LL_RCC_PLLM_DIV_32 * @arg @ref LL_RCC_PLLM_DIV_33 * @arg @ref LL_RCC_PLLM_DIV_34 * @arg @ref LL_RCC_PLLM_DIV_35 * @arg @ref LL_RCC_PLLM_DIV_36 * @arg @ref LL_RCC_PLLM_DIV_37 * @arg @ref LL_RCC_PLLM_DIV_38 * @arg @ref LL_RCC_PLLM_DIV_39 * @arg @ref LL_RCC_PLLM_DIV_40 * @arg @ref LL_RCC_PLLM_DIV_41 * @arg @ref LL_RCC_PLLM_DIV_42 * @arg @ref LL_RCC_PLLM_DIV_43 * @arg @ref LL_RCC_PLLM_DIV_44 * @arg @ref LL_RCC_PLLM_DIV_45 * @arg @ref LL_RCC_PLLM_DIV_46 * @arg @ref LL_RCC_PLLM_DIV_47 * @arg @ref LL_RCC_PLLM_DIV_48 * @arg @ref LL_RCC_PLLM_DIV_49 * @arg @ref LL_RCC_PLLM_DIV_50 * @arg @ref LL_RCC_PLLM_DIV_51 * @arg @ref LL_RCC_PLLM_DIV_52 * @arg @ref LL_RCC_PLLM_DIV_53 * @arg @ref LL_RCC_PLLM_DIV_54 * @arg @ref LL_RCC_PLLM_DIV_55 * @arg @ref LL_RCC_PLLM_DIV_56 * @arg @ref LL_RCC_PLLM_DIV_57 * @arg @ref LL_RCC_PLLM_DIV_58 * @arg @ref LL_RCC_PLLM_DIV_59 * @arg @ref LL_RCC_PLLM_DIV_60 * @arg @ref LL_RCC_PLLM_DIV_61 * @arg @ref LL_RCC_PLLM_DIV_62 * @arg @ref LL_RCC_PLLM_DIV_63 * @param __PLLN__ Between 50 and 432 * @param __PLLR__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 * @arg @ref LL_RCC_PLLR_DIV_3 * @arg @ref LL_RCC_PLLR_DIV_4 * @arg @ref LL_RCC_PLLR_DIV_5 * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_7 * @retval PLL clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) #endif /* RCC_PLLR_SYSCLK_SUPPORT */ /** * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLM__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLM_DIV_2 * @arg @ref LL_RCC_PLLM_DIV_3 * @arg @ref LL_RCC_PLLM_DIV_4 * @arg @ref LL_RCC_PLLM_DIV_5 * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 * @arg @ref LL_RCC_PLLM_DIV_9 * @arg @ref LL_RCC_PLLM_DIV_10 * @arg @ref LL_RCC_PLLM_DIV_11 * @arg @ref LL_RCC_PLLM_DIV_12 * @arg @ref LL_RCC_PLLM_DIV_13 * @arg @ref LL_RCC_PLLM_DIV_14 * @arg @ref LL_RCC_PLLM_DIV_15 * @arg @ref LL_RCC_PLLM_DIV_16 * @arg @ref LL_RCC_PLLM_DIV_17 * @arg @ref LL_RCC_PLLM_DIV_18 * @arg @ref LL_RCC_PLLM_DIV_19 * @arg @ref LL_RCC_PLLM_DIV_20 * @arg @ref LL_RCC_PLLM_DIV_21 * @arg @ref LL_RCC_PLLM_DIV_22 * @arg @ref LL_RCC_PLLM_DIV_23 * @arg @ref LL_RCC_PLLM_DIV_24 * @arg @ref LL_RCC_PLLM_DIV_25 * @arg @ref LL_RCC_PLLM_DIV_26 * @arg @ref LL_RCC_PLLM_DIV_27 * @arg @ref LL_RCC_PLLM_DIV_28 * @arg @ref LL_RCC_PLLM_DIV_29 * @arg @ref LL_RCC_PLLM_DIV_30 * @arg @ref LL_RCC_PLLM_DIV_31 * @arg @ref LL_RCC_PLLM_DIV_32 * @arg @ref LL_RCC_PLLM_DIV_33 * @arg @ref LL_RCC_PLLM_DIV_34 * @arg @ref LL_RCC_PLLM_DIV_35 * @arg @ref LL_RCC_PLLM_DIV_36 * @arg @ref LL_RCC_PLLM_DIV_37 * @arg @ref LL_RCC_PLLM_DIV_38 * @arg @ref LL_RCC_PLLM_DIV_39 * @arg @ref LL_RCC_PLLM_DIV_40 * @arg @ref LL_RCC_PLLM_DIV_41 * @arg @ref LL_RCC_PLLM_DIV_42 * @arg @ref LL_RCC_PLLM_DIV_43 * @arg @ref LL_RCC_PLLM_DIV_44 * @arg @ref LL_RCC_PLLM_DIV_45 * @arg @ref LL_RCC_PLLM_DIV_46 * @arg @ref LL_RCC_PLLM_DIV_47 * @arg @ref LL_RCC_PLLM_DIV_48 * @arg @ref LL_RCC_PLLM_DIV_49 * @arg @ref LL_RCC_PLLM_DIV_50 * @arg @ref LL_RCC_PLLM_DIV_51 * @arg @ref LL_RCC_PLLM_DIV_52 * @arg @ref LL_RCC_PLLM_DIV_53 * @arg @ref LL_RCC_PLLM_DIV_54 * @arg @ref LL_RCC_PLLM_DIV_55 * @arg @ref LL_RCC_PLLM_DIV_56 * @arg @ref LL_RCC_PLLM_DIV_57 * @arg @ref LL_RCC_PLLM_DIV_58 * @arg @ref LL_RCC_PLLM_DIV_59 * @arg @ref LL_RCC_PLLM_DIV_60 * @arg @ref LL_RCC_PLLM_DIV_61 * @arg @ref LL_RCC_PLLM_DIV_62 * @arg @ref LL_RCC_PLLM_DIV_63 * @param __PLLN__ Between 50/192(*) and 432 * * (*) value not defined in all devices. * @param __PLLQ__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLQ_DIV_2 * @arg @ref LL_RCC_PLLQ_DIV_3 * @arg @ref LL_RCC_PLLQ_DIV_4 * @arg @ref LL_RCC_PLLQ_DIV_5 * @arg @ref LL_RCC_PLLQ_DIV_6 * @arg @ref LL_RCC_PLLQ_DIV_7 * @arg @ref LL_RCC_PLLQ_DIV_8 * @arg @ref LL_RCC_PLLQ_DIV_9 * @arg @ref LL_RCC_PLLQ_DIV_10 * @arg @ref LL_RCC_PLLQ_DIV_11 * @arg @ref LL_RCC_PLLQ_DIV_12 * @arg @ref LL_RCC_PLLQ_DIV_13 * @arg @ref LL_RCC_PLLQ_DIV_14 * @arg @ref LL_RCC_PLLQ_DIV_15 * @retval PLL clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos )) #if defined(DSI) /** * @brief Helper macro to calculate the PLLCLK frequency used on DSI * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLM__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLM_DIV_2 * @arg @ref LL_RCC_PLLM_DIV_3 * @arg @ref LL_RCC_PLLM_DIV_4 * @arg @ref LL_RCC_PLLM_DIV_5 * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 * @arg @ref LL_RCC_PLLM_DIV_9 * @arg @ref LL_RCC_PLLM_DIV_10 * @arg @ref LL_RCC_PLLM_DIV_11 * @arg @ref LL_RCC_PLLM_DIV_12 * @arg @ref LL_RCC_PLLM_DIV_13 * @arg @ref LL_RCC_PLLM_DIV_14 * @arg @ref LL_RCC_PLLM_DIV_15 * @arg @ref LL_RCC_PLLM_DIV_16 * @arg @ref LL_RCC_PLLM_DIV_17 * @arg @ref LL_RCC_PLLM_DIV_18 * @arg @ref LL_RCC_PLLM_DIV_19 * @arg @ref LL_RCC_PLLM_DIV_20 * @arg @ref LL_RCC_PLLM_DIV_21 * @arg @ref LL_RCC_PLLM_DIV_22 * @arg @ref LL_RCC_PLLM_DIV_23 * @arg @ref LL_RCC_PLLM_DIV_24 * @arg @ref LL_RCC_PLLM_DIV_25 * @arg @ref LL_RCC_PLLM_DIV_26 * @arg @ref LL_RCC_PLLM_DIV_27 * @arg @ref LL_RCC_PLLM_DIV_28 * @arg @ref LL_RCC_PLLM_DIV_29 * @arg @ref LL_RCC_PLLM_DIV_30 * @arg @ref LL_RCC_PLLM_DIV_31 * @arg @ref LL_RCC_PLLM_DIV_32 * @arg @ref LL_RCC_PLLM_DIV_33 * @arg @ref LL_RCC_PLLM_DIV_34 * @arg @ref LL_RCC_PLLM_DIV_35 * @arg @ref LL_RCC_PLLM_DIV_36 * @arg @ref LL_RCC_PLLM_DIV_37 * @arg @ref LL_RCC_PLLM_DIV_38 * @arg @ref LL_RCC_PLLM_DIV_39 * @arg @ref LL_RCC_PLLM_DIV_40 * @arg @ref LL_RCC_PLLM_DIV_41 * @arg @ref LL_RCC_PLLM_DIV_42 * @arg @ref LL_RCC_PLLM_DIV_43 * @arg @ref LL_RCC_PLLM_DIV_44 * @arg @ref LL_RCC_PLLM_DIV_45 * @arg @ref LL_RCC_PLLM_DIV_46 * @arg @ref LL_RCC_PLLM_DIV_47 * @arg @ref LL_RCC_PLLM_DIV_48 * @arg @ref LL_RCC_PLLM_DIV_49 * @arg @ref LL_RCC_PLLM_DIV_50 * @arg @ref LL_RCC_PLLM_DIV_51 * @arg @ref LL_RCC_PLLM_DIV_52 * @arg @ref LL_RCC_PLLM_DIV_53 * @arg @ref LL_RCC_PLLM_DIV_54 * @arg @ref LL_RCC_PLLM_DIV_55 * @arg @ref LL_RCC_PLLM_DIV_56 * @arg @ref LL_RCC_PLLM_DIV_57 * @arg @ref LL_RCC_PLLM_DIV_58 * @arg @ref LL_RCC_PLLM_DIV_59 * @arg @ref LL_RCC_PLLM_DIV_60 * @arg @ref LL_RCC_PLLM_DIV_61 * @arg @ref LL_RCC_PLLM_DIV_62 * @arg @ref LL_RCC_PLLM_DIV_63 * @param __PLLN__ Between 50 and 432 * @param __PLLR__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 * @arg @ref LL_RCC_PLLR_DIV_3 * @arg @ref LL_RCC_PLLR_DIV_4 * @arg @ref LL_RCC_PLLR_DIV_5 * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_7 * @retval PLL clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) #endif /* DSI */ #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT) /** * @brief Helper macro to calculate the PLLCLK frequency used on I2S * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLM__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLM_DIV_2 * @arg @ref LL_RCC_PLLM_DIV_3 * @arg @ref LL_RCC_PLLM_DIV_4 * @arg @ref LL_RCC_PLLM_DIV_5 * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 * @arg @ref LL_RCC_PLLM_DIV_9 * @arg @ref LL_RCC_PLLM_DIV_10 * @arg @ref LL_RCC_PLLM_DIV_11 * @arg @ref LL_RCC_PLLM_DIV_12 * @arg @ref LL_RCC_PLLM_DIV_13 * @arg @ref LL_RCC_PLLM_DIV_14 * @arg @ref LL_RCC_PLLM_DIV_15 * @arg @ref LL_RCC_PLLM_DIV_16 * @arg @ref LL_RCC_PLLM_DIV_17 * @arg @ref LL_RCC_PLLM_DIV_18 * @arg @ref LL_RCC_PLLM_DIV_19 * @arg @ref LL_RCC_PLLM_DIV_20 * @arg @ref LL_RCC_PLLM_DIV_21 * @arg @ref LL_RCC_PLLM_DIV_22 * @arg @ref LL_RCC_PLLM_DIV_23 * @arg @ref LL_RCC_PLLM_DIV_24 * @arg @ref LL_RCC_PLLM_DIV_25 * @arg @ref LL_RCC_PLLM_DIV_26 * @arg @ref LL_RCC_PLLM_DIV_27 * @arg @ref LL_RCC_PLLM_DIV_28 * @arg @ref LL_RCC_PLLM_DIV_29 * @arg @ref LL_RCC_PLLM_DIV_30 * @arg @ref LL_RCC_PLLM_DIV_31 * @arg @ref LL_RCC_PLLM_DIV_32 * @arg @ref LL_RCC_PLLM_DIV_33 * @arg @ref LL_RCC_PLLM_DIV_34 * @arg @ref LL_RCC_PLLM_DIV_35 * @arg @ref LL_RCC_PLLM_DIV_36 * @arg @ref LL_RCC_PLLM_DIV_37 * @arg @ref LL_RCC_PLLM_DIV_38 * @arg @ref LL_RCC_PLLM_DIV_39 * @arg @ref LL_RCC_PLLM_DIV_40 * @arg @ref LL_RCC_PLLM_DIV_41 * @arg @ref LL_RCC_PLLM_DIV_42 * @arg @ref LL_RCC_PLLM_DIV_43 * @arg @ref LL_RCC_PLLM_DIV_44 * @arg @ref LL_RCC_PLLM_DIV_45 * @arg @ref LL_RCC_PLLM_DIV_46 * @arg @ref LL_RCC_PLLM_DIV_47 * @arg @ref LL_RCC_PLLM_DIV_48 * @arg @ref LL_RCC_PLLM_DIV_49 * @arg @ref LL_RCC_PLLM_DIV_50 * @arg @ref LL_RCC_PLLM_DIV_51 * @arg @ref LL_RCC_PLLM_DIV_52 * @arg @ref LL_RCC_PLLM_DIV_53 * @arg @ref LL_RCC_PLLM_DIV_54 * @arg @ref LL_RCC_PLLM_DIV_55 * @arg @ref LL_RCC_PLLM_DIV_56 * @arg @ref LL_RCC_PLLM_DIV_57 * @arg @ref LL_RCC_PLLM_DIV_58 * @arg @ref LL_RCC_PLLM_DIV_59 * @arg @ref LL_RCC_PLLM_DIV_60 * @arg @ref LL_RCC_PLLM_DIV_61 * @arg @ref LL_RCC_PLLM_DIV_62 * @arg @ref LL_RCC_PLLM_DIV_63 * @param __PLLN__ Between 50 and 432 * @param __PLLR__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 * @arg @ref LL_RCC_PLLR_DIV_3 * @arg @ref LL_RCC_PLLR_DIV_4 * @arg @ref LL_RCC_PLLR_DIV_5 * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_7 * @retval PLL clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */ #if defined(SPDIFRX) /** * @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLM__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLM_DIV_2 * @arg @ref LL_RCC_PLLM_DIV_3 * @arg @ref LL_RCC_PLLM_DIV_4 * @arg @ref LL_RCC_PLLM_DIV_5 * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 * @arg @ref LL_RCC_PLLM_DIV_9 * @arg @ref LL_RCC_PLLM_DIV_10 * @arg @ref LL_RCC_PLLM_DIV_11 * @arg @ref LL_RCC_PLLM_DIV_12 * @arg @ref LL_RCC_PLLM_DIV_13 * @arg @ref LL_RCC_PLLM_DIV_14 * @arg @ref LL_RCC_PLLM_DIV_15 * @arg @ref LL_RCC_PLLM_DIV_16 * @arg @ref LL_RCC_PLLM_DIV_17 * @arg @ref LL_RCC_PLLM_DIV_18 * @arg @ref LL_RCC_PLLM_DIV_19 * @arg @ref LL_RCC_PLLM_DIV_20 * @arg @ref LL_RCC_PLLM_DIV_21 * @arg @ref LL_RCC_PLLM_DIV_22 * @arg @ref LL_RCC_PLLM_DIV_23 * @arg @ref LL_RCC_PLLM_DIV_24 * @arg @ref LL_RCC_PLLM_DIV_25 * @arg @ref LL_RCC_PLLM_DIV_26 * @arg @ref LL_RCC_PLLM_DIV_27 * @arg @ref LL_RCC_PLLM_DIV_28 * @arg @ref LL_RCC_PLLM_DIV_29 * @arg @ref LL_RCC_PLLM_DIV_30 * @arg @ref LL_RCC_PLLM_DIV_31 * @arg @ref LL_RCC_PLLM_DIV_32 * @arg @ref LL_RCC_PLLM_DIV_33 * @arg @ref LL_RCC_PLLM_DIV_34 * @arg @ref LL_RCC_PLLM_DIV_35 * @arg @ref LL_RCC_PLLM_DIV_36 * @arg @ref LL_RCC_PLLM_DIV_37 * @arg @ref LL_RCC_PLLM_DIV_38 * @arg @ref LL_RCC_PLLM_DIV_39 * @arg @ref LL_RCC_PLLM_DIV_40 * @arg @ref LL_RCC_PLLM_DIV_41 * @arg @ref LL_RCC_PLLM_DIV_42 * @arg @ref LL_RCC_PLLM_DIV_43 * @arg @ref LL_RCC_PLLM_DIV_44 * @arg @ref LL_RCC_PLLM_DIV_45 * @arg @ref LL_RCC_PLLM_DIV_46 * @arg @ref LL_RCC_PLLM_DIV_47 * @arg @ref LL_RCC_PLLM_DIV_48 * @arg @ref LL_RCC_PLLM_DIV_49 * @arg @ref LL_RCC_PLLM_DIV_50 * @arg @ref LL_RCC_PLLM_DIV_51 * @arg @ref LL_RCC_PLLM_DIV_52 * @arg @ref LL_RCC_PLLM_DIV_53 * @arg @ref LL_RCC_PLLM_DIV_54 * @arg @ref LL_RCC_PLLM_DIV_55 * @arg @ref LL_RCC_PLLM_DIV_56 * @arg @ref LL_RCC_PLLM_DIV_57 * @arg @ref LL_RCC_PLLM_DIV_58 * @arg @ref LL_RCC_PLLM_DIV_59 * @arg @ref LL_RCC_PLLM_DIV_60 * @arg @ref LL_RCC_PLLM_DIV_61 * @arg @ref LL_RCC_PLLM_DIV_62 * @arg @ref LL_RCC_PLLM_DIV_63 * @param __PLLN__ Between 50 and 432 * @param __PLLR__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 * @arg @ref LL_RCC_PLLR_DIV_3 * @arg @ref LL_RCC_PLLR_DIV_4 * @arg @ref LL_RCC_PLLR_DIV_5 * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_7 * @retval PLL clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) #endif /* SPDIFRX */ #if defined(RCC_PLLCFGR_PLLR) #if defined(SAI1) /** * @brief Helper macro to calculate the PLLCLK frequency used on SAI * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLM__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLM_DIV_2 * @arg @ref LL_RCC_PLLM_DIV_3 * @arg @ref LL_RCC_PLLM_DIV_4 * @arg @ref LL_RCC_PLLM_DIV_5 * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 * @arg @ref LL_RCC_PLLM_DIV_9 * @arg @ref LL_RCC_PLLM_DIV_10 * @arg @ref LL_RCC_PLLM_DIV_11 * @arg @ref LL_RCC_PLLM_DIV_12 * @arg @ref LL_RCC_PLLM_DIV_13 * @arg @ref LL_RCC_PLLM_DIV_14 * @arg @ref LL_RCC_PLLM_DIV_15 * @arg @ref LL_RCC_PLLM_DIV_16 * @arg @ref LL_RCC_PLLM_DIV_17 * @arg @ref LL_RCC_PLLM_DIV_18 * @arg @ref LL_RCC_PLLM_DIV_19 * @arg @ref LL_RCC_PLLM_DIV_20 * @arg @ref LL_RCC_PLLM_DIV_21 * @arg @ref LL_RCC_PLLM_DIV_22 * @arg @ref LL_RCC_PLLM_DIV_23 * @arg @ref LL_RCC_PLLM_DIV_24 * @arg @ref LL_RCC_PLLM_DIV_25 * @arg @ref LL_RCC_PLLM_DIV_26 * @arg @ref LL_RCC_PLLM_DIV_27 * @arg @ref LL_RCC_PLLM_DIV_28 * @arg @ref LL_RCC_PLLM_DIV_29 * @arg @ref LL_RCC_PLLM_DIV_30 * @arg @ref LL_RCC_PLLM_DIV_31 * @arg @ref LL_RCC_PLLM_DIV_32 * @arg @ref LL_RCC_PLLM_DIV_33 * @arg @ref LL_RCC_PLLM_DIV_34 * @arg @ref LL_RCC_PLLM_DIV_35 * @arg @ref LL_RCC_PLLM_DIV_36 * @arg @ref LL_RCC_PLLM_DIV_37 * @arg @ref LL_RCC_PLLM_DIV_38 * @arg @ref LL_RCC_PLLM_DIV_39 * @arg @ref LL_RCC_PLLM_DIV_40 * @arg @ref LL_RCC_PLLM_DIV_41 * @arg @ref LL_RCC_PLLM_DIV_42 * @arg @ref LL_RCC_PLLM_DIV_43 * @arg @ref LL_RCC_PLLM_DIV_44 * @arg @ref LL_RCC_PLLM_DIV_45 * @arg @ref LL_RCC_PLLM_DIV_46 * @arg @ref LL_RCC_PLLM_DIV_47 * @arg @ref LL_RCC_PLLM_DIV_48 * @arg @ref LL_RCC_PLLM_DIV_49 * @arg @ref LL_RCC_PLLM_DIV_50 * @arg @ref LL_RCC_PLLM_DIV_51 * @arg @ref LL_RCC_PLLM_DIV_52 * @arg @ref LL_RCC_PLLM_DIV_53 * @arg @ref LL_RCC_PLLM_DIV_54 * @arg @ref LL_RCC_PLLM_DIV_55 * @arg @ref LL_RCC_PLLM_DIV_56 * @arg @ref LL_RCC_PLLM_DIV_57 * @arg @ref LL_RCC_PLLM_DIV_58 * @arg @ref LL_RCC_PLLM_DIV_59 * @arg @ref LL_RCC_PLLM_DIV_60 * @arg @ref LL_RCC_PLLM_DIV_61 * @arg @ref LL_RCC_PLLM_DIV_62 * @arg @ref LL_RCC_PLLM_DIV_63 * @param __PLLN__ Between 50 and 432 * @param __PLLR__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 * @arg @ref LL_RCC_PLLR_DIV_3 * @arg @ref LL_RCC_PLLR_DIV_4 * @arg @ref LL_RCC_PLLR_DIV_5 * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_7 * @param __PLLDIVR__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*) * * (*) value not defined in all devices. * @retval PLL clock frequency (in Hz) */ #if defined(RCC_DCKCFGR_PLLDIVR) #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos )) #else #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) #endif /* RCC_DCKCFGR_PLLDIVR */ #endif /* SAI1 */ #endif /* RCC_PLLCFGR_PLLR */ #if defined(RCC_PLLSAI_SUPPORT) /** * @brief Helper macro to calculate the PLLSAI frequency used for SAI domain * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLM__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIM_DIV_2 * @arg @ref LL_RCC_PLLSAIM_DIV_3 * @arg @ref LL_RCC_PLLSAIM_DIV_4 * @arg @ref LL_RCC_PLLSAIM_DIV_5 * @arg @ref LL_RCC_PLLSAIM_DIV_6 * @arg @ref LL_RCC_PLLSAIM_DIV_7 * @arg @ref LL_RCC_PLLSAIM_DIV_8 * @arg @ref LL_RCC_PLLSAIM_DIV_9 * @arg @ref LL_RCC_PLLSAIM_DIV_10 * @arg @ref LL_RCC_PLLSAIM_DIV_11 * @arg @ref LL_RCC_PLLSAIM_DIV_12 * @arg @ref LL_RCC_PLLSAIM_DIV_13 * @arg @ref LL_RCC_PLLSAIM_DIV_14 * @arg @ref LL_RCC_PLLSAIM_DIV_15 * @arg @ref LL_RCC_PLLSAIM_DIV_16 * @arg @ref LL_RCC_PLLSAIM_DIV_17 * @arg @ref LL_RCC_PLLSAIM_DIV_18 * @arg @ref LL_RCC_PLLSAIM_DIV_19 * @arg @ref LL_RCC_PLLSAIM_DIV_20 * @arg @ref LL_RCC_PLLSAIM_DIV_21 * @arg @ref LL_RCC_PLLSAIM_DIV_22 * @arg @ref LL_RCC_PLLSAIM_DIV_23 * @arg @ref LL_RCC_PLLSAIM_DIV_24 * @arg @ref LL_RCC_PLLSAIM_DIV_25 * @arg @ref LL_RCC_PLLSAIM_DIV_26 * @arg @ref LL_RCC_PLLSAIM_DIV_27 * @arg @ref LL_RCC_PLLSAIM_DIV_28 * @arg @ref LL_RCC_PLLSAIM_DIV_29 * @arg @ref LL_RCC_PLLSAIM_DIV_30 * @arg @ref LL_RCC_PLLSAIM_DIV_31 * @arg @ref LL_RCC_PLLSAIM_DIV_32 * @arg @ref LL_RCC_PLLSAIM_DIV_33 * @arg @ref LL_RCC_PLLSAIM_DIV_34 * @arg @ref LL_RCC_PLLSAIM_DIV_35 * @arg @ref LL_RCC_PLLSAIM_DIV_36 * @arg @ref LL_RCC_PLLSAIM_DIV_37 * @arg @ref LL_RCC_PLLSAIM_DIV_38 * @arg @ref LL_RCC_PLLSAIM_DIV_39 * @arg @ref LL_RCC_PLLSAIM_DIV_40 * @arg @ref LL_RCC_PLLSAIM_DIV_41 * @arg @ref LL_RCC_PLLSAIM_DIV_42 * @arg @ref LL_RCC_PLLSAIM_DIV_43 * @arg @ref LL_RCC_PLLSAIM_DIV_44 * @arg @ref LL_RCC_PLLSAIM_DIV_45 * @arg @ref LL_RCC_PLLSAIM_DIV_46 * @arg @ref LL_RCC_PLLSAIM_DIV_47 * @arg @ref LL_RCC_PLLSAIM_DIV_48 * @arg @ref LL_RCC_PLLSAIM_DIV_49 * @arg @ref LL_RCC_PLLSAIM_DIV_50 * @arg @ref LL_RCC_PLLSAIM_DIV_51 * @arg @ref LL_RCC_PLLSAIM_DIV_52 * @arg @ref LL_RCC_PLLSAIM_DIV_53 * @arg @ref LL_RCC_PLLSAIM_DIV_54 * @arg @ref LL_RCC_PLLSAIM_DIV_55 * @arg @ref LL_RCC_PLLSAIM_DIV_56 * @arg @ref LL_RCC_PLLSAIM_DIV_57 * @arg @ref LL_RCC_PLLSAIM_DIV_58 * @arg @ref LL_RCC_PLLSAIM_DIV_59 * @arg @ref LL_RCC_PLLSAIM_DIV_60 * @arg @ref LL_RCC_PLLSAIM_DIV_61 * @arg @ref LL_RCC_PLLSAIM_DIV_62 * @arg @ref LL_RCC_PLLSAIM_DIV_63 * @param __PLLSAIN__ Between 49/50(*) and 432 * * (*) value not defined in all devices. * @param __PLLSAIQ__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIQ_DIV_2 * @arg @ref LL_RCC_PLLSAIQ_DIV_3 * @arg @ref LL_RCC_PLLSAIQ_DIV_4 * @arg @ref LL_RCC_PLLSAIQ_DIV_5 * @arg @ref LL_RCC_PLLSAIQ_DIV_6 * @arg @ref LL_RCC_PLLSAIQ_DIV_7 * @arg @ref LL_RCC_PLLSAIQ_DIV_8 * @arg @ref LL_RCC_PLLSAIQ_DIV_9 * @arg @ref LL_RCC_PLLSAIQ_DIV_10 * @arg @ref LL_RCC_PLLSAIQ_DIV_11 * @arg @ref LL_RCC_PLLSAIQ_DIV_12 * @arg @ref LL_RCC_PLLSAIQ_DIV_13 * @arg @ref LL_RCC_PLLSAIQ_DIV_14 * @arg @ref LL_RCC_PLLSAIQ_DIV_15 * @param __PLLSAIDIVQ__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 * @retval PLLSAI clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U))) #if defined(RCC_PLLSAICFGR_PLLSAIP) /** * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLM__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIM_DIV_2 * @arg @ref LL_RCC_PLLSAIM_DIV_3 * @arg @ref LL_RCC_PLLSAIM_DIV_4 * @arg @ref LL_RCC_PLLSAIM_DIV_5 * @arg @ref LL_RCC_PLLSAIM_DIV_6 * @arg @ref LL_RCC_PLLSAIM_DIV_7 * @arg @ref LL_RCC_PLLSAIM_DIV_8 * @arg @ref LL_RCC_PLLSAIM_DIV_9 * @arg @ref LL_RCC_PLLSAIM_DIV_10 * @arg @ref LL_RCC_PLLSAIM_DIV_11 * @arg @ref LL_RCC_PLLSAIM_DIV_12 * @arg @ref LL_RCC_PLLSAIM_DIV_13 * @arg @ref LL_RCC_PLLSAIM_DIV_14 * @arg @ref LL_RCC_PLLSAIM_DIV_15 * @arg @ref LL_RCC_PLLSAIM_DIV_16 * @arg @ref LL_RCC_PLLSAIM_DIV_17 * @arg @ref LL_RCC_PLLSAIM_DIV_18 * @arg @ref LL_RCC_PLLSAIM_DIV_19 * @arg @ref LL_RCC_PLLSAIM_DIV_20 * @arg @ref LL_RCC_PLLSAIM_DIV_21 * @arg @ref LL_RCC_PLLSAIM_DIV_22 * @arg @ref LL_RCC_PLLSAIM_DIV_23 * @arg @ref LL_RCC_PLLSAIM_DIV_24 * @arg @ref LL_RCC_PLLSAIM_DIV_25 * @arg @ref LL_RCC_PLLSAIM_DIV_26 * @arg @ref LL_RCC_PLLSAIM_DIV_27 * @arg @ref LL_RCC_PLLSAIM_DIV_28 * @arg @ref LL_RCC_PLLSAIM_DIV_29 * @arg @ref LL_RCC_PLLSAIM_DIV_30 * @arg @ref LL_RCC_PLLSAIM_DIV_31 * @arg @ref LL_RCC_PLLSAIM_DIV_32 * @arg @ref LL_RCC_PLLSAIM_DIV_33 * @arg @ref LL_RCC_PLLSAIM_DIV_34 * @arg @ref LL_RCC_PLLSAIM_DIV_35 * @arg @ref LL_RCC_PLLSAIM_DIV_36 * @arg @ref LL_RCC_PLLSAIM_DIV_37 * @arg @ref LL_RCC_PLLSAIM_DIV_38 * @arg @ref LL_RCC_PLLSAIM_DIV_39 * @arg @ref LL_RCC_PLLSAIM_DIV_40 * @arg @ref LL_RCC_PLLSAIM_DIV_41 * @arg @ref LL_RCC_PLLSAIM_DIV_42 * @arg @ref LL_RCC_PLLSAIM_DIV_43 * @arg @ref LL_RCC_PLLSAIM_DIV_44 * @arg @ref LL_RCC_PLLSAIM_DIV_45 * @arg @ref LL_RCC_PLLSAIM_DIV_46 * @arg @ref LL_RCC_PLLSAIM_DIV_47 * @arg @ref LL_RCC_PLLSAIM_DIV_48 * @arg @ref LL_RCC_PLLSAIM_DIV_49 * @arg @ref LL_RCC_PLLSAIM_DIV_50 * @arg @ref LL_RCC_PLLSAIM_DIV_51 * @arg @ref LL_RCC_PLLSAIM_DIV_52 * @arg @ref LL_RCC_PLLSAIM_DIV_53 * @arg @ref LL_RCC_PLLSAIM_DIV_54 * @arg @ref LL_RCC_PLLSAIM_DIV_55 * @arg @ref LL_RCC_PLLSAIM_DIV_56 * @arg @ref LL_RCC_PLLSAIM_DIV_57 * @arg @ref LL_RCC_PLLSAIM_DIV_58 * @arg @ref LL_RCC_PLLSAIM_DIV_59 * @arg @ref LL_RCC_PLLSAIM_DIV_60 * @arg @ref LL_RCC_PLLSAIM_DIV_61 * @arg @ref LL_RCC_PLLSAIM_DIV_62 * @arg @ref LL_RCC_PLLSAIM_DIV_63 * @param __PLLSAIN__ Between 50 and 432 * @param __PLLSAIP__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIP_DIV_2 * @arg @ref LL_RCC_PLLSAIP_DIV_4 * @arg @ref LL_RCC_PLLSAIP_DIV_6 * @arg @ref LL_RCC_PLLSAIP_DIV_8 * @retval PLLSAI clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U)) #endif /* RCC_PLLSAICFGR_PLLSAIP */ #if defined(LTDC) /** * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLM__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIM_DIV_2 * @arg @ref LL_RCC_PLLSAIM_DIV_3 * @arg @ref LL_RCC_PLLSAIM_DIV_4 * @arg @ref LL_RCC_PLLSAIM_DIV_5 * @arg @ref LL_RCC_PLLSAIM_DIV_6 * @arg @ref LL_RCC_PLLSAIM_DIV_7 * @arg @ref LL_RCC_PLLSAIM_DIV_8 * @arg @ref LL_RCC_PLLSAIM_DIV_9 * @arg @ref LL_RCC_PLLSAIM_DIV_10 * @arg @ref LL_RCC_PLLSAIM_DIV_11 * @arg @ref LL_RCC_PLLSAIM_DIV_12 * @arg @ref LL_RCC_PLLSAIM_DIV_13 * @arg @ref LL_RCC_PLLSAIM_DIV_14 * @arg @ref LL_RCC_PLLSAIM_DIV_15 * @arg @ref LL_RCC_PLLSAIM_DIV_16 * @arg @ref LL_RCC_PLLSAIM_DIV_17 * @arg @ref LL_RCC_PLLSAIM_DIV_18 * @arg @ref LL_RCC_PLLSAIM_DIV_19 * @arg @ref LL_RCC_PLLSAIM_DIV_20 * @arg @ref LL_RCC_PLLSAIM_DIV_21 * @arg @ref LL_RCC_PLLSAIM_DIV_22 * @arg @ref LL_RCC_PLLSAIM_DIV_23 * @arg @ref LL_RCC_PLLSAIM_DIV_24 * @arg @ref LL_RCC_PLLSAIM_DIV_25 * @arg @ref LL_RCC_PLLSAIM_DIV_26 * @arg @ref LL_RCC_PLLSAIM_DIV_27 * @arg @ref LL_RCC_PLLSAIM_DIV_28 * @arg @ref LL_RCC_PLLSAIM_DIV_29 * @arg @ref LL_RCC_PLLSAIM_DIV_30 * @arg @ref LL_RCC_PLLSAIM_DIV_31 * @arg @ref LL_RCC_PLLSAIM_DIV_32 * @arg @ref LL_RCC_PLLSAIM_DIV_33 * @arg @ref LL_RCC_PLLSAIM_DIV_34 * @arg @ref LL_RCC_PLLSAIM_DIV_35 * @arg @ref LL_RCC_PLLSAIM_DIV_36 * @arg @ref LL_RCC_PLLSAIM_DIV_37 * @arg @ref LL_RCC_PLLSAIM_DIV_38 * @arg @ref LL_RCC_PLLSAIM_DIV_39 * @arg @ref LL_RCC_PLLSAIM_DIV_40 * @arg @ref LL_RCC_PLLSAIM_DIV_41 * @arg @ref LL_RCC_PLLSAIM_DIV_42 * @arg @ref LL_RCC_PLLSAIM_DIV_43 * @arg @ref LL_RCC_PLLSAIM_DIV_44 * @arg @ref LL_RCC_PLLSAIM_DIV_45 * @arg @ref LL_RCC_PLLSAIM_DIV_46 * @arg @ref LL_RCC_PLLSAIM_DIV_47 * @arg @ref LL_RCC_PLLSAIM_DIV_48 * @arg @ref LL_RCC_PLLSAIM_DIV_49 * @arg @ref LL_RCC_PLLSAIM_DIV_50 * @arg @ref LL_RCC_PLLSAIM_DIV_51 * @arg @ref LL_RCC_PLLSAIM_DIV_52 * @arg @ref LL_RCC_PLLSAIM_DIV_53 * @arg @ref LL_RCC_PLLSAIM_DIV_54 * @arg @ref LL_RCC_PLLSAIM_DIV_55 * @arg @ref LL_RCC_PLLSAIM_DIV_56 * @arg @ref LL_RCC_PLLSAIM_DIV_57 * @arg @ref LL_RCC_PLLSAIM_DIV_58 * @arg @ref LL_RCC_PLLSAIM_DIV_59 * @arg @ref LL_RCC_PLLSAIM_DIV_60 * @arg @ref LL_RCC_PLLSAIM_DIV_61 * @arg @ref LL_RCC_PLLSAIM_DIV_62 * @arg @ref LL_RCC_PLLSAIM_DIV_63 * @param __PLLSAIN__ Between 49/50(*) and 432 * * (*) value not defined in all devices. * @param __PLLSAIR__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIR_DIV_2 * @arg @ref LL_RCC_PLLSAIR_DIV_3 * @arg @ref LL_RCC_PLLSAIR_DIV_4 * @arg @ref LL_RCC_PLLSAIR_DIV_5 * @arg @ref LL_RCC_PLLSAIR_DIV_6 * @arg @ref LL_RCC_PLLSAIR_DIV_7 * @param __PLLSAIDIVR__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 * @retval PLLSAI clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos]))) #endif /* LTDC */ #endif /* RCC_PLLSAI_SUPPORT */ #if defined(RCC_PLLI2S_SUPPORT) #if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR) /** * @brief Helper macro to calculate the PLLI2S frequency used for SAI domain * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLM__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SM_DIV_2 * @arg @ref LL_RCC_PLLI2SM_DIV_3 * @arg @ref LL_RCC_PLLI2SM_DIV_4 * @arg @ref LL_RCC_PLLI2SM_DIV_5 * @arg @ref LL_RCC_PLLI2SM_DIV_6 * @arg @ref LL_RCC_PLLI2SM_DIV_7 * @arg @ref LL_RCC_PLLI2SM_DIV_8 * @arg @ref LL_RCC_PLLI2SM_DIV_9 * @arg @ref LL_RCC_PLLI2SM_DIV_10 * @arg @ref LL_RCC_PLLI2SM_DIV_11 * @arg @ref LL_RCC_PLLI2SM_DIV_12 * @arg @ref LL_RCC_PLLI2SM_DIV_13 * @arg @ref LL_RCC_PLLI2SM_DIV_14 * @arg @ref LL_RCC_PLLI2SM_DIV_15 * @arg @ref LL_RCC_PLLI2SM_DIV_16 * @arg @ref LL_RCC_PLLI2SM_DIV_17 * @arg @ref LL_RCC_PLLI2SM_DIV_18 * @arg @ref LL_RCC_PLLI2SM_DIV_19 * @arg @ref LL_RCC_PLLI2SM_DIV_20 * @arg @ref LL_RCC_PLLI2SM_DIV_21 * @arg @ref LL_RCC_PLLI2SM_DIV_22 * @arg @ref LL_RCC_PLLI2SM_DIV_23 * @arg @ref LL_RCC_PLLI2SM_DIV_24 * @arg @ref LL_RCC_PLLI2SM_DIV_25 * @arg @ref LL_RCC_PLLI2SM_DIV_26 * @arg @ref LL_RCC_PLLI2SM_DIV_27 * @arg @ref LL_RCC_PLLI2SM_DIV_28 * @arg @ref LL_RCC_PLLI2SM_DIV_29 * @arg @ref LL_RCC_PLLI2SM_DIV_30 * @arg @ref LL_RCC_PLLI2SM_DIV_31 * @arg @ref LL_RCC_PLLI2SM_DIV_32 * @arg @ref LL_RCC_PLLI2SM_DIV_33 * @arg @ref LL_RCC_PLLI2SM_DIV_34 * @arg @ref LL_RCC_PLLI2SM_DIV_35 * @arg @ref LL_RCC_PLLI2SM_DIV_36 * @arg @ref LL_RCC_PLLI2SM_DIV_37 * @arg @ref LL_RCC_PLLI2SM_DIV_38 * @arg @ref LL_RCC_PLLI2SM_DIV_39 * @arg @ref LL_RCC_PLLI2SM_DIV_40 * @arg @ref LL_RCC_PLLI2SM_DIV_41 * @arg @ref LL_RCC_PLLI2SM_DIV_42 * @arg @ref LL_RCC_PLLI2SM_DIV_43 * @arg @ref LL_RCC_PLLI2SM_DIV_44 * @arg @ref LL_RCC_PLLI2SM_DIV_45 * @arg @ref LL_RCC_PLLI2SM_DIV_46 * @arg @ref LL_RCC_PLLI2SM_DIV_47 * @arg @ref LL_RCC_PLLI2SM_DIV_48 * @arg @ref LL_RCC_PLLI2SM_DIV_49 * @arg @ref LL_RCC_PLLI2SM_DIV_50 * @arg @ref LL_RCC_PLLI2SM_DIV_51 * @arg @ref LL_RCC_PLLI2SM_DIV_52 * @arg @ref LL_RCC_PLLI2SM_DIV_53 * @arg @ref LL_RCC_PLLI2SM_DIV_54 * @arg @ref LL_RCC_PLLI2SM_DIV_55 * @arg @ref LL_RCC_PLLI2SM_DIV_56 * @arg @ref LL_RCC_PLLI2SM_DIV_57 * @arg @ref LL_RCC_PLLI2SM_DIV_58 * @arg @ref LL_RCC_PLLI2SM_DIV_59 * @arg @ref LL_RCC_PLLI2SM_DIV_60 * @arg @ref LL_RCC_PLLI2SM_DIV_61 * @arg @ref LL_RCC_PLLI2SM_DIV_62 * @arg @ref LL_RCC_PLLI2SM_DIV_63 * @param __PLLI2SN__ Between 50/192(*) and 432 * * (*) value not defined in all devices. * @param __PLLI2SQ_R__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*) * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*) * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*) * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*) * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*) * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*) * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*) * * (*) value not defined in all devices. * @param __PLLI2SDIVQ_R__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*) * * (*) value not defined in all devices. * @retval PLLI2S clock frequency (in Hz) */ #if defined(RCC_DCKCFGR_PLLI2SDIVQ) #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U))) #else #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos))) #endif /* RCC_DCKCFGR_PLLI2SDIVQ */ #endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */ #if defined(SPDIFRX) /** * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLM__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SM_DIV_2 * @arg @ref LL_RCC_PLLI2SM_DIV_3 * @arg @ref LL_RCC_PLLI2SM_DIV_4 * @arg @ref LL_RCC_PLLI2SM_DIV_5 * @arg @ref LL_RCC_PLLI2SM_DIV_6 * @arg @ref LL_RCC_PLLI2SM_DIV_7 * @arg @ref LL_RCC_PLLI2SM_DIV_8 * @arg @ref LL_RCC_PLLI2SM_DIV_9 * @arg @ref LL_RCC_PLLI2SM_DIV_10 * @arg @ref LL_RCC_PLLI2SM_DIV_11 * @arg @ref LL_RCC_PLLI2SM_DIV_12 * @arg @ref LL_RCC_PLLI2SM_DIV_13 * @arg @ref LL_RCC_PLLI2SM_DIV_14 * @arg @ref LL_RCC_PLLI2SM_DIV_15 * @arg @ref LL_RCC_PLLI2SM_DIV_16 * @arg @ref LL_RCC_PLLI2SM_DIV_17 * @arg @ref LL_RCC_PLLI2SM_DIV_18 * @arg @ref LL_RCC_PLLI2SM_DIV_19 * @arg @ref LL_RCC_PLLI2SM_DIV_20 * @arg @ref LL_RCC_PLLI2SM_DIV_21 * @arg @ref LL_RCC_PLLI2SM_DIV_22 * @arg @ref LL_RCC_PLLI2SM_DIV_23 * @arg @ref LL_RCC_PLLI2SM_DIV_24 * @arg @ref LL_RCC_PLLI2SM_DIV_25 * @arg @ref LL_RCC_PLLI2SM_DIV_26 * @arg @ref LL_RCC_PLLI2SM_DIV_27 * @arg @ref LL_RCC_PLLI2SM_DIV_28 * @arg @ref LL_RCC_PLLI2SM_DIV_29 * @arg @ref LL_RCC_PLLI2SM_DIV_30 * @arg @ref LL_RCC_PLLI2SM_DIV_31 * @arg @ref LL_RCC_PLLI2SM_DIV_32 * @arg @ref LL_RCC_PLLI2SM_DIV_33 * @arg @ref LL_RCC_PLLI2SM_DIV_34 * @arg @ref LL_RCC_PLLI2SM_DIV_35 * @arg @ref LL_RCC_PLLI2SM_DIV_36 * @arg @ref LL_RCC_PLLI2SM_DIV_37 * @arg @ref LL_RCC_PLLI2SM_DIV_38 * @arg @ref LL_RCC_PLLI2SM_DIV_39 * @arg @ref LL_RCC_PLLI2SM_DIV_40 * @arg @ref LL_RCC_PLLI2SM_DIV_41 * @arg @ref LL_RCC_PLLI2SM_DIV_42 * @arg @ref LL_RCC_PLLI2SM_DIV_43 * @arg @ref LL_RCC_PLLI2SM_DIV_44 * @arg @ref LL_RCC_PLLI2SM_DIV_45 * @arg @ref LL_RCC_PLLI2SM_DIV_46 * @arg @ref LL_RCC_PLLI2SM_DIV_47 * @arg @ref LL_RCC_PLLI2SM_DIV_48 * @arg @ref LL_RCC_PLLI2SM_DIV_49 * @arg @ref LL_RCC_PLLI2SM_DIV_50 * @arg @ref LL_RCC_PLLI2SM_DIV_51 * @arg @ref LL_RCC_PLLI2SM_DIV_52 * @arg @ref LL_RCC_PLLI2SM_DIV_53 * @arg @ref LL_RCC_PLLI2SM_DIV_54 * @arg @ref LL_RCC_PLLI2SM_DIV_55 * @arg @ref LL_RCC_PLLI2SM_DIV_56 * @arg @ref LL_RCC_PLLI2SM_DIV_57 * @arg @ref LL_RCC_PLLI2SM_DIV_58 * @arg @ref LL_RCC_PLLI2SM_DIV_59 * @arg @ref LL_RCC_PLLI2SM_DIV_60 * @arg @ref LL_RCC_PLLI2SM_DIV_61 * @arg @ref LL_RCC_PLLI2SM_DIV_62 * @arg @ref LL_RCC_PLLI2SM_DIV_63 * @param __PLLI2SN__ Between 50 and 432 * @param __PLLI2SP__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SP_DIV_2 * @arg @ref LL_RCC_PLLI2SP_DIV_4 * @arg @ref LL_RCC_PLLI2SP_DIV_6 * @arg @ref LL_RCC_PLLI2SP_DIV_8 * @retval PLLI2S clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U)) #endif /* SPDIFRX */ /** * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLM__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SM_DIV_2 * @arg @ref LL_RCC_PLLI2SM_DIV_3 * @arg @ref LL_RCC_PLLI2SM_DIV_4 * @arg @ref LL_RCC_PLLI2SM_DIV_5 * @arg @ref LL_RCC_PLLI2SM_DIV_6 * @arg @ref LL_RCC_PLLI2SM_DIV_7 * @arg @ref LL_RCC_PLLI2SM_DIV_8 * @arg @ref LL_RCC_PLLI2SM_DIV_9 * @arg @ref LL_RCC_PLLI2SM_DIV_10 * @arg @ref LL_RCC_PLLI2SM_DIV_11 * @arg @ref LL_RCC_PLLI2SM_DIV_12 * @arg @ref LL_RCC_PLLI2SM_DIV_13 * @arg @ref LL_RCC_PLLI2SM_DIV_14 * @arg @ref LL_RCC_PLLI2SM_DIV_15 * @arg @ref LL_RCC_PLLI2SM_DIV_16 * @arg @ref LL_RCC_PLLI2SM_DIV_17 * @arg @ref LL_RCC_PLLI2SM_DIV_18 * @arg @ref LL_RCC_PLLI2SM_DIV_19 * @arg @ref LL_RCC_PLLI2SM_DIV_20 * @arg @ref LL_RCC_PLLI2SM_DIV_21 * @arg @ref LL_RCC_PLLI2SM_DIV_22 * @arg @ref LL_RCC_PLLI2SM_DIV_23 * @arg @ref LL_RCC_PLLI2SM_DIV_24 * @arg @ref LL_RCC_PLLI2SM_DIV_25 * @arg @ref LL_RCC_PLLI2SM_DIV_26 * @arg @ref LL_RCC_PLLI2SM_DIV_27 * @arg @ref LL_RCC_PLLI2SM_DIV_28 * @arg @ref LL_RCC_PLLI2SM_DIV_29 * @arg @ref LL_RCC_PLLI2SM_DIV_30 * @arg @ref LL_RCC_PLLI2SM_DIV_31 * @arg @ref LL_RCC_PLLI2SM_DIV_32 * @arg @ref LL_RCC_PLLI2SM_DIV_33 * @arg @ref LL_RCC_PLLI2SM_DIV_34 * @arg @ref LL_RCC_PLLI2SM_DIV_35 * @arg @ref LL_RCC_PLLI2SM_DIV_36 * @arg @ref LL_RCC_PLLI2SM_DIV_37 * @arg @ref LL_RCC_PLLI2SM_DIV_38 * @arg @ref LL_RCC_PLLI2SM_DIV_39 * @arg @ref LL_RCC_PLLI2SM_DIV_40 * @arg @ref LL_RCC_PLLI2SM_DIV_41 * @arg @ref LL_RCC_PLLI2SM_DIV_42 * @arg @ref LL_RCC_PLLI2SM_DIV_43 * @arg @ref LL_RCC_PLLI2SM_DIV_44 * @arg @ref LL_RCC_PLLI2SM_DIV_45 * @arg @ref LL_RCC_PLLI2SM_DIV_46 * @arg @ref LL_RCC_PLLI2SM_DIV_47 * @arg @ref LL_RCC_PLLI2SM_DIV_48 * @arg @ref LL_RCC_PLLI2SM_DIV_49 * @arg @ref LL_RCC_PLLI2SM_DIV_50 * @arg @ref LL_RCC_PLLI2SM_DIV_51 * @arg @ref LL_RCC_PLLI2SM_DIV_52 * @arg @ref LL_RCC_PLLI2SM_DIV_53 * @arg @ref LL_RCC_PLLI2SM_DIV_54 * @arg @ref LL_RCC_PLLI2SM_DIV_55 * @arg @ref LL_RCC_PLLI2SM_DIV_56 * @arg @ref LL_RCC_PLLI2SM_DIV_57 * @arg @ref LL_RCC_PLLI2SM_DIV_58 * @arg @ref LL_RCC_PLLI2SM_DIV_59 * @arg @ref LL_RCC_PLLI2SM_DIV_60 * @arg @ref LL_RCC_PLLI2SM_DIV_61 * @arg @ref LL_RCC_PLLI2SM_DIV_62 * @arg @ref LL_RCC_PLLI2SM_DIV_63 * @param __PLLI2SN__ Between 50/192(*) and 432 * * (*) value not defined in all devices. * @param __PLLI2SR__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SR_DIV_2 * @arg @ref LL_RCC_PLLI2SR_DIV_3 * @arg @ref LL_RCC_PLLI2SR_DIV_4 * @arg @ref LL_RCC_PLLI2SR_DIV_5 * @arg @ref LL_RCC_PLLI2SR_DIV_6 * @arg @ref LL_RCC_PLLI2SR_DIV_7 * @retval PLLI2S clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos)) #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) /** * @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLM__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SM_DIV_2 * @arg @ref LL_RCC_PLLI2SM_DIV_3 * @arg @ref LL_RCC_PLLI2SM_DIV_4 * @arg @ref LL_RCC_PLLI2SM_DIV_5 * @arg @ref LL_RCC_PLLI2SM_DIV_6 * @arg @ref LL_RCC_PLLI2SM_DIV_7 * @arg @ref LL_RCC_PLLI2SM_DIV_8 * @arg @ref LL_RCC_PLLI2SM_DIV_9 * @arg @ref LL_RCC_PLLI2SM_DIV_10 * @arg @ref LL_RCC_PLLI2SM_DIV_11 * @arg @ref LL_RCC_PLLI2SM_DIV_12 * @arg @ref LL_RCC_PLLI2SM_DIV_13 * @arg @ref LL_RCC_PLLI2SM_DIV_14 * @arg @ref LL_RCC_PLLI2SM_DIV_15 * @arg @ref LL_RCC_PLLI2SM_DIV_16 * @arg @ref LL_RCC_PLLI2SM_DIV_17 * @arg @ref LL_RCC_PLLI2SM_DIV_18 * @arg @ref LL_RCC_PLLI2SM_DIV_19 * @arg @ref LL_RCC_PLLI2SM_DIV_20 * @arg @ref LL_RCC_PLLI2SM_DIV_21 * @arg @ref LL_RCC_PLLI2SM_DIV_22 * @arg @ref LL_RCC_PLLI2SM_DIV_23 * @arg @ref LL_RCC_PLLI2SM_DIV_24 * @arg @ref LL_RCC_PLLI2SM_DIV_25 * @arg @ref LL_RCC_PLLI2SM_DIV_26 * @arg @ref LL_RCC_PLLI2SM_DIV_27 * @arg @ref LL_RCC_PLLI2SM_DIV_28 * @arg @ref LL_RCC_PLLI2SM_DIV_29 * @arg @ref LL_RCC_PLLI2SM_DIV_30 * @arg @ref LL_RCC_PLLI2SM_DIV_31 * @arg @ref LL_RCC_PLLI2SM_DIV_32 * @arg @ref LL_RCC_PLLI2SM_DIV_33 * @arg @ref LL_RCC_PLLI2SM_DIV_34 * @arg @ref LL_RCC_PLLI2SM_DIV_35 * @arg @ref LL_RCC_PLLI2SM_DIV_36 * @arg @ref LL_RCC_PLLI2SM_DIV_37 * @arg @ref LL_RCC_PLLI2SM_DIV_38 * @arg @ref LL_RCC_PLLI2SM_DIV_39 * @arg @ref LL_RCC_PLLI2SM_DIV_40 * @arg @ref LL_RCC_PLLI2SM_DIV_41 * @arg @ref LL_RCC_PLLI2SM_DIV_42 * @arg @ref LL_RCC_PLLI2SM_DIV_43 * @arg @ref LL_RCC_PLLI2SM_DIV_44 * @arg @ref LL_RCC_PLLI2SM_DIV_45 * @arg @ref LL_RCC_PLLI2SM_DIV_46 * @arg @ref LL_RCC_PLLI2SM_DIV_47 * @arg @ref LL_RCC_PLLI2SM_DIV_48 * @arg @ref LL_RCC_PLLI2SM_DIV_49 * @arg @ref LL_RCC_PLLI2SM_DIV_50 * @arg @ref LL_RCC_PLLI2SM_DIV_51 * @arg @ref LL_RCC_PLLI2SM_DIV_52 * @arg @ref LL_RCC_PLLI2SM_DIV_53 * @arg @ref LL_RCC_PLLI2SM_DIV_54 * @arg @ref LL_RCC_PLLI2SM_DIV_55 * @arg @ref LL_RCC_PLLI2SM_DIV_56 * @arg @ref LL_RCC_PLLI2SM_DIV_57 * @arg @ref LL_RCC_PLLI2SM_DIV_58 * @arg @ref LL_RCC_PLLI2SM_DIV_59 * @arg @ref LL_RCC_PLLI2SM_DIV_60 * @arg @ref LL_RCC_PLLI2SM_DIV_61 * @arg @ref LL_RCC_PLLI2SM_DIV_62 * @arg @ref LL_RCC_PLLI2SM_DIV_63 * @param __PLLI2SN__ Between 50 and 432 * @param __PLLI2SQ__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SQ_DIV_2 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 * @retval PLLI2S clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos)) #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ #endif /* RCC_PLLI2S_SUPPORT */ /** * @brief Helper macro to calculate the HCLK frequency * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) * @param __AHBPRESCALER__ This parameter can be one of the following values: * @arg @ref LL_RCC_SYSCLK_DIV_1 * @arg @ref LL_RCC_SYSCLK_DIV_2 * @arg @ref LL_RCC_SYSCLK_DIV_4 * @arg @ref LL_RCC_SYSCLK_DIV_8 * @arg @ref LL_RCC_SYSCLK_DIV_16 * @arg @ref LL_RCC_SYSCLK_DIV_64 * @arg @ref LL_RCC_SYSCLK_DIV_128 * @arg @ref LL_RCC_SYSCLK_DIV_256 * @arg @ref LL_RCC_SYSCLK_DIV_512 * @retval HCLK clock frequency (in Hz) */ #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) /** * @brief Helper macro to calculate the PCLK1 frequency (ABP1) * @param __HCLKFREQ__ HCLK frequency * @param __APB1PRESCALER__ This parameter can be one of the following values: * @arg @ref LL_RCC_APB1_DIV_1 * @arg @ref LL_RCC_APB1_DIV_2 * @arg @ref LL_RCC_APB1_DIV_4 * @arg @ref LL_RCC_APB1_DIV_8 * @arg @ref LL_RCC_APB1_DIV_16 * @retval PCLK1 clock frequency (in Hz) */ #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) /** * @brief Helper macro to calculate the PCLK2 frequency (ABP2) * @param __HCLKFREQ__ HCLK frequency * @param __APB2PRESCALER__ This parameter can be one of the following values: * @arg @ref LL_RCC_APB2_DIV_1 * @arg @ref LL_RCC_APB2_DIV_2 * @arg @ref LL_RCC_APB2_DIV_4 * @arg @ref LL_RCC_APB2_DIV_8 * @arg @ref LL_RCC_APB2_DIV_16 * @retval PCLK2 clock frequency (in Hz) */ #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions * @{ */ /** @defgroup RCC_LL_EF_HSE HSE * @{ */ /** * @brief Enable the Clock Security System. * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS * @retval None */ __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) { SET_BIT(RCC->CR, RCC_CR_CSSON); } /** * @brief Enable HSE external oscillator (HSE Bypass) * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass * @retval None */ __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) { SET_BIT(RCC->CR, RCC_CR_HSEBYP); } /** * @brief Disable HSE external oscillator (HSE Bypass) * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass * @retval None */ __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) { CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); } /** * @brief Enable HSE crystal oscillator (HSE ON) * @rmtoll CR HSEON LL_RCC_HSE_Enable * @retval None */ __STATIC_INLINE void LL_RCC_HSE_Enable(void) { SET_BIT(RCC->CR, RCC_CR_HSEON); } /** * @brief Disable HSE crystal oscillator (HSE ON) * @rmtoll CR HSEON LL_RCC_HSE_Disable * @retval None */ __STATIC_INLINE void LL_RCC_HSE_Disable(void) { CLEAR_BIT(RCC->CR, RCC_CR_HSEON); } /** * @brief Check if HSE oscillator Ready * @rmtoll CR HSERDY LL_RCC_HSE_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) { return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); } /** * @} */ /** @defgroup RCC_LL_EF_HSI HSI * @{ */ /** * @brief Enable HSI oscillator * @rmtoll CR HSION LL_RCC_HSI_Enable * @retval None */ __STATIC_INLINE void LL_RCC_HSI_Enable(void) { SET_BIT(RCC->CR, RCC_CR_HSION); } /** * @brief Disable HSI oscillator * @rmtoll CR HSION LL_RCC_HSI_Disable * @retval None */ __STATIC_INLINE void LL_RCC_HSI_Disable(void) { CLEAR_BIT(RCC->CR, RCC_CR_HSION); } /** * @brief Check if HSI clock is ready * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) { return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); } /** * @brief Get HSI Calibration value * @note When HSITRIM is written, HSICAL is updated with the sum of * HSITRIM and the factory trim value * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration * @retval Between Min_Data = 0x00 and Max_Data = 0xFF */ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) { return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); } /** * @brief Set HSI Calibration trimming * @note user-programmable trimming value that is added to the HSICAL * @note Default value is 16, which, when added to the HSICAL value, * should trim the HSI to 16 MHz +/- 1 % * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming * @param Value Between Min_Data = 0 and Max_Data = 31 * @retval None */ __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) { MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); } /** * @brief Get HSI Calibration trimming * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming * @retval Between Min_Data = 0 and Max_Data = 31 */ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) { return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); } /** * @} */ /** @defgroup RCC_LL_EF_LSE LSE * @{ */ /** * @brief Enable Low Speed External (LSE) crystal. * @rmtoll BDCR LSEON LL_RCC_LSE_Enable * @retval None */ __STATIC_INLINE void LL_RCC_LSE_Enable(void) { SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); } /** * @brief Disable Low Speed External (LSE) crystal. * @rmtoll BDCR LSEON LL_RCC_LSE_Disable * @retval None */ __STATIC_INLINE void LL_RCC_LSE_Disable(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); } /** * @brief Enable external clock source (LSE bypass). * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass * @retval None */ __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) { SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); } /** * @brief Disable external clock source (LSE bypass). * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass * @retval None */ __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); } /** * @brief Check if LSE oscillator Ready * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) { return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); } #if defined(RCC_BDCR_LSEMOD) /** * @brief Enable LSE high drive mode. * @note LSE high drive mode can be enabled only when the LSE clock is disabled * @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode * @retval None */ __STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void) { SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); } /** * @brief Disable LSE high drive mode. * @note LSE high drive mode can be disabled only when the LSE clock is disabled * @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode * @retval None */ __STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); } #endif /* RCC_BDCR_LSEMOD */ /** * @} */ /** @defgroup RCC_LL_EF_LSI LSI * @{ */ /** * @brief Enable LSI Oscillator * @rmtoll CSR LSION LL_RCC_LSI_Enable * @retval None */ __STATIC_INLINE void LL_RCC_LSI_Enable(void) { SET_BIT(RCC->CSR, RCC_CSR_LSION); } /** * @brief Disable LSI Oscillator * @rmtoll CSR LSION LL_RCC_LSI_Disable * @retval None */ __STATIC_INLINE void LL_RCC_LSI_Disable(void) { CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); } /** * @brief Check if LSI is Ready * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) { return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); } /** * @} */ /** @defgroup RCC_LL_EF_System System * @{ */ /** * @brief Configure the system clock source * @rmtoll CFGR SW LL_RCC_SetSysClkSource * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL * @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) { MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); } /** * @brief Get the system clock source * @rmtoll CFGR SWS LL_RCC_GetSysClkSource * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) { return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); } /** * @brief Set AHB prescaler * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler * @param Prescaler This parameter can be one of the following values: * @arg @ref LL_RCC_SYSCLK_DIV_1 * @arg @ref LL_RCC_SYSCLK_DIV_2 * @arg @ref LL_RCC_SYSCLK_DIV_4 * @arg @ref LL_RCC_SYSCLK_DIV_8 * @arg @ref LL_RCC_SYSCLK_DIV_16 * @arg @ref LL_RCC_SYSCLK_DIV_64 * @arg @ref LL_RCC_SYSCLK_DIV_128 * @arg @ref LL_RCC_SYSCLK_DIV_256 * @arg @ref LL_RCC_SYSCLK_DIV_512 * @retval None */ __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); } /** * @brief Set APB1 prescaler * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler * @param Prescaler This parameter can be one of the following values: * @arg @ref LL_RCC_APB1_DIV_1 * @arg @ref LL_RCC_APB1_DIV_2 * @arg @ref LL_RCC_APB1_DIV_4 * @arg @ref LL_RCC_APB1_DIV_8 * @arg @ref LL_RCC_APB1_DIV_16 * @retval None */ __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); } /** * @brief Set APB2 prescaler * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler * @param Prescaler This parameter can be one of the following values: * @arg @ref LL_RCC_APB2_DIV_1 * @arg @ref LL_RCC_APB2_DIV_2 * @arg @ref LL_RCC_APB2_DIV_4 * @arg @ref LL_RCC_APB2_DIV_8 * @arg @ref LL_RCC_APB2_DIV_16 * @retval None */ __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); } /** * @brief Get AHB prescaler * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_SYSCLK_DIV_1 * @arg @ref LL_RCC_SYSCLK_DIV_2 * @arg @ref LL_RCC_SYSCLK_DIV_4 * @arg @ref LL_RCC_SYSCLK_DIV_8 * @arg @ref LL_RCC_SYSCLK_DIV_16 * @arg @ref LL_RCC_SYSCLK_DIV_64 * @arg @ref LL_RCC_SYSCLK_DIV_128 * @arg @ref LL_RCC_SYSCLK_DIV_256 * @arg @ref LL_RCC_SYSCLK_DIV_512 */ __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) { return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); } /** * @brief Get APB1 prescaler * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_APB1_DIV_1 * @arg @ref LL_RCC_APB1_DIV_2 * @arg @ref LL_RCC_APB1_DIV_4 * @arg @ref LL_RCC_APB1_DIV_8 * @arg @ref LL_RCC_APB1_DIV_16 */ __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) { return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); } /** * @brief Get APB2 prescaler * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_APB2_DIV_1 * @arg @ref LL_RCC_APB2_DIV_2 * @arg @ref LL_RCC_APB2_DIV_4 * @arg @ref LL_RCC_APB2_DIV_8 * @arg @ref LL_RCC_APB2_DIV_16 */ __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) { return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); } /** * @} */ /** @defgroup RCC_LL_EF_MCO MCO * @{ */ #if defined(RCC_CFGR_MCO1EN) /** * @brief Enable MCO1 output * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable * @retval None */ __STATIC_INLINE void LL_RCC_MCO1_Enable(void) { SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN); } /** * @brief Disable MCO1 output * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable * @retval None */ __STATIC_INLINE void LL_RCC_MCO1_Disable(void) { CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN); } #endif /* RCC_CFGR_MCO1EN */ #if defined(RCC_CFGR_MCO2EN) /** * @brief Enable MCO2 output * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable * @retval None */ __STATIC_INLINE void LL_RCC_MCO2_Enable(void) { SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN); } /** * @brief Disable MCO2 output * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable * @retval None */ __STATIC_INLINE void LL_RCC_MCO2_Disable(void) { CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN); } #endif /* RCC_CFGR_MCO2EN */ /** * @brief Configure MCOx * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n * CFGR MCO1PRE LL_RCC_ConfigMCO\n * CFGR MCO2 LL_RCC_ConfigMCO\n * CFGR MCO2PRE LL_RCC_ConfigMCO * @param MCOxSource This parameter can be one of the following values: * @arg @ref LL_RCC_MCO1SOURCE_HSI * @arg @ref LL_RCC_MCO1SOURCE_LSE * @arg @ref LL_RCC_MCO1SOURCE_HSE * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S * @arg @ref LL_RCC_MCO2SOURCE_HSE * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK * @param MCOxPrescaler This parameter can be one of the following values: * @arg @ref LL_RCC_MCO1_DIV_1 * @arg @ref LL_RCC_MCO1_DIV_2 * @arg @ref LL_RCC_MCO1_DIV_3 * @arg @ref LL_RCC_MCO1_DIV_4 * @arg @ref LL_RCC_MCO1_DIV_5 * @arg @ref LL_RCC_MCO2_DIV_1 * @arg @ref LL_RCC_MCO2_DIV_2 * @arg @ref LL_RCC_MCO2_DIV_3 * @arg @ref LL_RCC_MCO2_DIV_4 * @arg @ref LL_RCC_MCO2_DIV_5 * @retval None */ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) { MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U)); } /** * @} */ /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source * @{ */ #if defined(FMPI2C1) /** * @brief Configure FMPI2C clock source * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource * @param FMPI2CxSource This parameter can be one of the following values: * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI * @retval None */ __STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource) { MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource); } #endif /* FMPI2C1 */ #if defined(LPTIM1) /** * @brief Configure LPTIMx clock source * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource * @param LPTIMxSource This parameter can be one of the following values: * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE * @retval None */ __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) { MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource); } #endif /* LPTIM1 */ #if defined(SAI1) /** * @brief Configure SAIx clock source * @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n * DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n * DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n * DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource * @param SAIxSource This parameter can be one of the following values: * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*) * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*) * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*) * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*) * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*) * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*) * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*) * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*) * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*) * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*) * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*) * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*) * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) { MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); } #endif /* SAI1 */ #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) /** * @brief Configure SDIO clock source * @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n * DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource * @param SDIOxSource This parameter can be one of the following values: * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK * @retval None */ __STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource) { #if defined(RCC_DCKCFGR_SDIOSEL) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource); #else MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource); #endif /* RCC_DCKCFGR_SDIOSEL */ } #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) /** * @brief Configure 48Mhz domain clock source * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n * DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource * @param CK48MxSource This parameter can be one of the following values: * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*) * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource) { #if defined(RCC_DCKCFGR_CK48MSEL) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource); #else MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource); #endif /* RCC_DCKCFGR_CK48MSEL */ } #if defined(RNG) /** * @brief Configure RNG clock source * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n * DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource * @param RNGxSource This parameter can be one of the following values: * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*) * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) { #if defined(RCC_DCKCFGR_CK48MSEL) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource); #else MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource); #endif /* RCC_DCKCFGR_CK48MSEL */ } #endif /* RNG */ #if defined(USB_OTG_FS) || defined(USB_OTG_HS) /** * @brief Configure USB clock source * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n * DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource * @param USBxSource This parameter can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE_PLL * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*) * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) { #if defined(RCC_DCKCFGR_CK48MSEL) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource); #else MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource); #endif /* RCC_DCKCFGR_CK48MSEL */ } #endif /* USB_OTG_FS || USB_OTG_HS */ #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ #if defined(CEC) /** * @brief Configure CEC clock source * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE * @retval None */ __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source) { MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source); } #endif /* CEC */ /** * @brief Configure I2S clock source * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n * DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n * DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n * DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*) * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*) * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*) * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*) * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source) { #if defined(RCC_CFGR_I2SSRC) MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source); #else MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U)); #endif /* RCC_CFGR_I2SSRC */ } #if defined(DSI) /** * @brief Configure DSI clock source * @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL * @retval None */ __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) { MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source); } #endif /* DSI */ #if defined(DFSDM1_Channel0) /** * @brief Configure DFSDM Audio clock source * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n * DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*) * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) { MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U)); } /** * @brief Configure DFSDM Kernel clock source * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*) * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source) { MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source); } #endif /* DFSDM1_Channel0 */ #if defined(SPDIFRX) /** * @brief Configure SPDIFRX clock source * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource * @param SPDIFRXxSource This parameter can be one of the following values: * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource) { MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource); } #endif /* SPDIFRX */ #if defined(FMPI2C1) /** * @brief Get FMPI2C clock source * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource * @param FMPI2Cx This parameter can be one of the following values: * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI */ __STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx) { return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx)); } #endif /* FMPI2C1 */ #if defined(LPTIM1) /** * @brief Get LPTIMx clock source * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource * @param LPTIMx This parameter can be one of the following values: * @arg @ref LL_RCC_LPTIM1_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE */ __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) { return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)); } #endif /* LPTIM1 */ #if defined(SAI1) /** * @brief Get SAIx clock source * @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n * DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n * DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n * DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource * @param SAIx This parameter can be one of the following values: * @arg @ref LL_RCC_SAI1_CLKSOURCE (*) * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*) * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*) * * (*) value not defined in all devices. * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*) * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*) * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*) * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*) * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*) * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*) * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*) * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*) * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*) * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*) * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*) * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*) * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) { return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx); } #endif /* SAI1 */ #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) /** * @brief Get SDIOx clock source * @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n * DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource * @param SDIOx This parameter can be one of the following values: * @arg @ref LL_RCC_SDIO_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK */ __STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx) { #if defined(RCC_DCKCFGR_SDIOSEL) return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx)); #else return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx)); #endif /* RCC_DCKCFGR_SDIOSEL */ } #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) /** * @brief Get 48Mhz domain clock source * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n * DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource * @param CK48Mx This parameter can be one of the following values: * @arg @ref LL_RCC_CK48M_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*) * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx) { #if defined(RCC_DCKCFGR_CK48MSEL) return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx)); #else return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx)); #endif /* RCC_DCKCFGR_CK48MSEL */ } #if defined(RNG) /** * @brief Get RNGx clock source * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n * DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource * @param RNGx This parameter can be one of the following values: * @arg @ref LL_RCC_RNG_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*) * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) { #if defined(RCC_DCKCFGR_CK48MSEL) return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx)); #else return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx)); #endif /* RCC_DCKCFGR_CK48MSEL */ } #endif /* RNG */ #if defined(USB_OTG_FS) || defined(USB_OTG_HS) /** * @brief Get USBx clock source * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n * DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource * @param USBx This parameter can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE_PLL * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*) * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) { #if defined(RCC_DCKCFGR_CK48MSEL) return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx)); #else return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx)); #endif /* RCC_DCKCFGR_CK48MSEL */ } #endif /* USB_OTG_FS || USB_OTG_HS */ #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ #if defined(CEC) /** * @brief Get CEC Clock Source * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource * @param CECx This parameter can be one of the following values: * @arg @ref LL_RCC_CEC_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE */ __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) { return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx)); } #endif /* CEC */ /** * @brief Get I2S Clock Source * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n * DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n * DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n * DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource * @param I2Sx This parameter can be one of the following values: * @arg @ref LL_RCC_I2S1_CLKSOURCE * @arg @ref LL_RCC_I2S2_CLKSOURCE (*) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*) * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*) * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*) * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*) * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) { #if defined(RCC_CFGR_I2SSRC) return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); #else return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx); #endif /* RCC_CFGR_I2SSRC */ } #if defined(DFSDM1_Channel0) /** * @brief Get DFSDM Audio Clock Source * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n * DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource * @param DFSDMx This parameter can be one of the following values: * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*) * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) { return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx); } /** * @brief Get DFSDM Audio Clock Source * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource * @param DFSDMx This parameter can be one of the following values: * @arg @ref LL_RCC_DFSDM1_CLKSOURCE * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*) * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) { return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx)); } #endif /* DFSDM1_Channel0 */ #if defined(SPDIFRX) /** * @brief Get SPDIFRX clock source * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource * @param SPDIFRXx This parameter can be one of the following values: * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx) { return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx)); } #endif /* SPDIFRX */ #if defined(DSI) /** * @brief Get DSI Clock Source * @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource * @param DSIx This parameter can be one of the following values: * @arg @ref LL_RCC_DSI_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL */ __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) { return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx)); } #endif /* DSI */ /** * @} */ /** @defgroup RCC_LL_EF_RTC RTC * @{ */ /** * @brief Set RTC Clock Source * @note Once the RTC clock source has been selected, it cannot be changed anymore unless * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is * set). The BDRST bit can be used to reset them. * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE * @retval None */ __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) { MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); } /** * @brief Get RTC Clock Source * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE */ __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) { return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); } /** * @brief Enable RTC * @rmtoll BDCR RTCEN LL_RCC_EnableRTC * @retval None */ __STATIC_INLINE void LL_RCC_EnableRTC(void) { SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); } /** * @brief Disable RTC * @rmtoll BDCR RTCEN LL_RCC_DisableRTC * @retval None */ __STATIC_INLINE void LL_RCC_DisableRTC(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); } /** * @brief Check if RTC has been enabled or not * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) { return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); } /** * @brief Force the Backup domain reset * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset * @retval None */ __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) { SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); } /** * @brief Release the Backup domain reset * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset * @retval None */ __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); } /** * @brief Set HSE Prescalers for RTC Clock * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler * @param Prescaler This parameter can be one of the following values: * @arg @ref LL_RCC_RTC_NOCLOCK * @arg @ref LL_RCC_RTC_HSE_DIV_2 * @arg @ref LL_RCC_RTC_HSE_DIV_3 * @arg @ref LL_RCC_RTC_HSE_DIV_4 * @arg @ref LL_RCC_RTC_HSE_DIV_5 * @arg @ref LL_RCC_RTC_HSE_DIV_6 * @arg @ref LL_RCC_RTC_HSE_DIV_7 * @arg @ref LL_RCC_RTC_HSE_DIV_8 * @arg @ref LL_RCC_RTC_HSE_DIV_9 * @arg @ref LL_RCC_RTC_HSE_DIV_10 * @arg @ref LL_RCC_RTC_HSE_DIV_11 * @arg @ref LL_RCC_RTC_HSE_DIV_12 * @arg @ref LL_RCC_RTC_HSE_DIV_13 * @arg @ref LL_RCC_RTC_HSE_DIV_14 * @arg @ref LL_RCC_RTC_HSE_DIV_15 * @arg @ref LL_RCC_RTC_HSE_DIV_16 * @arg @ref LL_RCC_RTC_HSE_DIV_17 * @arg @ref LL_RCC_RTC_HSE_DIV_18 * @arg @ref LL_RCC_RTC_HSE_DIV_19 * @arg @ref LL_RCC_RTC_HSE_DIV_20 * @arg @ref LL_RCC_RTC_HSE_DIV_21 * @arg @ref LL_RCC_RTC_HSE_DIV_22 * @arg @ref LL_RCC_RTC_HSE_DIV_23 * @arg @ref LL_RCC_RTC_HSE_DIV_24 * @arg @ref LL_RCC_RTC_HSE_DIV_25 * @arg @ref LL_RCC_RTC_HSE_DIV_26 * @arg @ref LL_RCC_RTC_HSE_DIV_27 * @arg @ref LL_RCC_RTC_HSE_DIV_28 * @arg @ref LL_RCC_RTC_HSE_DIV_29 * @arg @ref LL_RCC_RTC_HSE_DIV_30 * @arg @ref LL_RCC_RTC_HSE_DIV_31 * @retval None */ __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) { MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); } /** * @brief Get HSE Prescalers for RTC Clock * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_RTC_NOCLOCK * @arg @ref LL_RCC_RTC_HSE_DIV_2 * @arg @ref LL_RCC_RTC_HSE_DIV_3 * @arg @ref LL_RCC_RTC_HSE_DIV_4 * @arg @ref LL_RCC_RTC_HSE_DIV_5 * @arg @ref LL_RCC_RTC_HSE_DIV_6 * @arg @ref LL_RCC_RTC_HSE_DIV_7 * @arg @ref LL_RCC_RTC_HSE_DIV_8 * @arg @ref LL_RCC_RTC_HSE_DIV_9 * @arg @ref LL_RCC_RTC_HSE_DIV_10 * @arg @ref LL_RCC_RTC_HSE_DIV_11 * @arg @ref LL_RCC_RTC_HSE_DIV_12 * @arg @ref LL_RCC_RTC_HSE_DIV_13 * @arg @ref LL_RCC_RTC_HSE_DIV_14 * @arg @ref LL_RCC_RTC_HSE_DIV_15 * @arg @ref LL_RCC_RTC_HSE_DIV_16 * @arg @ref LL_RCC_RTC_HSE_DIV_17 * @arg @ref LL_RCC_RTC_HSE_DIV_18 * @arg @ref LL_RCC_RTC_HSE_DIV_19 * @arg @ref LL_RCC_RTC_HSE_DIV_20 * @arg @ref LL_RCC_RTC_HSE_DIV_21 * @arg @ref LL_RCC_RTC_HSE_DIV_22 * @arg @ref LL_RCC_RTC_HSE_DIV_23 * @arg @ref LL_RCC_RTC_HSE_DIV_24 * @arg @ref LL_RCC_RTC_HSE_DIV_25 * @arg @ref LL_RCC_RTC_HSE_DIV_26 * @arg @ref LL_RCC_RTC_HSE_DIV_27 * @arg @ref LL_RCC_RTC_HSE_DIV_28 * @arg @ref LL_RCC_RTC_HSE_DIV_29 * @arg @ref LL_RCC_RTC_HSE_DIV_30 * @arg @ref LL_RCC_RTC_HSE_DIV_31 */ __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) { return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); } /** * @} */ #if defined(RCC_DCKCFGR_TIMPRE) /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM * @{ */ /** * @brief Set Timers Clock Prescalers * @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler * @param Prescaler This parameter can be one of the following values: * @arg @ref LL_RCC_TIM_PRESCALER_TWICE * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES * @retval None */ __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) { MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler); } /** * @brief Get Timers Clock Prescalers * @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_TIM_PRESCALER_TWICE * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES */ __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) { return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE)); } /** * @} */ #endif /* RCC_DCKCFGR_TIMPRE */ /** @defgroup RCC_LL_EF_PLL PLL * @{ */ /** * @brief Enable PLL * @rmtoll CR PLLON LL_RCC_PLL_Enable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_Enable(void) { SET_BIT(RCC->CR, RCC_CR_PLLON); } /** * @brief Disable PLL * @note Cannot be disabled if the PLL clock is used as the system clock * @rmtoll CR PLLON LL_RCC_PLL_Disable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_Disable(void) { CLEAR_BIT(RCC->CR, RCC_CR_PLLON); } /** * @brief Check if PLL Ready * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) { return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); } /** * @brief Configure PLL used for SYSCLK Domain * @note PLL Source and PLLM Divider can be written only when PLL, * PLLI2S and PLLSAI(*) are disabled * @note PLLN/PLLP can be written only when PLL is disabled * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @param PLLM This parameter can be one of the following values: * @arg @ref LL_RCC_PLLM_DIV_2 * @arg @ref LL_RCC_PLLM_DIV_3 * @arg @ref LL_RCC_PLLM_DIV_4 * @arg @ref LL_RCC_PLLM_DIV_5 * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 * @arg @ref LL_RCC_PLLM_DIV_9 * @arg @ref LL_RCC_PLLM_DIV_10 * @arg @ref LL_RCC_PLLM_DIV_11 * @arg @ref LL_RCC_PLLM_DIV_12 * @arg @ref LL_RCC_PLLM_DIV_13 * @arg @ref LL_RCC_PLLM_DIV_14 * @arg @ref LL_RCC_PLLM_DIV_15 * @arg @ref LL_RCC_PLLM_DIV_16 * @arg @ref LL_RCC_PLLM_DIV_17 * @arg @ref LL_RCC_PLLM_DIV_18 * @arg @ref LL_RCC_PLLM_DIV_19 * @arg @ref LL_RCC_PLLM_DIV_20 * @arg @ref LL_RCC_PLLM_DIV_21 * @arg @ref LL_RCC_PLLM_DIV_22 * @arg @ref LL_RCC_PLLM_DIV_23 * @arg @ref LL_RCC_PLLM_DIV_24 * @arg @ref LL_RCC_PLLM_DIV_25 * @arg @ref LL_RCC_PLLM_DIV_26 * @arg @ref LL_RCC_PLLM_DIV_27 * @arg @ref LL_RCC_PLLM_DIV_28 * @arg @ref LL_RCC_PLLM_DIV_29 * @arg @ref LL_RCC_PLLM_DIV_30 * @arg @ref LL_RCC_PLLM_DIV_31 * @arg @ref LL_RCC_PLLM_DIV_32 * @arg @ref LL_RCC_PLLM_DIV_33 * @arg @ref LL_RCC_PLLM_DIV_34 * @arg @ref LL_RCC_PLLM_DIV_35 * @arg @ref LL_RCC_PLLM_DIV_36 * @arg @ref LL_RCC_PLLM_DIV_37 * @arg @ref LL_RCC_PLLM_DIV_38 * @arg @ref LL_RCC_PLLM_DIV_39 * @arg @ref LL_RCC_PLLM_DIV_40 * @arg @ref LL_RCC_PLLM_DIV_41 * @arg @ref LL_RCC_PLLM_DIV_42 * @arg @ref LL_RCC_PLLM_DIV_43 * @arg @ref LL_RCC_PLLM_DIV_44 * @arg @ref LL_RCC_PLLM_DIV_45 * @arg @ref LL_RCC_PLLM_DIV_46 * @arg @ref LL_RCC_PLLM_DIV_47 * @arg @ref LL_RCC_PLLM_DIV_48 * @arg @ref LL_RCC_PLLM_DIV_49 * @arg @ref LL_RCC_PLLM_DIV_50 * @arg @ref LL_RCC_PLLM_DIV_51 * @arg @ref LL_RCC_PLLM_DIV_52 * @arg @ref LL_RCC_PLLM_DIV_53 * @arg @ref LL_RCC_PLLM_DIV_54 * @arg @ref LL_RCC_PLLM_DIV_55 * @arg @ref LL_RCC_PLLM_DIV_56 * @arg @ref LL_RCC_PLLM_DIV_57 * @arg @ref LL_RCC_PLLM_DIV_58 * @arg @ref LL_RCC_PLLM_DIV_59 * @arg @ref LL_RCC_PLLM_DIV_60 * @arg @ref LL_RCC_PLLM_DIV_61 * @arg @ref LL_RCC_PLLM_DIV_62 * @arg @ref LL_RCC_PLLM_DIV_63 * @param PLLN Between 50/192(*) and 432 * * (*) value not defined in all devices. * @param PLLP_R This parameter can be one of the following values: * @arg @ref LL_RCC_PLLP_DIV_2 * @arg @ref LL_RCC_PLLP_DIV_4 * @arg @ref LL_RCC_PLLP_DIV_6 * @arg @ref LL_RCC_PLLP_DIV_8 * @arg @ref LL_RCC_PLLR_DIV_2 (*) * @arg @ref LL_RCC_PLLR_DIV_3 (*) * @arg @ref LL_RCC_PLLR_DIV_4 (*) * @arg @ref LL_RCC_PLLR_DIV_5 (*) * @arg @ref LL_RCC_PLLR_DIV_6 (*) * @arg @ref LL_RCC_PLLR_DIV_7 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN, Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos); MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R); #if defined(RCC_PLLR_SYSCLK_SUPPORT) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R); #endif /* RCC_PLLR_SYSCLK_SUPPORT */ } /** * @brief Configure PLL used for 48Mhz domain clock * @note PLL Source and PLLM Divider can be written only when PLL, * PLLI2S and PLLSAI(*) are disabled * @note PLLN/PLLQ can be written only when PLL is disabled * @note This can be selected for USB, RNG, SDIO * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @param PLLM This parameter can be one of the following values: * @arg @ref LL_RCC_PLLM_DIV_2 * @arg @ref LL_RCC_PLLM_DIV_3 * @arg @ref LL_RCC_PLLM_DIV_4 * @arg @ref LL_RCC_PLLM_DIV_5 * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 * @arg @ref LL_RCC_PLLM_DIV_9 * @arg @ref LL_RCC_PLLM_DIV_10 * @arg @ref LL_RCC_PLLM_DIV_11 * @arg @ref LL_RCC_PLLM_DIV_12 * @arg @ref LL_RCC_PLLM_DIV_13 * @arg @ref LL_RCC_PLLM_DIV_14 * @arg @ref LL_RCC_PLLM_DIV_15 * @arg @ref LL_RCC_PLLM_DIV_16 * @arg @ref LL_RCC_PLLM_DIV_17 * @arg @ref LL_RCC_PLLM_DIV_18 * @arg @ref LL_RCC_PLLM_DIV_19 * @arg @ref LL_RCC_PLLM_DIV_20 * @arg @ref LL_RCC_PLLM_DIV_21 * @arg @ref LL_RCC_PLLM_DIV_22 * @arg @ref LL_RCC_PLLM_DIV_23 * @arg @ref LL_RCC_PLLM_DIV_24 * @arg @ref LL_RCC_PLLM_DIV_25 * @arg @ref LL_RCC_PLLM_DIV_26 * @arg @ref LL_RCC_PLLM_DIV_27 * @arg @ref LL_RCC_PLLM_DIV_28 * @arg @ref LL_RCC_PLLM_DIV_29 * @arg @ref LL_RCC_PLLM_DIV_30 * @arg @ref LL_RCC_PLLM_DIV_31 * @arg @ref LL_RCC_PLLM_DIV_32 * @arg @ref LL_RCC_PLLM_DIV_33 * @arg @ref LL_RCC_PLLM_DIV_34 * @arg @ref LL_RCC_PLLM_DIV_35 * @arg @ref LL_RCC_PLLM_DIV_36 * @arg @ref LL_RCC_PLLM_DIV_37 * @arg @ref LL_RCC_PLLM_DIV_38 * @arg @ref LL_RCC_PLLM_DIV_39 * @arg @ref LL_RCC_PLLM_DIV_40 * @arg @ref LL_RCC_PLLM_DIV_41 * @arg @ref LL_RCC_PLLM_DIV_42 * @arg @ref LL_RCC_PLLM_DIV_43 * @arg @ref LL_RCC_PLLM_DIV_44 * @arg @ref LL_RCC_PLLM_DIV_45 * @arg @ref LL_RCC_PLLM_DIV_46 * @arg @ref LL_RCC_PLLM_DIV_47 * @arg @ref LL_RCC_PLLM_DIV_48 * @arg @ref LL_RCC_PLLM_DIV_49 * @arg @ref LL_RCC_PLLM_DIV_50 * @arg @ref LL_RCC_PLLM_DIV_51 * @arg @ref LL_RCC_PLLM_DIV_52 * @arg @ref LL_RCC_PLLM_DIV_53 * @arg @ref LL_RCC_PLLM_DIV_54 * @arg @ref LL_RCC_PLLM_DIV_55 * @arg @ref LL_RCC_PLLM_DIV_56 * @arg @ref LL_RCC_PLLM_DIV_57 * @arg @ref LL_RCC_PLLM_DIV_58 * @arg @ref LL_RCC_PLLM_DIV_59 * @arg @ref LL_RCC_PLLM_DIV_60 * @arg @ref LL_RCC_PLLM_DIV_61 * @arg @ref LL_RCC_PLLM_DIV_62 * @arg @ref LL_RCC_PLLM_DIV_63 * @param PLLN Between 50/192(*) and 432 * * (*) value not defined in all devices. * @param PLLQ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLQ_DIV_2 * @arg @ref LL_RCC_PLLQ_DIV_3 * @arg @ref LL_RCC_PLLQ_DIV_4 * @arg @ref LL_RCC_PLLQ_DIV_5 * @arg @ref LL_RCC_PLLQ_DIV_6 * @arg @ref LL_RCC_PLLQ_DIV_7 * @arg @ref LL_RCC_PLLQ_DIV_8 * @arg @ref LL_RCC_PLLQ_DIV_9 * @arg @ref LL_RCC_PLLQ_DIV_10 * @arg @ref LL_RCC_PLLQ_DIV_11 * @arg @ref LL_RCC_PLLQ_DIV_12 * @arg @ref LL_RCC_PLLQ_DIV_13 * @arg @ref LL_RCC_PLLQ_DIV_14 * @arg @ref LL_RCC_PLLQ_DIV_15 * @retval None */ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); } #if defined(DSI) /** * @brief Configure PLL used for DSI clock * @note PLL Source and PLLM Divider can be written only when PLL, * PLLI2S and PLLSAI are disabled * @note PLLN/PLLR can be written only when PLL is disabled * @note This can be selected for DSI * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @param PLLM This parameter can be one of the following values: * @arg @ref LL_RCC_PLLM_DIV_2 * @arg @ref LL_RCC_PLLM_DIV_3 * @arg @ref LL_RCC_PLLM_DIV_4 * @arg @ref LL_RCC_PLLM_DIV_5 * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 * @arg @ref LL_RCC_PLLM_DIV_9 * @arg @ref LL_RCC_PLLM_DIV_10 * @arg @ref LL_RCC_PLLM_DIV_11 * @arg @ref LL_RCC_PLLM_DIV_12 * @arg @ref LL_RCC_PLLM_DIV_13 * @arg @ref LL_RCC_PLLM_DIV_14 * @arg @ref LL_RCC_PLLM_DIV_15 * @arg @ref LL_RCC_PLLM_DIV_16 * @arg @ref LL_RCC_PLLM_DIV_17 * @arg @ref LL_RCC_PLLM_DIV_18 * @arg @ref LL_RCC_PLLM_DIV_19 * @arg @ref LL_RCC_PLLM_DIV_20 * @arg @ref LL_RCC_PLLM_DIV_21 * @arg @ref LL_RCC_PLLM_DIV_22 * @arg @ref LL_RCC_PLLM_DIV_23 * @arg @ref LL_RCC_PLLM_DIV_24 * @arg @ref LL_RCC_PLLM_DIV_25 * @arg @ref LL_RCC_PLLM_DIV_26 * @arg @ref LL_RCC_PLLM_DIV_27 * @arg @ref LL_RCC_PLLM_DIV_28 * @arg @ref LL_RCC_PLLM_DIV_29 * @arg @ref LL_RCC_PLLM_DIV_30 * @arg @ref LL_RCC_PLLM_DIV_31 * @arg @ref LL_RCC_PLLM_DIV_32 * @arg @ref LL_RCC_PLLM_DIV_33 * @arg @ref LL_RCC_PLLM_DIV_34 * @arg @ref LL_RCC_PLLM_DIV_35 * @arg @ref LL_RCC_PLLM_DIV_36 * @arg @ref LL_RCC_PLLM_DIV_37 * @arg @ref LL_RCC_PLLM_DIV_38 * @arg @ref LL_RCC_PLLM_DIV_39 * @arg @ref LL_RCC_PLLM_DIV_40 * @arg @ref LL_RCC_PLLM_DIV_41 * @arg @ref LL_RCC_PLLM_DIV_42 * @arg @ref LL_RCC_PLLM_DIV_43 * @arg @ref LL_RCC_PLLM_DIV_44 * @arg @ref LL_RCC_PLLM_DIV_45 * @arg @ref LL_RCC_PLLM_DIV_46 * @arg @ref LL_RCC_PLLM_DIV_47 * @arg @ref LL_RCC_PLLM_DIV_48 * @arg @ref LL_RCC_PLLM_DIV_49 * @arg @ref LL_RCC_PLLM_DIV_50 * @arg @ref LL_RCC_PLLM_DIV_51 * @arg @ref LL_RCC_PLLM_DIV_52 * @arg @ref LL_RCC_PLLM_DIV_53 * @arg @ref LL_RCC_PLLM_DIV_54 * @arg @ref LL_RCC_PLLM_DIV_55 * @arg @ref LL_RCC_PLLM_DIV_56 * @arg @ref LL_RCC_PLLM_DIV_57 * @arg @ref LL_RCC_PLLM_DIV_58 * @arg @ref LL_RCC_PLLM_DIV_59 * @arg @ref LL_RCC_PLLM_DIV_60 * @arg @ref LL_RCC_PLLM_DIV_61 * @arg @ref LL_RCC_PLLM_DIV_62 * @arg @ref LL_RCC_PLLM_DIV_63 * @param PLLN Between 50 and 432 * @param PLLR This parameter can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 * @arg @ref LL_RCC_PLLR_DIV_3 * @arg @ref LL_RCC_PLLR_DIV_4 * @arg @ref LL_RCC_PLLR_DIV_5 * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_7 * @retval None */ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); } #endif /* DSI */ #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT) /** * @brief Configure PLL used for I2S clock * @note PLL Source and PLLM Divider can be written only when PLL, * PLLI2S and PLLSAI are disabled * @note PLLN/PLLR can be written only when PLL is disabled * @note This can be selected for I2S * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @param PLLM This parameter can be one of the following values: * @arg @ref LL_RCC_PLLM_DIV_2 * @arg @ref LL_RCC_PLLM_DIV_3 * @arg @ref LL_RCC_PLLM_DIV_4 * @arg @ref LL_RCC_PLLM_DIV_5 * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 * @arg @ref LL_RCC_PLLM_DIV_9 * @arg @ref LL_RCC_PLLM_DIV_10 * @arg @ref LL_RCC_PLLM_DIV_11 * @arg @ref LL_RCC_PLLM_DIV_12 * @arg @ref LL_RCC_PLLM_DIV_13 * @arg @ref LL_RCC_PLLM_DIV_14 * @arg @ref LL_RCC_PLLM_DIV_15 * @arg @ref LL_RCC_PLLM_DIV_16 * @arg @ref LL_RCC_PLLM_DIV_17 * @arg @ref LL_RCC_PLLM_DIV_18 * @arg @ref LL_RCC_PLLM_DIV_19 * @arg @ref LL_RCC_PLLM_DIV_20 * @arg @ref LL_RCC_PLLM_DIV_21 * @arg @ref LL_RCC_PLLM_DIV_22 * @arg @ref LL_RCC_PLLM_DIV_23 * @arg @ref LL_RCC_PLLM_DIV_24 * @arg @ref LL_RCC_PLLM_DIV_25 * @arg @ref LL_RCC_PLLM_DIV_26 * @arg @ref LL_RCC_PLLM_DIV_27 * @arg @ref LL_RCC_PLLM_DIV_28 * @arg @ref LL_RCC_PLLM_DIV_29 * @arg @ref LL_RCC_PLLM_DIV_30 * @arg @ref LL_RCC_PLLM_DIV_31 * @arg @ref LL_RCC_PLLM_DIV_32 * @arg @ref LL_RCC_PLLM_DIV_33 * @arg @ref LL_RCC_PLLM_DIV_34 * @arg @ref LL_RCC_PLLM_DIV_35 * @arg @ref LL_RCC_PLLM_DIV_36 * @arg @ref LL_RCC_PLLM_DIV_37 * @arg @ref LL_RCC_PLLM_DIV_38 * @arg @ref LL_RCC_PLLM_DIV_39 * @arg @ref LL_RCC_PLLM_DIV_40 * @arg @ref LL_RCC_PLLM_DIV_41 * @arg @ref LL_RCC_PLLM_DIV_42 * @arg @ref LL_RCC_PLLM_DIV_43 * @arg @ref LL_RCC_PLLM_DIV_44 * @arg @ref LL_RCC_PLLM_DIV_45 * @arg @ref LL_RCC_PLLM_DIV_46 * @arg @ref LL_RCC_PLLM_DIV_47 * @arg @ref LL_RCC_PLLM_DIV_48 * @arg @ref LL_RCC_PLLM_DIV_49 * @arg @ref LL_RCC_PLLM_DIV_50 * @arg @ref LL_RCC_PLLM_DIV_51 * @arg @ref LL_RCC_PLLM_DIV_52 * @arg @ref LL_RCC_PLLM_DIV_53 * @arg @ref LL_RCC_PLLM_DIV_54 * @arg @ref LL_RCC_PLLM_DIV_55 * @arg @ref LL_RCC_PLLM_DIV_56 * @arg @ref LL_RCC_PLLM_DIV_57 * @arg @ref LL_RCC_PLLM_DIV_58 * @arg @ref LL_RCC_PLLM_DIV_59 * @arg @ref LL_RCC_PLLM_DIV_60 * @arg @ref LL_RCC_PLLM_DIV_61 * @arg @ref LL_RCC_PLLM_DIV_62 * @arg @ref LL_RCC_PLLM_DIV_63 * @param PLLN Between 50 and 432 * @param PLLR This parameter can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 * @arg @ref LL_RCC_PLLR_DIV_3 * @arg @ref LL_RCC_PLLR_DIV_4 * @arg @ref LL_RCC_PLLR_DIV_5 * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_7 * @retval None */ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); } #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */ #if defined(SPDIFRX) /** * @brief Configure PLL used for SPDIFRX clock * @note PLL Source and PLLM Divider can be written only when PLL, * PLLI2S and PLLSAI are disabled * @note PLLN/PLLR can be written only when PLL is disabled * @note This can be selected for SPDIFRX * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @param PLLM This parameter can be one of the following values: * @arg @ref LL_RCC_PLLM_DIV_2 * @arg @ref LL_RCC_PLLM_DIV_3 * @arg @ref LL_RCC_PLLM_DIV_4 * @arg @ref LL_RCC_PLLM_DIV_5 * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 * @arg @ref LL_RCC_PLLM_DIV_9 * @arg @ref LL_RCC_PLLM_DIV_10 * @arg @ref LL_RCC_PLLM_DIV_11 * @arg @ref LL_RCC_PLLM_DIV_12 * @arg @ref LL_RCC_PLLM_DIV_13 * @arg @ref LL_RCC_PLLM_DIV_14 * @arg @ref LL_RCC_PLLM_DIV_15 * @arg @ref LL_RCC_PLLM_DIV_16 * @arg @ref LL_RCC_PLLM_DIV_17 * @arg @ref LL_RCC_PLLM_DIV_18 * @arg @ref LL_RCC_PLLM_DIV_19 * @arg @ref LL_RCC_PLLM_DIV_20 * @arg @ref LL_RCC_PLLM_DIV_21 * @arg @ref LL_RCC_PLLM_DIV_22 * @arg @ref LL_RCC_PLLM_DIV_23 * @arg @ref LL_RCC_PLLM_DIV_24 * @arg @ref LL_RCC_PLLM_DIV_25 * @arg @ref LL_RCC_PLLM_DIV_26 * @arg @ref LL_RCC_PLLM_DIV_27 * @arg @ref LL_RCC_PLLM_DIV_28 * @arg @ref LL_RCC_PLLM_DIV_29 * @arg @ref LL_RCC_PLLM_DIV_30 * @arg @ref LL_RCC_PLLM_DIV_31 * @arg @ref LL_RCC_PLLM_DIV_32 * @arg @ref LL_RCC_PLLM_DIV_33 * @arg @ref LL_RCC_PLLM_DIV_34 * @arg @ref LL_RCC_PLLM_DIV_35 * @arg @ref LL_RCC_PLLM_DIV_36 * @arg @ref LL_RCC_PLLM_DIV_37 * @arg @ref LL_RCC_PLLM_DIV_38 * @arg @ref LL_RCC_PLLM_DIV_39 * @arg @ref LL_RCC_PLLM_DIV_40 * @arg @ref LL_RCC_PLLM_DIV_41 * @arg @ref LL_RCC_PLLM_DIV_42 * @arg @ref LL_RCC_PLLM_DIV_43 * @arg @ref LL_RCC_PLLM_DIV_44 * @arg @ref LL_RCC_PLLM_DIV_45 * @arg @ref LL_RCC_PLLM_DIV_46 * @arg @ref LL_RCC_PLLM_DIV_47 * @arg @ref LL_RCC_PLLM_DIV_48 * @arg @ref LL_RCC_PLLM_DIV_49 * @arg @ref LL_RCC_PLLM_DIV_50 * @arg @ref LL_RCC_PLLM_DIV_51 * @arg @ref LL_RCC_PLLM_DIV_52 * @arg @ref LL_RCC_PLLM_DIV_53 * @arg @ref LL_RCC_PLLM_DIV_54 * @arg @ref LL_RCC_PLLM_DIV_55 * @arg @ref LL_RCC_PLLM_DIV_56 * @arg @ref LL_RCC_PLLM_DIV_57 * @arg @ref LL_RCC_PLLM_DIV_58 * @arg @ref LL_RCC_PLLM_DIV_59 * @arg @ref LL_RCC_PLLM_DIV_60 * @arg @ref LL_RCC_PLLM_DIV_61 * @arg @ref LL_RCC_PLLM_DIV_62 * @arg @ref LL_RCC_PLLM_DIV_63 * @param PLLN Between 50 and 432 * @param PLLR This parameter can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 * @arg @ref LL_RCC_PLLR_DIV_3 * @arg @ref LL_RCC_PLLR_DIV_4 * @arg @ref LL_RCC_PLLR_DIV_5 * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_7 * @retval None */ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); } #endif /* SPDIFRX */ #if defined(RCC_PLLCFGR_PLLR) #if defined(SAI1) /** * @brief Configure PLL used for SAI clock * @note PLL Source and PLLM Divider can be written only when PLL, * PLLI2S and PLLSAI are disabled * @note PLLN/PLLR can be written only when PLL is disabled * @note This can be selected for SAI * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n * DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @param PLLM This parameter can be one of the following values: * @arg @ref LL_RCC_PLLM_DIV_2 * @arg @ref LL_RCC_PLLM_DIV_3 * @arg @ref LL_RCC_PLLM_DIV_4 * @arg @ref LL_RCC_PLLM_DIV_5 * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 * @arg @ref LL_RCC_PLLM_DIV_9 * @arg @ref LL_RCC_PLLM_DIV_10 * @arg @ref LL_RCC_PLLM_DIV_11 * @arg @ref LL_RCC_PLLM_DIV_12 * @arg @ref LL_RCC_PLLM_DIV_13 * @arg @ref LL_RCC_PLLM_DIV_14 * @arg @ref LL_RCC_PLLM_DIV_15 * @arg @ref LL_RCC_PLLM_DIV_16 * @arg @ref LL_RCC_PLLM_DIV_17 * @arg @ref LL_RCC_PLLM_DIV_18 * @arg @ref LL_RCC_PLLM_DIV_19 * @arg @ref LL_RCC_PLLM_DIV_20 * @arg @ref LL_RCC_PLLM_DIV_21 * @arg @ref LL_RCC_PLLM_DIV_22 * @arg @ref LL_RCC_PLLM_DIV_23 * @arg @ref LL_RCC_PLLM_DIV_24 * @arg @ref LL_RCC_PLLM_DIV_25 * @arg @ref LL_RCC_PLLM_DIV_26 * @arg @ref LL_RCC_PLLM_DIV_27 * @arg @ref LL_RCC_PLLM_DIV_28 * @arg @ref LL_RCC_PLLM_DIV_29 * @arg @ref LL_RCC_PLLM_DIV_30 * @arg @ref LL_RCC_PLLM_DIV_31 * @arg @ref LL_RCC_PLLM_DIV_32 * @arg @ref LL_RCC_PLLM_DIV_33 * @arg @ref LL_RCC_PLLM_DIV_34 * @arg @ref LL_RCC_PLLM_DIV_35 * @arg @ref LL_RCC_PLLM_DIV_36 * @arg @ref LL_RCC_PLLM_DIV_37 * @arg @ref LL_RCC_PLLM_DIV_38 * @arg @ref LL_RCC_PLLM_DIV_39 * @arg @ref LL_RCC_PLLM_DIV_40 * @arg @ref LL_RCC_PLLM_DIV_41 * @arg @ref LL_RCC_PLLM_DIV_42 * @arg @ref LL_RCC_PLLM_DIV_43 * @arg @ref LL_RCC_PLLM_DIV_44 * @arg @ref LL_RCC_PLLM_DIV_45 * @arg @ref LL_RCC_PLLM_DIV_46 * @arg @ref LL_RCC_PLLM_DIV_47 * @arg @ref LL_RCC_PLLM_DIV_48 * @arg @ref LL_RCC_PLLM_DIV_49 * @arg @ref LL_RCC_PLLM_DIV_50 * @arg @ref LL_RCC_PLLM_DIV_51 * @arg @ref LL_RCC_PLLM_DIV_52 * @arg @ref LL_RCC_PLLM_DIV_53 * @arg @ref LL_RCC_PLLM_DIV_54 * @arg @ref LL_RCC_PLLM_DIV_55 * @arg @ref LL_RCC_PLLM_DIV_56 * @arg @ref LL_RCC_PLLM_DIV_57 * @arg @ref LL_RCC_PLLM_DIV_58 * @arg @ref LL_RCC_PLLM_DIV_59 * @arg @ref LL_RCC_PLLM_DIV_60 * @arg @ref LL_RCC_PLLM_DIV_61 * @arg @ref LL_RCC_PLLM_DIV_62 * @arg @ref LL_RCC_PLLM_DIV_63 * @param PLLN Between 50 and 432 * @param PLLR This parameter can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 * @arg @ref LL_RCC_PLLR_DIV_3 * @arg @ref LL_RCC_PLLR_DIV_4 * @arg @ref LL_RCC_PLLR_DIV_5 * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_7 * @param PLLDIVR This parameter can be one of the following values: * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*) * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*) * * (*) value not defined in all devices. * @retval None */ #if defined(RCC_DCKCFGR_PLLDIVR) __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) #else __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) #endif /* RCC_DCKCFGR_PLLDIVR */ { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); #if defined(RCC_DCKCFGR_PLLDIVR) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR); #endif /* RCC_DCKCFGR_PLLDIVR */ } #endif /* SAI1 */ #endif /* RCC_PLLCFGR_PLLR */ /** * @brief Configure PLL clock source * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource * @param PLLSource This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @retval None */ __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); } /** * @brief Get the oscillator used as PLL clock source. * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) { return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); } /** * @brief Get Main PLL multiplication factor for VCO * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN * @retval Between 50/192(*) and 432 * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) { return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); } /** * @brief Get Main PLL division factor for PLLP * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLP_DIV_2 * @arg @ref LL_RCC_PLLP_DIV_4 * @arg @ref LL_RCC_PLLP_DIV_6 * @arg @ref LL_RCC_PLLP_DIV_8 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) { return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); } /** * @brief Get Main PLL division factor for PLLQ * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock) * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLQ_DIV_2 * @arg @ref LL_RCC_PLLQ_DIV_3 * @arg @ref LL_RCC_PLLQ_DIV_4 * @arg @ref LL_RCC_PLLQ_DIV_5 * @arg @ref LL_RCC_PLLQ_DIV_6 * @arg @ref LL_RCC_PLLQ_DIV_7 * @arg @ref LL_RCC_PLLQ_DIV_8 * @arg @ref LL_RCC_PLLQ_DIV_9 * @arg @ref LL_RCC_PLLQ_DIV_10 * @arg @ref LL_RCC_PLLQ_DIV_11 * @arg @ref LL_RCC_PLLQ_DIV_12 * @arg @ref LL_RCC_PLLQ_DIV_13 * @arg @ref LL_RCC_PLLQ_DIV_14 * @arg @ref LL_RCC_PLLQ_DIV_15 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) { return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); } #if defined(RCC_PLLCFGR_PLLR) /** * @brief Get Main PLL division factor for PLLR * @note used for PLLCLK (system clock) * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 * @arg @ref LL_RCC_PLLR_DIV_3 * @arg @ref LL_RCC_PLLR_DIV_4 * @arg @ref LL_RCC_PLLR_DIV_5 * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_7 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) { return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); } #endif /* RCC_PLLCFGR_PLLR */ #if defined(RCC_DCKCFGR_PLLDIVR) /** * @brief Get Main PLL division factor for PLLDIVR * @note used for PLLSAICLK (SAI1 and SAI2 clock) * @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLDIVR_DIV_1 * @arg @ref LL_RCC_PLLDIVR_DIV_2 * @arg @ref LL_RCC_PLLDIVR_DIV_3 * @arg @ref LL_RCC_PLLDIVR_DIV_4 * @arg @ref LL_RCC_PLLDIVR_DIV_5 * @arg @ref LL_RCC_PLLDIVR_DIV_6 * @arg @ref LL_RCC_PLLDIVR_DIV_7 * @arg @ref LL_RCC_PLLDIVR_DIV_8 * @arg @ref LL_RCC_PLLDIVR_DIV_9 * @arg @ref LL_RCC_PLLDIVR_DIV_10 * @arg @ref LL_RCC_PLLDIVR_DIV_11 * @arg @ref LL_RCC_PLLDIVR_DIV_12 * @arg @ref LL_RCC_PLLDIVR_DIV_13 * @arg @ref LL_RCC_PLLDIVR_DIV_14 * @arg @ref LL_RCC_PLLDIVR_DIV_15 * @arg @ref LL_RCC_PLLDIVR_DIV_16 * @arg @ref LL_RCC_PLLDIVR_DIV_17 * @arg @ref LL_RCC_PLLDIVR_DIV_18 * @arg @ref LL_RCC_PLLDIVR_DIV_19 * @arg @ref LL_RCC_PLLDIVR_DIV_20 * @arg @ref LL_RCC_PLLDIVR_DIV_21 * @arg @ref LL_RCC_PLLDIVR_DIV_22 * @arg @ref LL_RCC_PLLDIVR_DIV_23 * @arg @ref LL_RCC_PLLDIVR_DIV_24 * @arg @ref LL_RCC_PLLDIVR_DIV_25 * @arg @ref LL_RCC_PLLDIVR_DIV_26 * @arg @ref LL_RCC_PLLDIVR_DIV_27 * @arg @ref LL_RCC_PLLDIVR_DIV_28 * @arg @ref LL_RCC_PLLDIVR_DIV_29 * @arg @ref LL_RCC_PLLDIVR_DIV_30 * @arg @ref LL_RCC_PLLDIVR_DIV_31 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void) { return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR)); } #endif /* RCC_DCKCFGR_PLLDIVR */ /** * @brief Get Division factor for the main PLL and other PLL * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLM_DIV_2 * @arg @ref LL_RCC_PLLM_DIV_3 * @arg @ref LL_RCC_PLLM_DIV_4 * @arg @ref LL_RCC_PLLM_DIV_5 * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 * @arg @ref LL_RCC_PLLM_DIV_9 * @arg @ref LL_RCC_PLLM_DIV_10 * @arg @ref LL_RCC_PLLM_DIV_11 * @arg @ref LL_RCC_PLLM_DIV_12 * @arg @ref LL_RCC_PLLM_DIV_13 * @arg @ref LL_RCC_PLLM_DIV_14 * @arg @ref LL_RCC_PLLM_DIV_15 * @arg @ref LL_RCC_PLLM_DIV_16 * @arg @ref LL_RCC_PLLM_DIV_17 * @arg @ref LL_RCC_PLLM_DIV_18 * @arg @ref LL_RCC_PLLM_DIV_19 * @arg @ref LL_RCC_PLLM_DIV_20 * @arg @ref LL_RCC_PLLM_DIV_21 * @arg @ref LL_RCC_PLLM_DIV_22 * @arg @ref LL_RCC_PLLM_DIV_23 * @arg @ref LL_RCC_PLLM_DIV_24 * @arg @ref LL_RCC_PLLM_DIV_25 * @arg @ref LL_RCC_PLLM_DIV_26 * @arg @ref LL_RCC_PLLM_DIV_27 * @arg @ref LL_RCC_PLLM_DIV_28 * @arg @ref LL_RCC_PLLM_DIV_29 * @arg @ref LL_RCC_PLLM_DIV_30 * @arg @ref LL_RCC_PLLM_DIV_31 * @arg @ref LL_RCC_PLLM_DIV_32 * @arg @ref LL_RCC_PLLM_DIV_33 * @arg @ref LL_RCC_PLLM_DIV_34 * @arg @ref LL_RCC_PLLM_DIV_35 * @arg @ref LL_RCC_PLLM_DIV_36 * @arg @ref LL_RCC_PLLM_DIV_37 * @arg @ref LL_RCC_PLLM_DIV_38 * @arg @ref LL_RCC_PLLM_DIV_39 * @arg @ref LL_RCC_PLLM_DIV_40 * @arg @ref LL_RCC_PLLM_DIV_41 * @arg @ref LL_RCC_PLLM_DIV_42 * @arg @ref LL_RCC_PLLM_DIV_43 * @arg @ref LL_RCC_PLLM_DIV_44 * @arg @ref LL_RCC_PLLM_DIV_45 * @arg @ref LL_RCC_PLLM_DIV_46 * @arg @ref LL_RCC_PLLM_DIV_47 * @arg @ref LL_RCC_PLLM_DIV_48 * @arg @ref LL_RCC_PLLM_DIV_49 * @arg @ref LL_RCC_PLLM_DIV_50 * @arg @ref LL_RCC_PLLM_DIV_51 * @arg @ref LL_RCC_PLLM_DIV_52 * @arg @ref LL_RCC_PLLM_DIV_53 * @arg @ref LL_RCC_PLLM_DIV_54 * @arg @ref LL_RCC_PLLM_DIV_55 * @arg @ref LL_RCC_PLLM_DIV_56 * @arg @ref LL_RCC_PLLM_DIV_57 * @arg @ref LL_RCC_PLLM_DIV_58 * @arg @ref LL_RCC_PLLM_DIV_59 * @arg @ref LL_RCC_PLLM_DIV_60 * @arg @ref LL_RCC_PLLM_DIV_61 * @arg @ref LL_RCC_PLLM_DIV_62 * @arg @ref LL_RCC_PLLM_DIV_63 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) { return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); } /** * @brief Configure Spread Spectrum used for PLL * @note These bits must be written before enabling PLL * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum * @param Mod Between Min_Data=0 and Max_Data=8191 * @param Inc Between Min_Data=0 and Max_Data=32767 * @param Sel This parameter can be one of the following values: * @arg @ref LL_RCC_SPREAD_SELECT_CENTER * @arg @ref LL_RCC_SPREAD_SELECT_DOWN * @retval None */ __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel) { MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel); } /** * @brief Get Spread Spectrum Modulation Period for PLL * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation * @retval Between Min_Data=0 and Max_Data=8191 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void) { return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER)); } /** * @brief Get Spread Spectrum Incrementation Step for PLL * @note Must be written before enabling PLL * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation * @retval Between Min_Data=0 and Max_Data=32767 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void) { return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos); } /** * @brief Get Spread Spectrum Selection for PLL * @note Must be written before enabling PLL * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_SPREAD_SELECT_CENTER * @arg @ref LL_RCC_SPREAD_SELECT_DOWN */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void) { return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL)); } /** * @brief Enable Spread Spectrum for PLL. * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void) { SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); } /** * @brief Disable Spread Spectrum for PLL. * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void) { CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); } /** * @} */ #if defined(RCC_PLLI2S_SUPPORT) /** @defgroup RCC_LL_EF_PLLI2S PLLI2S * @{ */ /** * @brief Enable PLLI2S * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable * @retval None */ __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) { SET_BIT(RCC->CR, RCC_CR_PLLI2SON); } /** * @brief Disable PLLI2S * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable * @retval None */ __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) { CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); } /** * @brief Check if PLLI2S Ready * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) { return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY)); } #if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)) /** * @brief Configure PLLI2S used for SAI domain clock * @note PLL Source and PLLM Divider can be written only when PLL, * PLLI2S and PLLSAI(*) are disabled * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled * @note This can be selected for SAI * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n * DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n * DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) * * (*) value not defined in all devices. * @param PLLM This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SM_DIV_2 * @arg @ref LL_RCC_PLLI2SM_DIV_3 * @arg @ref LL_RCC_PLLI2SM_DIV_4 * @arg @ref LL_RCC_PLLI2SM_DIV_5 * @arg @ref LL_RCC_PLLI2SM_DIV_6 * @arg @ref LL_RCC_PLLI2SM_DIV_7 * @arg @ref LL_RCC_PLLI2SM_DIV_8 * @arg @ref LL_RCC_PLLI2SM_DIV_9 * @arg @ref LL_RCC_PLLI2SM_DIV_10 * @arg @ref LL_RCC_PLLI2SM_DIV_11 * @arg @ref LL_RCC_PLLI2SM_DIV_12 * @arg @ref LL_RCC_PLLI2SM_DIV_13 * @arg @ref LL_RCC_PLLI2SM_DIV_14 * @arg @ref LL_RCC_PLLI2SM_DIV_15 * @arg @ref LL_RCC_PLLI2SM_DIV_16 * @arg @ref LL_RCC_PLLI2SM_DIV_17 * @arg @ref LL_RCC_PLLI2SM_DIV_18 * @arg @ref LL_RCC_PLLI2SM_DIV_19 * @arg @ref LL_RCC_PLLI2SM_DIV_20 * @arg @ref LL_RCC_PLLI2SM_DIV_21 * @arg @ref LL_RCC_PLLI2SM_DIV_22 * @arg @ref LL_RCC_PLLI2SM_DIV_23 * @arg @ref LL_RCC_PLLI2SM_DIV_24 * @arg @ref LL_RCC_PLLI2SM_DIV_25 * @arg @ref LL_RCC_PLLI2SM_DIV_26 * @arg @ref LL_RCC_PLLI2SM_DIV_27 * @arg @ref LL_RCC_PLLI2SM_DIV_28 * @arg @ref LL_RCC_PLLI2SM_DIV_29 * @arg @ref LL_RCC_PLLI2SM_DIV_30 * @arg @ref LL_RCC_PLLI2SM_DIV_31 * @arg @ref LL_RCC_PLLI2SM_DIV_32 * @arg @ref LL_RCC_PLLI2SM_DIV_33 * @arg @ref LL_RCC_PLLI2SM_DIV_34 * @arg @ref LL_RCC_PLLI2SM_DIV_35 * @arg @ref LL_RCC_PLLI2SM_DIV_36 * @arg @ref LL_RCC_PLLI2SM_DIV_37 * @arg @ref LL_RCC_PLLI2SM_DIV_38 * @arg @ref LL_RCC_PLLI2SM_DIV_39 * @arg @ref LL_RCC_PLLI2SM_DIV_40 * @arg @ref LL_RCC_PLLI2SM_DIV_41 * @arg @ref LL_RCC_PLLI2SM_DIV_42 * @arg @ref LL_RCC_PLLI2SM_DIV_43 * @arg @ref LL_RCC_PLLI2SM_DIV_44 * @arg @ref LL_RCC_PLLI2SM_DIV_45 * @arg @ref LL_RCC_PLLI2SM_DIV_46 * @arg @ref LL_RCC_PLLI2SM_DIV_47 * @arg @ref LL_RCC_PLLI2SM_DIV_48 * @arg @ref LL_RCC_PLLI2SM_DIV_49 * @arg @ref LL_RCC_PLLI2SM_DIV_50 * @arg @ref LL_RCC_PLLI2SM_DIV_51 * @arg @ref LL_RCC_PLLI2SM_DIV_52 * @arg @ref LL_RCC_PLLI2SM_DIV_53 * @arg @ref LL_RCC_PLLI2SM_DIV_54 * @arg @ref LL_RCC_PLLI2SM_DIV_55 * @arg @ref LL_RCC_PLLI2SM_DIV_56 * @arg @ref LL_RCC_PLLI2SM_DIV_57 * @arg @ref LL_RCC_PLLI2SM_DIV_58 * @arg @ref LL_RCC_PLLI2SM_DIV_59 * @arg @ref LL_RCC_PLLI2SM_DIV_60 * @arg @ref LL_RCC_PLLI2SM_DIV_61 * @arg @ref LL_RCC_PLLI2SM_DIV_62 * @arg @ref LL_RCC_PLLI2SM_DIV_63 * @param PLLN Between 50/192(*) and 432 * * (*) value not defined in all devices. * @param PLLQ_R This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*) * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*) * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*) * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*) * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*) * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*) * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*) * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*) * * (*) value not defined in all devices. * @param PLLDIVQ_R This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*) * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*) * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R) { __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); #if defined(RCC_PLLI2SCFGR_PLLI2SM) MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); #else MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); #endif /* RCC_PLLI2SCFGR_PLLI2SM */ MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos); #if defined(RCC_DCKCFGR_PLLI2SDIVQ) MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R); MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R); #else MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R); MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R); #endif /* RCC_DCKCFGR_PLLI2SDIVQ */ } #endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */ #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) /** * @brief Configure PLLI2S used for 48Mhz domain clock * @note PLL Source and PLLM Divider can be written only when PLL, * PLLI2S and PLLSAI(*) are disabled * @note PLLN/PLLQ can be written only when PLLI2S is disabled * @note This can be selected for RNG, USB, SDIO * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) * * (*) value not defined in all devices. * @param PLLM This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SM_DIV_2 * @arg @ref LL_RCC_PLLI2SM_DIV_3 * @arg @ref LL_RCC_PLLI2SM_DIV_4 * @arg @ref LL_RCC_PLLI2SM_DIV_5 * @arg @ref LL_RCC_PLLI2SM_DIV_6 * @arg @ref LL_RCC_PLLI2SM_DIV_7 * @arg @ref LL_RCC_PLLI2SM_DIV_8 * @arg @ref LL_RCC_PLLI2SM_DIV_9 * @arg @ref LL_RCC_PLLI2SM_DIV_10 * @arg @ref LL_RCC_PLLI2SM_DIV_11 * @arg @ref LL_RCC_PLLI2SM_DIV_12 * @arg @ref LL_RCC_PLLI2SM_DIV_13 * @arg @ref LL_RCC_PLLI2SM_DIV_14 * @arg @ref LL_RCC_PLLI2SM_DIV_15 * @arg @ref LL_RCC_PLLI2SM_DIV_16 * @arg @ref LL_RCC_PLLI2SM_DIV_17 * @arg @ref LL_RCC_PLLI2SM_DIV_18 * @arg @ref LL_RCC_PLLI2SM_DIV_19 * @arg @ref LL_RCC_PLLI2SM_DIV_20 * @arg @ref LL_RCC_PLLI2SM_DIV_21 * @arg @ref LL_RCC_PLLI2SM_DIV_22 * @arg @ref LL_RCC_PLLI2SM_DIV_23 * @arg @ref LL_RCC_PLLI2SM_DIV_24 * @arg @ref LL_RCC_PLLI2SM_DIV_25 * @arg @ref LL_RCC_PLLI2SM_DIV_26 * @arg @ref LL_RCC_PLLI2SM_DIV_27 * @arg @ref LL_RCC_PLLI2SM_DIV_28 * @arg @ref LL_RCC_PLLI2SM_DIV_29 * @arg @ref LL_RCC_PLLI2SM_DIV_30 * @arg @ref LL_RCC_PLLI2SM_DIV_31 * @arg @ref LL_RCC_PLLI2SM_DIV_32 * @arg @ref LL_RCC_PLLI2SM_DIV_33 * @arg @ref LL_RCC_PLLI2SM_DIV_34 * @arg @ref LL_RCC_PLLI2SM_DIV_35 * @arg @ref LL_RCC_PLLI2SM_DIV_36 * @arg @ref LL_RCC_PLLI2SM_DIV_37 * @arg @ref LL_RCC_PLLI2SM_DIV_38 * @arg @ref LL_RCC_PLLI2SM_DIV_39 * @arg @ref LL_RCC_PLLI2SM_DIV_40 * @arg @ref LL_RCC_PLLI2SM_DIV_41 * @arg @ref LL_RCC_PLLI2SM_DIV_42 * @arg @ref LL_RCC_PLLI2SM_DIV_43 * @arg @ref LL_RCC_PLLI2SM_DIV_44 * @arg @ref LL_RCC_PLLI2SM_DIV_45 * @arg @ref LL_RCC_PLLI2SM_DIV_46 * @arg @ref LL_RCC_PLLI2SM_DIV_47 * @arg @ref LL_RCC_PLLI2SM_DIV_48 * @arg @ref LL_RCC_PLLI2SM_DIV_49 * @arg @ref LL_RCC_PLLI2SM_DIV_50 * @arg @ref LL_RCC_PLLI2SM_DIV_51 * @arg @ref LL_RCC_PLLI2SM_DIV_52 * @arg @ref LL_RCC_PLLI2SM_DIV_53 * @arg @ref LL_RCC_PLLI2SM_DIV_54 * @arg @ref LL_RCC_PLLI2SM_DIV_55 * @arg @ref LL_RCC_PLLI2SM_DIV_56 * @arg @ref LL_RCC_PLLI2SM_DIV_57 * @arg @ref LL_RCC_PLLI2SM_DIV_58 * @arg @ref LL_RCC_PLLI2SM_DIV_59 * @arg @ref LL_RCC_PLLI2SM_DIV_60 * @arg @ref LL_RCC_PLLI2SM_DIV_61 * @arg @ref LL_RCC_PLLI2SM_DIV_62 * @arg @ref LL_RCC_PLLI2SM_DIV_63 * @param PLLN Between 50 and 432 * @param PLLQ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SQ_DIV_2 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 * @retval None */ __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) { __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); #if defined(RCC_PLLI2SCFGR_PLLI2SM) MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); #else MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); #endif /* RCC_PLLI2SCFGR_PLLI2SM */ MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ); } #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ #if defined(SPDIFRX) /** * @brief Configure PLLI2S used for SPDIFRX domain clock * @note PLL Source and PLLM Divider can be written only when PLL, * PLLI2S and PLLSAI(*) are disabled * @note PLLN/PLLP can be written only when PLLI2S is disabled * @note This can be selected for SPDIFRX * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @param PLLM This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SM_DIV_2 * @arg @ref LL_RCC_PLLI2SM_DIV_3 * @arg @ref LL_RCC_PLLI2SM_DIV_4 * @arg @ref LL_RCC_PLLI2SM_DIV_5 * @arg @ref LL_RCC_PLLI2SM_DIV_6 * @arg @ref LL_RCC_PLLI2SM_DIV_7 * @arg @ref LL_RCC_PLLI2SM_DIV_8 * @arg @ref LL_RCC_PLLI2SM_DIV_9 * @arg @ref LL_RCC_PLLI2SM_DIV_10 * @arg @ref LL_RCC_PLLI2SM_DIV_11 * @arg @ref LL_RCC_PLLI2SM_DIV_12 * @arg @ref LL_RCC_PLLI2SM_DIV_13 * @arg @ref LL_RCC_PLLI2SM_DIV_14 * @arg @ref LL_RCC_PLLI2SM_DIV_15 * @arg @ref LL_RCC_PLLI2SM_DIV_16 * @arg @ref LL_RCC_PLLI2SM_DIV_17 * @arg @ref LL_RCC_PLLI2SM_DIV_18 * @arg @ref LL_RCC_PLLI2SM_DIV_19 * @arg @ref LL_RCC_PLLI2SM_DIV_20 * @arg @ref LL_RCC_PLLI2SM_DIV_21 * @arg @ref LL_RCC_PLLI2SM_DIV_22 * @arg @ref LL_RCC_PLLI2SM_DIV_23 * @arg @ref LL_RCC_PLLI2SM_DIV_24 * @arg @ref LL_RCC_PLLI2SM_DIV_25 * @arg @ref LL_RCC_PLLI2SM_DIV_26 * @arg @ref LL_RCC_PLLI2SM_DIV_27 * @arg @ref LL_RCC_PLLI2SM_DIV_28 * @arg @ref LL_RCC_PLLI2SM_DIV_29 * @arg @ref LL_RCC_PLLI2SM_DIV_30 * @arg @ref LL_RCC_PLLI2SM_DIV_31 * @arg @ref LL_RCC_PLLI2SM_DIV_32 * @arg @ref LL_RCC_PLLI2SM_DIV_33 * @arg @ref LL_RCC_PLLI2SM_DIV_34 * @arg @ref LL_RCC_PLLI2SM_DIV_35 * @arg @ref LL_RCC_PLLI2SM_DIV_36 * @arg @ref LL_RCC_PLLI2SM_DIV_37 * @arg @ref LL_RCC_PLLI2SM_DIV_38 * @arg @ref LL_RCC_PLLI2SM_DIV_39 * @arg @ref LL_RCC_PLLI2SM_DIV_40 * @arg @ref LL_RCC_PLLI2SM_DIV_41 * @arg @ref LL_RCC_PLLI2SM_DIV_42 * @arg @ref LL_RCC_PLLI2SM_DIV_43 * @arg @ref LL_RCC_PLLI2SM_DIV_44 * @arg @ref LL_RCC_PLLI2SM_DIV_45 * @arg @ref LL_RCC_PLLI2SM_DIV_46 * @arg @ref LL_RCC_PLLI2SM_DIV_47 * @arg @ref LL_RCC_PLLI2SM_DIV_48 * @arg @ref LL_RCC_PLLI2SM_DIV_49 * @arg @ref LL_RCC_PLLI2SM_DIV_50 * @arg @ref LL_RCC_PLLI2SM_DIV_51 * @arg @ref LL_RCC_PLLI2SM_DIV_52 * @arg @ref LL_RCC_PLLI2SM_DIV_53 * @arg @ref LL_RCC_PLLI2SM_DIV_54 * @arg @ref LL_RCC_PLLI2SM_DIV_55 * @arg @ref LL_RCC_PLLI2SM_DIV_56 * @arg @ref LL_RCC_PLLI2SM_DIV_57 * @arg @ref LL_RCC_PLLI2SM_DIV_58 * @arg @ref LL_RCC_PLLI2SM_DIV_59 * @arg @ref LL_RCC_PLLI2SM_DIV_60 * @arg @ref LL_RCC_PLLI2SM_DIV_61 * @arg @ref LL_RCC_PLLI2SM_DIV_62 * @arg @ref LL_RCC_PLLI2SM_DIV_63 * @param PLLN Between 50 and 432 * @param PLLP This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SP_DIV_2 * @arg @ref LL_RCC_PLLI2SP_DIV_4 * @arg @ref LL_RCC_PLLI2SP_DIV_6 * @arg @ref LL_RCC_PLLI2SP_DIV_8 * @retval None */ __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); #if defined(RCC_PLLI2SCFGR_PLLI2SM) MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); #else MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); #endif /* RCC_PLLI2SCFGR_PLLI2SM */ MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP); } #endif /* SPDIFRX */ /** * @brief Configure PLLI2S used for I2S1 domain clock * @note PLL Source and PLLM Divider can be written only when PLL, * PLLI2S and PLLSAI(*) are disabled * @note PLLN/PLLR can be written only when PLLI2S is disabled * @note This can be selected for I2S * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) * * (*) value not defined in all devices. * @param PLLM This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SM_DIV_2 * @arg @ref LL_RCC_PLLI2SM_DIV_3 * @arg @ref LL_RCC_PLLI2SM_DIV_4 * @arg @ref LL_RCC_PLLI2SM_DIV_5 * @arg @ref LL_RCC_PLLI2SM_DIV_6 * @arg @ref LL_RCC_PLLI2SM_DIV_7 * @arg @ref LL_RCC_PLLI2SM_DIV_8 * @arg @ref LL_RCC_PLLI2SM_DIV_9 * @arg @ref LL_RCC_PLLI2SM_DIV_10 * @arg @ref LL_RCC_PLLI2SM_DIV_11 * @arg @ref LL_RCC_PLLI2SM_DIV_12 * @arg @ref LL_RCC_PLLI2SM_DIV_13 * @arg @ref LL_RCC_PLLI2SM_DIV_14 * @arg @ref LL_RCC_PLLI2SM_DIV_15 * @arg @ref LL_RCC_PLLI2SM_DIV_16 * @arg @ref LL_RCC_PLLI2SM_DIV_17 * @arg @ref LL_RCC_PLLI2SM_DIV_18 * @arg @ref LL_RCC_PLLI2SM_DIV_19 * @arg @ref LL_RCC_PLLI2SM_DIV_20 * @arg @ref LL_RCC_PLLI2SM_DIV_21 * @arg @ref LL_RCC_PLLI2SM_DIV_22 * @arg @ref LL_RCC_PLLI2SM_DIV_23 * @arg @ref LL_RCC_PLLI2SM_DIV_24 * @arg @ref LL_RCC_PLLI2SM_DIV_25 * @arg @ref LL_RCC_PLLI2SM_DIV_26 * @arg @ref LL_RCC_PLLI2SM_DIV_27 * @arg @ref LL_RCC_PLLI2SM_DIV_28 * @arg @ref LL_RCC_PLLI2SM_DIV_29 * @arg @ref LL_RCC_PLLI2SM_DIV_30 * @arg @ref LL_RCC_PLLI2SM_DIV_31 * @arg @ref LL_RCC_PLLI2SM_DIV_32 * @arg @ref LL_RCC_PLLI2SM_DIV_33 * @arg @ref LL_RCC_PLLI2SM_DIV_34 * @arg @ref LL_RCC_PLLI2SM_DIV_35 * @arg @ref LL_RCC_PLLI2SM_DIV_36 * @arg @ref LL_RCC_PLLI2SM_DIV_37 * @arg @ref LL_RCC_PLLI2SM_DIV_38 * @arg @ref LL_RCC_PLLI2SM_DIV_39 * @arg @ref LL_RCC_PLLI2SM_DIV_40 * @arg @ref LL_RCC_PLLI2SM_DIV_41 * @arg @ref LL_RCC_PLLI2SM_DIV_42 * @arg @ref LL_RCC_PLLI2SM_DIV_43 * @arg @ref LL_RCC_PLLI2SM_DIV_44 * @arg @ref LL_RCC_PLLI2SM_DIV_45 * @arg @ref LL_RCC_PLLI2SM_DIV_46 * @arg @ref LL_RCC_PLLI2SM_DIV_47 * @arg @ref LL_RCC_PLLI2SM_DIV_48 * @arg @ref LL_RCC_PLLI2SM_DIV_49 * @arg @ref LL_RCC_PLLI2SM_DIV_50 * @arg @ref LL_RCC_PLLI2SM_DIV_51 * @arg @ref LL_RCC_PLLI2SM_DIV_52 * @arg @ref LL_RCC_PLLI2SM_DIV_53 * @arg @ref LL_RCC_PLLI2SM_DIV_54 * @arg @ref LL_RCC_PLLI2SM_DIV_55 * @arg @ref LL_RCC_PLLI2SM_DIV_56 * @arg @ref LL_RCC_PLLI2SM_DIV_57 * @arg @ref LL_RCC_PLLI2SM_DIV_58 * @arg @ref LL_RCC_PLLI2SM_DIV_59 * @arg @ref LL_RCC_PLLI2SM_DIV_60 * @arg @ref LL_RCC_PLLI2SM_DIV_61 * @arg @ref LL_RCC_PLLI2SM_DIV_62 * @arg @ref LL_RCC_PLLI2SM_DIV_63 * @param PLLN Between 50/192(*) and 432 * * (*) value not defined in all devices. * @param PLLR This parameter can be one of the following values: * @arg @ref LL_RCC_PLLI2SR_DIV_2 * @arg @ref LL_RCC_PLLI2SR_DIV_3 * @arg @ref LL_RCC_PLLI2SR_DIV_4 * @arg @ref LL_RCC_PLLI2SR_DIV_5 * @arg @ref LL_RCC_PLLI2SR_DIV_6 * @arg @ref LL_RCC_PLLI2SR_DIV_7 * @retval None */ __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) { __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); #if defined(RCC_PLLI2SCFGR_PLLI2SM) MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); #else MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); #endif /* RCC_PLLI2SCFGR_PLLI2SM */ MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR); } /** * @brief Get I2SPLL multiplication factor for VCO * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN * @retval Between 50/192(*) and 432 * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void) { return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); } #if defined(RCC_PLLI2SCFGR_PLLI2SQ) /** * @brief Get I2SPLL division factor for PLLI2SQ * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLI2SQ_DIV_2 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 */ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void) { return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ)); } #endif /* RCC_PLLI2SCFGR_PLLI2SQ */ /** * @brief Get I2SPLL division factor for PLLI2SR * @note used for PLLI2SCLK (I2S clock) * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLI2SR_DIV_2 * @arg @ref LL_RCC_PLLI2SR_DIV_3 * @arg @ref LL_RCC_PLLI2SR_DIV_4 * @arg @ref LL_RCC_PLLI2SR_DIV_5 * @arg @ref LL_RCC_PLLI2SR_DIV_6 * @arg @ref LL_RCC_PLLI2SR_DIV_7 */ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void) { return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR)); } #if defined(RCC_PLLI2SCFGR_PLLI2SP) /** * @brief Get I2SPLL division factor for PLLI2SP * @note used for PLLSPDIFRXCLK (SPDIFRX clock) * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLI2SP_DIV_2 * @arg @ref LL_RCC_PLLI2SP_DIV_4 * @arg @ref LL_RCC_PLLI2SP_DIV_6 * @arg @ref LL_RCC_PLLI2SP_DIV_8 */ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void) { return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP)); } #endif /* RCC_PLLI2SCFGR_PLLI2SP */ #if defined(RCC_DCKCFGR_PLLI2SDIVQ) /** * @brief Get I2SPLL division factor for PLLI2SDIVQ * @note used PLLSAICLK selected (SAI clock) * @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 */ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void) { return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ)); } #endif /* RCC_DCKCFGR_PLLI2SDIVQ */ #if defined(RCC_DCKCFGR_PLLI2SDIVR) /** * @brief Get I2SPLL division factor for PLLI2SDIVR * @note used PLLSAICLK selected (SAI clock) * @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 */ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void) { return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR)); } #endif /* RCC_DCKCFGR_PLLI2SDIVR */ /** * @brief Get division factor for PLLI2S input clock * @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLI2SM_DIV_2 * @arg @ref LL_RCC_PLLI2SM_DIV_3 * @arg @ref LL_RCC_PLLI2SM_DIV_4 * @arg @ref LL_RCC_PLLI2SM_DIV_5 * @arg @ref LL_RCC_PLLI2SM_DIV_6 * @arg @ref LL_RCC_PLLI2SM_DIV_7 * @arg @ref LL_RCC_PLLI2SM_DIV_8 * @arg @ref LL_RCC_PLLI2SM_DIV_9 * @arg @ref LL_RCC_PLLI2SM_DIV_10 * @arg @ref LL_RCC_PLLI2SM_DIV_11 * @arg @ref LL_RCC_PLLI2SM_DIV_12 * @arg @ref LL_RCC_PLLI2SM_DIV_13 * @arg @ref LL_RCC_PLLI2SM_DIV_14 * @arg @ref LL_RCC_PLLI2SM_DIV_15 * @arg @ref LL_RCC_PLLI2SM_DIV_16 * @arg @ref LL_RCC_PLLI2SM_DIV_17 * @arg @ref LL_RCC_PLLI2SM_DIV_18 * @arg @ref LL_RCC_PLLI2SM_DIV_19 * @arg @ref LL_RCC_PLLI2SM_DIV_20 * @arg @ref LL_RCC_PLLI2SM_DIV_21 * @arg @ref LL_RCC_PLLI2SM_DIV_22 * @arg @ref LL_RCC_PLLI2SM_DIV_23 * @arg @ref LL_RCC_PLLI2SM_DIV_24 * @arg @ref LL_RCC_PLLI2SM_DIV_25 * @arg @ref LL_RCC_PLLI2SM_DIV_26 * @arg @ref LL_RCC_PLLI2SM_DIV_27 * @arg @ref LL_RCC_PLLI2SM_DIV_28 * @arg @ref LL_RCC_PLLI2SM_DIV_29 * @arg @ref LL_RCC_PLLI2SM_DIV_30 * @arg @ref LL_RCC_PLLI2SM_DIV_31 * @arg @ref LL_RCC_PLLI2SM_DIV_32 * @arg @ref LL_RCC_PLLI2SM_DIV_33 * @arg @ref LL_RCC_PLLI2SM_DIV_34 * @arg @ref LL_RCC_PLLI2SM_DIV_35 * @arg @ref LL_RCC_PLLI2SM_DIV_36 * @arg @ref LL_RCC_PLLI2SM_DIV_37 * @arg @ref LL_RCC_PLLI2SM_DIV_38 * @arg @ref LL_RCC_PLLI2SM_DIV_39 * @arg @ref LL_RCC_PLLI2SM_DIV_40 * @arg @ref LL_RCC_PLLI2SM_DIV_41 * @arg @ref LL_RCC_PLLI2SM_DIV_42 * @arg @ref LL_RCC_PLLI2SM_DIV_43 * @arg @ref LL_RCC_PLLI2SM_DIV_44 * @arg @ref LL_RCC_PLLI2SM_DIV_45 * @arg @ref LL_RCC_PLLI2SM_DIV_46 * @arg @ref LL_RCC_PLLI2SM_DIV_47 * @arg @ref LL_RCC_PLLI2SM_DIV_48 * @arg @ref LL_RCC_PLLI2SM_DIV_49 * @arg @ref LL_RCC_PLLI2SM_DIV_50 * @arg @ref LL_RCC_PLLI2SM_DIV_51 * @arg @ref LL_RCC_PLLI2SM_DIV_52 * @arg @ref LL_RCC_PLLI2SM_DIV_53 * @arg @ref LL_RCC_PLLI2SM_DIV_54 * @arg @ref LL_RCC_PLLI2SM_DIV_55 * @arg @ref LL_RCC_PLLI2SM_DIV_56 * @arg @ref LL_RCC_PLLI2SM_DIV_57 * @arg @ref LL_RCC_PLLI2SM_DIV_58 * @arg @ref LL_RCC_PLLI2SM_DIV_59 * @arg @ref LL_RCC_PLLI2SM_DIV_60 * @arg @ref LL_RCC_PLLI2SM_DIV_61 * @arg @ref LL_RCC_PLLI2SM_DIV_62 * @arg @ref LL_RCC_PLLI2SM_DIV_63 */ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void) { #if defined(RCC_PLLI2SCFGR_PLLI2SM) return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM)); #else return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); #endif /* RCC_PLLI2SCFGR_PLLI2SM */ } /** * @brief Get the oscillator used as PLL clock source. * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void) { #if defined(RCC_PLLI2SCFGR_PLLI2SSRC) uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC); uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U; return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1); #else return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ } /** * @} */ #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_PLLSAI_SUPPORT) /** @defgroup RCC_LL_EF_PLLSAI PLLSAI * @{ */ /** * @brief Enable PLLSAI * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable * @retval None */ __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void) { SET_BIT(RCC->CR, RCC_CR_PLLSAION); } /** * @brief Disable PLLSAI * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable * @retval None */ __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void) { CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); } /** * @brief Check if PLLSAI Ready * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void) { return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY)); } /** * @brief Configure PLLSAI used for SAI domain clock * @note PLL Source and PLLM Divider can be written only when PLL, * PLLI2S and PLLSAI(*) are disabled * @note PLLN/PLLQ can be written only when PLLSAI is disabled * @note This can be selected for SAI * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n * DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @param PLLM This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIM_DIV_2 * @arg @ref LL_RCC_PLLSAIM_DIV_3 * @arg @ref LL_RCC_PLLSAIM_DIV_4 * @arg @ref LL_RCC_PLLSAIM_DIV_5 * @arg @ref LL_RCC_PLLSAIM_DIV_6 * @arg @ref LL_RCC_PLLSAIM_DIV_7 * @arg @ref LL_RCC_PLLSAIM_DIV_8 * @arg @ref LL_RCC_PLLSAIM_DIV_9 * @arg @ref LL_RCC_PLLSAIM_DIV_10 * @arg @ref LL_RCC_PLLSAIM_DIV_11 * @arg @ref LL_RCC_PLLSAIM_DIV_12 * @arg @ref LL_RCC_PLLSAIM_DIV_13 * @arg @ref LL_RCC_PLLSAIM_DIV_14 * @arg @ref LL_RCC_PLLSAIM_DIV_15 * @arg @ref LL_RCC_PLLSAIM_DIV_16 * @arg @ref LL_RCC_PLLSAIM_DIV_17 * @arg @ref LL_RCC_PLLSAIM_DIV_18 * @arg @ref LL_RCC_PLLSAIM_DIV_19 * @arg @ref LL_RCC_PLLSAIM_DIV_20 * @arg @ref LL_RCC_PLLSAIM_DIV_21 * @arg @ref LL_RCC_PLLSAIM_DIV_22 * @arg @ref LL_RCC_PLLSAIM_DIV_23 * @arg @ref LL_RCC_PLLSAIM_DIV_24 * @arg @ref LL_RCC_PLLSAIM_DIV_25 * @arg @ref LL_RCC_PLLSAIM_DIV_26 * @arg @ref LL_RCC_PLLSAIM_DIV_27 * @arg @ref LL_RCC_PLLSAIM_DIV_28 * @arg @ref LL_RCC_PLLSAIM_DIV_29 * @arg @ref LL_RCC_PLLSAIM_DIV_30 * @arg @ref LL_RCC_PLLSAIM_DIV_31 * @arg @ref LL_RCC_PLLSAIM_DIV_32 * @arg @ref LL_RCC_PLLSAIM_DIV_33 * @arg @ref LL_RCC_PLLSAIM_DIV_34 * @arg @ref LL_RCC_PLLSAIM_DIV_35 * @arg @ref LL_RCC_PLLSAIM_DIV_36 * @arg @ref LL_RCC_PLLSAIM_DIV_37 * @arg @ref LL_RCC_PLLSAIM_DIV_38 * @arg @ref LL_RCC_PLLSAIM_DIV_39 * @arg @ref LL_RCC_PLLSAIM_DIV_40 * @arg @ref LL_RCC_PLLSAIM_DIV_41 * @arg @ref LL_RCC_PLLSAIM_DIV_42 * @arg @ref LL_RCC_PLLSAIM_DIV_43 * @arg @ref LL_RCC_PLLSAIM_DIV_44 * @arg @ref LL_RCC_PLLSAIM_DIV_45 * @arg @ref LL_RCC_PLLSAIM_DIV_46 * @arg @ref LL_RCC_PLLSAIM_DIV_47 * @arg @ref LL_RCC_PLLSAIM_DIV_48 * @arg @ref LL_RCC_PLLSAIM_DIV_49 * @arg @ref LL_RCC_PLLSAIM_DIV_50 * @arg @ref LL_RCC_PLLSAIM_DIV_51 * @arg @ref LL_RCC_PLLSAIM_DIV_52 * @arg @ref LL_RCC_PLLSAIM_DIV_53 * @arg @ref LL_RCC_PLLSAIM_DIV_54 * @arg @ref LL_RCC_PLLSAIM_DIV_55 * @arg @ref LL_RCC_PLLSAIM_DIV_56 * @arg @ref LL_RCC_PLLSAIM_DIV_57 * @arg @ref LL_RCC_PLLSAIM_DIV_58 * @arg @ref LL_RCC_PLLSAIM_DIV_59 * @arg @ref LL_RCC_PLLSAIM_DIV_60 * @arg @ref LL_RCC_PLLSAIM_DIV_61 * @arg @ref LL_RCC_PLLSAIM_DIV_62 * @arg @ref LL_RCC_PLLSAIM_DIV_63 * @param PLLN Between 49/50(*) and 432 * * (*) value not defined in all devices. * @param PLLQ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIQ_DIV_2 * @arg @ref LL_RCC_PLLSAIQ_DIV_3 * @arg @ref LL_RCC_PLLSAIQ_DIV_4 * @arg @ref LL_RCC_PLLSAIQ_DIV_5 * @arg @ref LL_RCC_PLLSAIQ_DIV_6 * @arg @ref LL_RCC_PLLSAIQ_DIV_7 * @arg @ref LL_RCC_PLLSAIQ_DIV_8 * @arg @ref LL_RCC_PLLSAIQ_DIV_9 * @arg @ref LL_RCC_PLLSAIQ_DIV_10 * @arg @ref LL_RCC_PLLSAIQ_DIV_11 * @arg @ref LL_RCC_PLLSAIQ_DIV_12 * @arg @ref LL_RCC_PLLSAIQ_DIV_13 * @arg @ref LL_RCC_PLLSAIQ_DIV_14 * @arg @ref LL_RCC_PLLSAIQ_DIV_15 * @param PLLDIVQ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 * @retval None */ __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); #if defined(RCC_PLLSAICFGR_PLLSAIM) MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM); #else MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); #endif /* RCC_PLLSAICFGR_PLLSAIM */ MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ); MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ); } #if defined(RCC_PLLSAICFGR_PLLSAIP) /** * @brief Configure PLLSAI used for 48Mhz domain clock * @note PLL Source and PLLM Divider can be written only when PLL, * PLLI2S and PLLSAI(*) are disabled * @note PLLN/PLLP can be written only when PLLSAI is disabled * @note This can be selected for USB, RNG, SDIO * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @param PLLM This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIM_DIV_2 * @arg @ref LL_RCC_PLLSAIM_DIV_3 * @arg @ref LL_RCC_PLLSAIM_DIV_4 * @arg @ref LL_RCC_PLLSAIM_DIV_5 * @arg @ref LL_RCC_PLLSAIM_DIV_6 * @arg @ref LL_RCC_PLLSAIM_DIV_7 * @arg @ref LL_RCC_PLLSAIM_DIV_8 * @arg @ref LL_RCC_PLLSAIM_DIV_9 * @arg @ref LL_RCC_PLLSAIM_DIV_10 * @arg @ref LL_RCC_PLLSAIM_DIV_11 * @arg @ref LL_RCC_PLLSAIM_DIV_12 * @arg @ref LL_RCC_PLLSAIM_DIV_13 * @arg @ref LL_RCC_PLLSAIM_DIV_14 * @arg @ref LL_RCC_PLLSAIM_DIV_15 * @arg @ref LL_RCC_PLLSAIM_DIV_16 * @arg @ref LL_RCC_PLLSAIM_DIV_17 * @arg @ref LL_RCC_PLLSAIM_DIV_18 * @arg @ref LL_RCC_PLLSAIM_DIV_19 * @arg @ref LL_RCC_PLLSAIM_DIV_20 * @arg @ref LL_RCC_PLLSAIM_DIV_21 * @arg @ref LL_RCC_PLLSAIM_DIV_22 * @arg @ref LL_RCC_PLLSAIM_DIV_23 * @arg @ref LL_RCC_PLLSAIM_DIV_24 * @arg @ref LL_RCC_PLLSAIM_DIV_25 * @arg @ref LL_RCC_PLLSAIM_DIV_26 * @arg @ref LL_RCC_PLLSAIM_DIV_27 * @arg @ref LL_RCC_PLLSAIM_DIV_28 * @arg @ref LL_RCC_PLLSAIM_DIV_29 * @arg @ref LL_RCC_PLLSAIM_DIV_30 * @arg @ref LL_RCC_PLLSAIM_DIV_31 * @arg @ref LL_RCC_PLLSAIM_DIV_32 * @arg @ref LL_RCC_PLLSAIM_DIV_33 * @arg @ref LL_RCC_PLLSAIM_DIV_34 * @arg @ref LL_RCC_PLLSAIM_DIV_35 * @arg @ref LL_RCC_PLLSAIM_DIV_36 * @arg @ref LL_RCC_PLLSAIM_DIV_37 * @arg @ref LL_RCC_PLLSAIM_DIV_38 * @arg @ref LL_RCC_PLLSAIM_DIV_39 * @arg @ref LL_RCC_PLLSAIM_DIV_40 * @arg @ref LL_RCC_PLLSAIM_DIV_41 * @arg @ref LL_RCC_PLLSAIM_DIV_42 * @arg @ref LL_RCC_PLLSAIM_DIV_43 * @arg @ref LL_RCC_PLLSAIM_DIV_44 * @arg @ref LL_RCC_PLLSAIM_DIV_45 * @arg @ref LL_RCC_PLLSAIM_DIV_46 * @arg @ref LL_RCC_PLLSAIM_DIV_47 * @arg @ref LL_RCC_PLLSAIM_DIV_48 * @arg @ref LL_RCC_PLLSAIM_DIV_49 * @arg @ref LL_RCC_PLLSAIM_DIV_50 * @arg @ref LL_RCC_PLLSAIM_DIV_51 * @arg @ref LL_RCC_PLLSAIM_DIV_52 * @arg @ref LL_RCC_PLLSAIM_DIV_53 * @arg @ref LL_RCC_PLLSAIM_DIV_54 * @arg @ref LL_RCC_PLLSAIM_DIV_55 * @arg @ref LL_RCC_PLLSAIM_DIV_56 * @arg @ref LL_RCC_PLLSAIM_DIV_57 * @arg @ref LL_RCC_PLLSAIM_DIV_58 * @arg @ref LL_RCC_PLLSAIM_DIV_59 * @arg @ref LL_RCC_PLLSAIM_DIV_60 * @arg @ref LL_RCC_PLLSAIM_DIV_61 * @arg @ref LL_RCC_PLLSAIM_DIV_62 * @arg @ref LL_RCC_PLLSAIM_DIV_63 * @param PLLN Between 50 and 432 * @param PLLP This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIP_DIV_2 * @arg @ref LL_RCC_PLLSAIP_DIV_4 * @arg @ref LL_RCC_PLLSAIP_DIV_6 * @arg @ref LL_RCC_PLLSAIP_DIV_8 * @retval None */ __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); #if defined(RCC_PLLSAICFGR_PLLSAIM) MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM); #else MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); #endif /* RCC_PLLSAICFGR_PLLSAIM */ MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP); } #endif /* RCC_PLLSAICFGR_PLLSAIP */ #if defined(LTDC) /** * @brief Configure PLLSAI used for LTDC domain clock * @note PLL Source and PLLM Divider can be written only when PLL, * PLLI2S and PLLSAI(*) are disabled * @note PLLN/PLLR can be written only when PLLSAI is disabled * @note This can be selected for LTDC * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n * DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @param PLLM This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIM_DIV_2 * @arg @ref LL_RCC_PLLSAIM_DIV_3 * @arg @ref LL_RCC_PLLSAIM_DIV_4 * @arg @ref LL_RCC_PLLSAIM_DIV_5 * @arg @ref LL_RCC_PLLSAIM_DIV_6 * @arg @ref LL_RCC_PLLSAIM_DIV_7 * @arg @ref LL_RCC_PLLSAIM_DIV_8 * @arg @ref LL_RCC_PLLSAIM_DIV_9 * @arg @ref LL_RCC_PLLSAIM_DIV_10 * @arg @ref LL_RCC_PLLSAIM_DIV_11 * @arg @ref LL_RCC_PLLSAIM_DIV_12 * @arg @ref LL_RCC_PLLSAIM_DIV_13 * @arg @ref LL_RCC_PLLSAIM_DIV_14 * @arg @ref LL_RCC_PLLSAIM_DIV_15 * @arg @ref LL_RCC_PLLSAIM_DIV_16 * @arg @ref LL_RCC_PLLSAIM_DIV_17 * @arg @ref LL_RCC_PLLSAIM_DIV_18 * @arg @ref LL_RCC_PLLSAIM_DIV_19 * @arg @ref LL_RCC_PLLSAIM_DIV_20 * @arg @ref LL_RCC_PLLSAIM_DIV_21 * @arg @ref LL_RCC_PLLSAIM_DIV_22 * @arg @ref LL_RCC_PLLSAIM_DIV_23 * @arg @ref LL_RCC_PLLSAIM_DIV_24 * @arg @ref LL_RCC_PLLSAIM_DIV_25 * @arg @ref LL_RCC_PLLSAIM_DIV_26 * @arg @ref LL_RCC_PLLSAIM_DIV_27 * @arg @ref LL_RCC_PLLSAIM_DIV_28 * @arg @ref LL_RCC_PLLSAIM_DIV_29 * @arg @ref LL_RCC_PLLSAIM_DIV_30 * @arg @ref LL_RCC_PLLSAIM_DIV_31 * @arg @ref LL_RCC_PLLSAIM_DIV_32 * @arg @ref LL_RCC_PLLSAIM_DIV_33 * @arg @ref LL_RCC_PLLSAIM_DIV_34 * @arg @ref LL_RCC_PLLSAIM_DIV_35 * @arg @ref LL_RCC_PLLSAIM_DIV_36 * @arg @ref LL_RCC_PLLSAIM_DIV_37 * @arg @ref LL_RCC_PLLSAIM_DIV_38 * @arg @ref LL_RCC_PLLSAIM_DIV_39 * @arg @ref LL_RCC_PLLSAIM_DIV_40 * @arg @ref LL_RCC_PLLSAIM_DIV_41 * @arg @ref LL_RCC_PLLSAIM_DIV_42 * @arg @ref LL_RCC_PLLSAIM_DIV_43 * @arg @ref LL_RCC_PLLSAIM_DIV_44 * @arg @ref LL_RCC_PLLSAIM_DIV_45 * @arg @ref LL_RCC_PLLSAIM_DIV_46 * @arg @ref LL_RCC_PLLSAIM_DIV_47 * @arg @ref LL_RCC_PLLSAIM_DIV_48 * @arg @ref LL_RCC_PLLSAIM_DIV_49 * @arg @ref LL_RCC_PLLSAIM_DIV_50 * @arg @ref LL_RCC_PLLSAIM_DIV_51 * @arg @ref LL_RCC_PLLSAIM_DIV_52 * @arg @ref LL_RCC_PLLSAIM_DIV_53 * @arg @ref LL_RCC_PLLSAIM_DIV_54 * @arg @ref LL_RCC_PLLSAIM_DIV_55 * @arg @ref LL_RCC_PLLSAIM_DIV_56 * @arg @ref LL_RCC_PLLSAIM_DIV_57 * @arg @ref LL_RCC_PLLSAIM_DIV_58 * @arg @ref LL_RCC_PLLSAIM_DIV_59 * @arg @ref LL_RCC_PLLSAIM_DIV_60 * @arg @ref LL_RCC_PLLSAIM_DIV_61 * @arg @ref LL_RCC_PLLSAIM_DIV_62 * @arg @ref LL_RCC_PLLSAIM_DIV_63 * @param PLLN Between 49/50(*) and 432 * * (*) value not defined in all devices. * @param PLLR This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIR_DIV_2 * @arg @ref LL_RCC_PLLSAIR_DIV_3 * @arg @ref LL_RCC_PLLSAIR_DIV_4 * @arg @ref LL_RCC_PLLSAIR_DIV_5 * @arg @ref LL_RCC_PLLSAIR_DIV_6 * @arg @ref LL_RCC_PLLSAIR_DIV_7 * @param PLLDIVR This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 * @retval None */ __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR); MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR); } #endif /* LTDC */ /** * @brief Get division factor for PLLSAI input clock * @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAIM_DIV_2 * @arg @ref LL_RCC_PLLSAIM_DIV_3 * @arg @ref LL_RCC_PLLSAIM_DIV_4 * @arg @ref LL_RCC_PLLSAIM_DIV_5 * @arg @ref LL_RCC_PLLSAIM_DIV_6 * @arg @ref LL_RCC_PLLSAIM_DIV_7 * @arg @ref LL_RCC_PLLSAIM_DIV_8 * @arg @ref LL_RCC_PLLSAIM_DIV_9 * @arg @ref LL_RCC_PLLSAIM_DIV_10 * @arg @ref LL_RCC_PLLSAIM_DIV_11 * @arg @ref LL_RCC_PLLSAIM_DIV_12 * @arg @ref LL_RCC_PLLSAIM_DIV_13 * @arg @ref LL_RCC_PLLSAIM_DIV_14 * @arg @ref LL_RCC_PLLSAIM_DIV_15 * @arg @ref LL_RCC_PLLSAIM_DIV_16 * @arg @ref LL_RCC_PLLSAIM_DIV_17 * @arg @ref LL_RCC_PLLSAIM_DIV_18 * @arg @ref LL_RCC_PLLSAIM_DIV_19 * @arg @ref LL_RCC_PLLSAIM_DIV_20 * @arg @ref LL_RCC_PLLSAIM_DIV_21 * @arg @ref LL_RCC_PLLSAIM_DIV_22 * @arg @ref LL_RCC_PLLSAIM_DIV_23 * @arg @ref LL_RCC_PLLSAIM_DIV_24 * @arg @ref LL_RCC_PLLSAIM_DIV_25 * @arg @ref LL_RCC_PLLSAIM_DIV_26 * @arg @ref LL_RCC_PLLSAIM_DIV_27 * @arg @ref LL_RCC_PLLSAIM_DIV_28 * @arg @ref LL_RCC_PLLSAIM_DIV_29 * @arg @ref LL_RCC_PLLSAIM_DIV_30 * @arg @ref LL_RCC_PLLSAIM_DIV_31 * @arg @ref LL_RCC_PLLSAIM_DIV_32 * @arg @ref LL_RCC_PLLSAIM_DIV_33 * @arg @ref LL_RCC_PLLSAIM_DIV_34 * @arg @ref LL_RCC_PLLSAIM_DIV_35 * @arg @ref LL_RCC_PLLSAIM_DIV_36 * @arg @ref LL_RCC_PLLSAIM_DIV_37 * @arg @ref LL_RCC_PLLSAIM_DIV_38 * @arg @ref LL_RCC_PLLSAIM_DIV_39 * @arg @ref LL_RCC_PLLSAIM_DIV_40 * @arg @ref LL_RCC_PLLSAIM_DIV_41 * @arg @ref LL_RCC_PLLSAIM_DIV_42 * @arg @ref LL_RCC_PLLSAIM_DIV_43 * @arg @ref LL_RCC_PLLSAIM_DIV_44 * @arg @ref LL_RCC_PLLSAIM_DIV_45 * @arg @ref LL_RCC_PLLSAIM_DIV_46 * @arg @ref LL_RCC_PLLSAIM_DIV_47 * @arg @ref LL_RCC_PLLSAIM_DIV_48 * @arg @ref LL_RCC_PLLSAIM_DIV_49 * @arg @ref LL_RCC_PLLSAIM_DIV_50 * @arg @ref LL_RCC_PLLSAIM_DIV_51 * @arg @ref LL_RCC_PLLSAIM_DIV_52 * @arg @ref LL_RCC_PLLSAIM_DIV_53 * @arg @ref LL_RCC_PLLSAIM_DIV_54 * @arg @ref LL_RCC_PLLSAIM_DIV_55 * @arg @ref LL_RCC_PLLSAIM_DIV_56 * @arg @ref LL_RCC_PLLSAIM_DIV_57 * @arg @ref LL_RCC_PLLSAIM_DIV_58 * @arg @ref LL_RCC_PLLSAIM_DIV_59 * @arg @ref LL_RCC_PLLSAIM_DIV_60 * @arg @ref LL_RCC_PLLSAIM_DIV_61 * @arg @ref LL_RCC_PLLSAIM_DIV_62 * @arg @ref LL_RCC_PLLSAIM_DIV_63 */ __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void) { #if defined(RCC_PLLSAICFGR_PLLSAIM) return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM)); #else return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); #endif /* RCC_PLLSAICFGR_PLLSAIM */ } /** * @brief Get SAIPLL multiplication factor for VCO * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN * @retval Between 49/50(*) and 432 * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void) { return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); } /** * @brief Get SAIPLL division factor for PLLSAIQ * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAIQ_DIV_2 * @arg @ref LL_RCC_PLLSAIQ_DIV_3 * @arg @ref LL_RCC_PLLSAIQ_DIV_4 * @arg @ref LL_RCC_PLLSAIQ_DIV_5 * @arg @ref LL_RCC_PLLSAIQ_DIV_6 * @arg @ref LL_RCC_PLLSAIQ_DIV_7 * @arg @ref LL_RCC_PLLSAIQ_DIV_8 * @arg @ref LL_RCC_PLLSAIQ_DIV_9 * @arg @ref LL_RCC_PLLSAIQ_DIV_10 * @arg @ref LL_RCC_PLLSAIQ_DIV_11 * @arg @ref LL_RCC_PLLSAIQ_DIV_12 * @arg @ref LL_RCC_PLLSAIQ_DIV_13 * @arg @ref LL_RCC_PLLSAIQ_DIV_14 * @arg @ref LL_RCC_PLLSAIQ_DIV_15 */ __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void) { return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ)); } #if defined(RCC_PLLSAICFGR_PLLSAIR) /** * @brief Get SAIPLL division factor for PLLSAIR * @note used for PLLSAICLK (SAI clock) * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAIR_DIV_2 * @arg @ref LL_RCC_PLLSAIR_DIV_3 * @arg @ref LL_RCC_PLLSAIR_DIV_4 * @arg @ref LL_RCC_PLLSAIR_DIV_5 * @arg @ref LL_RCC_PLLSAIR_DIV_6 * @arg @ref LL_RCC_PLLSAIR_DIV_7 */ __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void) { return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR)); } #endif /* RCC_PLLSAICFGR_PLLSAIR */ #if defined(RCC_PLLSAICFGR_PLLSAIP) /** * @brief Get SAIPLL division factor for PLLSAIP * @note used for PLL48MCLK (48M domain clock) * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAIP_DIV_2 * @arg @ref LL_RCC_PLLSAIP_DIV_4 * @arg @ref LL_RCC_PLLSAIP_DIV_6 * @arg @ref LL_RCC_PLLSAIP_DIV_8 */ __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void) { return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP)); } #endif /* RCC_PLLSAICFGR_PLLSAIP */ /** * @brief Get SAIPLL division factor for PLLSAIDIVQ * @note used PLLSAICLK selected (SAI clock) * @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 */ __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void) { return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ)); } #if defined(RCC_DCKCFGR_PLLSAIDIVR) /** * @brief Get SAIPLL division factor for PLLSAIDIVR * @note used for LTDC domain clock * @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 */ __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void) { return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR)); } #endif /* RCC_DCKCFGR_PLLSAIDIVR */ /** * @} */ #endif /* RCC_PLLSAI_SUPPORT */ /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management * @{ */ /** * @brief Clear LSI ready interrupt flag * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY * @retval None */ __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); } /** * @brief Clear LSE ready interrupt flag * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY * @retval None */ __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) { SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); } /** * @brief Clear HSI ready interrupt flag * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY * @retval None */ __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); } /** * @brief Clear HSE ready interrupt flag * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY * @retval None */ __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) { SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); } /** * @brief Clear PLL ready interrupt flag * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY * @retval None */ __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); } #if defined(RCC_PLLI2S_SUPPORT) /** * @brief Clear PLLI2S ready interrupt flag * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY * @retval None */ __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_PLLSAI_SUPPORT) /** * @brief Clear PLLSAI ready interrupt flag * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY * @retval None */ __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); } #endif /* RCC_PLLSAI_SUPPORT */ /** * @brief Clear Clock security system interrupt flag * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS * @retval None */ __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) { SET_BIT(RCC->CIR, RCC_CIR_CSSC); } /** * @brief Check if LSI ready interrupt occurred or not * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); } /** * @brief Check if LSE ready interrupt occurred or not * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); } /** * @brief Check if HSI ready interrupt occurred or not * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); } /** * @brief Check if HSE ready interrupt occurred or not * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); } /** * @brief Check if PLL ready interrupt occurred or not * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); } #if defined(RCC_PLLI2S_SUPPORT) /** * @brief Check if PLLI2S ready interrupt occurred or not * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF)); } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_PLLSAI_SUPPORT) /** * @brief Check if PLLSAI ready interrupt occurred or not * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF)); } #endif /* RCC_PLLSAI_SUPPORT */ /** * @brief Check if Clock security system interrupt occurred or not * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) { return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); } /** * @brief Check if RCC flag Independent Watchdog reset is set or not. * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); } /** * @brief Check if RCC flag Low Power reset is set or not. * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); } /** * @brief Check if RCC flag Pin reset is set or not. * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); } /** * @brief Check if RCC flag POR/PDR reset is set or not. * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); } /** * @brief Check if RCC flag Software reset is set or not. * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); } /** * @brief Check if RCC flag Window Watchdog reset is set or not. * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); } #if defined(RCC_CSR_BORRSTF) /** * @brief Check if RCC flag BOR reset is set or not. * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)); } #endif /* RCC_CSR_BORRSTF */ /** * @brief Set RMVF bit to clear the reset flags. * @rmtoll CSR RMVF LL_RCC_ClearResetFlags * @retval None */ __STATIC_INLINE void LL_RCC_ClearResetFlags(void) { SET_BIT(RCC->CSR, RCC_CSR_RMVF); } /** * @} */ /** @defgroup RCC_LL_EF_IT_Management IT Management * @{ */ /** * @brief Enable LSI ready interrupt * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY * @retval None */ __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); } /** * @brief Enable LSE ready interrupt * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY * @retval None */ __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) { SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); } /** * @brief Enable HSI ready interrupt * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY * @retval None */ __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); } /** * @brief Enable HSE ready interrupt * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY * @retval None */ __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) { SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); } /** * @brief Enable PLL ready interrupt * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY * @retval None */ __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); } #if defined(RCC_PLLI2S_SUPPORT) /** * @brief Enable PLLI2S ready interrupt * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY * @retval None */ __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_PLLSAI_SUPPORT) /** * @brief Enable PLLSAI ready interrupt * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY * @retval None */ __STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); } #endif /* RCC_PLLSAI_SUPPORT */ /** * @brief Disable LSI ready interrupt * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY * @retval None */ __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) { CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); } /** * @brief Disable LSE ready interrupt * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY * @retval None */ __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) { CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); } /** * @brief Disable HSI ready interrupt * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY * @retval None */ __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) { CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); } /** * @brief Disable HSE ready interrupt * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY * @retval None */ __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) { CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); } /** * @brief Disable PLL ready interrupt * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY * @retval None */ __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) { CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); } #if defined(RCC_PLLI2S_SUPPORT) /** * @brief Disable PLLI2S ready interrupt * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY * @retval None */ __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) { CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_PLLSAI_SUPPORT) /** * @brief Disable PLLSAI ready interrupt * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY * @retval None */ __STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void) { CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); } #endif /* RCC_PLLSAI_SUPPORT */ /** * @brief Checks if LSI ready interrupt source is enabled or disabled. * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); } /** * @brief Checks if LSE ready interrupt source is enabled or disabled. * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); } /** * @brief Checks if HSI ready interrupt source is enabled or disabled. * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); } /** * @brief Checks if HSE ready interrupt source is enabled or disabled. * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); } /** * @brief Checks if PLL ready interrupt source is enabled or disabled. * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); } #if defined(RCC_PLLI2S_SUPPORT) /** * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE)); } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_PLLSAI_SUPPORT) /** * @brief Checks if PLLSAI ready interrupt source is enabled or disabled. * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE)); } #endif /* RCC_PLLSAI_SUPPORT */ /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_EF_Init De-initialization function * @{ */ ErrorStatus LL_RCC_DeInit(void); /** * @} */ /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions * @{ */ void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); #if defined(FMPI2C1) uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource); #endif /* FMPI2C1 */ #if defined(LPTIM1) uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); #endif /* LPTIM1 */ #if defined(SAI1) uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); #endif /* SAI1 */ #if defined(SDIO) uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource); #endif /* SDIO */ #if defined(RNG) uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); #endif /* RNG */ #if defined(USB_OTG_FS) || defined(USB_OTG_HS) uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); #endif /* USB_OTG_FS || USB_OTG_HS */ #if defined(DFSDM1_Channel0) uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource); #endif /* DFSDM1_Channel0 */ uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); #if defined(CEC) uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); #endif /* CEC */ #if defined(LTDC) uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); #endif /* LTDC */ #if defined(SPDIFRX) uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource); #endif /* SPDIFRX */ #if defined(DSI) uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); #endif /* DSI */ /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /** * @} */ /** * @} */ #endif /* defined(RCC) */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F4xx_LL_RCC_H */

Details