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SourceVuSTM32 Libraries and SamplesCMSISNVIC_Type

NVIC_Type struct

Structure type to access the Nested Vectored Interrupt Controller (NVIC).

Syntax

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Summary

Declaration

from core_cm4.h:411

typedef struct { __IOM uint32_t ISER[8U]; uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; uint32_t RESERVED5[644U]; __OM uint32_t STIR; } NVIC_Type;

Fields

Field

Declared as

Description

NVIC_Type::ISER

__IOM uint32_t[8U]

Offset: 0x000 (R/W) Interrupt Set Enable Register.

NVIC_Type::RESERVED0

uint32_t[24U]

NVIC_Type::ICER

__IOM uint32_t[8U]

Offset: 0x080 (R/W) Interrupt Clear Enable Register.

NVIC_Type::RESERVED1

uint32_t[24U]

NVIC_Type::ISPR

__IOM uint32_t[8U]

Offset: 0x100 (R/W) Interrupt Set Pending Register.

NVIC_Type::RESERVED2

uint32_t[24U]

NVIC_Type::ICPR

__IOM uint32_t[8U]

Offset: 0x180 (R/W) Interrupt Clear Pending Register.

NVIC_Type::RESERVED3

uint32_t[24U]

NVIC_Type::IABR

__IOM uint32_t[8U]

Offset: 0x200 (R/W) Interrupt Active bit Register.

NVIC_Type::RESERVED4

uint32_t[56U]

__IOM uint8_t[240U]

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide).

NVIC_Type::RESERVED5

uint32_t[644U]

NVIC_Type::STIR

__OM uint32_t

Offset: 0xE00 ( /W) Software Trigger Interrupt Register.

Examples

References

from examples