Symbols
loading...
Files
loading...
SummarySyntaxReferences

Fields

Field
Declared as
Description
__IO uint32_t
DSI Host Version Register, Address offset: 0x00.
__IO uint32_t
DSI Host Control Register, Address offset: 0x04.
__IO uint32_t
DSI HOST Clock Control Register, Address offset: 0x08.
__IO uint32_t
DSI Host LTDC VCID Register, Address offset: 0x0C.
__IO uint32_t
DSI Host LTDC Color Coding Register, Address offset: 0x10.
__IO uint32_t
DSI Host LTDC Polarity Configuration Register, Address offset: 0x14.
__IO uint32_t
DSI Host Low-Power Mode Configuration Register, Address offset: 0x18.
uint32_t[4]
Reserved, 0x1C - 0x2B.
__IO uint32_t
DSI Host Protocol Configuration Register, Address offset: 0x2C.
__IO uint32_t
DSI Host Generic VCID Register, Address offset: 0x30.
__IO uint32_t
DSI Host Mode Configuration Register, Address offset: 0x34.
__IO uint32_t
DSI Host Video Mode Configuration Register, Address offset: 0x38.
__IO uint32_t
DSI Host Video Packet Configuration Register, Address offset: 0x3C.
__IO uint32_t
DSI Host Video Chunks Configuration Register, Address offset: 0x40.
__IO uint32_t
DSI Host Video Null Packet Configuration Register, Address offset: 0x44.
__IO uint32_t
DSI Host Video HSA Configuration Register, Address offset: 0x48.
__IO uint32_t
DSI Host Video HBP Configuration Register, Address offset: 0x4C.
__IO uint32_t
DSI Host Video Line Configuration Register, Address offset: 0x50.
__IO uint32_t
DSI Host Video VSA Configuration Register, Address offset: 0x54.
__IO uint32_t
DSI Host Video VBP Configuration Register, Address offset: 0x58.
__IO uint32_t
DSI Host Video VFP Configuration Register, Address offset: 0x5C.
__IO uint32_t
DSI Host Video VA Configuration Register, Address offset: 0x60.
__IO uint32_t
DSI Host LTDC Command Configuration Register, Address offset: 0x64.
__IO uint32_t
DSI Host Command Mode Configuration Register, Address offset: 0x68.
__IO uint32_t
DSI Host Generic Header Configuration Register, Address offset: 0x6C.
__IO uint32_t
DSI Host Generic Payload Data Register, Address offset: 0x70.
__IO uint32_t
DSI Host Generic Packet Status Register, Address offset: 0x74.
__IO uint32_t[6]
DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F.
__IO uint32_t
DSI Host 3D Configuration Register, Address offset: 0x90.
__IO uint32_t
DSI Host Clock Lane Configuration Register, Address offset: 0x94.
__IO uint32_t
DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98.
__IO uint32_t
DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C.
__IO uint32_t
DSI Host PHY Control Register, Address offset: 0xA0.
__IO uint32_t
DSI Host PHY Configuration Register, Address offset: 0xA4.
__IO uint32_t
DSI Host PHY ULPS Control Register, Address offset: 0xA8.
__IO uint32_t
DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC.
__IO uint32_t
DSI Host PHY Status Register, Address offset: 0xB0.
uint32_t[2]
Reserved, 0xB4 - 0xBB.
__IO uint32_t[2]
DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3.
__IO uint32_t[2]
DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB.
uint32_t[3]
Reserved, 0xD0 - 0xD7.
__IO uint32_t[2]
DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF.
uint32_t[8]
Reserved, 0xE0 - 0xFF.
__IO uint32_t
DSI Host Video Shadow Control Register, Address offset: 0x100.
uint32_t[2]
Reserved, 0x104 - 0x10B.
__IO uint32_t
DSI Host LTDC Current VCID Register, Address offset: 0x10C.
__IO uint32_t
DSI Host LTDC Current Color Coding Register, Address offset: 0x110.
uint32_t
Reserved, 0x114.
__IO uint32_t
DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118.
uint32_t[7]
Reserved, 0x11C - 0x137.
__IO uint32_t
DSI Host Video Mode Current Configuration Register, Address offset: 0x138.
__IO uint32_t
DSI Host Video Packet Current Configuration Register, Address offset: 0x13C.
__IO uint32_t
DSI Host Video Chunks Current Configuration Register, Address offset: 0x140.
__IO uint32_t
DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144.
__IO uint32_t
DSI Host Video HSA Current Configuration Register, Address offset: 0x148.
__IO uint32_t
DSI Host Video HBP Current Configuration Register, Address offset: 0x14C.
__IO uint32_t
DSI Host Video Line Current Configuration Register, Address offset: 0x150.
__IO uint32_t
DSI Host Video VSA Current Configuration Register, Address offset: 0x154.
__IO uint32_t
DSI Host Video VBP Current Configuration Register, Address offset: 0x158.
__IO uint32_t
DSI Host Video VFP Current Configuration Register, Address offset: 0x15C.
__IO uint32_t
DSI Host Video VA Current Configuration Register, Address offset: 0x160.
uint32_t[11]
Reserved, 0x164 - 0x18F.
__IO uint32_t
DSI Host 3D Current Configuration Register, Address offset: 0x190.
uint32_t[155]
Reserved, 0x194 - 0x3FF.
__IO uint32_t
DSI Wrapper Configuration Register, Address offset: 0x400.
__IO uint32_t
DSI Wrapper Control Register, Address offset: 0x404.
__IO uint32_t
DSI Wrapper Interrupt Enable Register, Address offset: 0x408.
__IO uint32_t
DSI Wrapper Interrupt and Status Register, Address offset: 0x40C.
__IO uint32_t
DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410.
uint32_t
Reserved, 0x414.
__IO uint32_t[5]
DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B.
uint32_t
Reserved, 0x42C.
__IO uint32_t
DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430.

References

from examples