pwm_config_set_clkdiv_mode() function

PWM configuration struct to modify

PWM divide/count mode

Initialise a PWM with settings from a configuration object Use the pwm_get_default_config() function to initialise a config structure, make changes as needed using the pwm_config_* functions, then call this function to set up the PWM.

Set PWM counter wrap value in a PWM configuration Set the highest value the counter will reach before returning to 0. Also known as TOP.

Set PWM clock divider in a PWM configuration If the divide mode is free-running, the PWM counter runs at clk_sys / div. Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge) before passing them on to the PWM counter.

Set PWM clock divider in a PWM configuration If the divide mode is free-running, the PWM counter runs at clk_sys / div. Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge) before passing them on to the PWM counter.

Set PWM clock divider in a PWM configuration using an 8:4 fractional value If the divide mode is free-running, the PWM counter runs at clk_sys / div. Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge) before passing them on to the PWM counter.

Set phase correction in a PWM configuration Setting phase control to true means that instead of wrapping back to zero when the wrap point is reached, the PWM starts counting back down. The output frequency is halved when phase-correct mode is enabled.

Set output polarity in a PWM configuration