pio_sm_set_pins() function

The PIO instance; e.g. pio0 or pio1

State machine index (0..3) to use

the pin values to set

Write a word of data to a state machine's TX FIFO, blocking if the FIFO is full

Enable or disable a PIO state machine

Return the instance number of a PIO instance

Immediately execute an instruction on a state machine This instruction is executed instead of the next instruction in the normal control flow on the state machine. Subsequent calls to this method replace the previous executed instruction if it is still running. \see pio_sm_is_exec_stalled() to see if an executed instruction is still running (i.e. it is stalled on some condition)

Claim a free state machine on a PIO instance

Mark a state machine as no longer used Method for cooperative claiming of hardware.

Read a word of data from a state machine's RX FIFO, blocking if the FIFO is empty

Determine if a state machine's RX FIFO is empty

Attempt to load the program \see pio_can_add_program() if you need to check whether the program can be loaded

Resets the state machine to a consistent state, and configures it This method: - Disables the state machine (if running) - Clears the FIFOs - Applies the configuration specified by 'config' - Resets any internal state e.g. shift counters - Jumps to the initial program location given by 'initial_pc' The state machine is left disabled on return from this call.

Mark a state machine as used Method for cooperative claiming of hardware. Will cause a panic if the state machine is already claimed. Use of this method by libraries detects accidental configurations that would fail in unpredictable ways.

Setup the function select for a GPIO to use output from the given PIO instance PIO appears as an alternate function in the GPIO muxing, just like an SPI or UART. This function configures that multiplexing to connect a given PIO instance to a GPIO. Note that this is not necessary for a state machine to be able to read the *input* value from a GPIO, but only for it to set the output value or output enable.

Determine if a state machine's TX FIFO is full

Determine whether the given program can (at the time of the call) be loaded onto the PIO instance

Use a state machine to set the same pin direction for multiple consecutive pins for the PIO instance This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set the pin direction on consecutive pins, before restoring the state machine's pin configuration to what it was. This method is provided as a convenience to set initial pin directions, and should not be used against a state machine that is enabled.

Remove a program from a PIO instance's instruction memory

Empty out a state machine's TX FIFO This method executes `pull` instructions on the state machine until the TX FIFO is empty. This disturbs the contents of the OSR, so see also pio_sm_clear_fifos() which clears both FIFOs but leaves the state machine's internal state undisturbed. \sa pio_sm_clear_fifos()

Return the base GPIO base for the PIO instance \if rp2040_specific This method always return 0 in RP2040 \endif

Apply a state machine configuration to a state machine

Return the DREQ to use for pacing transfers to/from a particular state machine FIFO

Restart a state machine with a known state This method clears the ISR, shift counters, clock divider counter pin write flags, delay counter, latched EXEC instruction, and IRQ wait condition.

Enable/Disable a single source on a PIO's specified (0/1) IRQ index

Clear a state machine's TX and RX FIFOs

Finds a PIO and statemachine and adds a program into PIO memory

Finds a PIO and statemachine and adds a program into PIO memory This variation of pio_claim_free_sm_and_add_program is useful on RP2350 QFN80 where the "GPIO Base" must be set per PIO instance to either address the 32 GPIOs (0->31) or the 32 GPIOS (16-47). No single PIO instance can interact with both pins 0->15 or 32->47 at the same time. This method takes additional information about the GPIO pins needed (via gpi_base and gpio_count), and optionally will set the GPIO base (\see pio_set_gpio_base) of an unused PIO instance if necessary

Enable or disable multiple PIO state machines Note that this method just sets the enabled state of the state machine; if now enabled they continue exactly from where they left off. \see pio_enable_sm_mask_in_sync() if you wish to enable multiple state machines and ensure their clock dividers are in sync.

Restart a state machine's clock divider from a phase of 0 Each state machine's clock divider is a free-running piece of hardware, that generates a pattern of clock enable pulses for the state machine, based *only* on the configured integer/fractional divisor. The pattern of running/halted cycles slows the state machine's execution to some controlled rate. This function clears the divider's integer and fractional phase accumulators so that it restarts this pattern from the beginning. It is called automatically by pio_sm_init() but can also be called at a later time, when you enable the state machine, to ensure precisely consistent timing each time you load and run a given PIO program. More commonly this hardware mechanism is used to synchronise the execution clocks of multiple state machines -- see pio_clkdiv_restart_sm_mask().

Restart multiple state machines' clock dividers on multiple PIOs from a phase of 0. Each state machine's clock divider is a free-running piece of hardware, that generates a pattern of clock enable pulses for the state machine, based *only* on the configured integer/fractional divisor. The pattern of running/halted cycles slows the state machine's execution to some controlled rate. This function simultaneously clears the integer and fractional phase accumulators of multiple state machines' clock dividers. If these state machines all have the same integer and fractional divisors configured, their clock dividers will run in precise deterministic lockstep from this point. With their execution clocks synchronised in this way, it is then safe to e.g. have multiple state machines performing a 'wait irq' on the same flag, and all clear it on the same cycle. Also note that this function can be called whilst state machines are running (e.g. if you have just changed the clock divisors of some state machines and wish to resynchronise them), and that disabling a state machine does not halt its clock divider: that is, if multiple state machines have their clocks synchronised, you can safely disable and re-enable one of the state machines without losing synchronisation.

Return the funcsel number of a PIO instance

Determine if a state machine's TX FIFO is empty

Determine if an instruction set by pio_sm_exec() is stalled executing

Immediately execute an instruction on a state machine and wait for it to complete This instruction is executed instead of the next instruction in the normal control flow on the state machine. Subsequent calls to this method replace the previous executed instruction if it is still running. \see pio_sm_is_exec_stalled() to see if an executed instruction is still running (i.e. it is stalled on some condition)

Write a word of data to a state machine's TX FIFO This is a raw FIFO access that does not check for fullness. If the FIFO is full, the FIFO contents and state are not affected by the write attempt. Hardware sets the TXOVER sticky flag for this FIFO in FDEBUG, to indicate that the system attempted to write to a full FIFO. \sa pio_sm_put_blocking()

Read a word of data from a state machine's RX FIFO This is a raw FIFO access that does not check for emptiness. If the FIFO is empty, the hardware ignores the attempt to read from the FIFO (the FIFO remains in an empty state following the read) and the sticky RXUNDER flag for this FIFO is set in FDEBUG to indicate that the system tried to read from this FIFO when empty. The data returned by this function is undefined when the FIFO is empty. \sa pio_sm_get_blocking()

set the current clock divider for a state machine using a 16:8 fraction

set the current clock divider for a state machine

Set the base GPIO base for the PIO instance Since an individual PIO accesses only 32 pins, to be able to access more pins, the PIO instance must specify a base GPIO where the instance's "pin 0" maps. For RP2350 the valid values are 0 and 16, indicating the PIO instance has access to pins 0-31, or 16-47 respectively.

Determine whether the given program can (at the time of the call) be loaded onto the PIO instance starting at a particular location

Attempt to load the program at the specified instruction memory offset \see pio_can_add_program_at_offset() if you need to check whether the program can be loaded

Clears all of a PIO instance's instruction memory

Use a state machine to set a value on multiple pins for the PIO instance This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set values on up to 32 pins, before restoring the state machine's pin configuration to what it was. This method is provided as a convenience to set initial pin states, and should not be used against a state machine that is enabled.

Use a state machine to set the pin directions for multiple pins for the PIO instance This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set pin directions on up to 32 pins, before restoring the state machine's pin configuration to what it was. This method is provided as a convenience to set initial pin directions, and should not be used against a state machine that is enabled.

Mark multiple state machines as used Method for cooperative claiming of hardware. Will cause a panic if any of the state machines are already claimed. Use of this method by libraries detects accidental configurations that would fail in unpredictable ways.

Determine if a PIO state machine is claimed

Removes a program from PIO memory and unclaims the state machine

Enable or disable multiple PIO state machines Note that this method just sets the enabled state of the state machine; if now enabled they continue exactly from where they left off. \see pio_enable_sm_mask_in_sync() if you wish to enable multiple state machines and ensure their clock dividers are in sync.

Restart multiple state machine with a known state This method clears the ISR, shift counters, clock divider counter pin write flags, delay counter, latched EXEC instruction, and IRQ wait condition.

Restart multiple state machines' clock dividers from a phase of 0. Each state machine's clock divider is a free-running piece of hardware, that generates a pattern of clock enable pulses for the state machine, based *only* on the configured integer/fractional divisor. The pattern of running/halted cycles slows the state machine's execution to some controlled rate. This function simultaneously clears the integer and fractional phase accumulators of multiple state machines' clock dividers. If these state machines all have the same integer and fractional divisors configured, their clock dividers will run in precise deterministic lockstep from this point. With their execution clocks synchronised in this way, it is then safe to e.g. have multiple state machines performing a 'wait irq' on the same flag, and all clear it on the same cycle. Also note that this function can be called whilst state machines are running (e.g. if you have just changed the clock divisors of some state machines and wish to resynchronise them), and that disabling a state machine does not halt its clock divider: that is, if multiple state machines have their clocks synchronised, you can safely disable and re-enable one of the state machines without losing synchronisation.

Enable multiple PIO state machines synchronizing their clock dividers This is equivalent to calling both pio_set_sm_mask_enabled() and pio_clkdiv_restart_sm_mask() on the *same* clock cycle. All state machines specified by 'mask' are started simultaneously and, assuming they have the same clock divisors, their divided clocks will stay precisely synchronised.

Enable multiple PIO state machines on multiple PIOs synchronizing their clock dividers This is equivalent to calling both pio_set_sm_multi_mask_enabled() and pio_clkdiv_restart_sm_multi_mask() on the *same* clock cycle. All state machines specified by 'mask' are started simultaneously and, assuming they have the same clock divisors, their divided clocks will stay precisely synchronised.

Enable/Disable a single source on a PIO's IRQ 0

Enable/Disable a single source on a PIO's IRQ 1

Enable/Disable multiple sources on a PIO's IRQ 0

Enable/Disable multiple sources on a PIO's IRQ 1

Return the number of elements currently in a state machine's TX FIFO

Set the current wrap configuration for a state machine

Set the current 'out' pins for a state machine 'out' pins can overlap with the 'in', 'set' and 'sideset' pins

Set the current 'sideset' pins for a state machine 'sideset' pins can overlap with the 'in', 'out' and 'set' pins

Set the 'jmp' pin for a state machine

Clear a particular PIO interrupt

Return the current program counter for a state machine

Enable/Disable multiple sources on a PIO's specified (0/1) IRQ index

Determine if a particular PIO interrupt is set

Determine if a state machine's RX FIFO is full

Return the number of elements currently in a state machine's RX FIFO

Set the current 'set' pins for a state machine 'set' pins can overlap with the 'in', 'out' and 'sideset' pins

Set the current 'in' pins for a state machine 'in' pins can overlap with the 'out', 'set' and 'sideset' pins

Return an IRQ for a PIO hardware instance