interp_config struct

Send configuration to a lane If an invalid configuration is specified (ie a lane specific item is set on wrong lane), depending on setup this function can panic.

Set the interpolator mask range Sets the range of bits (least to most) that are allowed to pass through the interpolator

Set the interpolator shift value Sets the number of bits the accumulator is shifted before masking, on each iteration.

Set sign extension Enables signed mode, where the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP results appear extended to 32 bits when read by processor.

Set blend mode If enabled, LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsig

Set raw add option When enabled, mask + shift is bypassed for LANE0 result. This does not affect the FULL result.

Enable cross input Allows feeding of the accumulator content from the other lane back in to this lanes shift+mask hardware. This will take effect even if the interp_config_set_add_raw option is set as the cross input mux is before the shift+mask bypass

Enable cross results Allows feeding of the other lane’s result into this lane’s accumulator on a POP operation.

Set interpolator clamp mode (Interpolator 1 only) Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is a shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED

Set interpolator Force bits ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM