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dma_hw_t struct
Syntax
typedef struct
{
dma_channel_hw_t ch[16];
union {
struct {
_REG_(DMA_INTR_OFFSET)
io_rw_32 intr;
_REG_(DMA_INTE0_OFFSET)
io_rw_32 inte0;
_REG_(DMA_INTF0_OFFSET)
io_rw_32 intf0;
_REG_(DMA_INTS0_OFFSET)
io_rw_32 ints0;
uint32_t __pad0;
_REG_(DMA_INTE1_OFFSET)
io_rw_32 inte1;
_REG_(DMA_INTF1_OFFSET)
io_rw_32 intf1;
_REG_(DMA_INTS1_OFFSET)
io_rw_32 ints1;
uint32_t __pad1;
_REG_(DMA_INTE2_OFFSET)
io_rw_32 inte2;
_REG_(DMA_INTF2_OFFSET)
io_rw_32 intf2;
_REG_(DMA_INTS2_OFFSET)
io_rw_32 ints2;
uint32_t __pad2;
_REG_(DMA_INTE3_OFFSET)
io_rw_32 inte3;
_REG_(DMA_INTF3_OFFSET)
io_rw_32 intf3;
_REG_(DMA_INTS3_OFFSET)
io_rw_32 ints3;
};
dma_irq_ctrl_hw_t irq_ctrl[4];
};
_REG_(DMA_TIMER0_OFFSET)
io_rw_32 timer[4];
_REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET)
io_wo_32 multi_channel_trigger;
_REG_(DMA_SNIFF_CTRL_OFFSET)
io_rw_32 sniff_ctrl;
_REG_(DMA_SNIFF_DATA_OFFSET)
io_rw_32 sniff_data;
uint32_t _pad0;
_REG_(DMA_FIFO_LEVELS_OFFSET)
io_ro_32 fifo_levels;
_REG_(DMA_CHAN_ABORT_OFFSET)
io_wo_32 abort;
_REG_(DMA_N_CHANNELS_OFFSET)
io_ro_32 n_channels;
uint32_t _pad1[5];
_REG_(DMA_SECCFG_CH0_OFFSET)
io_rw_32 seccfg_ch[16];
_REG_(DMA_SECCFG_IRQ0_OFFSET)
io_rw_32 seccfg_irq[4];
_REG_(DMA_SECCFG_MISC_OFFSET)
io_rw_32 seccfg_misc;
uint32_t _pad2[11];
_REG_(DMA_MPU_CTRL_OFFSET)
io_rw_32 mpu_ctrl;
dma_mpu_region_hw_t mpu_region[8];
} dma_hw_t;
Fields
Field
Declared as
uint32_t
uint32_t[5]
uint32_t[11]